Circuit boards and electronic devices

Abstract

This application provides a circuit board and an electronic device, including a first reference layer and a second reference layer disposed opposite to each other along the thickness direction of the circuit board. At least two lead layers are located between the first and second reference layers. The circuit board also includes multiple lead units, with leads in the lead units located on different lead layers. The leads in each lead unit extend along a first direction, and the leads in each lead unit are staggered along the first direction so that the projections of the leads on the first reference layer are staggered. The first direction is either the length direction or the width direction of the circuit board. This application provides a circuit board that can achieve complete circuits for signals in leads located on different lead layers without adding reference layers, thereby reducing the cost of the circuit board.

Description

Technical Field

[0001] This invention relates to the field of server technology, and more particularly to a circuit board and electronic device. Background Technology

[0002] Electronic devices can include various electronic devices such as servers and controllers.

[0003] With increasing demands for packaging density in electronic devices, high-density components are becoming more prevalent. These components typically have a large number of pins. Circuit boards include vias and lead-out layers. Lead-out layers have wires electrically connected to the vias. The pins of high-density components connect to these vias and, through these vias, to different leads on the lead-out layers, thus connecting to other components on the circuit board via these leads. As the number of pins in high-density components increases, so does the number of leads. Therefore, it is necessary to increase the number of lead-out layers to accommodate these different leads. Furthermore, reference layers are needed between different lead-out layers to ensure that signals in the leads on the lead-out layers have complete loops.

[0004] The addition of lead-out layers and reference layers increases the number of layers on the circuit board, thereby increasing the cost of the circuit board. Summary of the Invention

[0005] This application provides a circuit board and an electronic device. By staggering the leads in different lead units along their extension directions, signals in leads located on different lead layers can have complete loops without adding a reference layer, thereby reducing the cost of the circuit board.

[0006] The first aspect of this application provides a circuit board including a first reference layer and a second reference layer disposed opposite to each other along the thickness direction of the circuit board, with at least two lead layers between the first reference layer and the second reference layer, and the circuit board further includes a plurality of lead units, wherein the leads in the lead units are located on different lead layers.

[0007] All leads in the lead unit extend along a first direction, and the leads in the lead unit are staggered along the first direction so that the projections of the leads on the first reference layer are staggered, wherein the first direction is the length direction or width direction of the circuit board.

[0008] The circuit board provided in this application embodiment comprises a first reference layer, a second reference layer, at least two lead layers, and multiple lead units. The at least two lead layers are located between the first and second reference layers, and the leads in the lead units are located on different lead layers. The leads in each lead unit extend along a first direction and are staggered along this direction, so that the projections of the leads on the first reference layer are staggered. This means that the leads correspond to different regions on the first (or second) reference layer along the thickness direction of the circuit board, and the signals transmitted in the leads can form complete loops with different regions on the first (or second) reference layer. Therefore, it avoids adding a reference layer between adjacent lead layers, thereby reducing the cost of the circuit board. The circuit board provided in this application embodiment, by staggering the leads in different lead units along their extension directions, can achieve complete loops for signals in leads located on different lead layers without adding a reference layer, thereby reducing the cost of the circuit board.

[0009] In one possible implementation, the circuit board provided in this application includes a first lead layer and a second lead layer, which are located between a first reference layer and a second reference layer along the thickness direction of the circuit board. The lead unit includes multiple first lead units and multiple second lead units. Each first lead unit includes a first lead located on the first lead layer, and each second lead unit includes a second lead located on the second lead layer. Both the first and second leads extend along a first direction and are staggered along this direction, so that their projections on the first reference layer are staggered. The projections of the first and second leads on the first reference layer (or second reference layer) along the thickness direction of the circuit board are staggered along their extension directions, allowing signals transmitted in both leads to form complete loops with different areas on the first reference layer (or second reference layer). This avoids the need to add a reference layer between adjacent lead layers, thereby reducing the cost of the circuit board.

[0010] In one possible implementation, the circuit board provided in this application includes a first via unit and a second via unit. The first via unit is electrically connected to a first lead, and the second via unit is electrically connected to a second lead. Both the first and second via units are used to connect to pins on high-density components. Thus, the pins of the high-density components are connected one-to-one with the first lead through the first via unit and one-to-one with the second lead through the second via unit.

[0011] In one possible implementation, the circuit board provided in this application embodiment includes a third lead layer and a fourth lead layer, which are located between a first reference layer and a second reference layer along the thickness direction of the circuit board. The lead unit includes multiple third lead units and multiple fourth lead units. Each third lead unit includes a third positive lead and a third negative lead, and each fourth lead unit includes a fourth positive lead and a fourth negative lead. The third positive lead and the fourth positive lead are located on the third lead layer, and the third negative lead and the fourth negative lead are located on the fourth lead layer. All three leads extend along a first direction. The third positive lead and the third negative lead need to be coupled between different lead layers, and the fourth positive lead and the fourth negative lead also need to be coupled between different lead layers. Therefore, no reference layer is required between the third lead layer and the fourth lead layer.

[0012] In one possible implementation, the circuit board provided in this application has a third positive lead and a third negative lead overlapping along a first direction, such that their projections on the first reference layer overlap; and a fourth positive lead and a fourth negative lead overlapping along the first direction, such that their projections on the first reference layer overlap. This reduces the spacing between the third positive lead and the third negative lead, facilitating interlayer coupling between them. It also reduces the spacing between the fourth positive lead and the fourth negative lead, further facilitating interlayer coupling between them.

[0013] In one possible implementation, the circuit board provided in this application has a third positive lead and a fourth positive lead offset along a first direction, so that their projections on the first reference layer are offset; the third negative lead and the fourth negative lead are offset along their extension direction, so that their projections on the first reference layer are offset. Thus, the projections of the third lead unit and the fourth lead unit onto the first reference layer (or the second reference layer) along the thickness direction of the circuit board are offset along their extension direction, and the signals transmitted in the third lead unit and the fourth lead unit can form complete loops with different areas on the first reference layer (or the second reference layer).

[0014] In one possible implementation, the circuit board provided in this application includes a third via unit and a fourth via unit. The third via unit includes a third positive via and a third negative via, and the fourth via unit includes a fourth positive via and a fourth negative via. The third positive via is electrically connected to a third positive lead, and the third negative via is electrically connected to a third negative lead. The fourth positive via is electrically connected to a fourth positive lead, and the fourth negative via is electrically connected to a fourth negative lead. The third positive via, third negative via, fourth positive via, and fourth negative via are all used to connect to pins on high-density components. The pins of the high-density components are connected one-to-one with the third positive lead through the third positive via, one-to-one with the third negative lead through the third negative via, one-to-one with the fourth positive lead through the fourth positive via, and one-to-one with the fourth negative via through the fourth negative via.

[0015] In one possible implementation, the circuit board provided in this application includes a first region and a second region, with a plurality of third via units located in the first region and a plurality of fourth via units located in the second region. By respectively arranging the third and fourth via units in the first and second regions, the third and fourth via units can be spatially spaced apart to facilitate wiring in the circuit board.

[0016] In one possible implementation, the circuit board provided in this application further includes a dielectric layer, with a dielectric layer disposed between each pair of the first reference layer, the second reference layer, and the lead layer. The dielectric layer can serve as insulation and support between each reference layer and the lead layer.

[0017] A second aspect of this application provides an electronic device, including an electronic device body and the aforementioned circuit board located within the electronic device body. The circuit board is provided with high-density components, which are electrically connected to the circuit board.

[0018] These and other aspects, embodiments, and advantages of the exemplary embodiments will become apparent from the accompanying drawings and the examples described below. However, it should be understood that the specification and drawings are for illustrative purposes only and are not intended to limit the scope of this application; details are provided in the appended claims. Other aspects and advantages of this application will be set forth in the following description, and in part will be obvious from the description or may be learned by practice of the application. Furthermore, various aspects and advantages of this application may be realized and obtained by means and combinations particularly pointed out in the appended claims. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application;

[0020] Figure 2 This is a schematic diagram of the structure of high-density components in an electronic device provided in an embodiment of this application;

[0021] Figure 3 This is a schematic diagram of the circuit board structure in related technologies;

[0022] Figure 4 for Figure 3 Sectional view of line AA in the middle;

[0023] Figure 5 This is a schematic diagram of the circuit board structure in related technology two;

[0024] Figure 6 for Figure 5 Sectional view of the middle BB line;

[0025] Figure 7 A schematic diagram of the circuit board structure provided in the embodiments of this application. Figure 1 ;

[0026] Figure 8 for Figure 7 Top view;

[0027] Figure 9 for Figure 7 A cross-sectional view of the CC line;

[0028] Figure 10 A schematic diagram of the circuit board structure provided in the embodiments of this application. Figure 2 ;

[0029] Figure 11 for Figure 10 Top view;

[0030] Figure 12 for Figure 10 Sectional view of the DD line;

[0031] Figure 13 A schematic diagram of the circuit board structure provided in the embodiments of this application. Figure 3 ;

[0032] Figure 14 for Figure 13 Top view;

[0033] Figure 15 for Figure 13 A cross-sectional view of the EE line.

[0034] Explanation of reference numerals in the attached figures:

[0035] 10. Electronic devices;

[0036] 100. Electronic device body;

[0037] 200n, Circuit board; 210n, Pad; 220n, Via; 230n, Outgoing layer; 240n, Lead; 241n, Receive differential pair lead; 242n, Transmit differential pair lead; 250n, Reference layer; 260n, Insulating layer;

[0038] 200, Circuit board; 200a, First area; 200b, Second area;

[0039] 210. First reference layer; 211. Loop region;

[0040] 220. Second reference layer;

[0041] 230. Lead layer; 231. First lead layer; 232. Second lead layer; 233. Third lead layer; 234. Fourth lead layer;

[0042] 240, Lead unit; 241, First lead unit; 2411, First lead; 242, Second lead unit; 2421, Second lead; 243, Third lead unit; 243a, Third positive lead; 243b, Third negative lead; 244, Fourth lead unit; 244a, Fourth positive lead; 244b, Fourth negative lead;

[0043] 250. First via unit;

[0044] 260. Second via unit;

[0045] 270. Third via unit; 271. Third positive via; 272. Third negative via;

[0046] 280. Fourth via unit; 281. Fourth positive via; 282. Fourth negative via;

[0047] 290. Dielectric layer;

[0048] 300. High-density components; 310. Component body; 320. Pins;

[0049] 400. Cables;

[0050] X, length direction;

[0051] Y, width direction;

[0052] Z, thickness direction. Detailed Implementation

[0053] The terminology used in the implementation section of this application is only for explaining specific embodiments of this application and is not intended to limit this application. The implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0054] Figure 1A schematic diagram of the structure of an electronic device provided in an embodiment of this application. See also... Figure 1 As shown, the electronic device 10 includes an electronic device body 100 and a circuit board 200 located inside the electronic device body 100. High-density components 300 are disposed on the circuit board 200 and are electrically connected to the circuit board 200.

[0055] The electronic device body 100 may be a housing, and the circuit board 200 is installed in the housing. Figure 1 The electronic device shown has its top cover removed to allow a clear view of the internal structure.

[0056] The electronic device 10 may include one circuit board 200, or two or more circuit boards 200. The circuit boards 200 can be mounted on the side or bottom wall of the electronic device body 100 using fasteners, depending on the number and layout of the circuit boards 200 in the electronic device 10. Figure 1 In the illustrated embodiment, the electronic device 10 includes two circuit boards 200, both of which are mounted on the bottom wall of the electronic device body 100, and the circuit boards 200 are electrically connected to each other via a cable 400.

[0057] Electronic devices may include various electronic devices such as servers and controllers. In this embodiment, a server is used as an example for illustration. A server may be a desktop server, blade server, rack server, cabinet server, or other types.

[0058] As the demand for server computing density increases, more and more high-density components are being used in servers. Specifically, electronic device 10 also includes various high-density components 300, which are all soldered onto circuit board 200 for electrical connection with circuit board 200.

[0059] The high-density component 300 has multiple pins, all of which connect to leads in the circuit board 200 for transmitting different signals. The high-density component 300 can be available in various package types, such as LCC (Leadless Chip Carriers) packages, QFN (Quad Flat No-lead Package) packages, and BGA (Ball Grid Array) packages. Among these, BGA packages are widely used in various servers due to their advantages such as a large number of pins and pin coplanarity.

[0060] The following uses BGA packaged devices as an example to illustrate the structure of high-density components 300 and the connection method between high-density components 300 and circuit board 200.

[0061] Figure 2 This is a schematic diagram of the structure of high-density components in an electronic device provided in an embodiment of this application.

[0062] See Figure 2 As shown, the high-density component 300 includes a device body 310 and multiple pins 320 located at the bottom of the device body 310. In a BGA device, the multiple pins 320 are arranged in an array at the bottom of the device body 310 in the form of solder balls, thereby making full use of the space at the bottom of the device body 310. The number of pins 320 is increasing to meet the packaging density requirements of the electronic device 10.

[0063] Figure 3 This is a schematic diagram of the circuit board structure in related technology one; Figure 4 for Figure 3 The cross-sectional view along line AA shows that, in related technologies, the circuit board is represented by 200n, and each component in the circuit board 200n is also suffixed with n to distinguish it from the circuit board 200 in the embodiments of this application.

[0064] See Figure 3 and Figure 4 As shown, the circuit board 200n is typically a flat cuboid. For ease of description, the direction in which the thickness of the circuit board 200n extends is called the thickness direction Z, the direction in which the length of the circuit board 200n extends is called the length direction X, and the direction in which the width of the circuit board 200n extends is called the width direction Y. On one surface of the circuit board 200n along its thickness direction Z, there are pads 210n that correspond one-to-one with the pins 320 on the high-density component 300. The circuit board 200n has multiple vias 220n extending along its thickness direction. One end of each via 220n is connected to a pad 210n. The vias 220n and the pads 210n can be concentrically positioned. The pins 320 on the high-density component 300 are electrically connected to the vias 220n through the pads 210n.

[0065] The circuit board 200n includes a trace layer 230n disposed in the thickness direction Z. A lead 240n is disposed on the trace layer 230n, and the other end of a via 220n extends along the thickness direction Z to the trace layer 230n to connect with the lead 240n on the trace layer 230n, thereby connecting to other devices on the circuit board 200n via the lead 240n. In related art, the lead 240n in the circuit board 200n is a single-ended lead.

[0066] As the number of pins 320 on the high-density component 300 increases, the number of leads 240n electrically connected to the pins 320 also increases. Different pins 320 correspond to different signals, therefore the leads 240n need to be led out from different output layers 230n on the circuit board 200. This results in an increase in the number of output layers 230n on the circuit board 200. Figure 4 For simplicity, only two lead layers 230n are shown. Along the thickness direction Z of the circuit board 200, reference layers 250n need to be added on both sides of the lead layers 230n. The reference layers 250n are used to ensure that the signals in the leads 240n have a complete signal loop, so as to reduce mutual interference between signals in the leads 240n.

[0067] The increase in the number of output layers 230n and reference layers 250n leads to an increase in the number of layers on the circuit board 200n, which in turn increases the cost of the circuit board 200n.

[0068] In circuit boards where signal transmission quality requirements are not high, the number of layers in circuit board 200n can be reduced by removing the side reference layer 250n between adjacent output layers 230n, thereby reducing the cost of circuit board 200n. Meanwhile, the thickness of the insulating layer 260n between signal layers can be increased to reduce crosstalk in signal transmission between two adjacent output layers 230n. However, this solution is not suitable for circuit boards 200n where signal transmission quality requirements are relatively high.

[0069] Figure 5 This is a schematic diagram of the circuit board structure in related technology two; Figure 6 for Figure 5 A cross-sectional view along the BB line.

[0070] See Figure 5 and Figure 6 As shown, unlike in related technology one, in related technology two, the lead 240n in circuit board 200n uses differential pair leads.

[0071] Please continue reading Figure 6 As shown, lead 240n includes a receive differential pair lead 241n for receiving signals and a transmit differential pair lead 242n for transmitting signals. To avoid mutual interference between the receive differential pair lead 241n and the transmit differential pair lead 242n during signal transmission, the receive differential pair lead 241n and the transmit differential pair lead 242n are typically placed in different output layers 230n, and a reference layer 250n is added between the output layers 230n.

[0072] The increase in the number of output layers 230n and reference layers 250n leads to an increase in the number of layers on the circuit board 200n, which in turn increases the cost of the circuit board 200n.

[0073] Based on this, embodiments of this application provide a circuit board that avoids the need to add a reference layer between two adjacent lead layers, thereby reducing the cost of the circuit board.

[0074] Figure 7 A schematic diagram of the circuit board structure provided in the embodiments of this application. Figure 1 ; Figure 8 for Figure 7 Top view; Figure 9 for Figure 7 A sectional view of the CC line. For clarity, [the text is incomplete]. Figure 7 and Figure 8 The first reference layer 210 and the second reference layer 220 are shown in dashed lines. Figure 7 The lead layer 230 is not shown; only the lead unit 240 disposed in the lead layer 230 is shown.

[0075] See Figures 7 to 9 As shown, the circuit board 200 provided in this application embodiment includes a first reference layer 210 and a second reference layer 220 disposed opposite to each other along the thickness direction Z of the circuit board 200. There are at least two lead layers 230 between the first reference layer 210 and the second reference layer 220. The circuit board 200 also includes a plurality of lead units 240, and the leads in the lead units 240 are located on different lead layers 230. The leads in the lead units 240 all extend along a first direction, and the leads in the lead units 240 are staggered along the first direction so that the projections of the leads on the first reference layer 210 are staggered, wherein the first direction is the length direction X or the width direction Y of the circuit board.

[0076] Specifically, circuit board 200 is usually a flat cuboid. For ease of description, the direction in which the thickness of circuit board 200 extends is called the thickness direction Z, the direction in which the length of circuit board 200n extends is called the length direction X, and the direction in which the width of circuit board 200 extends is called the width direction Y.

[0077] Please continue reading Figure 7 and Figure 9 As shown, the first reference layer 210 and the second reference layer 220 are disposed opposite to each other along the thickness direction Z of the circuit board 200. The first reference layer 210 and the second reference layer 220 can be power layers or ground layers in the circuit board 200. The first reference layer 210 and the second reference layer 220 have a large area of ​​copper plating. The first reference layer 210 and the second reference layer 220 are used to enable the lead unit 240 in the lead layer 230 to form a complete loop with the copper plating at corresponding positions on the first reference layer 210 and the second reference layer 220 when transmitting signals, which can improve the anti-interference capability of the leads in the lead unit 240 when transmitting signals.

[0078] Please continue reading Figure 7 and Figure 9As shown, the circuit board 200 also includes lead layers 230. There can be two or more lead layers 230, depending on the number of pins 320 in the high-density components 300. In this embodiment, two lead layers 230 are used as an example. The two lead layers 230 are located between the first reference layer 210 and the second reference layer 220, and are spaced apart along the thickness direction Z of the circuit board 200. Each lead layer 230 has multiple lead units 240 for signal transmission.

[0079] The lead unit 240 includes leads, which are electrically connected one-to-one with the pins 320 in the high-density component 300 to electrically connect the high-density component 300 to the circuit board 200.

[0080] The lead can extend along the length direction X or the width direction Y of the circuit board 200. The lead can also extend along other directions in the plane formed by the length direction X and the width direction Y. In this embodiment, the lead extends along the length direction X.

[0081] As the number of pins 320 in the high-density component 300 increases, lead units 240 need to be placed on different lead layers 230. The leads placed on different lead layers 230 are used to transmit different signals, therefore, crosstalk exists between the leads. In related technologies, a reference layer is added between different lead layers 230 to ensure that signals in leads located on different lead layers 230 have a complete return path.

[0082] In this embodiment, by staggering the leads in different lead units 240 along their extension directions, signals located on leads in different lead layers 230 can have complete loops without adding a reference layer.

[0083] Please continue reading Figure 8 and Figure 9 As shown, the projections of the leads along the thickness direction Z of the circuit board 200 onto the first reference layer 210 (or the second reference layer 220) are staggered along their extension direction. That is, the leads along the thickness direction Z of the circuit board 200 correspond to different regions on the first reference layer 210 (or the second reference layer 220). This region is called the loop region 211. Figure 8 In this circuit, each lead unit 240 has a lead corresponding to a loop region 211, and the signals transmitted in the lead can form a complete loop with the loop region 211 on the first reference layer 210 (or the second reference layer 220). Therefore, it is possible to avoid adding a reference layer between two adjacent lead layers 230, thereby reducing the cost of the circuit board 200.

[0084] The lead unit 240 can be a single-ended lead or a differential pair lead. The following describes the arrangement of the leads in the lead unit 240 on the lead layer 230 when the lead unit 240 is a single-ended lead or a differential pair lead.

[0085] First, when the lead unit 240 is a single-ended lead, the arrangement of the leads in the lead unit 240 on the lead layer 230 will be explained.

[0086] Figure 10 A schematic diagram of the circuit board structure provided in the embodiments of this application. Figure 2 ; Figure 11 for Figure 10 Top view; Figure 12 for Figure 10 A sectional view of the DD line. For clarity, [the text is incomplete]. Figure 10 and Figure 11 The first reference layer 210 and the second reference layer 220 are shown in dashed lines. Figure 10 The first lead layer 231 and the second lead layer 232 are not shown; only the first lead unit 241 disposed in the first lead layer 231 and the second lead unit 242 disposed in the second lead layer 232 are shown.

[0087] See Figures 10 to 12 As shown, the lead layer 230 includes a first lead layer 231 and a second lead layer 232, which are located between the first reference layer 210 and the second reference layer 220 along the thickness direction Z of the circuit board 200; the lead unit 240 includes a plurality of first lead units 241 and a plurality of second lead units 242, the first lead unit 241 includes a first lead 2411 located on the first lead layer 231, and the second lead unit 242 includes a second lead 2421 located on the second lead layer 232; both the first lead 2411 and the second lead 2421 extend along a first direction, and are staggered along the first direction so that the projections of the first lead 2411 and the second lead 2421 on the first reference layer 210 are staggered.

[0088] Specifically, the two lead layers 230 between the first reference layer 210 and the second reference layer 220 are referred to as the first lead layer 231 and the second lead layer 232, respectively.

[0089] The lead unit 240 located on the first lead layer 231 is called the first lead unit 241, and the lead unit 240 located on the second lead layer 232 is called the second lead unit 242. Since the signal is transmitted through a single-ended lead, the first lead unit 241 includes one lead, called the first lead 2411, and the second lead unit 242 also includes one lead, called the second lead 2421. Figures 10 to 12 Two first leads 2411 and three second leads 2421 are schematically shown.

[0090] Please continue reading Figure 10 and Figure 11 As shown, both the first lead 2411 and the second lead 2421 extend along the length direction X of the circuit board 200. Please continue to refer to... Figure 12 As shown, the projections of the first lead 2411 and the second lead 2421 onto the first reference layer 210 (or the second reference layer 220) along the thickness direction Z of the circuit board 200 are staggered along their extension direction. That is, the first lead 2411 and the second lead 2421 correspond to different loop regions 211 on the first reference layer 210 (or the second reference layer 220) along the thickness direction Z of the circuit board 200. Signals transmitted in both the first lead 2411 and the second lead 2421 can form a complete loop with the loop region 211 on the first reference layer 210 (or the second reference layer 220). Therefore, it is possible to avoid adding a reference layer between two adjacent lead layers 230, thereby reducing the cost of the circuit board 200.

[0091] The following describes the specific connection method between the first lead 2411 and the second lead 2421 and the pin 320 in the high-density component 300 when the lead unit 240 is a single-ended lead.

[0092] Please continue reading Figure 10 and Figure 11 As shown, the circuit board 200 includes a first via unit 250 and a second via unit 260. The first via unit 250 is electrically connected to a first lead 2411, and the second via unit 260 is electrically connected to a second lead 2421. Both the first via unit 250 and the second via unit 260 are used to connect to pins 320 on the high-density component 300. Wherein... Figure 10 and Figure 11 In addition to the first via unit 250 and the second via unit 260, other vias are also schematically shown.

[0093] Specifically, the first via unit 250 is disposed between the first lead layer 231 and the upper surface of the circuit board 200 along the thickness direction Z of the circuit board 200. One end of the first via unit 250 is connected to the pin 320 in the high-density component 300, and the other end of the first via unit 250 is connected to the first lead 2411. Thus, the pin 320 in the high-density component 300 is connected to the first lead 2411 one by one through the first via unit 250.

[0094] The second via unit 260 is disposed along the thickness direction Z of the circuit board 200 between the second lead layer 232 and the upper surface of the circuit board 200. One end of the second via unit 260 is connected to the pin 320 in the high-density component 300, and the other end of the second via unit 260 is connected to the second lead 2421. Thus, the pin 320 in the high-density component 300 is connected to the second lead 2421 one by one through the second via unit 260.

[0095] The following describes the arrangement of the leads in lead unit 240 on lead layer 230 when lead unit 240 is a differential pair lead.

[0096] A differential pair consists of two leads: one for transmitting a positive signal and the other for transmitting a negative signal. Subtracting the negative signal from the positive signal yields a useful signal with twice the strength. Furthermore, because the two leads in a differential pair are parallel and of equal length, the interference levels on both leads are similar. Subtracting the interference signals on each lead effectively eliminates interference between them; this process is called differential pair coupling. Therefore, differential pairs offer high signal strength and good interference immunity, and are typically used in circuit board wiring where high signal quality is required.

[0097] Figure 13 A schematic diagram of the circuit board structure provided in the embodiments of this application. Figure 3 ; Figure 14 for Figure 13 Top view; Figure 15 for Figure 13 A sectional view of the DD line. For clarity, [the text is incomplete]. Figure 13 and Figure 14 The first reference layer 210 and the second reference layer 220 are shown in dashed lines. Figure 13 The third lead layer 233 and the fourth lead layer 234 are not shown; only the third lead unit 243 disposed in the third lead layer 233 and the fourth lead unit 244 disposed in the fourth lead layer 234 are shown.

[0098] See Figures 13 to 15As shown, lead layer 230 includes a third lead layer 233 and a fourth lead layer 234, which are located between the first reference layer 210 and the second reference layer 220 along the thickness direction Z of the circuit board 200; lead unit 240 includes a plurality of third lead units 243 and a plurality of fourth lead units 244, the third lead unit 243 includes a third positive lead 243a and a third negative lead 243b, and the fourth lead unit 244 includes a fourth positive lead 244a and a fourth negative lead 244b. The third positive lead 243a and the fourth positive lead 244a are located on the third lead layer 233, and the third negative lead 243b and the fourth negative lead 244b are located on the fourth lead layer 234; the third positive lead 243a, the third negative lead 243b, the fourth positive lead 244a, and the fourth negative lead 244b all extend along a first direction.

[0099] A third lead layer 233 and a fourth lead layer 234 are further disposed between the first reference layer 210 and the second reference layer 220. It should be noted that the third lead layer 233 and the fourth lead layer 234 are only used for ease of distinction from the first lead layer 231 and the second lead layer 232 in the above embodiments. The first lead layer 231 and the third lead layer 233 can be the same lead layer 230 or different lead layers 230; the second lead layer 232 and the fourth lead layer 234 can be the same lead layer 230 or different lead layers 230.

[0100] Differential pair leads typically include receive differential pair leads for receiving signals and transmit differential pair leads for transmitting signals.

[0101] The third lead unit 243 can be a receiving differential pair lead, and the third lead unit 243 includes a third positive lead 243a and a third negative lead 243b.

[0102] Both the third positive lead 243a and the third negative lead 243b extend along the length direction X of the circuit board 200. The third positive lead 243a is located on the third lead layer 233, and the third negative lead 243b is located on the fourth lead layer 234. That is, the third positive lead 243a and the third negative lead 243b are located on two adjacent lead layers 230. The third positive lead 243a and the third negative lead 243b need to be coupled between different lead layers 230. Therefore, no reference layer is needed between the third lead layer 233 and the fourth lead layer 234. This coupling method, where the third positive lead 243a and the third negative lead 243b need to be coupled between different lead layers 230, is called interlayer coupling.

[0103] The fourth lead unit 244 can be a transmit differential pair lead, and the fourth lead unit 244 includes a fourth positive lead 244a and a fourth negative lead 244b.

[0104] Both the fourth positive lead 244a and the fourth negative lead 244b extend along the length direction X of the circuit board 200. The fourth positive lead 244a is located on the third lead layer 233, and the fourth negative lead 244b is located on the fourth lead layer 234. That is to say, the fourth positive lead 244a and the fourth negative lead 244b are located on two adjacent lead layers 230. The fourth positive lead 244a and the fourth negative lead 244b need to be coupled between different lead layers 230. Therefore, no reference layer is needed between the third lead layer 233 and the fourth lead layer 234.

[0105] Furthermore, by placing the third positive lead 243a and the fourth positive lead 244a on the third lead layer 233, and the third negative lead 243b and the fourth negative lead 244b on the fourth lead layer 234, the space on the third lead layer 233 and the fourth lead layer 234 can be fully utilized.

[0106] Please continue reading Figure 14 and Figure 15 As shown, the third positive lead 243a and the third negative lead 243b overlap along the first direction so that the projections of the third positive lead 243a and the third negative lead 243b on the first reference layer 210 overlap; the fourth positive lead 244a and the fourth negative lead 244b overlap along the first direction so that the projections of the fourth positive lead 244a and the fourth negative lead 244b on the first reference layer 210 overlap.

[0107] In other words, the third positive lead 243a and the third negative lead 243b are aligned along the thickness direction Z of the circuit board 200, which reduces the spacing between the third positive lead 243a and the third negative lead 243b, so as to facilitate interlayer coupling between the third positive lead 243a and the third negative lead 243b.

[0108] The fourth positive lead 244a and the fourth negative lead 244b are aligned along the thickness direction Z of the circuit board 200, thereby reducing the spacing between the fourth positive lead 244a and the fourth negative lead 244b to facilitate interlayer coupling between them.

[0109] Please continue reading Figure 14 and Figure 15 As shown, the third positive lead 243a and the fourth positive lead 244a are staggered along the first direction so that their projections on the first reference layer 210 are staggered; the third negative lead 243b and the fourth negative lead 244b are staggered along their extension direction so that their projections on the first reference layer 210 are staggered.

[0110] The projections of the third positive lead 243a and the fourth positive lead 244a on the first reference layer 210 (or the second reference layer 220) along the thickness direction Z of the circuit board 200 are staggered along their extension direction. That is, the third positive lead 243a and the fourth positive lead 244a correspond to different loop regions 211 on the first reference layer 210 (or the second reference layer 220) in the thickness direction Z.

[0111] The projections of the third negative lead 243b and the fourth negative lead 244b on the first reference layer 210 (or the second reference layer 220) along the thickness direction Z of the circuit board 200 are staggered along their extension direction. That is, the third negative lead 243b and the fourth negative lead 244b correspond to different loop regions 211 on the first reference layer 210 (or the second reference layer 220) in the thickness direction Z.

[0112] Since the projections of the third positive lead 243a and the third negative lead 243b on the first reference layer 210 overlap, and the projections of the fourth positive lead 244a and the fourth negative lead 244b on the first reference layer 210 overlap, that is, the projections of the third lead unit 243 and the fourth lead unit 244 on the first reference layer 210 (or the second reference layer 220) along the thickness direction Z of the circuit board 200 are staggered along their extension direction, the signals transmitted in the third lead unit 243 and the fourth lead unit 244 can form a complete circuit with the loop region 211 on the first reference layer 210 (or the second reference layer 220).

[0113] Therefore, compared to related technology two, which places the receiving differential pair lead 241n on one lead layer and the transmitting differential pair lead 242n on another lead layer, requiring the addition of a reference layer 250n between the receiving differential pair lead 241n and the transmitting differential pair lead 242n to form complete signal loops with the reference layer 250n respectively, this approach is more efficient. Figures 13 to 15 In the illustrated embodiment, by setting the positive and negative leads in the same lead unit 240 in different lead layers 230 for interlayer coupling, and by setting the projections of different lead units 240 on the first reference layer 210 (or the second reference layer 220) along the thickness direction Z of the circuit board 200 to be staggered along its extension direction, the signals transmitted in different lead units 240 can all form a complete circuit with the loop region 211 on the first reference layer 210 (or the second reference layer 220). As a result, the number of reference layers in the circuit board 200 can be reduced, thereby reducing the cost of the circuit board 200.

[0114] The following describes the specific connection method between the third lead unit 243 and the fourth lead unit 244 and the pin 320 in the high-density component 300 when the lead unit 240 is a differential pair lead.

[0115] Please continue reading Figure 13 and Figure 14 As shown, the circuit board 200 includes a third via unit 270 and a fourth via unit 280. The third via unit 270 includes a third positive via 271 and a third negative via 272, and the fourth via unit 280 includes a fourth positive via 281 and a fourth negative via 282. The third positive via 271 is electrically connected to the third positive lead 243a, and the third negative via 272 is electrically connected to the third negative lead 243b. The fourth positive via 281 is electrically connected to the fourth positive lead 244a, and the fourth negative via 282 is electrically connected to the fourth negative lead 244b. The third positive via 271, the third negative via 272, the fourth positive via 281, and the fourth negative via 282 are all used to connect to the pins 320 on the high-density component 300.

[0116] Please continue reading Figure 14 As shown, the circuit board 200 includes a first region 200a and a second region 200b, a plurality of third via units 270 are located in the first region 200a, and a plurality of fourth via units 280 are located in the second region 200b.

[0117] Specifically, the circuit board 200 is divided into a first region 200a and a second region 200b by the surface formed by the length direction X and the width direction Y of the circuit board 200. The third via unit 270 and the fourth via unit 280 are respectively disposed in the first region 200a and the second region 200b. The third via unit 270 and the fourth via unit 280 can be spatially separated to facilitate wiring in the circuit board 200.

[0118] The third positive via 271 is disposed along the thickness direction Z of the circuit board 200 between the third lead layer 233 and the upper surface of the circuit board 200. One end of the third positive via 271 is connected to the pin 320 in the high-density component 300, and the other end of the third positive via 271 is connected to the third positive lead 243a. Thus, the pin 320 in the high-density component 300 is connected to the third positive lead 243a one by one through the third positive via 271.

[0119] The third negative via 272 is disposed along the thickness direction Z of the circuit board 200 between the fourth lead layer 234 and the upper surface of the circuit board 200. One end of the third negative via 272 is connected to the pin 320 in the high-density component 300, and the other end of the third negative via 272 is connected to the third negative lead 243b. Thus, the pin 320 in the high-density component 300 is connected to the third negative lead 243b one by one through the third negative via 272.

[0120] The fourth positive via 281 is disposed along the thickness direction Z of the circuit board 200 between the third lead layer 233 and the upper surface of the circuit board 200. One end of the fourth positive via 281 is connected to the pin 320 in the high-density component 300, and the other end of the fourth positive via 281 is connected to the fourth positive lead 244a. Thus, the pin 320 in the high-density component 300 is connected to the fourth positive lead 244a one by one through the fourth positive via 281.

[0121] The fourth negative via 282 is disposed along the thickness direction Z of the circuit board 200 between the fourth lead layer 234 and the upper surface of the circuit board 200. One end of the fourth negative via 282 is connected to the pin 320 in the high-density component 300, and the other end of the fourth negative via 282 is connected to the fourth negative lead 244b. Thus, the pin 320 in the high-density component 300 is connected to the fourth negative lead 244b one by one through the fourth negative via 282.

[0122] Please continue reading Figure 9 , Figure 12 and Figure 15 As shown, the circuit board 200 also includes a dielectric layer 290, which is disposed between each pair of the first reference layer 210, the second reference layer 220, and the lead layer 230. The dielectric layer 290 is typically made of resin material and serves as insulation and support between the reference layers and the lead layer 230.

[0123] In the description of the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, an indirect connection through an intermediate medium, or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances.

[0124] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0125] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of this application, and are not intended to limit them. Although the embodiments of this application have been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A circuit board, characterized in that, The circuit board includes a first reference layer and a second reference layer disposed opposite to each other along the thickness direction of the circuit board, with at least two lead layers between the first reference layer and the second reference layer, and the circuit board also includes a plurality of lead units, wherein the leads in the lead units are located on different lead layers; The leads in the lead unit extend along the length of the circuit board. The leads in any lead unit on the lead layer are staggered from the leads in the lead units on the other lead layers along the width of the circuit board, so that the projections of the leads on the first reference layer are staggered. The first reference layer and the second reference layer have multiple loop regions, and each lead corresponds to a different loop region along the thickness direction of the circuit board, so that the signal transmitted in each lead forms a complete loop with its corresponding loop region.

2. The circuit board according to claim 1, characterized in that, The lead layer includes a first lead layer and a second lead layer, wherein the first lead layer and the second lead layer are located between the first reference layer and the second reference layer along the thickness direction of the circuit board; The lead unit includes a plurality of first lead units and a plurality of second lead units. The first lead unit includes a first lead located on the first lead layer. The second lead unit includes a second lead located on the second lead layer. Both the first lead and the second lead extend along the length direction of the circuit board, and the first lead and the second lead are staggered along the width direction of the circuit board so that the projections of the first lead and the second lead on the first reference layer are staggered.

3. The circuit board according to claim 2, characterized in that, The circuit board includes a first via unit and a second via unit. The first via unit is electrically connected to the first lead, and the second via unit is electrically connected to the second lead. Both the first via unit and the second via unit are used to connect to the pins on high-density components.

4. The circuit board according to claim 1, characterized in that, The lead layer includes a third lead layer and a fourth lead layer, which are located between the first reference layer and the second reference layer along the thickness direction of the circuit board. The lead unit includes a plurality of third lead units and a plurality of fourth lead units. The third lead unit includes a third positive lead and a third negative lead. The fourth lead unit includes a fourth positive lead and a fourth negative lead. The third positive lead and the fourth positive lead are located on the third lead layer. The third negative lead and the fourth negative lead are located on the fourth lead layer. The third positive lead, the third negative lead, the fourth positive lead, and the fourth negative lead all extend along the length of the circuit board.

5. The circuit board according to claim 4, characterized in that, The third positive lead and the third negative lead overlap along the width direction of the circuit board so that the projections of the third positive lead and the third negative lead on the first reference layer overlap; the fourth positive lead and the fourth negative lead overlap along the width direction of the circuit board so that the projections of the fourth positive lead and the fourth negative lead on the first reference layer overlap.

6. The circuit board according to claim 5, characterized in that, The third positive lead and the fourth positive lead are staggered along the width direction of the circuit board so that the projections of the third positive lead and the fourth positive lead on the first reference layer are staggered. The third negative lead and the fourth negative lead are offset along the width direction of the circuit board so that their projections on the first reference layer are offset.

7. The circuit board according to claim 6, characterized in that, The circuit board includes a third via unit and a fourth via unit. The third via unit includes a third positive via and a third negative via. The fourth via unit includes a fourth positive via and a fourth negative via. The third positive via is electrically connected to the third positive lead, and the third negative via is electrically connected to the third negative lead; the fourth positive via is electrically connected to the fourth positive lead, and the fourth negative via is electrically connected to the fourth negative lead; The third positive via, the third negative via, the fourth positive via, and the fourth negative via are all used to connect to the pins on high-density components.

8. The circuit board according to claim 7, characterized in that, The circuit board includes a first region and a second region, with a plurality of third via units located in the first region and a plurality of fourth via units located in the second region.

9. The circuit board according to any one of claims 1 to 8, characterized in that, The circuit board also includes an insulating layer, with the insulating layer disposed between each pair of the first reference layer, the second reference layer, and the lead layer.

10. An electronic device, characterized in that, The device includes an electronic device body and a circuit board as described in any one of claims 1 to 9 located within the electronic device body, wherein the circuit board is provided with high-density components and the high-density components are electrically connected to the circuit board.

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