A method and device for simulating SWD debugging port using a universal SPI interface

Abstract

The invention discloses a method and device for simulating a SWD debugging port of a universal SPI interface, comprising: controlling a burner to start working, connecting a target chip based on SWDIO and SWCLK through an LPSPI peripheral combined with a level conversion chip; selecting binary firmware and reading information of a memory; detecting a key state to determine whether to program the target chip; if so, transmitting the data to the LPSPI peripheral to simulate the SWD protocol and transmitting the data to the target chip; detecting whether the programming of the target chip is completed; if so, ending the process; the invention simulates the SWD timing by combining the LPSPI peripheral with the level conversion chip, reduces the frame interval time of data transmission and reception, thereby speeding up data transmission and accelerating the overall debugging speed.

Description

Technical Field

[0001] The present invention relates to the technical field of debugging, and in particular to a method and a device for simulating a SWD debugging port with a universal SPI interface. Background Art

[0002] Serial Wire Debug (SWD) is a two-wire protocol for accessing the ARM debug interface. It is part of the ARM debug interface specification and is an alternative to JTAG. The physical layer of SWD consists of two wires, one data line (SWDIO) and one clock line (SWCLK). In SWD terminology, the host refers to the system that controls the debugger, and the target is the system being debugged, which is the ARM chip. SWCLK is a clock signal that is always driven by the host. Both parties will drive the SWDIO line to send data. A high level on SWDIO represents a logic "1" and a low level represents a logic "0". The protocol specifies when each party will drive the SWDIO line. Three different phases are specified. Each transaction starts with the host sending a request, and the target answers with the correct signal. In the data phase, who controls in the data phase depends on the type of request issued by the host. If it is the host that issues a write request, the host will drive SWDIO. In a read request, the target will drive the line to transfer data from the target to the host. In all phases, data is transmitted LSB (least significant bit) first. The target will sample and place the data on the line on the rising edge of the clock. It can communicate directly with the serial wire debug port (SW-DP), which in turn can access one or more access ports, which can access other parts of the system (AHB-AP). In other words, the AHB-AP can access the internal memory map of the core. Since the internal flash, SRAM, debug components and peripherals are all memory mapped, this AP can control the entire device, including programming the target flash.

[0003] The existing technology generally uses GPIO flip level to simulate SWD timing, but the timing speed of GPIO flip level simulation is slow and cannot fully utilize the SWD bandwidth. After sending the request, the GPIO needs to be switched to input mode for data sampling. When the GPIO is switched to input mode to read the timing response, the lower the frequency, the longer the cycle for reading one bit, which is easily affected by interference, thereby causing debugging errors. Summary of the invention

[0004] The present invention provides a method and device for simulating a SWD debugging port through a universal SPI interface, so as to solve the problems of slow speed and instability caused by the existing GPIO simulating SWD timing.

[0005] In a first aspect, the present invention provides a method for simulating a SWD debug port with a universal SPI interface, the method comprising the following steps:

[0006] Control the programmer to start working, connect the target chip based on SWDIO and SWCLK through the LPSPI peripheral combined with the level conversion chip;

[0007] Select the binary firmware and read the memory information;

[0008] Detect the button status to determine whether to program the target chip. If so, transmit the data to the LPSPI peripheral to simulate the SWD protocol and transmit the data to the target chip.

[0009] Check whether the programming of the target chip is completed. If so, end the process.

[0010] Furthermore, after detecting the button status and determining whether to program the target chip, the method further includes:

[0011] If not, reselect the binary firmware and read the information in the memory;

[0012] After the detection of whether the programming of the target chip is completed, the method further includes:

[0013] If not, reselect the binary firmware and read the information in the memory.

[0014] Further, the control burner starts working, connects the target chip based on SWDIO and SWCLK through the LPSPI peripheral combined with the level conversion chip, including:

[0015] Connect the MOSI and MISO of the LPSPI peripheral of the programmer to the level conversion chip to form the SWDIO line output of the SWD protocol;

[0016] Connect the level conversion chip through the SCK of the LPSPI peripheral to form the SWCLK line output of the SWD protocol;

[0017] Control TVCC to pull SWDIO and SWCLK to the logic high level state;

[0018] It is detected that SWDIO and SWCLK are connected to the target chip and enter the working stage.

[0019] Further, the control burner starts working, connects the target chip based on SWDIO and SWCLK through the LPSPI peripheral combined with the level conversion chip, including:

[0020] Send the connection sequence of the set clock cycle through the SCK of the LPSPI peripheral of the programmer, and send the line reset sequence corresponding to the set clock cycle through the data output of the SWDIO of the LPSPI;

[0021] Control the LPSPI peripheral to send two consecutive clock intervals and convert the JTAG protocol of the debug port to the SWD protocol;

[0022] Control the LPSPI peripheral to continue sending the line reset sequence, switch the SWD protocol state, and enter the request phase.

[0023] Further, the control burner starts working, connects the target chip based on SWDIO and SWCLK through the LPSPI peripheral combined with the level conversion chip, including:

[0024] Control the LPSPI peripheral of the programmer to send a request packet to the target chip and receive the response packet ACK from the target chip;

[0025] Control the MOSI of the LPSPI peripheral to shut down, and MISO to receive the response signal;

[0026] When it detects that MISO has received the correct response signal, the programmer responds;

[0027] If it detects that MISO has received the expected response signal, the writer will retry the connection after the set time.

[0028] If it detects that MISO receives an erroneous response signal, a sticky error bit is generated in the CTRL / STAT register, and no request is responded to. The programmer is then controlled to perform an initialization sequence to re-enter the start phase.

[0029] Further, the transmission to the LPSPI peripheral simulates the SWD protocol and transmits the data to the target chip, including:

[0030] Transmitted to the LPSPI peripheral to simulate the SWD protocol and enter the data stage;

[0031] The data phase consists of n data bits and m parity bits. The parity bit is calculated based on all n data bits. If the number of 1s in the data bits is odd, the parity bit should be 1, otherwise it should be 0.

[0032] After completing the data phase, the programmer continues to clock the interface for at least t cycles to allow the transaction to pass through the SW-DP clock, inserting idle clock cycles through the SCK of the LPSPI peripheral, and outputting a low logic level signal at MOSI during the idle clock cycle.

[0033] Further, the selecting of the binary firmware and reading the information of the memory includes:

[0034] By reading the binary file firmware of eMMC, simulating it into SWD protocol through LPSPI peripheral combined with level conversion chip, the binary firmware is written into the target chip to program the target chip.

[0035] Furthermore, it also includes:

[0036] Control the programmer to display the UI effect on the screen through the LCD interface;

[0037] Map the eMMC to a USB disk through the USB interface for operation.

[0038] In a second aspect, the present invention also provides a device for simulating a SWD debug port with a universal SPI interface, comprising: a burner, a target chip, a SWD transmission interface device, a human-computer interaction device, a memory and a power module, wherein the human-computer interaction device comprises a button; the burner is connected to the target chip via SWDIO and SWCLK, and the power module is used to provide power.

[0039] The burner is used to select binary firmware and read information from the memory; detect the state of the button to determine whether to program the target chip, and if so, transmit it to the LPSPI peripheral to simulate the SWD protocol and transmit the data to the target chip; the burner is also used to detect whether the programming of the target chip is completed, and if so, end the process.

[0040] Further, the SWD transmission interface device includes a level conversion chip and an LPSPI peripheral;

[0041] The MOSI and MISO of the LPSPI peripheral of the programmer are respectively connected to the level conversion chip to form the SWDIO line output of the SWD protocol; the SCK of the LPSPI peripheral is connected to the level conversion chip to form the SWCLK line output of the SWD protocol; the programmer controls TVCC to pull SWDIO and SWCLK to a logic high level state; the programmer detects that SWDIO and SWCLK are connected to the target chip and enters the working stage.

[0042] The present invention controls a burner to start working, connects a target chip based on SWDIO and SWCLK through an LPSPI peripheral combined with a level conversion chip; selects binary firmware and reads information of a memory; detects a key state to determine whether to program the target chip; if so, transmits the data to the LPSPI peripheral to simulate the SWD protocol and transmits the data to the target chip; detects whether programming of the target chip is completed; if so, ends the process; the present invention simulates the SWD timing by combining the LPSPI peripheral with the level conversion chip, reduces the frame interval time of data transmission and reception, thereby speeding up data transmission and accelerating the overall debugging speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a flow chart of a method for simulating a SWD debugging port through a general SPI interface provided by the present invention;

[0044] Figure 2 It is a structural schematic diagram of a device for simulating a SWD debugging port with a universal SPI interface provided by the present invention;

[0045] Figure 3 This is the circuit diagram of the LPSPI peripheral emulating SWD;

[0046] Figure 4 This is the timing diagram of switching the SWD protocol at the beginning stage;

[0047] Figure 5 This is a diagram showing the meaning of each logic level bit in the 8-bit request packet in the request phase of SWD;

[0048] Figure 6 It is a timing diagram in the data phase;

[0049] Figure 7 This is a circuit diagram for controlling the level output;

[0050] Figure 8 It is the circuit diagram of the memory;

[0051] Fig. 9 This is the circuit diagram of the LCD interface;

[0052] Fig.10 This is the circuit diagram of the USB interface;

[0053] Fig.11 It is a structural schematic diagram of a computer device provided by the present invention. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical scheme and advantages of the present application clearer, the specific embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. It is understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for the convenience of description, only the part related to the present application but not all the contents are shown in the accompanying drawings. Before discussing the exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow chart describes each operation (or step) as a sequential process, many of the operations therein can be implemented in parallel, concurrently or simultaneously. In addition, the order of each operation can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the accompanying drawings. The process can correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.

[0055] The present invention solves the problems of slow speed and instability caused by the existing GPIO simulation SWD timing, and establishes a set of universal SPI interface simulation SWD debugging port method.

[0056] The method for simulating a SWD debug port with a universal SPI interface provided in the embodiment can be performed by a device for simulating a SWD debug port with a universal SPI interface, which can be implemented by software and / or hardware and integrated in a device for simulating a SWD debug port with a universal SPI interface. The device for simulating a SWD debug port with a universal SPI interface can be a computer or other device.

[0057] Figure 1 This is a flowchart of a method for simulating a SWD debugging port using a universal SPI interface provided by the present invention. Figure 1 , the method comprises the following steps:

[0058] Step 110, control the programmer to start working, connect the target chip based on SWDIO and SWCLK through the LPSPI peripheral combined with the level conversion chip.

[0059] Specifically, the MOSI and MISO of the LPSPI peripheral of the burner are respectively connected to the level conversion chip to form the SWDIO line output of the SWD protocol; the SCK of the LPSPI peripheral is connected to the level conversion chip to form the SWCLK line output of the SWD protocol; TVCC is controlled to pull SWDIO and SWCLK to a logic high level state; it is detected that SWDIO and SWCLK are connected to the target chip and enter the working stage.

[0060] For example, please refer to Figure 2 and Figure 3 , MOSI of the LPSPI peripheral is the output terminal from the host to the target chip, and MISO is the input terminal from the target chip to the host. MOSI is connected to the A-end input of the level conversion chip U24, and MISO is connected to the B-port output of the level conversion chip U25 to form the SWDIO line output in the SWD protocol. The 5th pin DIR of U24 is controlled to control the shutdown of the MOSI output. U25 is specifically used to receive the response data output by the target to the host.

[0061] The SCK of the LPSPI peripheral is input through the A terminal of the level conversion chip U26, and output as SWCLK in the SWD protocol at the B port. The 6th pin of the level conversion chip U26R matches the voltage value of the compatible target through the TVCC voltage, so as to be compatible with the target level logic signal.

[0062] In the initial stage, SWDIO and SWCLK will be pulled up to the logic high state by TVCC, and when connected to the target SWDIO, SWCLK, it can proceed to the start stage.

[0063] Optionally, the model of the programmer is IMXRT1064, the model of the level conversion chip U24 is SN74VC1T45DCKR, the model of the level conversion chip U25 is SN74VC1T45DCKR, and the model of the level conversion chip U26 is SN74VC1T45DCKR.

[0064] In some embodiments, a connection sequence with a set clock cycle is sent through the SCK of the LPSPI peripheral of the burner, and a line reset sequence corresponding to the set clock cycle is sent through the data output of the SWDIO of the LPSPI; the LPSPI peripheral is controlled to send continuous clock intervals twice, and the JTAG protocol of the debug port is converted to the SWD protocol; the LPSPI peripheral is controlled to continue sending the line reset sequence, switch the SWD protocol state, and enter the request stage.

[0065] Please refer to Figure 4 , which is the timing diagram for switching the SWD protocol at the beginning stage. At the beginning stage, a connection sequence of 50 clock cycles can be sent through the SCK of the LPSPI peripheral, and this sequence is also used as a line reset sequence that requires sending 50 1s on the SWDIO data output. Then the send selection sequence is defined as 0xE79E. LPSPI sends it in two times without inserting an idle clock interval in between, converting the JTAG protocol of the debug port to the SWD protocol, and then sending a line reset sequence to switch to the SWD protocol state, followed by the request stage.

[0066] In some embodiments, the LPSPI peripheral of the programmer is controlled to send a request packet to the target chip and receive a response packet ACK from the target chip; MOSI of the LPSPI peripheral is controlled to be turned off, and MISO receives a response signal; when it is detected that MISO receives a correct response signal, the programmer responds; when it is detected that MISO receives a waiting response signal, the programmer retries the connection after a set time; when it is detected that MISO receives an incorrect response signal, a sticky error bit is generated in the CTRL / STAT register, and no request is responded to, the programmer is controlled to perform an initialization sequence to re-enter the start stage.

[0067] For example, Figure 5It is the meaning of each logic level bit in the 8-bit request packet in the request phase status of SWD. The first bit is always 1. The next bit specifies whether the transaction is a DP (debug port) or AP (access port) transaction. If this bit is zero, the transaction is a DP access. Bit 2 is the read-write bit. If this bit is 1, the transaction is a read access (from the target to the host). Bits 3 and 4 are address bits A2 and A3. These bits specify which of the four registers is selected for the transaction. Bit 5 is a parity bit. The target needs to use the parity bit to verify the integrity of the request. If the number of 1s is even, the parity bit should be zero. Bit 6 is the stop bit. This bit is always zero. The 7th bit is the last bit and is always 1.

[0068] After sending the 8-bit request packet, the target will respond with an ACK packet. At this time, it is necessary to control the 5th pin of the level conversion chip U24, turn off the output state of LPSPI's MOSI, and let the level conversion chip U25 transmit the response signal to MISO. MISO receives the correct response, and the data phase can begin. If a response other than the correct one is received, if it is a waiting response, the host must retry the operation later. If the target responds to an incorrect response, there will be a sticky error bit in the CTRL / STAT register. Before using any AP command, it must clear the sticky error bit because the target will respond to an error as long as a sticky error bit is set. If the target sees a protocol error, it will immediately stop driving the line, that is, it will not respond to any request. If the host sees that the target has no response, it must perform the initialization sequence again. Then return to the beginning stage.

[0069] Step 120: Select binary firmware and read information from the memory.

[0070] Specifically, by reading the binary file firmware of the eMMC, simulating the SWD protocol through the LPSPI peripheral combined with the level conversion chip, the binary firmware is written into the target chip to program the target chip.

[0071] For example, please refer to Figure 8 , is an eMMC memory, model KLM8G1GETF-B041, capacity 8GB. It is used to store various binary file firmware of the target chip. The pins SD2_DATA0 to SD2_DATA7 and the pins SD2_CMD, SD2_CLK, and SD2_nRST are used on the peripheral pins of the mmc connected to IMXRT1064. IMXRT1064 can read and erase the eMMC initialization. IMXRT1064 reads the binary file firmware of the eMMC, and writes the binary firmware to the target to program the target through the LPSPI peripheral and the level conversion chip to simulate the SWD protocol.

[0072] Step 130, detect the button status and determine whether to program the target chip. If so, transmit the data to the LPSPI peripheral to simulate the SWD protocol and transmit the data to the target chip.

[0073] If not, reselect the binary firmware and read the information in the memory.

[0074] Specifically, the data is transmitted to the LPSPI peripheral to simulate the SWD protocol and enter the data phase; the data phase consists of n data bits and m 1 parity bits. The parity bit is calculated based on all n data bits. If the number of 1s in the data bits is odd, the parity bit should be 1, otherwise it is 0; after completing the data phase, the programmer continues the clock interface for at least t cycles to allow the transaction to pass through the SW-DP clock, insert an idle clock cycle through the SCK of the LPSPI peripheral, and output a low logic level signal on MOSI during the idle clock cycle.

[0075] For example, Figure 6 This is the timing diagram in the data phase. The data phase consists of 32 data bits and 1 parity bit. The parity bit is calculated based on all 32 data bits. If the number of 1s in the data word is odd, the parity bit should be 1, otherwise it is 0. After the data phase, the host must continue the clock interface for at least 8 cycles to ensure that the transaction passes the SW-DP clock. The idle clock cycle can be inserted through the SCK of the LPSPI peripheral. MOSI outputs a low logic level signal in the idle clock cycle. Avoid interruption in the middle.

[0076] Please refer to Figure 7 The hardware schematic diagram for controlling the level output is used to provide a reference level of 1.8V to 5V for the level conversion chip. The output voltage range of the power chip is 1.8V to 3.3V. The three ports of VSEL1 / 2 / 3 of the power chip are connected to the GPIO pins on the burner. Their connection status can determine the output state of the voltage of the power chip. The truth table of their connection status is on the right side of the schematic diagram. The SW and VOUT output LC filter circuits of the power chip are connected to TVCC-O through MOS tubes, but this can only output 1.8V to 3.3V. The following VSEL_4 and VSEL_EN are connected to the GPIO pins of the burner. VSEL_EN is connected to the emitter. When it is low, the B1 pin of the power chip is disabled and no longer outputs voltage. When VSEL_4 is 1, the transistor Q2 is turned on, and Q9 and Q11 can be turned on when the turn-on voltage is met, providing a 5V reference voltage to the level conversion chip. In summary, a reference level output of 1.8V to 5V can be provided to the level conversion chip.

[0077] Optionally, the model of the power chip is RT5707WSC and the model of the MOS tube is SSM3J328R-LF.

[0078] Step 140: Check whether the programming of the target chip is completed. If so, end the process.

[0079] If not, reselect the binary firmware and read the information in the memory.

[0080] Furthermore, it also includes: controlling the burner to display the interface UI effect on the screen through the LCD interface; mapping the eMMC to a USB disk through the USB interface for operation.

[0081] For example, please refer to Fig. 9 , is the hardware schematic diagram of the LCD interface. The LCDIF_D[15:0] bus is mainly connected to the LCDIF peripheral of the programmer. IMXRT1064 displays the UI effect on the screen through the LCD interface to realize the human-computer interaction function. The LCD_BL pin gives a low level through the GPIO pin of IMXRT1064 to control the transistor Q1 to turn on and light up the screen backlight.

[0082] For example, please refer to Fig.10 , is the USB interface schematic diagram, OTG1_DN and OTG1_DP are connected to USB_OTG1_DN and USB_OTG1_DP of the burner, filtered by L3, and then connected to the TYPE-C socket through U7. U7 is a transient suppression diode to prevent USB overvoltage from damaging the chip. It is mainly connected to the USB peripherals of the burner. Through the USB peripherals, the eMMC can be mapped to a U disk for user operation.

[0083] As mentioned above, the LPSPI peripheral of the IMXRT1064 burner of the present invention is a low-power serial peripheral interface, which can be used as a master line or a slave line. The CPU overhead used is very small. The SCK frequency and the delay between the SCK system and the SCK edge can be flexibly configured. The LSPI rate is faster than the GPIO flip rate and has higher stability. The transmission and reception of LSPI are all completed through FIFO, which can reduce the waiting time for reading the response during SWD. The LPSPI is combined with a level conversion chip to be compatible with the level logic signals of different target chips to simulate SWD to achieve faster programming and debugging functions.

[0084] Based on the above embodiments, Figure 2 This is a schematic diagram of the structure of a device for simulating a SWD debugging port with a universal SPI interface provided by the present invention. Figure 2The device for simulating a SWD debug port with a universal SPI interface provided in this embodiment includes: a burner, a target chip, a SWD transmission interface device, a human-computer interaction device, a memory and a power module, wherein the human-computer interaction device includes a button; the SWD transmission interface device includes a level conversion chip and an LPSPI peripheral, and the power module is used to provide power.

[0085] Among them, the burner is combined with a level conversion chip through an LPSPI peripheral and connected to a target chip based on SWDIO and SWCLK; the burner is used to select binary firmware and read information from a memory, detect the state of the button, and determine whether to program the target chip. If so, the data is transmitted to the LPSPI peripheral to simulate the SWD protocol and transmit the data to the target chip; the burner is also used to detect whether programming of the target chip is completed; if so, the process ends.

[0086] Furthermore, it also includes a data transmission device, which includes a USB interface. The human-computer interaction device also includes an LCD interface. The burner displays the interface UI effect on the screen through the LCD interface; the burner maps the eMMC to a U disk through the USB interface for operation.

[0087] In the above, the control burner starts working, connects the target chip based on SWDIO and SWCLK through the LPSPI peripheral combined with the level conversion chip; selects the binary firmware and reads the information of the memory; detects the key state to determine whether to program the target chip; if so, transmits it to the LPSPI peripheral to simulate the SWD protocol and transmits the data to the target chip; detects whether the programming of the target chip is completed; if so, ends the process; the present invention simulates the SWD timing by combining the LPSPI peripheral with the level conversion chip, reduces the frame interval time of data transmission and reception, thereby speeding up data transmission and accelerating the overall debugging speed.

[0088] The device for simulating a SWD debug port with a universal SPI interface provided by the present invention can be used to execute the method for simulating a SWD debug port with a universal SPI interface provided by the above embodiment, and has corresponding functions and beneficial effects.

[0089] The present invention also provides a computer device, which can integrate the device for simulating a SWD debugging port with a universal SPI interface provided by the present invention. Fig.11 Schematic diagram of the structure of a computer device provided by the present invention. Fig.11The computer device includes: an input device 43, an output device 44, a memory 42 and one or more processors 41; the memory 42 is used to store one or more programs; when the one or more programs are executed by the one or more processors 41, the one or more processors 41 implement the universal SPI interface simulating SWD debug port method provided in the above embodiment. The input device 43, the output device 44, the memory 42 and the processor 41 can be connected by a bus or other means. Fig.11 The example of connecting through bus is taken in the following.

[0090] The processor 41 executes various functional applications and data processing of the device by running the software programs, instructions and modules stored in the memory 41, that is, implements the above-mentioned general SPI interface simulating SWD debug port method.

[0091] The computer device provided above can be used to execute the universal SPI interface simulating SWD debug port method provided in the above embodiment, and has corresponding functions and beneficial effects.

[0092] The present invention also provides a storage medium containing computer executable instructions. When the computer executable instructions are executed by a computer processor, they are used to execute a method for simulating a SWD debug port using a universal SPI interface. The method comprises: controlling a burner to start working, connecting a target chip based on SWDIO and SWCLK through an LPSPI peripheral combined with a level conversion chip; selecting binary firmware and reading information from a memory; detecting a key state to determine whether to program the target chip; if so, transmitting the data to the LPSPI peripheral to simulate the SWD protocol and transmitting the data to the target chip; detecting whether programming of the target chip is completed; if so, ending the process.

[0093] Storage medium - any of various types of memory devices or storage devices. The term "storage medium" is intended to include: installation media, such as CD-ROM, floppy disk or tape devices; computer device memory or random access memory, such as DRAM, DDRRAM, SRAM, EDORAM, Rambus RAM, etc.; non-volatile memory, such as flash memory, magnetic media (such as hard disk or optical storage); registers or other similar types of memory elements, etc. The storage medium may also include other types of memory or combinations thereof. In addition, the storage medium may be located in a first computer device in which the program is executed, or may be located in a different second computer device, which is connected to the first computer device via a network (such as the Internet). The second computer device can provide program instructions to the first computer for execution. The term "storage medium" may include two or more storage media that may reside in different locations (for example, in different computer devices connected via a network). The storage medium may store program instructions (for example, embodied as a computer program) that can be executed by one or more processors.

[0094] Of course, the storage medium containing computer executable instructions provided by the present invention is not limited to the general SPI interface simulating SWD debug port method as described above, and can also execute related operations in the general SPI interface simulating SWD debug port method provided in any embodiment of the present application.

[0095] The apparatus, storage medium and computer device for simulating the SWD debug port of the universal SPI interface provided in the above embodiments can execute the method for simulating the SWD debug port of the universal SPI interface provided in any embodiment of the present application. For technical details not described in detail in the above embodiments, please refer to the method for simulating the SWD debug port of the universal SPI interface provided in any embodiment of the present application.

[0096] The above are only preferred embodiments of the present application and the technical principles used. The present application is not limited to the specific embodiments described herein, and various obvious changes, readjustments and substitutions that can be made by those skilled in the art will not deviate from the scope of protection of the present application. Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the claims.

Claims

1. A method for simulating a SWD debugging port using a general SPI interface, characterized in that: The method comprises the following steps: Control the programmer to start working, connect the target chip based on SWDIO and SWCLK through the LPSPI peripheral combined with the level conversion chip; Select the binary firmware and read the memory information; Detect the button status to determine whether to program the target chip. If so, transmit the data to the LPSPI peripheral to simulate the SWD protocol and transmit the data to the target chip. Check whether the programming of the target chip is completed, if so, end the process; Control the programmer to start working, connect the target chip based on SWDIO and SWCLK through the LPSPI peripheral combined with the level conversion chip, including: Send the connection sequence of the set clock cycle through the SCK of the LPSPI peripheral of the programmer, and send the line reset sequence corresponding to the set clock cycle through the data output of the SWDIO of the LPSPI; Control the LPSPI peripheral to send two consecutive clock intervals and convert the JTAG protocol of the debug port to the SWD protocol; Control the LPSPI peripheral to continue sending the line reset sequence, switch the SWD protocol state, and enter the request phase; Control the programmer to start working, connect the target chip based on SWDIO and SWCLK through the LPSPI peripheral combined with the level conversion chip, and also include: Control the LPSPI peripheral of the programmer to send a request packet to the target chip and receive the response packet ACK from the target chip; Control the MOSI of the LPSPI peripheral to shut down, and MISO to receive the response signal; When it detects that MISO has received the correct response signal, the programmer responds; If it detects that MISO has received the expected response signal, the writer will retry the connection after the set time. If it detects that MISO receives an erroneous response signal, a sticky error bit is generated in the CTRL / STAT register, and no request is responded to. The programmer is then controlled to perform an initialization sequence to re-enter the start phase.

2. The method for simulating a SWD debugging port using a universal SPI interface according to claim 1, wherein: After detecting the button status and determining whether to program the target chip, the method further includes: If not, reselect the binary firmware and read the information of the memory; after the detection of whether the programming of the target chip is completed, it also includes: If not, reselect the binary firmware and read the information in the memory.

3. The method for simulating a SWD debugging port using a universal SPI interface according to claim 1, wherein: The control programmer starts working by combining the LPSPI peripheral with the level conversion chip and connecting the target chip based on SWDIO and SWCLK. First, it includes: Connect the MOSI and MISO of the LPSPI peripheral of the programmer to the level conversion chip to form the SWDIO line output of the SWD protocol; Connect the level conversion chip through the SCK of the LPSPI peripheral to form the SWCLK line output of the SWD protocol; Control TVCC to pull SWDIO and SWCLK to the logic high level state; It is detected that SWDIO and SWCLK are connected to the target chip and enter the working stage.

4. The method for simulating a SWD debugging port using a universal SPI interface according to claim 1, wherein: The transmission to the LPSPI peripheral simulates the SWD protocol and transmits the data to the target chip, including: Transmitted to the LPSPI peripheral to simulate the SWD protocol and enter the data stage; The data phase consists of n data bits and m parity bits. The parity bit is calculated based on all n data bits. If the number of 1s in the data bits is odd, the parity bit should be 1, otherwise it should be 0. After completing the data phase, the programmer continues to clock the interface for at least t cycles to allow the transaction to pass through the SW-DP clock, inserting idle clock cycles through the SCK of the LPSPI peripheral, and outputting a low logic level signal at MOSI during the idle clock cycle.

5. The method for simulating a SWD debugging port using a universal SPI interface according to claim 1, wherein: The step of selecting the binary firmware and reading the information of the memory includes: By reading the binary file firmware of eMMC, simulating it into SWD protocol through LPSPI peripheral combined with level conversion chip, the binary firmware is written into the target chip to program the target chip.

6. The method for simulating a SWD debugging port using a universal SPI interface according to claim 1, wherein: Also includes: Control the programmer to display the UI effect on the screen through the LCD interface; Map the eMMC to a USB disk through the USB interface for operation.

7. A device for simulating a SWD debugging port with a general SPI interface, characterized in that: A method for simulating a SWD debugging port using a universal SPI interface as shown in any one of claims 1 to 6, It includes: a burner, a target chip, a SWD transmission interface device, a human-computer interaction device, a memory and a power module, wherein the human-computer interaction device includes a button; the SWD transmission interface device includes a level conversion chip and an LPSPI peripheral, and the power module is used to provide power; The programmer is connected to the target chip based on SWDIO and SWCLK through the LPSPI peripheral combined with the level conversion chip; The burner is used to select binary firmware and read information from the memory, detect the state of the button, determine whether to program the target chip, and if so, transmit it to the LPSPI peripheral to simulate the SWD protocol and transmit the data to the target chip; The burner is also used to detect whether the programming of the target chip is completed, and if so, the process ends.

8. The device for simulating a SWD debugging port using a universal SPI interface according to claim 7, characterized in that: It also includes a data transmission device, the data transmission device includes a USB interface, and the human-computer interaction device also includes an LCD interface. The burner displays the UI effect on the screen through the LCD interface; the burner maps the eMMC to a USB disk through the USB interface for operation.

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