Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate having a first opening therein, the first opening exposing a portion of the sidewall surface of the substrate; forming a first barrier layer and a second barrier layer located on the surface of the first barrier layer within the first opening; forming a dielectric layer structure on the surface of the substrate; forming a second opening within the dielectric layer structure, the second opening exposing the sidewall surface of the dielectric layer structure, the sidewall surface of the second barrier layer, and a portion of the surface of the first barrier layer; wherein the etching process for forming the second opening has a first ratio between the etching rate of the second barrier layer material and the etching rate of the first barrier layer material, and the loss of the second barrier layer material is greater than that of the first barrier layer material within the same time interval; and the composite barrier layer of the first and second barrier layers has increased lateral and longitudinal losses in high aspect ratio etching compared to a barrier layer consisting only of the first barrier layer, resulting in an increased bottom critical dimension of the etched second opening.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the development of 3D NAND flash memory, the introduction of three-dimensional structures has further increased the etching aspect ratio of these structures, placing higher demands on etching technology. The material of the etching barrier layer has a significant impact on the critical dimensions and morphology of the etched structure.

[0003] However, defects still exist in the etching barrier layer in high aspect ratio etching. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the morphology of the structure after etching.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate having a first opening therein, the first opening exposing a portion of the sidewall surface of the substrate; forming a first barrier layer and a second barrier layer located on the surface of the first barrier layer within the first opening; forming a dielectric layer structure on the surface of the substrate; forming a second opening within the dielectric layer structure, the second opening exposing the sidewall surface of the dielectric layer structure, the sidewall surface of the second barrier layer, and a portion of the surface of the first barrier layer, wherein the etching process for forming the second opening has an etching rate for the second barrier layer material that is proportional to the etching rate for the first barrier layer material.

[0006] Optionally, the method for forming the first barrier layer includes: forming an initial first barrier layer within the first opening; planarizing the initial first barrier layer until the surface of the initial first barrier layer is flush with the substrate; and etching back the initial first barrier layer to form the first barrier layer.

[0007] Optionally, the method for forming the second barrier layer includes: forming an initial second barrier layer on the surface of the first barrier layer; and planarizing the initial second barrier layer until the substrate surface is exposed to form the second barrier layer.

[0008] Optionally, the etching method includes dry etching.

[0009] Optionally, the thickness ratio of the first barrier layer to the second barrier layer is in the range of 3:7 to 7:3.

[0010] Optionally, the material of the first barrier layer includes aluminum oxide; the thickness range of the first barrier layer is: The formation process of the first barrier layer includes physical vapor deposition and chemical vapor deposition; the process parameters of the formation process of the first barrier layer include: the deposition time of the first barrier layer is 25 minutes to 45 minutes, the gas pressure intensity of the first barrier layer is 1 torr to 2 torr, and the deposition temperature of the first barrier layer is 350℃ to 450℃.

[0011] Optionally, the material of the second barrier layer includes silicon oxide; the thickness range of the second barrier layer is: The process for forming the second barrier layer includes HARP; the process parameters for forming the second barrier layer include: a deposition time of 25 to 45 minutes, a deposition pressure of 600 torr, a deposition temperature of 500°C to 600°C, and the gases used for deposition include tetraethoxysilane and ozone, with the tetraethoxysilane flow rate ranging from 1000 sccm to 10000 sccm and the ozone flow rate ranging from 50000 sccm to 10000 sccm.

[0012] Optionally, the first ratio ranges from 10:1 to 20:1.

[0013] Optionally, the method for forming the second opening includes: forming a hard mask layer on the surface of the dielectric layer structure; using the hard mask layer as a mask, etching the dielectric layer structure to form a second opening, wherein the second opening exposes the sidewall surface of the dielectric layer structure, the sidewall surface of the second barrier layer, and a portion of the surface of the first barrier layer.

[0014] Optionally, the dielectric layer structure includes: a stack of a plurality of first dielectric layers and second dielectric layers; the number of the first dielectric layers ranges from 1 to 3 layers; the number of the second dielectric layers ranges from 1 to 3 layers; the materials of the first dielectric layers include: silicon oxide, silicon nitride, silicon oxynitride, and amorphous carbon; the materials of the second dielectric layers include silicon oxide, silicon nitride, silicon oxynitride, and amorphous carbon.

[0015] Optionally, after forming the second opening, the method further includes: forming a channel within the second opening; after forming the channel, removing the first dielectric layer and forming a gate layer between adjacent second dielectric layers; after forming the gate layer, removing the second dielectric layer and performing source / drain doping on the channel exposed by the adjacent gate layers; and after performing source / drain doping, forming a source / drain conductive layer between adjacent gate layers.

[0016] Accordingly, the present invention also provides a semiconductor structure, comprising: a substrate having a first opening, the first opening exposing a portion of the sidewall surface of the substrate; a first barrier layer located within the first opening and a second barrier layer located on the surface of the first barrier layer, the material of the second barrier layer being different from that of the first barrier layer; and a device layer located on the surface of the substrate, the device layer having a second opening, the second opening exposing the sidewall surface of the device layer, the sidewall surface of the second barrier layer, and a portion of the surface of the first barrier layer.

[0017] Optionally, the first barrier layer material includes aluminum oxide; the thickness range of the first barrier layer is:

[0018] Optionally, the second barrier layer material includes silicon oxide; the thickness range of the second barrier layer is:

[0019] Optionally, the thickness ratio of the first barrier layer to the second barrier layer is in the range of 3:7 to 7:3.

[0020] Optionally, it also includes a channel located within the second opening.

[0021] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0022] In the semiconductor structure of the present invention, the material of the second barrier layer is different from that of the first barrier layer. The etching conditions can be adjusted for the second barrier layer and the first barrier layer material so that the loss of the second barrier layer is greater than that of the first barrier layer. As a result, the composite barrier layer of the first barrier layer and the second barrier layer has increased lateral and longitudinal losses in high aspect ratio etching compared to the barrier layer with only the first barrier layer material. This increases the critical bottom dimension of the second opening obtained by etching, solves the problem of incomplete etching of the second opening, and improves the morphology of the second opening.

[0023] In the semiconductor structure formation method of the present invention, a first barrier layer and a second barrier layer located on the surface of the first barrier layer are formed in the first opening. The etching process for forming the second opening has a first ratio between the etching rate of the second barrier layer material and the etching rate of the first barrier layer material. The loss of the second barrier layer is greater than that of the first barrier layer. As a result, the composite barrier layer of the first barrier layer and the second barrier layer has increased lateral and longitudinal losses in high aspect ratio etching compared to a barrier layer with only the first barrier layer material. The bottom critical dimension of the etched second opening is increased, which solves the problem of incomplete etching of the second opening and improves the morphology of the second opening. Attached Figure Description

[0024] Figures 1 to 8 This is a cross-sectional structural diagram illustrating the formation process of the semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0025] As described in the background section, in existing high aspect ratio etching, the etching barrier layer still has defects.

[0026] In one embodiment of a high aspect ratio etch barrier layer, aluminum oxide is used as the barrier layer, resulting in insufficient etching and a smaller critical size of the etched opening.

[0027] To address the aforementioned technical problems, the present invention provides a semiconductor structure and its formation method. A first barrier layer and a second barrier layer are formed within the first opening. The etching process for forming the second opening has a first ratio between the etching rate of the second barrier layer material and the etching rate of the first barrier layer material. The loss of the second barrier layer is greater than that of the first barrier layer. This results in increased lateral and longitudinal losses in high aspect ratio etching of the composite barrier layer (first and second barrier layers) compared to a barrier layer consisting only of the first barrier layer material. The bottom critical dimension of the etched second opening is increased, solving the problem of incomplete etching of the second opening and improving its morphology.

[0028] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0029] Figures 1 to 8 This is a cross-sectional structural diagram illustrating the formation process of the semiconductor structure according to an embodiment of the present invention.

[0030] Please refer to Figure 1 A substrate 100 is provided, the substrate 100 having a first opening 101 that exposes a portion of the sidewall surface of the substrate 100.

[0031] The substrate 100 material includes: silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium.

[0032] The first opening 101 provides a structural basis for the subsequent formation of the first barrier layer 103 and the second barrier layer 105 located on the surface of the first barrier layer 103.

[0033] The size range of the first opening 101 along the direction parallel to the surface of the substrate 100 is 50nm to 150nm.

[0034] The depth range of the first opening 101 is:

[0035] A first barrier layer 103 and a second barrier layer 105 are formed within the first opening 101. Please refer to [reference needed] for details. Figures 2 to 6 .

[0036] Please refer to Figure 2 An initial first barrier layer 102 is formed within the first opening 101.

[0037] The material of the initial first barrier layer 102 includes aluminum oxide.

[0038] The method for forming the initial first barrier layer 102 includes chemical vapor deposition.

[0039] The thickness range of the initial first barrier layer 102 is:

[0040] The process parameters for forming the initial first barrier layer 102 include: the deposition time for the initial first barrier layer 102 is 25 minutes to 45 minutes, the gas pressure intensity for deposition of the initial first barrier layer 102 is 1 torr to 2 torr, and the temperature range for deposition of the initial first barrier layer 102 is 350℃ to 450℃.

[0041] The initial first barrier layer 102 provides a structural basis for the subsequent formation of the first barrier layer 103.

[0042] In the subsequent etching process to form the second opening, the etching rate of the second barrier layer material is in a first ratio to the etching rate of the first barrier layer material, with the first ratio ranging from 10:1 to 20:1. Therefore, the etching rate of the initial first barrier layer 102 is less than the etching rate of the subsequently formed second barrier layer 105. Within the same time frame, the material loss of the second barrier layer 105 is greater than that of the first barrier layer 103. This results in increased lateral and longitudinal losses in high aspect ratio etching for the composite barrier layer of the first barrier layer 103 and the second barrier layer 105 compared to a barrier layer consisting only of the first barrier layer 103. Consequently, the critical bottom dimension of the etched second opening 109 is increased, resolving the problem of incomplete etching of the second opening 109 and improving its morphology.

[0043] Please refer to Figure 3 The initial first barrier layer 102 is planarized until the surface of the initial first barrier layer 102 is flush with the substrate 100.

[0044] The purpose of the planarization process is to make the initial first barrier layer 102 uniform in thickness, so as to provide a structural basis for subsequent etching.

[0045] The planarization methods include mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing (CMP). Specifically, in this embodiment, the planarization method is CMP. Unlike traditional purely mechanical or purely chemical polishing methods, CMP, through the combined action of chemicals and machinery, avoids the surface damage caused by purely mechanical polishing and the drawbacks of purely chemical polishing, such as slow polishing speed, poor surface smoothness, and poor polishing consistency. CMP is widely used for high planarization polishing of various materials at the nanoscale.

[0046] Please refer to Figure 4 The initial first barrier layer 102 is etched back to form the first barrier layer 103.

[0047] The etching method includes: dry etching.

[0048] Specifically, in this embodiment, the material of the first barrier layer 103 includes aluminum oxide; the thickness range of the first barrier layer 103 is:

[0049] In the subsequent etching process to form the second opening, the etching rate of the second barrier layer material is in a first ratio to the etching rate of the first barrier layer material, with the first ratio ranging from 10:1 to 20:1. Therefore, the etching rate of the first barrier layer 103 is less than the etching rate of the second barrier layer 105 formed subsequently. Within the same time frame, the material loss of the second barrier layer 105 is greater than that of the first barrier layer 103. This results in increased lateral and longitudinal losses in high aspect ratio etching compared to a barrier layer consisting only of the first barrier layer 103, leading to an increased bottom critical dimension of the etched second opening 109. This solves the problem of incomplete etching of the second opening 109 and improves its morphology.

[0050] Please refer to Figure 5 An initial second barrier layer 104 is formed on the surface of the first barrier layer 103.

[0051] The material of the initial second barrier layer 104 includes silicon oxide.

[0052] The method for forming the initial second barrier layer 104 includes HARP.

[0053] The thickness range of the initial second barrier layer 104 is:

[0054] The process parameters for forming the initial second barrier layer 104 include: a deposition time of 25 to 45 minutes, a gas pressure of 600 torr, a deposition temperature of 500°C to 600°C, and the gas used for deposition includes tetraethoxysilane and ozone, with the tetraethoxysilane flow rate ranging from 1000 sccm to 10000 sccm and the ozone flow rate ranging from 50000 sccm to 10000 sccm.

[0055] The initial second barrier layer 104 provides a structural basis for the subsequent formation of the second barrier layer 105.

[0056] In the subsequent etching process to form the second opening, the etching rate of the second barrier layer material is in a first ratio to the etching rate of the first barrier layer material, and the range of the first ratio is 10:1 to 20:1. Therefore, the etching rate of the first barrier layer 103 material is less than the etching rate of the initial second barrier layer 104 material. Within the same time frame, the material loss of the initial second barrier layer 104 is greater than the material loss of the first barrier layer 103 material. This results in increased lateral and longitudinal losses in high aspect ratio etching of the composite barrier layer formed subsequently with the first barrier layer 103 and the second barrier layer 105 compared to a barrier layer consisting only of the first barrier layer 103 material. Consequently, the critical bottom dimension of the etched second opening 109 is increased, solving the problem of incomplete etching of the second opening 109 and improving the morphology of the second opening 109.

[0057] Please refer to Figure 6 The initial second barrier layer 104 is planarized until the surface of the substrate 100 is exposed, forming the second barrier layer 105.

[0058] The planarization methods include mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing (CMP). Specifically, in this embodiment, the planarization method is CMP. Unlike traditional purely mechanical or purely chemical polishing methods, CMP, through the combined action of chemicals and machinery, avoids the surface damage caused by purely mechanical polishing and the drawbacks of purely chemical polishing, such as slow polishing speed, poor surface smoothness, and poor polishing consistency. CMP is widely used for high planarization polishing of various materials at the nanoscale.

[0059] The purpose of the planarization process is to make the second barrier layer 105 uniform in thickness and located within the first opening 101.

[0060] Specifically, in this embodiment, the material of the second barrier layer 105 includes silicon oxide; the thickness range of the second barrier layer 105 is:

[0061] Specifically, in this embodiment, the thickness ratio of the first barrier layer 103 to the second barrier layer 105 is in the range of 3:7 to 7:3.

[0062] In the subsequent etching process to form the second opening, the etching rate of the second barrier layer material is in a first ratio to the etching rate of the first barrier layer material, with the first ratio ranging from 10:1 to 20:1. Therefore, the etching rate of the second barrier layer 105 material is greater than that of the first barrier layer 103 material. Within the same time frame, the material loss of the second barrier layer 105 is greater than that of the first barrier layer 103. This results in increased lateral and longitudinal losses in high aspect ratio etching for the composite barrier layer of the first barrier layer 103 and the second barrier layer 105 compared to a barrier layer consisting only of the first barrier layer 103 material. Consequently, the critical bottom dimension of the second opening 109 obtained through subsequent etching is increased, resolving the problem of incomplete etching of the second opening 109 and improving its morphology.

[0063] Please refer to Figure 7 A dielectric layer structure 106 is formed on the surface of the substrate 100.

[0064] Specifically, in this embodiment, the dielectric layer structure 106 includes a stack of a plurality of first dielectric layers 107 and second dielectric layers 108, wherein the first dielectric layers 107 and second dielectric layers 108 are used to form a NAND flash memory.

[0065] In other embodiments, the dielectric layer structure may also be a single layer or multiple layers of other materials.

[0066] Specifically, in this embodiment, the thickness of the dielectric layer structure 106 ranges from 2μm to 10μm; the number of layers of the first dielectric layer 107 ranges from 1 to 3; and the number of layers of the second dielectric layer 108 ranges from 1 to 3.

[0067] The first dielectric layer 107 is made of the following materials: silicon oxide, silicon nitride, silicon oxynitride, and amorphous carbon.

[0068] The second dielectric layer 108 material includes: silicon oxide, silicon nitride, silicon oxynitride, and amorphous carbon.

[0069] The first dielectric layer 107 provides the structural basis for the subsequent formation of the gate layer.

[0070] The second dielectric layer 108 provides a structural basis for the subsequent formation of the source and drain conductive layers.

[0071] Please refer to Figure 8 A second opening 109 is formed in the dielectric layer structure 106. The second opening 109 exposes the sidewall surface of the dielectric layer structure 106, the sidewall surface of the second barrier layer 105, and a portion of the surface of the first barrier layer 103. The etching process that forms the second opening 109 has a first ratio between the etching rate of the second barrier layer 103 material and the etching rate of the first barrier layer 103 material.

[0072] The first ratio ranges from 10:1 to 20:1.

[0073] The method for forming the second opening 109 includes: forming a hard mask layer (not shown) on the surface of the dielectric layer structure 106; using the hard mask layer as a mask, etching the dielectric layer structure 106 to form the second opening 109, wherein the second opening 109 exposes the sidewall surface of the dielectric layer structure 106, the sidewall surface of the second barrier layer 105, and a portion of the surface of the first barrier layer 103.

[0074] The etching methods include wet etching and dry etching.

[0075] The etching process has a first ratio between the etching rate of the second barrier layer 103 material and the etching rate of the first barrier layer 103 material. The range of the first ratio is 10:1 to 20:1. The etching rate of the first barrier layer 103 material is less than the etching rate of the second barrier layer 105 material. In the same time period, the loss of the second barrier layer 105 material is greater than the loss of the first barrier layer 103 material. This results in increased lateral and longitudinal losses in high aspect ratio etching of the composite barrier layer of the first barrier layer 103 and the second barrier layer 105 compared to a barrier layer consisting only of the first barrier layer 103 material. Consequently, the critical bottom dimension of the etched second opening 109 is increased, solving the problem of incomplete etching of the second opening 109 and improving the morphology of the second opening 109.

[0076] After forming the second opening 109, the method further includes: forming a channel (not shown) within the second opening 109; after forming the channel, removing the first dielectric layer 107 and forming a gate layer (not shown) between adjacent second dielectric layers 108; after forming the gate layer, removing the second dielectric layer 108 and performing source / drain doping on the channel exposed by the adjacent gate layers; and after performing source / drain doping, forming a source / drain conductive layer (not shown) between adjacent gate layers.

[0077] Accordingly, embodiments of the present invention also propose a semiconductor structure, please refer to [further details]. Figure 8Includes: a substrate 100 having a first opening 101 (e.g., ... Figure 1 As shown), the first opening 101 exposes a portion of the sidewall surface of the substrate 100; a first barrier layer 103 is located within the first opening 101, and a second barrier layer 105 is located on the surface of the first barrier layer 103, the material of the second barrier layer 105 being different from that of the first barrier layer 103; a device layer 106 is located on the surface of the substrate 100, the device layer having a second opening 109, the second opening 109 exposing the sidewall surface of the device layer 106, the sidewall surface of the second barrier layer 105, and a portion of the surface of the first barrier layer 103.

[0078] The semiconductor structure includes: a substrate 100 having a first opening 101 that exposes a portion of the sidewall surface of the substrate 100.

[0079] The substrate 100 material includes: silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium.

[0080] The size range of the first opening 101 along the direction parallel to the surface of the substrate 100 is 50nm to 150nm.

[0081] The depth range of the first opening 101 is:

[0082] The semiconductor structure includes a first barrier layer 103 located within the first opening 101 and a second barrier layer 105 located on the surface of the first barrier layer 103, wherein the material of the second barrier layer 105 is different from that of the first barrier layer 103.

[0083] The first barrier layer 103 is made of aluminum oxide; the thickness of the first barrier layer 103 is within the range of:

[0084] The second barrier layer 105 is made of silicon oxide; the thickness of the second barrier layer 105 is:

[0085] The thickness ratio of the first barrier layer 103 to the second barrier layer 105 is in the range of 3:7 to 7:3.

[0086] The semiconductor structure includes a device layer 106 located on the surface of the substrate 100, the device layer 106 having a second opening 109, the second opening 109 exposing the sidewall surface of the device layer 106, the sidewall surface of the second barrier layer 105, and a portion of the surface of the first barrier layer 103.

[0087] The thickness of the device layer 106 ranges from 2 μm to 10 μm.

[0088] The semiconductor structure includes a channel (not shown) located within the second opening 109.

[0089] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having a first opening that exposes a portion of the sidewall surface of the substrate; A first barrier layer located within the first opening and a second barrier layer located on the surface of the first barrier layer, wherein the material of the second barrier layer is different from that of the first barrier layer; A device layer located on the surface of the substrate has a second opening formed by etching. The etching rate on the second barrier layer material is greater than the etching rate on the first barrier layer material. The second opening exposes the sidewall surface of the device layer, the sidewall surface of the second barrier layer, and a portion of the surface of the first barrier layer.

2. The semiconductor structure as described in claim 1, characterized in that, The first barrier layer material includes aluminum oxide; the thickness of the first barrier layer ranges from 1000 Å to 3000 Å.

3. The semiconductor structure as described in claim 1, characterized in that, The second barrier layer material includes silicon oxide; the thickness of the second barrier layer ranges from 1000 Å to 2000 Å.

4. The semiconductor structure as described in claim 1, characterized in that, The thickness ratio of the first barrier layer to the second barrier layer is in the range of 3:7 to 7:

3.

5. The semiconductor structure as described in claim 1, characterized in that, Also includes: The channel located within the second opening.

6. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided having a first opening therein, the first opening exposing a portion of the sidewall surface of the substrate; A first barrier layer and a second barrier layer located on the surface of the first barrier layer are formed within the first opening; A dielectric layer structure is formed on the surface of the substrate; A second opening is formed within the dielectric layer structure, the second opening exposing the sidewall surface of the dielectric layer structure, the sidewall surface of the second barrier layer, and a portion of the surface of the first barrier layer. The etching process for forming the second opening has a first ratio between the etching rate of the second barrier layer material and the etching rate of the first barrier layer material, the first ratio being greater than 1.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The method for forming the first barrier layer includes: forming an initial first barrier layer in the first opening; planarizing the initial first barrier layer until the surface of the initial first barrier layer is flush with the substrate; and etching the initial first barrier layer back to form the first barrier layer.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The method for forming the second barrier layer includes: forming an initial second barrier layer on the surface of the first barrier layer; and planarizing the initial second barrier layer until the substrate surface is exposed to form the second barrier layer.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, The etching method includes dry etching.

10. The method for forming a semiconductor structure as described in claim 6, characterized in that, The thickness ratio of the first barrier layer to the second barrier layer is in the range of 3:7 to 7:

3.

11. The method for forming a semiconductor structure as described in claim 6, characterized in that, The material of the first barrier layer includes aluminum oxide; the thickness of the first barrier layer ranges from 1000 Å to 3000 Å. The formation process of the first barrier layer includes physical vapor deposition and chemical vapor deposition; the process parameters of the formation process of the first barrier layer include: the deposition time of the first barrier layer is 25 minutes to 45 minutes, the gas pressure intensity of the first barrier layer is 1 torr to 2 torr, and the deposition temperature of the first barrier layer is 350℃ to 450℃.

12. The method for forming a semiconductor structure as described in claim 6, characterized in that, The material of the second barrier layer includes silicon oxide; the thickness of the second barrier layer ranges from 1000 Å to 2000 Å; the formation process of the second barrier layer includes HARP. The process parameters for forming the second barrier layer include: a deposition time of 25 to 45 minutes, a deposition pressure of 600 torr, a deposition temperature of 500°C to 600°C, and the gases used for deposition include tetraethoxysilane and ozone, with the tetraethoxysilane flow rate ranging from 1000 sccm to 10000 sccm and the ozone flow rate ranging from 50000 sccm to 10000 sccm.

13. The method for forming a semiconductor structure as described in claim 6, characterized in that, The first ratio ranges from 10:1 to 20:

1.

14. The method for forming a semiconductor structure as described in claim 6, characterized in that, The method for forming the second opening includes: forming a hard mask layer on the surface of the dielectric layer structure; using the hard mask layer as a mask, etching the dielectric layer structure to form a second opening, wherein the second opening exposes the sidewall surface of the dielectric layer structure, the sidewall surface of the second barrier layer, and a portion of the surface of the first barrier layer.

15. The method for forming a semiconductor structure as described in claim 6, characterized in that, The dielectric layer structure includes: a stack of several first dielectric layers and second dielectric layers; the number of first dielectric layers ranges from 1 to 3; the number of second dielectric layers ranges from 1 to 3; the materials of the first dielectric layers include: silicon oxide, silicon nitride, silicon oxynitride, and amorphous carbon; the materials of the second dielectric layers include silicon oxide, silicon nitride, silicon oxynitride, and amorphous carbon.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, After forming the second opening, the method further includes: forming a channel within the second opening; after forming the channel, removing the first dielectric layer and forming a gate layer between adjacent second dielectric layers; after forming the gate layer, removing the second dielectric layer and performing source / drain doping on the channel exposed by the adjacent gate layers; and after performing source / drain doping, forming source / drain conductivity between adjacent gate layers.

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