Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and a method for forming the semiconductor structure include: a substrate including a first region and a second region; a first nanowire structure located on the first region, including a first bottom structure and a plurality of first nanowires vertically stacked on the first bottom structure; a second nanowire structure located on the second region, including a second bottom structure and a plurality of second nanowires vertically stacked; an isolation layer located on the substrate, wherein the top surface of the isolation layer on the first region is lower than the top surface of the isolation layer on the second region; a first gate structure and a second gate structure located on the isolation layer, wherein the first gate structure surrounds the first nanowire and the second gate structure surrounds the second nanowire; first source and drain doped regions located on either side of the first gate structure, wherein the bottom plane of the first source and drain doped regions is higher than or flush with the top plane of the isolation layer; and second source and drain doped regions located within the second nanowire structure and within the isolation layer on either side of the second gate structure. The semiconductor structure has improved performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] Gate-All-Around (GAA) transistors, as the next-generation logic transistor structure, are used in both ordinary logic devices and static random-access memory (SRAM) devices. This will require the simultaneous use of ordinary logic devices and SRAM devices on the same substrate, necessitating optimization for both logic and SRAM applications.

[0003] As SRAM cell heights shrink as their area increases, avoiding the merging of PU transistors and PU transistors with PD transistors becomes a challenge for SRAM cell designers and process integration. Conventional P-type logic devices also require merging to enhance device performance.

[0004] Therefore, in the all-around gate technology node, how to simultaneously meet the needs of P-type ordinary logic devices and static random access memory devices is an urgent problem that needs to be solved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to simultaneously meet the requirements of a P-type common logic device and a static random access memory device.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region; forming an initial first nanowire structure on the first region, the initial first nanowire structure comprising: a first bottom structure and a plurality of first stacking structures vertically stacked on the first bottom structure; forming an initial second nanowire structure on the second region, the initial second nanowire structure comprising: a second bottom structure and a plurality of second stacking structures vertically stacked on the second bottom structure; forming an isolation layer on the substrate, the isolation layer being located on the sidewall surface of the initial first nanowire structure and the sidewall surface of the initial second nanowire structure, the isolation layer exposing the sidewall surface of the first stacking structure and the sidewall surface of the second stacking structure, and the top surface of the isolation layer on the first region being lower than the top surface of the isolation layer on the second region a first dummy gate structure and a second dummy gate structure are formed on the isolation layer, the first dummy gate structure spans the initial first nanowire structure, and the second dummy gate structure spans the initial second nanowire structure; a portion of the initial first nanowire structure on both sides of the first dummy gate structure is removed, and a first opening is formed in the initial first nanowire structure on both sides of the first dummy gate structure, and the bottom plane of the first opening is flush with the top plane of the isolation layer; a portion of the initial second nanowire structure on both sides of the second dummy gate structure is removed, and a second opening is formed in the initial second nanowire structure on both sides of the second dummy gate structure and in the isolation layer, and the depths of the first opening and the second opening are the same; a first source-drain doped region is formed in the first opening; and a second source-drain doped region is formed in the second opening.

[0007] Correspondingly, the technical solution of the present invention also provides a semiconductor structure, comprising: a substrate, the substrate comprising a first region and a second region; a first nanowire structure located on the first region, the first nanowire structure comprising: a first bottom structure and a plurality of first nanowires vertically stacked on the first bottom structure, with a third groove between adjacent first nanowires and between the first nanowire and the first bottom structure; a second nanowire structure located on the second region, the second nanowire structure comprising: a second bottom structure and a plurality of second nanowires vertically stacked on the second bottom structure, with a fourth groove between adjacent second nanowires and between the second nanowire and the second bottom structure; an isolation layer located on the substrate, the isolation layer being located on the sidewall surface of the first nanowire structure and the sidewall surface of the second nanowire structure, the isolation layer exposing the sidewall surface of the first nanowire and the sidewall surface of the second nanowire, and the isolation layer on the first region The top surface is lower than the top surface of the isolation layer on the second region, and the top surface of the isolation layer on the first region is lower than the top surface of the first bottom structure; a first gate structure and a second gate structure are located on the isolation layer, the first gate structure spans the first nanowire structure and is located in the third groove, the first gate structure surrounds the first nanowire, the second gate structure spans the second nanowire structure and is located in the fourth groove, and the second gate structure surrounds the second nanowire; first source and drain doping regions are located on both sides of the first gate structure, the first source and drain doping regions are located in the first nanowire structures on both sides of the first gate structure, and the bottom plane of the first source and drain doping regions is higher than or flush with the top plane of the isolation layer; second source and drain doping regions are located on both sides of the second gate structure, the second source and drain doping regions are located in the second nanowire structures on both sides of the second gate structure and in the isolation layer, and the depths of the first source and drain doping regions and the second source and drain doping regions are the same.

[0008] Optionally, it also includes: a first groove located between adjacent first nanowires and between the first nanowire and the first bottom structure; a second groove located between adjacent second nanowires and between the second nanowire and the second bottom structure; a third sidewall located in the first groove, the third sidewall located on the sidewall of the first gate structure and the outer surface of the third sidewall is flush with the surface of the sidewall of the first nanowire; a fourth sidewall located in the second groove, the fourth sidewall located on the sidewall of the second gate structure and the outer surface of the fourth sidewall is flush with the surface of the sidewall of the second nanowire.

[0009] Optionally, the material of the first source / drain doping region includes silicon germanium; the material of the second source / drain doping region includes silicon germanium.

[0010] Optionally, the material of the first nanowire and the second nanowire includes silicon.

[0011] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0012] The technical solution of the present invention makes the top surface of the isolation layer on the first area lower than the top surface of the isolation layer on the second area, so that the bottom plane of the first opening formed subsequently is flush with the top plane of the isolation layer, and the bottom of the second opening formed is located in the isolation layer. The isolation layer limits the growth of the second source-drain doped region in the second opening, so that the volume of the first source-drain doped region is larger than the volume of the second source-drain doped region, so that the second source-drain doped region is not prone to bridging, thereby meeting the needs of forming different devices in the first area and the second area. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figures 1 to 3 is a structural schematic diagram of a semiconductor structure forming process in one embodiment;

[0014] Figures 4 to 22 It is a structural schematic diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0015] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0016] As described in the background art, simultaneously meeting the requirements of P-type common logic devices and static random access memory devices is an urgent problem to be solved.

[0017] Figures 1 to 3 This is a schematic structural diagram of a semiconductor structure forming process in one embodiment.

[0018] Please refer to Figures 1 to 3 , Figure 1 yes Figure 2 and Figure 3 A top view of Figure 2 yes Figure 1 Schematic diagram of the cross-section structure along the section line BB1, Figure 3 yes Figure 1Schematic diagram of the cross-sectional structure along the section line AA1 in the semiconductor structure, comprising: providing a substrate 100, the substrate 100 comprising a first region I and a second region II; forming an initial first nanowire structure on the first region I, the initial first nanowire structure comprising: a first bottom structure 101 and a plurality of first stacked structures vertically stacked on the first bottom structure, the first stacked structure comprising a first sacrificial layer 102 and a first nanowire 103 located on the first sacrificial layer 102; forming an initial second nanowire structure on the second region II, the initial second nanowire structure comprising: a second bottom structure 104 and a plurality of first stacked structures vertically stacked on the first bottom structure A plurality of second stacked structures are vertically stacked on the bottom structure, the second stacked structure includes a second sacrificial layer (not shown) and a second nanowire 106 located on the second sacrificial layer; an isolation layer 107 is formed on the substrate 100, the isolation layer 107 is located on the sidewall surface of the initial first nanowire structure and the sidewall surface of the initial second nanowire structure, and the isolation layer 107 exposes the sidewall surface of the first stacked structure and the sidewall surface of the second stacked structure; a first dummy gate structure 110 and a second dummy gate structure 108 are formed on the isolation layer 107, the first dummy gate structure 110 spans the initial first nanowire structure, and the second dummy gate structure 108 spans the initial second nanowire structure; forming a first spacer (not shown) on the sidewall of the first dummy gate structure 110, the first spacer is also located on the sidewall of the initial first nanowire structure, and forming a second spacer (not shown) on the sidewall of the second dummy gate structure 108, the second spacer is also located on the sidewall of the initial second nanowire structure; removing part of the initial first nanowire structure on both sides of the first dummy gate structure, forming a first opening (not shown) in the initial first nanowire structure on both sides of the first dummy gate structure; removing part of the initial second nanowire structure on both sides of the second dummy gate structure, and forming a first opening (not shown) in the initial second nanowire structure on both sides of the second dummy gate structure. A second opening (not shown) is formed in the nanowire structure; the portion of the first sacrificial layer 102 exposed by the first opening is removed, and a third sidewall 114 is formed on the sidewall of the first sacrificial layer 102, and the outer surface of the third sidewall 114 is flush with the sidewall surface of the first nanowire 103; the portion of the second sacrificial layer exposed by the second opening is removed, and a fourth sidewall (not shown) is formed on the sidewall of the second sacrificial layer, and the outer surface of the fourth sidewall is flush with the sidewall surface of the second nanowire; after the third sidewall 114 and the fourth sidewall are formed, a first source-drain doped region 115 is formed in the first opening; and a second source-drain doped region 116 is formed in the second opening.

[0019] The first region I of the substrate 100 is used to form a GAA logic device, and the second region II is used to form a static random access memory device. The static random access memory is composed of multiple independent transistors, and the formed transistors are independent of each other. Therefore, adjacent second source and drain doping regions 116 need to have a certain distance; and the GAA logic device requires the first source and drain doping regions 115 to contact each other to obtain a larger volume to enhance the channel control capability.

[0020] During the formation of the semiconductor structure, when part of the initial first nanowire structure on both sides of the first pseudo-gate structure is removed to form the first opening, part of the first sidewall remains on the sidewall of the first opening, and when part of the initial second nanowire structure on both sides of the second pseudo-gate structure is removed, part of the first sidewall remains on the sidewall of the second opening; when the third sidewall 114 and the fourth sidewall are subsequently formed, the process of first deposition and then removal causes the remaining first sidewall and second sidewall to be removed as well. Therefore, the sidewall of the second opening on the second region II does not restrict the growth of the second sidewall, so that when the first source and drain doping region 115 and the second source and drain doping region 116 are formed at the same time, the growth volume of the second source and drain doping region 116 is also large due to the lack of position restriction in the second opening, which makes it easy for bridging to occur, causing adjacent transistors with their respective functions to short-circuit, thereby affecting the performance of the static random access memory device.

[0021] In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming a semiconductor structure, by making the top surface of the isolation layer on the first region lower than the top surface of the isolation layer on the second region, so that the bottom plane of the subsequently formed first opening is flush with the top plane of the isolation layer, and the bottom of the formed second opening is located in the isolation layer. The isolation layer limits the growth of the second source-drain doped region in the second opening, so that the volume of the first source-drain doped region is larger than the volume of the second source-drain doped region, so that the second source-drain doped region is not prone to bridging, so as to meet the needs of forming different devices in the first region and the second region.

[0022] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0023] Figures 4 to 22 It is a structural schematic diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0024] Please refer to Figures 4 to 6 , Figure 4 for Figure 5 and Figure 6 A top view of Figure 5 for Figure 4 Schematic diagram of the cross-section structure along the section line AA1, Figure 6 for Figure 4A schematic diagram of the cross-sectional structure along the section line BB1 ​​is provided, wherein a substrate 200 is provided, and the substrate 200 includes a first region I and a second region II; an initial first nanowire structure is formed on the first region I, and the initial first nanowire structure includes: a first bottom structure 201 and a plurality of first stacking structures vertically stacked on the first bottom structure 201, the first stacking structure includes a first sacrificial layer 202 and a first nanowire 203 located on the first sacrificial layer 202; an initial second nanowire structure is formed on the second region II, and the initial second nanowire structure includes: a second bottom structure 204 and a plurality of second stacking structures vertically stacked on the second bottom structure 204, the second stacking structure includes a second sacrificial layer 205 and a second nanowire 206 located on the second sacrificial layer 205.

[0025] The plurality of initial first nanowire structures and the plurality of initial second nanowire structures are parallel to each other.

[0026] The materials of the first sacrificial layer 202 and the second sacrificial layer 205 include single crystal silicon or single crystal silicon germanium; the materials of the first nanowire 203 and the second nanowire 206 include single crystal silicon or single crystal silicon germanium.

[0027] In this embodiment, the material of the first sacrificial layer 202 and the second sacrificial layer 205 includes silicon germanium, and the material of the first nanowire 203 and the second nanowire 206 includes silicon.

[0028] In this embodiment, the substrate 200 is made of silicon.

[0029] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0030] Please refer to Figure 7 , Figure 7 For Figure 5 Based on the schematic diagram, an initial isolation layer 207 is formed on the substrate 200, and the initial isolation layer 207 is located on the sidewall surface of the initial first nanowire structure and the sidewall surface of the initial second nanowire structure. The initial isolation layer 207 exposes the sidewall surface of the first stacking structure and the sidewall surface of the second stacking structure.

[0031] The material of the initial isolation layer 207 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride.

[0032] In this embodiment, the material of the initial isolation layer 207 includes silicon oxide.

[0033] Please refer to Figure 8 , remove part of the initial isolation layer 207 on the first region I to form an isolation layer 230, the isolation layer 230 is located on the sidewall surface of the initial first nanowire structure and the sidewall surface of the initial second nanowire structure, the isolation layer 230 exposes the sidewall surface of the first stacking structure and the sidewall surface of the second stacking structure, the top surface of the isolation layer 230 on the first region I is lower than the top surface of the isolation layer 230 on the second region II, and the top surface of the isolation layer 230 on the first region I is lower than the top surface of the first bottom structure 201.

[0034] Please refer to Figures 9 to 12 , Figure 9 for Figure 10 、 Figure 11 and Figure 12 A top view of Figure 10 for Figure 9 Schematic diagram of the cross-section structure along the section line AA1, Figure 11 for Figure 9 Schematic diagram of the cross-section structure along the section line BB1, Figure 12 for Figure 9 In the cross-sectional structural diagram along the section line CC1, a first dummy gate structure 220 and a second dummy gate structure 208 are formed on the isolation layer 230. The first dummy gate structure 220 spans the initial first nanowire structure, and the second dummy gate structure 208 spans the initial second nanowire structure.

[0035] The first dummy gate structure 220 includes a first dummy gate dielectric layer (not shown) and a first dummy gate layer (not labeled) located on the first dummy gate dielectric layer. The second dummy gate structure 208 includes a second dummy gate dielectric layer (not shown) and a second dummy gate layer (not labeled) located on the second dummy gate dielectric layer.

[0036] The materials of the first dummy gate dielectric layer and the second dummy gate dielectric layer include silicon oxide or low-K (K is less than 3.9) material; the materials of the first dummy gate layer and the second dummy gate layer include polysilicon.

[0037] Please refer to Figure 13 and Figure 14 , Figure 13 For Figure 11 The structural diagram of the foundation, Figure 14 For Figure 10 Based on the structural schematic diagram, a first sidewall 209 is formed on the sidewall of the first pseudo gate structure 220, and the first sidewall 209 is also located on the sidewall of the initial first nanowire structure. A second sidewall (not shown) is formed on the sidewall of the second pseudo gate structure 208, and the second sidewall is also located on the sidewall of the initial second nanowire structure.

[0038] In this embodiment, the first sidewall spacer 209 and the second sidewall spacer are formed simultaneously.

[0039] The first spacer 209 and the second spacer include dielectric materials. The dielectric materials include one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0040] In this embodiment, the materials of the first spacer 209 and the second spacer include silicon nitride.

[0041] Please continue to refer to Figure 13 and Figure 14 , remove part of the initial first nanowire structure on both sides of the first dummy gate structure 220, form a first opening 210 in the initial first nanowire structure on both sides of the first dummy gate structure, and the bottom plane of the first opening 210 is flush with the top plane of the isolation layer 230 of the first region I; remove part of the initial second nanowire structure on both sides of the second dummy gate structure 208, form a second opening 211 in the initial second nanowire structure on both sides of the second dummy gate structure and in the isolation layer 230 of the second region II, and the depths of the first opening 210 and the second opening 211 are the same.

[0042] In this embodiment, the first opening 210 and the second opening 211 are formed simultaneously. The first opening 210 exposes the surface of the first bottom structure 201 , and the second opening 211 exposes the surface of the second bottom structure 204 .

[0043] In this embodiment, a portion of the first sidewall 209 remains on the sidewall of the first opening 210 .

[0044] Since the top surface of the isolation layer 230 on the first region I is lower than the top surface of the isolation layer 230 on the second region II, when the first opening 210 and the second opening 211 are formed at the same time, the bottom of the second opening 211 is located in the isolation layer 230. The isolation layer 230 plays a role in position restriction when the second source and drain doping regions are subsequently formed, thereby preventing the second source and drain doping regions from becoming too large and contacting each other.

[0045] Next, the portion of the first sacrificial layer 202 exposed by the first opening 210 is removed, and a third sidewall spacer is formed on the sidewall of the first sacrificial layer 202. The outer surface of the third sidewall spacer is flush with the sidewall surface of the first nanowire 203. The portion of the second sacrificial layer 205 exposed by the second opening 211 is removed, and a fourth sidewall spacer is formed on the sidewall of the second sacrificial layer 205. The outer surface of the fourth sidewall spacer is flush with the sidewall surface of the second nanowire 206. The formation process of the third and fourth sidewalls can be referred to. Figures 15 to 19 .

[0046] Please refer to Figure 15 , Figure 15 For Figure 13Based on the schematic diagram, the portion of the first sacrificial layer 202 exposed by the first opening 210 is removed to form a first groove 212 between adjacent first nanowires 203 and between the first nanowire 203 and the first bottom structure 201; the portion of the second sacrificial layer 205 exposed by the second opening 211 is removed to form a second groove (not shown) between adjacent second nanowires 206 and between the second nanowire 206 and the second bottom structure 204.

[0047] The process of removing the first sacrificial layer 202 and the second sacrificial layer 205 includes a dry etching process, and the dry etching process has a relatively large selectivity for the first nanowire 203 and the second nanowire 206 .

[0048] Please refer to Figure 16 and Figure 17 , Figure 16 For Figure 15 Based on the schematic diagram, Figure 17 For Figure 14 Based on the schematic diagram, a sidewall material layer 213 is formed in the first groove 212, the second groove, the sidewall surface and bottom surface of the first opening 210, the sidewall surface and bottom surface of the second opening 211, the surface of the isolation layer 230, the surface of the initial first nanowire structure and the surface of the initial second nanowire structure.

[0049] The material of the spacer material layer 213 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0050] The material of the spacer material layer 213 is the same as that of the first spacer 209 and the second spacer 209. In this embodiment, the material of the spacer material layer 213 includes silicon nitride.

[0051] Please refer to Figure 18 and Figure 19 , Figure 18 For Figure 16 Based on the schematic diagram, Figure 19 For Figure 17 Based on the schematic diagram, the sidewall material layer 213 of the sidewall surface and bottom surface of the first opening 210, the sidewall surface and bottom surface of the second opening 211, the surface of the isolation layer 230, the surface of the initial first nanowire structure and the surface of the initial second nanowire structure is removed to form a third sidewall 214 in the first groove 212 and a fourth sidewall (not shown) in the second groove.

[0052] While removing the sidewall material layer 213 on the first opening sidewall surface and bottom surface, the second opening sidewall surface and bottom surface, the isolation layer surface, the initial first nanowire structure surface and the initial second nanowire structure surface, it also includes: removing the first sidewall 209 remaining on the sidewall of the first opening 210.

[0053] The process of removing the spacer material layer 213 includes a dry etching process.

[0054] In this embodiment, when the spacer material layer 213 is removed, the isolation layer 203 is also partially consumed naturally.

[0055] Please refer to Figure 20 and Figure 21 , Figure 20 For Figure 18 Based on the schematic diagram, Figure 21 For Figure 19 Based on the schematic diagram, a first source-drain doping region 215 is formed in the first opening 210; a second source-drain doping region 216 is formed in the second opening 211, and the volume of the second source-drain doping region 216 is smaller than the volume of the first source-drain doping region 215. The first source-drain doping region 215 and the second source-drain doping region 216 are formed at the same time.

[0056] In this embodiment, the material of the first source / drain doping region 215 includes silicon germanium; the material of the second source / drain doping region 216 includes silicon germanium.

[0057] The first region I of the substrate 200 is used to form a GAA logic device, and the second region II is used to form a static random access memory device. The static random access memory is composed of multiple independent transistors, and the formed transistors are independent of each other. Therefore, adjacent second source and drain doping regions 216 need to have a certain distance; and the GAA logic device requires the first source and drain doping regions 215 to contact each other to obtain a larger volume to enhance the channel control capability.

[0058] Since the isolation layer 230 at the bottom of the second opening 210 serves to limit the position when the second source-drain doped region 216 grows, the volume of the formed second source-drain doped region 216 is smaller than the volume of the first source-drain doped region 215, so that the second source-drain doped region 216 is not prone to bridging, thereby meeting the needs of forming different devices in the first region I and the second region II.

[0059] Please refer to Figure 22 , Figure 22 For Figure 20 Based on the schematic diagram, after forming the first source-drain doped region 215 and the second source-drain doped region 216, it also includes: forming a first gate structure 217, the first gate structure 217 surrounds the first nanowire 203; forming a second gate structure (not shown), the second gate structure surrounds the second nanowire 206.

[0060] The method for forming the first gate structure 217 and the second gate structure includes: forming a dielectric layer 221 on the first dummy gate structure 220, the second dummy gate structure 208, the isolation layer 230, the initial first nanowire structure and the initial second nanowire structure, wherein the first dummy gate structure 220, the second dummy gate structure 208, the first source-drain doped region 215 and the second source-drain doped region 216 are located in the dielectric layer 221; removing the first dummy gate structure 220 to form a first gate opening (not shown) in the dielectric layer 221; removing the second dummy gate structure to form a second gate opening (not shown) in the dielectric layer 221; and removing the first sacrificial layer 221 exposed by the first gate structure opening. 02, forming a first nanowire structure, and forming a third groove (not shown) between adjacent first nanowires 203 and between the first nanowire 203 and the first bottom structure 201; removing the second sacrificial layer 205 exposed by the opening of the second gate structure 208 to form a second nanowire structure, and forming a fourth groove (not shown) between adjacent second nanowires 206 and between the second nanowire 206 and the second bottom structure 204; forming a first gate structure 217 in the first gate opening, the first gate structure spanning the first nanowire structure and located in the third groove; forming a second gate structure in the second gate opening, the second gate structure spanning the second nanowire structure and located in the fourth groove.

[0061] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 21 and Figure 22 ,include:

[0062] A substrate 200 including a first region I and a second region II;

[0063] a first nanowire structure located on the first region I, the first nanowire structure comprising: a first bottom structure 201 and a plurality of first nanowires 203 vertically stacked on the first bottom structure 201, with third grooves between adjacent first nanowires 203 and between the first nanowires 203 and the first bottom structure 201;

[0064] a second nanowire structure located on the second region II, the second nanowire structure comprising: a second bottom structure 204 and a plurality of second nanowires 206 vertically stacked on the second bottom structure 204, with a fourth groove between adjacent second nanowires 206 and between the second nanowire 206 and the second bottom structure 204;

[0065] an isolation layer 230 located on the substrate 200, the isolation layer 230 being located on the sidewall surfaces of the first nanowire structure and the second nanowire structure, the isolation layer 230 exposing the sidewall surfaces of the first nanowire 203 and the second nanowire 206, the top surface of the isolation layer 230 on the first region I being lower than the top surface of the isolation layer 230 on the second region II, and the top surface of the isolation layer 230 on the first region I being lower than the top surface of the first bottom structure 201;

[0066] a first gate structure 217 and a second gate structure located on the isolation layer 230 , wherein the first gate structure spans the first nanowire structure and is located in the third groove, and the first gate structure surrounds the first nanowire 203 ; and the second gate structure spans the second nanowire structure and is located in the fourth groove, and the second gate structure surrounds the second nanowire 206 ;

[0067] First source / drain doped regions 215 located on both sides of the first gate structure 217 . The first source / drain doped regions 215 are located in the first nanowire structure on both sides of the first gate structure 217 , and the bottom plane of the first source / drain doped regions 215 is higher than or flush with the top plane of the isolation layer 230 .

[0068] The second source-drain doping region 216 is located on both sides of the second gate structure. The second source-drain doping region 216 is located in the second nanowire structure and the isolation layer 230 on both sides of the second gate structure. The first source-drain doping region 215 and the second source-drain doping region 216 have the same depth, and the volume of the second source-drain doping region 216 is smaller than the volume of the first source-drain doping region 215.

[0069] In this embodiment, it also includes: a first groove located between adjacent first nanowires 203 and between the first nanowire 203 and the first bottom structure 201; a second groove located between adjacent second nanowires 206 and between the second nanowire 206 and the second bottom structure 204; a third sidewall 214 located in the first groove, the third sidewall 214 is located on the sidewall of the first gate structure 217 and the outer surface of the third sidewall 214 is flush with the sidewall surface of the first nanowire 203; a fourth sidewall located in the second groove, the fourth sidewall is located on the sidewall of the second gate structure and the outer surface of the fourth sidewall is flush with the sidewall surface of the second nanowire 206.

[0070] In this embodiment, the material of the first source / drain doping region 215 includes silicon germanium; the material of the second source / drain doping region 216 includes silicon germanium.

[0071] In this embodiment, the material of the first nanowire 203 and the second nanowire 206 includes silicon.

[0072] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate comprising a first region and a second region; forming an initial first nanowire structure on the first region, the initial first nanowire structure comprising: a first bottom structure and a plurality of first stacked structures vertically stacked on the first bottom structure; forming an initial second nanowire structure on the second region, the initial second nanowire structure comprising: a second bottom structure and a plurality of second stacked structures vertically stacked on the second bottom structure; forming an isolation layer on the substrate, the isolation layer being located on the sidewall surface of the initial first nanowire structure and the sidewall surface of the initial second nanowire structure, the isolation layer exposing the sidewall surface of the first stacked structure and the sidewall surface of the second stacked structure, the top surface of the isolation layer on the first region being lower than the top surface of the isolation layer on the second region, and the top surface of the isolation layer on the first region being lower than the top surface of the first bottom structure; forming a first dummy gate structure and a second dummy gate structure on the isolation layer, wherein the first dummy gate structure spans the initial first nanowire structure, and the second dummy gate structure spans the initial second nanowire structure; removing a portion of the initial first nanowire structure on both sides of the first dummy gate structure, forming a first opening in the initial first nanowire structure on both sides of the first dummy gate structure, wherein a bottom plane of the first opening is flush with a top plane of the isolation layer; removing a portion of the initial second nanowire structure on both sides of the second dummy gate structure, forming second openings in the initial second nanowire structure on both sides of the second dummy gate structure and in the isolation layer, wherein the first opening and the second opening have the same depth; forming a first source-drain doped region in the first opening; A second source-drain doped region is formed in the second opening.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the isolation layer includes: forming an initial isolation layer on a substrate, the initial isolation layer being located on the sidewall surface of the initial first nanowire structure and the sidewall surface of the initial second nanowire structure, the initial isolation layer exposing the sidewall surface of the first stacking structure and the sidewall surface of the second stacking structure; removing a portion of the initial isolation layer on the first area to form an isolation layer, the top surface of the isolation layer on the first area being lower than the top surface of the isolation layer on the second area, and the top surface of the isolation layer on the first area being lower than the top surface of the first bottom structure.

3. The method for forming a semiconductor structure according to claim 1, wherein: The first stack structure includes a first sacrificial layer and a first nanowire located on the first sacrificial layer; the second stack structure includes a second sacrificial layer and a second nanowire located on the second sacrificial layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: Before removing a portion of the initial first nanowire structure on both sides of the first dummy gate structure and a portion of the initial second nanowire structure on both sides of the second dummy gate structure, the method further includes: forming a first spacer on the sidewall of the first dummy gate structure, the first spacer also being located on the sidewall of the initial first nanowire structure, and forming a second spacer on the sidewall of the second dummy gate structure, the second spacer also being located on the sidewall of the initial second nanowire structure; The first opening sidewall also has a portion of the first sidewall remaining.

5. The method for forming a semiconductor structure according to claim 4, wherein: Before forming the first source-drain doped region in the first opening and forming the second source-drain doped region in the second opening, the method further includes: The portion of the first sacrificial layer exposed by the first opening is removed, and a third side wall is formed on the side wall of the first sacrificial layer, and the outer surface of the third side wall is flush with the surface of the side wall of the first nanowire; the portion of the second sacrificial layer exposed by the second opening is removed, and a fourth side wall is formed on the side wall of the second sacrificial layer, and the outer surface of the fourth side wall is flush with the surface of the side wall of the second nanowire.

6. The method for forming a semiconductor structure according to claim 5, wherein: The method for forming the first and second side walls includes: removing the portion of the first sacrificial layer exposed by the first opening to form a first groove between adjacent first nanowires and between the first nanowire and the first bottom structure; removing the portion of the second sacrificial layer exposed by the second opening to form a second groove between adjacent second nanowires and between the second nanowire and the second bottom structure; forming a side wall material layer in the first groove, in the second groove, on the side wall surface and bottom surface of the first opening, on the side wall surface and bottom surface of the second opening, on the surface of the isolation layer, on the surface of the initial first nanowire structure, and on the surface of the initial second nanowire structure; removing the side wall material layer on the side wall surface and bottom surface of the first opening, on the side wall surface and bottom surface of the second opening, on the surface of the isolation layer, on the surface of the initial first nanowire structure, and on the surface of the initial second nanowire structure, to form a third side wall in the first groove and a fourth side wall in the second groove.

7. The method for forming a semiconductor structure according to claim 6, wherein: While removing the sidewall material layer on the first opening sidewall surface and bottom surface, the second opening sidewall surface and bottom surface, the isolation layer surface, the initial first nanowire structure surface and the initial second nanowire structure surface, it also includes: removing the first sidewall remaining on the first opening sidewall.

8. The method for forming a semiconductor structure according to claim 3, wherein: After forming the first source-drain doped region and the second source-drain doped region, the method further includes: forming a first gate structure, the first gate structure surrounding the first nanowire; and forming a second gate structure, the second gate structure surrounding the second nanowire.

9. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the first gate structure and the second gate structure includes: forming a dielectric layer on a first dummy gate structure, a second dummy gate structure, an isolation layer, an initial first nanowire structure, and an initial second nanowire structure, wherein the first dummy gate structure, the second dummy gate structure, the first source-drain doped region, and the second source-drain doped region are located in the dielectric layer; removing the first dummy gate structure to form a first gate opening in the dielectric layer; removing the second dummy gate structure to form a second gate opening in the dielectric layer; removing the first sacrificial layer exposed by the opening of the first gate structure to form a first nanowire structure, and forming a third groove between adjacent first nanowires and between the first nanowire and the first bottom structure; removing the second sacrificial layer exposed by the opening of the second gate structure to form a second nanowire structure, and forming a fourth groove between adjacent second nanowires and between the second nanowire and the second bottom structure; forming a first gate structure in the first gate opening, the first gate structure spanning the first nanowire structure and being located in the third groove; forming a second gate structure in the second gate opening, the second gate structure spanning the second nanowire structure and being located in the fourth groove.

10. The method for forming a semiconductor structure according to claim 3, wherein: The materials of the first sacrificial layer and the second sacrificial layer include silicon germanium, and the materials of the first nanowire and the second nanowire include silicon.

11. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first source / drain doping region includes silicon germanium; the material of the second source / drain doping region includes silicon germanium.

12. A semiconductor structure, characterized in that: include: a substrate comprising a first region and a second region; a first nanowire structure located on the first region, the first nanowire structure comprising: a first bottom structure and a plurality of first nanowires vertically stacked on the first bottom structure, with third grooves between adjacent first nanowires and between the first nanowires and the first bottom structure; a second nanowire structure located on the second region, the second nanowire structure comprising: a second bottom structure and a plurality of second nanowires vertically stacked on the second bottom structure, with fourth grooves between adjacent second nanowires and between the second nanowires and the second bottom structure; an isolation layer located on the substrate, the isolation layer being located on the sidewall surface of the first nanowire structure and the sidewall surface of the second nanowire structure, the isolation layer exposing the first nanowire sidewall surface and the second nanowire sidewall surface, the top surface of the isolation layer on the first region being lower than the top surface of the isolation layer on the second region, and the top surface of the isolation layer on the first region being lower than the top surface of the first bottom structure; a first gate structure and a second gate structure located on the isolation layer, wherein the first gate structure spans the first nanowire structure and is located in the third groove, the first gate structure surrounds the first nanowire, the second gate structure spans the second nanowire structure and is located in the fourth groove, and the second gate structure surrounds the second nanowire; First source and drain doped regions are located on both sides of the first gate structure, the first source and drain doped regions are located in the first nanowire structure on both sides of the first gate structure, and the bottom plane of the first source and drain doped regions is higher than or flush with the top plane of the isolation layer; A second source-drain doped region is located on both sides of the second gate structure, the second source-drain doped region is located in the second nanowire structure and the isolation layer on both sides of the second gate structure, the first source-drain doped region and the second source-drain doped region have the same depth, and the volume of the second source-drain doped region is smaller than the volume of the first source-drain doped region.

13. The semiconductor structure according to claim 12, wherein: Also includes: a first groove located between adjacent first nanowires and between the first nanowires and the first bottom structure; a second groove located between adjacent second nanowires and between the second nanowire and the second bottom structure; A third sidewall spacer is located in the first groove, the third sidewall spacer is located on the sidewall of the first gate structure, and the outer surface of the third sidewall spacer is flush with the surface of the first nanowire sidewall; a fourth sidewall spacer is located in the second groove, the fourth sidewall spacer is located on the sidewall of the second gate structure, and the outer surface of the fourth sidewall spacer is flush with the surface of the second nanowire sidewall.

14. The semiconductor structure according to claim 12, wherein: The material of the first source / drain doping region includes silicon germanium; the material of the second source / drain doping region includes silicon germanium.

15. The semiconductor structure according to claim 12, wherein: The materials of the first nanowire and the second nanowire include silicon.

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