Chip placement carrier, manufacturing method and chip level testing method

Abstract

The present invention discloses a chip placement carrier suitable for a wafer-level tester, a manufacturing method and a chip-level testing method. By setting a specific chip placement carrier and utilizing a sorting machine function to place the chip on the chip placement carrier, the tester is finally used to test the chip, thereby realizing chip-level testing of semiconductor chips.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor chip testing, and in particular relates to a chip placement carrier suitable for a wafer-level testing machine, a manufacturing method, and a chip-level testing method. Background Art

[0002] Currently, in the field of chip production such as lasers and detectors, most of the production routes are: making chips on wafers, (wafer-level) photoelectric performance testing, scratching or cutting, and finally sorting and shipping.

[0003] However, there are certain performance testing defects in the above production route: 1) The performance tested after the (wafer-level) optoelectronic performance test is not necessarily equivalent to the device performance of the bare die (chip) after scratching. The reasons include: After the (wafer-level) test, it is still necessary to go through processes such as scratching and sorting. This process may cause certain damage to the device performance, resulting in deviations in the final bare die device performance. 2) For optoelectronic devices with different PN surfaces, during the (wafer-level) test, all devices on the wafer share the same N surface. If the back-side process is not done well, after scratching and cutting, the resistance value and voltage of the bare die device will show abnormal deviations. Therefore, chip-level testing can represent the performance of the final shipped device.

[0004] In the prior art, if the wafer is tested after being split and sorted, most of the time, the chips need to be manually clamped and tested, which is not possible for mass production testing. Moreover, the manufacturer has certain capabilities for wafer testing, sorting and shipment, but does not have chip-level testing equipment and chip-level mass production testing capabilities.

[0005] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0006] The purpose of the present invention is to provide a chip placement carrier, a manufacturing method and a chip-level testing method suitable for a wafer-level tester, which to a certain extent solve the problems of the prior art that arise in the production process and realize chip-level testing.

[0007] In order to achieve the above object, a specific embodiment of the present invention provides a chip placement carrier suitable for a wafer-level tester, comprising:

[0008] The substrate has a first surface, wherein the first surface is concavely formed with a placement groove;

[0009] a passivation layer formed on an inner wall of the placement groove and extending to the first surface; and

[0010] The metal layer is formed on the passivation layer on the bottom wall of the placement groove and at least a portion of the metal layer extends to the passivation layer on the first surface.

[0011] In one or more embodiments of the present invention, an angle a between the side wall and the bottom wall of the placement groove is an obtuse angle.

[0012] In one or more embodiments of the present invention, an adsorption hole is formed on the substrate in the area where the placement groove is located, and the adsorption hole is arranged to penetrate the passivation layer and the metal layer.

[0013] In one or more embodiments of the present invention, the substrate has a second surface arranged opposite to the first surface, a groove is arranged on the second surface toward the first surface, and the adsorption hole is located in the groove.

[0014] A specific embodiment of the present invention provides a method for manufacturing the chip placement carrier suitable for a wafer-level tester, comprising:

[0015] Providing a substrate having a first surface and a second surface disposed opposite to each other;

[0016] forming a placement groove on the first surface;

[0017] forming a passivation layer on the first surface and the inner wall of the placement groove;

[0018] A metal layer is formed on the passivation layer, wherein the metal layer exposes a portion of the passivation layer.

[0019] In one or more embodiments of the present invention, the manufacturing method further includes:

[0020] forming an adsorption hole penetrating the metal layer, the passivation layer and the substrate in the placement groove;

[0021] A groove is formed on the second surface through a thinning process, and the adsorption hole is located in the groove.

[0022] A specific embodiment of the present invention provides a chip-level testing method for a semiconductor chip, comprising:

[0023] Providing the above-mentioned chip placement carrier suitable for a wafer-level tester;

[0024] Cut the wafer into several chips, place the chips in the placement slots of the chip placement tray, and vacuum adsorb them;

[0025] The probes of the tester are respectively contacted with the p-level and n-level of the chip or respectively contacted with the p-level of the chip and the metal layer of the chip carrier;

[0026] Automatic testing.

[0027] In one or more embodiments of the present invention, placing a chip in a placement slot of a chip placement tray and vacuum adsorbing the chip includes:

[0028] Place the chip carrier on the carrier of the sorting machine;

[0029] Set the sorting spacing and placement height of the sorting machine;

[0030] The chip is transferred to the placement slot of the chip placement tray by the sorting machine;

[0031] Then place the chip on the carrier plate and place it on the test machine for vacuum adsorption.

[0032] Same as above, is the order of operations reversed? Because the chip is placed first and then tested.

[0033] In one or more embodiments of the present invention, the chip is a PN skew chip;

[0034] Placing the chip in a placement slot of a chip placement carrier, wherein the n-level of the chip is in contact with and electrically connected to the metal layer of the chip placement carrier;

[0035] The positive probe of the tester contacts the p-level of the chip, and the negative probe of the tester contacts the metal layer of the carrier where the chip is placed.

[0036] In one or more embodiments of the present invention, the chip is a PN same-plane chip;

[0037] Placing the chip in a placement groove of a chip placement carrier, wherein a side of the chip without an electrode is in contact with a metal layer of the chip placement carrier;

[0038] The positive probe of the tester contacts the p-level of the chip, and the negative probe of the tester contacts the n-level of the chip.

[0039] In one or more embodiments of the present invention, the tester may be a wafer-level tester or a chip-level tester.

[0040] Compared with the prior art, the chip placement carrier, manufacturing method and chip-level testing method suitable for a wafer-level tester of the present invention first utilize semiconductor manufacturing technology to manufacture a specific chip placement carrier, then utilize the sorting machine function to place the chip on the chip placement carrier, and finally utilize a tester to test the chip, thereby realizing chip-level testing of semiconductor chips.

[0041] The chip placement carrier of the present invention is suitable for the chip placement carrier of a wafer-level tester, the manufacturing method and the chip-level testing method. (For enterprises), there is no need to purchase special testing equipment, which can save at least one million in equipment costs, and there is no need to outsource testing, which also saves a certain amount of time cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 A cross-sectional view of a chip placement carrier suitable for a wafer-level tester in one embodiment of the present invention;

[0044] Figure 2 It is a process flow chart of a method for manufacturing a chip placement carrier suitable for a wafer-level tester in one embodiment of the present invention;

[0045] Figure 3a-3e A process step diagram of a method for manufacturing a chip placement carrier suitable for a wafer-level tester in one embodiment of the present invention;

[0046] Figure 4 A flowchart of a chip-level testing method according to an embodiment of the present invention;

[0047] Figure 5 A schematic diagram of PN out-of-plane chip testing in a chip-level testing method according to an embodiment of the present invention;

[0048] Figure 6 Schematic diagram of PN same-plane chip testing in a chip-level testing method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0050] As mentioned in the background technology, in the current production field of laser, detector and other chips, most of the production routes are: making chips on wafers, (wafer-level) photoelectric performance testing, scratching or cutting, and finally sorting and shipping.

[0051] However, there are certain performance testing defects in the above production route:

[0052] 1) The performance after (wafer-level) optoelectronic performance testing is not necessarily equivalent to the device performance of the bare die (chip) after scratching. The reasons include: after (wafer-level) testing, it is still necessary to go through processes such as scratching and sorting. This process may cause certain damage to the device performance, resulting in deviations in the final bare die device performance.

[0053] 2) For optoelectronic devices with PN heterogeneous surfaces, during (wafer-level) testing, all devices on the wafer share the same N surface. If the back-side process is not done well, the resistance and voltage of the bare die device will have abnormal deviations after scratching and cutting.

[0054] Therefore, chip-level testing can represent the performance of the final shipped device. However, in the prior art, for chip-level testing, after the wafer is split and sorted, most of the chips need to be manually clamped and tested manually, which is not suitable for mass production testing.

[0055] Based on this, the present application provides a chip placement carrier, a manufacturing method and a chip-level testing method suitable for a wafer-level tester. Through the design of a special chip placement carrier, a carrier is provided for the chip, so that the chip is adapted to the wafer-level tester, and then a sorting machine and a wafer-level tester are used to realize chip-level automated testing of semiconductor chips.

[0056] like Figure 1 As shown, a chip placement carrier suitable for a wafer-level tester in one embodiment of the present invention includes: a substrate 10, a passivation layer 20 and a metal layer 30. The substrate 10 has a first surface 10a, and the first surface 10a is concavely formed with a placement groove 11. The passivation layer 20 is formed on the inner wall of the placement groove 11 and extends to cover the first surface 10a. The metal layer 30 is formed on the passivation layer 20 on the bottom wall of the placement groove 11 and at least a portion of it extends to the passivation layer 20 on the first surface 10a.

[0057] The substrate 10 is a semiconductor substrate, which can be made of Si, GaAs, etc. The size of the substrate 10 can be 3 inches, 4 inches, 6 inches, 8 inches or 12 inches, and the thickness is not limited.

[0058] The placement groove 11 can be formed on the first surface 10a of the substrate 10 by photolithography and etching processes. An angle a is formed between the side wall and the bottom wall of the placement groove 11, and the angle a is preferably an obtuse angle. The purpose of using an obtuse angle a is to improve the convenience and stability of the chip when it is placed in the placement groove 11. In the process of placing the chip, there may be a deviation in the placement position, resulting in the chip not being completely placed in the placement groove 11, for example, it will rest on the side wall. Or during the overall transfer process, the chip is disturbed by external forces and there will be a position deviation. Therefore, after setting the angle a to an obtuse angle, even if the above situation occurs, the chip can automatically slide to the bottom of the placement groove 11 through the subsequent vacuum adsorption function, and completely fit with the bottom to achieve position fixation and calibration.

[0059] A passivation film of a certain thickness is grown on the inner wall of the placement groove 11 and the first surface 10a of the substrate 10 to form a passivation layer 20. The passivation layer 20 plays an insulating role. During the test process, the influence of the substrate 10 on the performance of the chip can be avoided.

[0060] The predetermined area in the placement groove 11 and on the first surface 10a of the substrate 10 is defined by a photolithography process. Adhesion layer metal and gold are sequentially evaporated in the predetermined area. The adhesion layer metal and gold together constitute the metal layer 30. The purpose of the adhesion layer metal is to avoid the risk of gold falling off when gold is directly plated on the passivation layer 20. Among them, the predetermined area includes the bottom wall of the placement groove 11, part of the side wall of the placement groove 11 and part of the first surface 10a of the substrate 10. It should be noted that the edge of the metal layer 30 should be located in the passivation layer 20.

[0061] The chip placement carrier for the wafer-level tester of this embodiment is formed with an adsorption hole 12 which is set through the substrate 10 in the area where the placement groove 11 is located. The adsorption hole 12 is also set through the passivation layer 20 and the metal layer 30. It can be understood that the formation of the adsorption hole 12 can also be formed by first defining a predetermined area through a photolithography process, and then etching the metal layer 30, the passivation layer 20 and the substrate 10 in sequence through dry etching or wet etching.

[0062] A groove 13 is formed on the second surface 10b of the substrate 10 opposite to the first surface 10a and is concave toward the first surface 10a. The adsorption hole 12 is located in the groove 13. The groove 13 can be formed by a thinning process to assist the adsorption hole 12 in vacuum adsorption.

[0063] refer to Figure 2 As shown, the present application provides a method for manufacturing the chip placement carrier applicable to the wafer-level tester, comprising:

[0064] S1: Provide a substrate, wherein the substrate has a first surface and a second surface that are opposite to each other.

[0065] refer to Figure 3a As shown, the substrate 10 is a semiconductor substrate, which can be made of Si, GaAs, etc. The size of the substrate 10 can be 3 inches, 4 inches, 6 inches, 8 inches or 12 inches, and the thickness is not limited.

[0066] S2: forming a placement groove on the first surface of the substrate.

[0067] refer to Figure 3b As shown, a placement groove 11 is formed on the first surface 10 a of the substrate 10 by a photolithography process.

[0068] Exemplarily, a photoresist is used to define the position where the chip is placed (the position where the placement groove 11 needs to be set) on the wafer substrate 10. The pattern of the photoresist is transferred to the substrate 10, and the placement groove 11 is etched or corroded on the substrate 10 for placing the chip. Among them, an angle a is formed between the side wall and the bottom wall of the placement groove 11, and the angle a is preferably an obtuse angle, which can improve the convenience and stability of the subsequent chip placement in the placement groove 11.

[0069] S3: forming a passivation layer on the first surface of the substrate and the inner wall of the placement groove.

[0070] refer to Figure 3c As shown, a passivation film of a certain thickness is grown on the inner wall of the placement groove 11 and the first surface 10a of the substrate 10 to form a passivation layer 20. The passivation layer 20 plays an insulating role. During the test process, the influence of the substrate 10 on the performance of the chip can be avoided.

[0071] S4: forming a metal layer on the passivation layer, wherein the metal layer exposes a portion of the passivation layer.

[0072] refer to Figure 3d As shown, the predetermined area in the placement groove 11 and on the first surface 10a of the substrate 10 where the metal layer 30 needs to be plated is defined by photolithography, photolithography and development. Adhesion layer metal and gold are sequentially evaporated in the predetermined area. The layer metal and gold together constitute the metal layer 30. The purpose of the adhesion layer metal is to avoid the risk of gold falling off when gold is directly plated on the passivation layer 20. Among them, the predetermined area includes the bottom wall of the placement groove 11, part of the side wall of the placement groove 11 and part of the first surface 10a of the substrate 10. It should be noted that the edge of the metal layer 30 should be located in the passivation layer 20.

[0073] S5: forming an adsorption hole penetrating the metal layer, the passivation layer and the substrate in the placement groove.

[0074] refer to Figure 3e As shown, the position and pattern size of the vacuum adsorption hole 12 are defined by photoresist, photolithography and development. The metal layer 30, the passivation layer 20 and the substrate 10 are etched in sequence by dry etching or wet etching to form the adsorption hole 12.

[0075] S6: forming a groove on the second surface through a thinning process, wherein the adsorption hole is located in the groove.

[0076] refer to Figure 4 As shown, the present application provides a chip-level testing method for a semiconductor chip, comprising:

[0077] S10: Provide the chip placement tray suitable for the wafer-level tester.

[0078] S20: Cut the wafer into a plurality of chips, place the chips in the placement grooves of the chip placement carrier, and vacuum adsorb the chips.

[0079] S30: Probes of the test machine are respectively contacted with the p-level and n-level of the chip or respectively contacted with the p-level of the chip and the metal layer of the chip carrier.

[0080] S40: Automatic test.

[0081] Specifically, first, place the chip carrier on a side platform of the sorting machine.

[0082] Secondly, place the wafer on the blue film for slicing and cutting, and then expand the film. Place the expanded blue film on the other side of the carrier on the sorting machine.

[0083] The sorting machine sets parameters such as sorting spacing and placement height;

[0084] The sorting machine uses a pin to lift up the chip on the blue film, and after the nozzle sucks the chip, it transfers the chip from the blue film to the placement slot in the chip placement carrier and places it one by one in sequence.

[0085] Among them, reference Figure 5 As shown, if the chip is a PN chip, the chip is placed in the placement slot of the chip placement tray, and the n-level of the chip contacts and is electrically connected to the metal layer of the chip placement tray. The chip placement tray containing the chip is placed on the wafer-level automatic test machine, and the vacuum is turned on to suck the chip. Adjust the position of the test machine probe, the positive probe b contacts the p electrode of the chip, and the negative probe c contacts the metal layer of the chip placement tray. The test machine performs automatic testing.

[0086] refer to Figure 6 As shown, if the chip is a PN same-side chip; then place the chip in the placement slot of the chip placement carrier, and the side of the chip without an electrode is in contact with the metal layer of the chip placement carrier. Place the chip placement carrier containing the chip on the wafer-level automatic test machine, and turn on the vacuum to suck the chip. Adjust the position of the test machine probe, so that the positive probe b contacts the p electrode of the chip and the negative probe c contacts the n electrode of the chip. The test machine performs automatic testing.

[0087] The chip placement carrier, manufacturing method and chip-level testing method suitable for a wafer-level tester of the present invention use the manufacturing process of semiconductor device processing to manufacture the chip placement carrier to provide a carrier for chip-level testing; use a sorting machine to neatly place the chips on the blue film on the chip placement carrier; use the vacuum adsorption function of the tester to indirectly adsorb the chips through the vacuum adsorption holes of the chip placement carrier to avoid chip movement during the test process, and finally realize automatic testing of the chip.

[0088] The chip placement carrier, manufacturing method and chip-level testing method suitable for a wafer-level testing machine of the present invention reorganize the chip processing flow of the FAB factory, so that the flow becomes: wafer-level testing (optional), wafer scratching and cutting, film expansion, sorting, chip testing, sorting, and shipping.

[0089] Compared with the prior art, the chip placement carrier, manufacturing method and chip-level testing method suitable for a wafer-level tester of the present invention first utilize semiconductor manufacturing technology to manufacture a specific chip placement carrier, then utilize the sorting machine function to place the chip on the chip placement carrier, and finally utilize a tester to test the chip, thereby realizing chip-level testing of semiconductor chips.

[0090] The chip placement carrier, manufacturing method and chip-level testing method suitable for a wafer-level tester of the present invention do not need to purchase dedicated testing equipment (for enterprises), which can save at least one million in equipment costs, and do not need to outsource testing, which also saves a certain amount of time costs.

[0091] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0092] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A chip placement carrier suitable for a wafer-level tester, characterized in that: include: The substrate has a first surface, wherein the first surface is concavely formed with a placement groove; A passivation layer formed on the inner wall of the placement groove and extending to the first surface; as well as a metal layer formed on the passivation layer on the bottom wall of the placement groove and at least a portion of which extends to the passivation layer on the first surface; The angle a between the side wall and the bottom wall of the placement groove is an obtuse angle; An adsorption hole is formed on the substrate in the area where the placement groove is located, and the adsorption hole is arranged to penetrate the passivation layer and the metal layer; The substrate has a second surface arranged opposite to the first surface, a groove is arranged on the second surface toward the first surface, and the adsorption hole is located in the groove.

2. A method for manufacturing a chip placement carrier suitable for a wafer-level tester as claimed in claim 1, characterized in that: include: Providing a substrate having a first surface and a second surface disposed opposite to each other; forming a placement groove on the first surface; forming a passivation layer on the first surface and the inner wall of the placement groove; forming a metal layer on the passivation layer, wherein the metal layer exposes a portion of the passivation layer; forming an adsorption hole penetrating the metal layer, the passivation layer and the substrate in the placement groove; A groove is formed on the second surface through a thinning process, and the adsorption hole is located in the groove.

3. A chip-level testing method for a semiconductor chip, characterized in that: include: Providing a chip placement carrier suitable for a wafer-level tester as claimed in claim 1; Cut the wafer into several chips, place the chips in the placement slots of the chip placement tray, and vacuum adsorb them; The probes of the tester are respectively contacted with the p-level and n-level of the chip or respectively contacted with the p-level of the chip and the metal layer of the chip carrier; Automatic testing.

4. The chip-level testing method for a semiconductor chip according to claim 3, characterized in that: Place the chip in the placement slot of the chip placement tray and vacuum adsorb it, including: Place the chip carrier on the carrier of the sorting machine; Set the sorting spacing and placement height of the sorting machine; The chip is transferred to the placement slot of the chip placement tray by the sorting machine; Then place the chip on the carrier plate and place it on the test machine for vacuum adsorption.

5. The chip-level testing method for a semiconductor chip according to claim 3, characterized in that: The chip is a PN skew chip; Placing the chip in a placement slot of a chip placement carrier, wherein the n-level of the chip is in contact with and electrically connected to the metal layer of the chip placement carrier; The positive probe of the tester contacts the p-level of the chip, and the negative probe of the tester contacts the metal layer of the carrier where the chip is placed.

6. The chip-level testing method for a semiconductor chip according to claim 3, characterized in that: The chip is a PN same-plane chip; Placing the chip in a placement groove of a chip placement carrier, wherein a side of the chip without an electrode is in contact with a metal layer of the chip placement carrier; The positive probe of the tester contacts the p-level of the chip, and the negative probe of the tester contacts the n-level of the chip.

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