Memory control method and storage device

Abstract

The present invention provides a memory control method and a memory device. The memory device includes a memory controller and a memory module, and the memory device is electrically connected to a host system. The memory control method includes: the host system sends an identification instruction to the memory controller to obtain identification information of the memory module transmitted by the memory controller; generates a command sequence table corresponding to the memory module according to the identification information; transmits the command sequence table to the memory controller; sends a corresponding call instruction to the memory controller according to the execution requirement, for calling one of multiple command sequences in the command sequence table once or multiple times to control the memory module. Therefore, the compatibility of the memory controller can be improved and the cost of firmware development can be reduced.

Description

Technical Field

[0001] The present invention relates to a memory management technology, and in particular to a memory control method and a storage device. Background Art

[0002] Non-volatile memory modules (such as flash memory modules) have the advantages of non-volatile data storage, low power consumption and fast data access. Generally speaking, non-volatile memory modules are controlled by a memory controller, which is connected to the host system through a connection interface. The host system will issue commands to the memory controller, through which the memory controller performs operations such as reading, writing, and erasing on the non-volatile memory module. However, there are many manufacturers that make non-volatile memory modules, and each manufacturer may use different operation commands. When the memory controller is to be adapted to non-volatile memory modules produced by different manufacturers, different firmware needs to be developed to adapt to these different operation commands. Alternatively, even non-volatile memory modules produced by the same manufacturer may use different operation commands due to different models, specifications, etc. The above problems will increase the firmware development cost of the memory controller. Summary of the invention

[0003] The invention provides a memory control method, which can reduce the cost of firmware development.

[0004] An embodiment of the present invention provides a memory control method for a host system, wherein the host system is electrically connected to a memory controller, and the method comprises: the host system sends an identification instruction to the memory controller to obtain identification information of a memory module transmitted by the memory controller; generates a command sequence table corresponding to the memory module according to the identification information, wherein the command sequence table includes multiple command sequences and their corresponding index values, and each of the multiple command sequences includes multiple sub-commands; transmits the command sequence table to the memory controller; and sends a corresponding call instruction to the memory controller according to execution requirements, wherein the call instruction includes an index value and a data parameter, and is used to call and execute one of the multiple command sequences in the command sequence table once or multiple times to control the memory module.

[0005] An embodiment of the present invention also provides a memory control method for a memory controller, wherein the memory controller is electrically connected to a host system and a memory module, and the method comprises: the memory controller responds to an identification instruction sent by the host system, obtains identification information of the memory module and transmits it to the host system; receives and stores a command sequence table corresponding to the memory module generated by the host system, wherein the command sequence table includes multiple command sequences and their corresponding index values, and each of the multiple command sequences includes multiple sub-commands; responds to a call instruction sent by the host system, selects a corresponding command sequence in the command sequence table according to the index value in the call instruction; and parses the corresponding command sequence to obtain the sub-commands contained therein, and controls the memory module according to data parameters in the call instruction and the obtained sub-commands.

[0006] From another perspective, an embodiment of the present invention provides a storage device, including a connection interface unit for connecting to a host system; a memory module; and a memory controller connected to the connection interface and the memory module; wherein the memory controller is used to respond to an identification instruction sent by the host system, obtain identification information of the memory module and transmit it to the host system; is used to receive and store a command sequence table corresponding to the memory module generated by the host system, wherein the command sequence table includes multiple command sequences and their corresponding index values, and each of the multiple command sequences includes multiple sub-commands; is used to respond to a call instruction sent by the host system, select a corresponding command sequence in the command sequence table according to the index value in the call instruction; and is used to parse the corresponding command sequence to obtain the sub-commands contained therein, and control the memory module according to the data parameters in the call instruction and the obtained sub-commands.

[0007] Through the memory control method provided by the present invention, the memory controller does not need to identify the memory model and operation command format, but only needs to identify the predefined subcommands. Therefore, a set of firmware can be compatible with different models of memory, and there is no restriction on the compatible memory model, which greatly reduces the firmware development cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a storage device according to an embodiment of the present invention;

[0009] Figure 2 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0010] Figure 3 is a flow chart showing a memory control method according to an embodiment;

[0011] Figure 4 is a schematic diagram showing a command sequence table according to an embodiment;

[0012] Figure 5is a schematic diagram showing a predefined sub-command table according to an embodiment;

[0013] Figure 6 is a schematic diagram showing sub-commands included in a command sequence according to an embodiment. DETAILED DESCRIPTION

[0014] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0015] Figure 1 is a schematic diagram of a storage device according to an embodiment of the present invention. Figure 1 The data storage system includes a storage device 10 and a host system 11. The host system 11 can be any type of computer system, such as a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server or a vehicle-mounted computer, etc., and the type of the host system 11 is not limited thereto.

[0016] The storage device 10 is connected to the host system 11 and is used to store data from the host system 11. For example, the storage device 10 may include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices. The host system 11 may communicate with the storage device 10 through an embedded Multi-Media Card (embedded Multi-Media Card, eMMC), a universal flash memory (Universal FlashStorage, UFS), a fast peripheral component interconnect (Peripheral Component Interconnect Express, PCIExpress), a fast non-volatile memory (Non-Volatile Memory Express, NVM express), a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA), a universal serial bus (Universal Serial Bus, USB) or other types of connection interface standards. Therefore, the host system 11 can store data to the storage device 10 and / or read data from the storage device 10.

[0017] The storage device 10 includes a connection interface unit 101, a memory module 102, and a memory controller 103. The connection interface unit 101 is used to connect the storage device 10 to the host system 11. For example, the connection interface unit 101 may support connection interface standards such as eMMC, UFS, PCI Express, NVM express, SATA, PCI Express, or USB. The storage device 10 can communicate with the host system 11 (e.g., exchange signals, instructions, and / or data) via the connection interface unit 101.

[0018] The memory module 102 is used to store data. The memory module 102 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also called threshold voltage). For example, the memory module 102 may include a single level cell (SLC) NAND type flash memory module, a multi level cell (MLC) NAND type flash memory module, a triple level cell (TLC) NAND type flash memory module, a quad level cell (QLC) NAND type flash memory module and / or other memory modules having the same or similar characteristics.

[0019] The memory controller 103 is connected to the connection interface unit 101 and the memory module 102. The memory controller 103 can be regarded as the control core of the memory device 10 and is used to control the memory device 10. For example, the memory controller 103 can be responsible for controlling and / or managing the entire or partial operation of the memory device 10. For example, the memory controller 103 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application specific integrated circuits (ASIC), programmable logic devices (PLD) or other similar devices or combinations of these devices. In one embodiment, the memory controller 103 includes a flash memory controller.

[0020] In one embodiment, the memory controller 103 may further include a buffer memory, a power management circuit, an encoding circuit, a decoding circuit and / or various other types of circuit modules, which are not limited by the present invention. The buffer memory is used to cache data. The power management circuit is used to manage the power of the storage device 10. The encoding circuit is used to encode the data to be stored in the memory module 102 to generate an error correction code (and / or an error checking code). The decoding circuit is used to decode the data read from the memory module 102 to correct possible errors in the read data. For example, the encoding circuit and / or the decoding circuit may use various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), Exclusive OR (XOR) code, etc. to encode and decode data.

[0021] The memory module 102 may receive a command from the memory controller 103 and access the storage unit according to the command. For example, when data is to be stored, the memory controller 103 may send a write command to the memory module 102 to instruct the memory module 102 to store the data in a specific storage unit. When data is to be read, the memory controller 103 may send a read command to the memory module 102 to instruct the memory module 102 to read data from a specific storage unit. When data is to be deleted, the memory controller 103 may send an erase command to the memory module 102 to instruct the memory module 102 to erase the data stored in the specific storage unit. In addition, the memory controller 103 may also send other types of commands to the memory module 102 to instruct the memory module 102 to perform corresponding operations, which is not limited by the present invention.

[0022] Figure 2 FIG. 1 is a schematic diagram of a management memory module according to an embodiment of the present invention. Figure 1 and Figure 2 The memory module 102 includes a plurality of physical units 201 ( 1 ) to 201 (B). Each physical unit includes a plurality of storage cells and is used for non-volatile storage of data.

[0023] In one embodiment, a physical unit may include one or more physical erase units. A physical erase unit may include multiple physical programming units. For example, a physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (Bytes, B), and a physical programming unit may include 8 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, a physical programming unit can be regarded as a physical page. For example, the data capacity of a physical programming unit may be 4 kilobytes (4KB), and the present invention is not limited thereto.

[0024] In one embodiment, a physical programming unit is the smallest unit to which data is synchronously written in the memory module 102. For example, when a programming operation is performed on a physical programming unit to write data to the physical programming unit, multiple storage cells in the physical programming unit can be synchronously programmed to store corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to the physical programming unit to change the threshold voltage of at least part of the storage cells in the physical programming unit. The threshold voltage of each storage cell can reflect the bit data stored in the storage cell. In the following embodiments, a physical programming unit is also referred to as a physical sub-unit.

[0025] In one embodiment, multiple memory cells in the same physical erase unit can be erased synchronously. For example, when performing an erase operation on a physical erase unit, an erase voltage can be applied to multiple physical programming cells in the physical erase unit to change the threshold voltage of at least part of the memory cells in these physical programming cells and clear the bit data stored in each memory cell in these physical programming cells.

[0026] In one embodiment, the memory controller 103 may logically associate the physical units 201(1)-201(A) with the data area 21 and associate the physical units 201(A+1)-201(B) with the spare area 22. The physical units 201(1)-201(A) in the data area 21 are used to store data (also referred to as user data) from the host system 11. For example, each physical unit in the data area 21 may store valid data and / or invalid data. In addition, the physical units 201(A+1)-201(B) in the spare area 22 do not store data.

[0027] In one embodiment, if a physical unit does not store valid data, the physical unit can be associated with the idle area 22. In one embodiment, the idle area 22 is also called a free pool. In addition, the physical unit associated with the idle area 22 can be erased to clear the data in the physical unit.

[0028] In one embodiment, when data (i.e., user data) from the host system 11 needs to be stored, the memory controller 103 may select one or more physical units from the idle area 22 and instruct the memory module 102 to store the data from the host system 11 into the selected physical units. At the same time, the selected physical units may be associated with the data area 21.

[0029] In one embodiment, the memory controller 103 may configure a plurality of logical units 202 (1) to 202 (C) to map the physical units 201 (1) to 201 (A) in the data area 21. For example, a logical unit may correspond to a logical block address (LBA) or other logical management units. A logical unit may be mapped to one or more physical units in the data area 21.

[0030] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory controller 103 may determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory controller 103 may determine that the physical unit does not currently store any valid data (and / or the data in the physical unit are all invalid data).

[0031] In one embodiment, the memory controller 103 may record the mapping relationship between the logical unit and the physical unit in a logical-to-physical mapping table. When receiving an access instruction (such as a read instruction, a write instruction, a delete instruction, or other types of instructions) from the host system 11, the memory controller 103 may instruct the memory module 102 to perform a corresponding operation behavior according to the information in the logical-to-physical mapping table.

[0032] In one embodiment, the memory controller 103 may configure a logical block number (LBN) for each logical unit. A specific logical block number may be used to represent a specific logical unit. Different logical block numbers may be used to represent different logical units. In one embodiment, the memory controller 103 may use this logical block number to manage each logical unit.

[0033] In one embodiment, a logical unit may include multiple logical sub-units. In one embodiment, the memory controller 103 may configure a logical page number (LPN) for each logical sub-unit in the logical unit. In one embodiment, the memory controller 103 may use the logical block number in combination with the logical page number to manage the logical sub-units in each logical unit. For example, the memory controller 103 may use a logical block number of "1" and a logical page number of "2" to represent the second logical sub-unit in the first logical unit, and so on.

[0034] A first aspect of an embodiment of the present application provides a memory control method for a host system 11 . Figure 3 is a flow chart showing a memory control method according to an embodiment. Figure 1 and Figure 3 In step 301, the host system 11 sends an identification instruction to the memory controller 103 to obtain identification information of the memory module 102 transmitted by the memory controller 103. The identification information is, for example, a flash ID of the memory module 102. In other embodiments, the identification information may also include information such as the manufacturer, product name, and specifications of the memory module 102, but the present disclosure is not limited thereto.

[0035] In step 302 , the host system 11 generates a command sequence table corresponding to the current memory module 102 according to the above identification information.

[0036] For example, Figure 4 FIG. 1 is a schematic diagram showing a command sequence table according to an embodiment. Figure 4The command sequence table 400 includes a plurality of command sequences, each of which has a corresponding index value. For the sake of simplicity, the command sequence table 400 only shows a portion of the command sequences. For example, the index value "0" corresponds to the command sequence "FCL_READ_UNIQUE_ID", which is used to read the unique identifier of the flash memory; the index value "1" corresponds to the command sequence "FCL_SLC_ERASE", which is used to erase the physical unit in the SLC mode; the index value "2" corresponds to the command sequence "FCL_XLC_ERASE", which is used to erase the physical unit in the MLC, TLC, QLC and other modes; the index value "3" corresponds to the command sequence "FCL_SLC_PROGRAM", which is used to perform programming (or writing) according to the SLC mode; the index value "4" corresponds to the command sequence "FCL_XLC_PROGRAM", which is used to perform programming (or writing) according to the MLC, TLC, QLC and other modes; the index value "5" corresponds to the command sequence "FCL_SLC_READ", which is used to read the physical unit in the SLC mode. In this embodiment, the index value is set to decimal. In other embodiments, it can be binary, octal, hexadecimal or other bases, and this application does not limit it.

[0037] Each command sequence includes multiple subcommands, for example, the command sequence "FCL_XLC_ERASE" includes subcommands 411-418. Each subcommand includes a command field 421 and three parameter fields 422-424. The command field 421 is used to store an operation code (op code) to indicate the type of the predefined subcommand. The parameter fields 422-424 are used to indicate the execution format of the predefined subcommand, in which the execution parameters required for the execution command are stored. In some embodiments, the command sequence table 400 includes a maximum of 32 command sequences, and each command sequence includes a maximum of 128 subcommands, each subcommand has a size of 4 bytes, wherein the size of the command field 421 is 1 Byte, and the size of each parameter field 422-424 is 1 Byte. However, the present disclosure does not limit the number and content of the command sequences, nor does it limit the number of subcommands in each command sequence, nor does it limit the size of each subcommand.

[0038] The above subcommands are selected from a predefined subcommand table, which is a predefined set of common commands that can be recognized by the host system 11 and the memory controller 103. For different models of memory modules 102, the host system 11 adapts to different operation command formats by setting execution parameters in the predefined subcommands and combining different predefined subcommands. Figure 5As shown in Table 500, Table 500 shows a plurality of predefined subcommands, each of which includes 1 command field and 3 parameter fields. The command field stores an operation code, and the parameter field stores execution parameters, and "NU" indicates that the corresponding execution parameters are empty. For example, the subcommand with the operation code "0x02" is used to set a delay, the first parameter field is used to set whether the time unit is microseconds, and the second and third parameter fields are used to record the delay time. For the sake of simplicity, Table 500 only shows part of the predefined subcommands, and the present disclosure does not limit the content and quantity of the predefined subcommands. In this example, the operation code cannot be modified, and the format of the subcommand (including several fields, the length and content of each field) cannot be modified. The host system 11 can determine the execution parameters of the subcommand, but after generating the command sequence table, the execution parameters of these subcommands cannot be modified. In this embodiment, the command field and the parameter field are set to hexadecimal, and in other embodiments, they can be other bases such as binary, octal or decimal, which are not limited by the present application.

[0039] The host system 11 determines the operation command format corresponding to the current memory module 102 according to the identification information, selects one or more of the plurality of predefined subcommands to form each command sequence in the command sequence table, and determines the execution parameters in the plurality of predefined subcommands according to the operation command format. For example, the command sequence "FCL_SLC_ERASE" includes subcommands with operation codes of 0x10, 0x13, 0x30, 0x02, 0x01, 0x31, 0x14, and 0xFF. Similarly, for other command sequences, the host system 11 will select other appropriate predefined subcommands.

[0040] The same command sequence may include multiple predefined subcommands with the same opcode, and the execution parameters of these predefined subcommands may be the same or different. Different command sequences may also include predefined subcommands with the same opcode, and the execution parameters of these predefined subcommands may be the same or different. In other words, the host system 11 combines the command sequence it needs from the predefined subcommands, and the combination of these subcommands needs to comply with the composition rules and the execution format of the memory module 102. For example, the amount of data that can be read at one time by a certain model of memory module 102 is 4k, while the amount of data that can be read at one time by another model of memory module 102 is 2k. The host system 11 can generate different command sequence tables according to the execution parameters of the corresponding design subcommands.

[0041] For memory modules 102 of different models, the predefined sub-commands forming the command sequence implementing the same function may also be different. For example, the command sequence "FCL_SLC_ERASE" generated for two memory modules 102 of different models may contain different numbers, orders or types of sub-commands.

[0042] Please refer to the reply Figure 3 In step 303 , the host system 11 transmits the generated command sequence table to the memory controller 103 , and the command sequence table is stored in the memory controller 103 .

[0043] In some embodiments, if the host system adds, modifies or deletes a command sequence in the current command sequence table, a new command sequence table is generated and sent to the memory controller 103 to replace the current command sequence table. The command sequence table cannot be added, modified or deleted by the memory controller 103.

[0044] In step 304, the host system 11 sends a corresponding call instruction to the memory controller 103 according to the execution requirement. The call instruction includes an index value and a data parameter. The index value corresponds to a command sequence in the command sequence table, and is used to call and execute one of the multiple command sequences in the command sequence table one or more times to control the memory module 102. Figure 4 For example, when the host system 11 wants to execute the command sequence "FCL_SLC_ERASE", the index value in the call instruction can be set to 1, and the data parameter can include the address of the logical unit. Alternatively, when the host system 11 wants to execute the command sequence "FCL_SLC_READ", the index value in the call instruction can be set to 5, and the data parameter can include the address of the target block or page. Alternatively, when the host system 11 wants to read a large amount of data at one time, the index value in the call instruction can be set to 5, and the command sequence "FCL_SLC_READ" can be called multiple times, and the data parameter can include the number of executions and the address of the target block or page.

[0045] The second aspect of the embodiment of the present application provides a memory control method for the memory controller 103. After the host system 11 executes step 301 to send an identification instruction to the memory controller 103, the memory controller 103 responds to the identification instruction sent by the host system 11, obtains the identification information of the memory module 102 and transmits it to the host system 11.

[0046] After the host system 11 executes step 303 to send the command sequence table to the memory controller 103, the memory controller 103 receives and stores the command sequence table corresponding to the memory module 102 generated by the host system 11, wherein the command sequence table includes multiple command sequences and their corresponding index values, and each of the multiple command sequences includes multiple sub-commands. The command sequence table, command sequence and sub-commands are specifically described above and will not be repeated here.

[0047] After the host system 11 executes step 304 to send the corresponding call instruction to the memory controller 103 according to the execution requirement, the memory controller 103 responds to the call instruction sent by the host system and selects the corresponding command sequence in the command sequence table according to the index value in the call instruction.

[0048] And, after the memory controller 103 obtains the command sequence corresponding to the above index value, it parses the corresponding command sequence to obtain the sub-commands contained therein, and controls the memory module 102 according to the data parameters in the call instruction and the obtained sub-commands. Continuing with the above example, when the index value is 1, the memory controller 103 will query the command sequence table according to this index value and obtain the sub-commands contained in the command sequence "FCL_SLC_ERASE". Please refer to Figure 6 In this example, the command sequence "FCL_SLC_ERASE" includes sub-commands 601~610. Each sub-command 601~610 contains four fields. The first field records the operation code, and the last three fields record the execution parameters ( Figure 6 The numbers in the columns are all in hexadecimal. If there is no value recorded in the column, it means that the column is invalid. In this embodiment, the command column and the parameter column are set to hexadecimal. In other embodiments, they can be binary, octal or decimal, etc., which is not limited by this application.

[0049] First, for subcommand 601, the operation code is "10", which means that an instruction is to be sent to the memory module 102, and the instruction to be sent is "DA", which indicates the pre-instruction of the SLC. For subcommand 602, the operation code is "10", which means that an instruction is to be sent to the memory module 102, and the instruction to be sent is "60", which is the first instruction to be executed for erasing. For subcommand 603, the operation code is "13", which means that a row address is to be sent to the memory module 102, and the corresponding data parameter is obtained from the call instruction as the row address. For subcommand 604, the operation code is "10", which means that an instruction is to be sent to the memory module 102, and the instruction to be sent is "D0", which indicates that the second instruction to be executed for erasing. For subcommand 605, the operation code is "30", which indicates starting the timer. For subcommand 606, the operation code is "02", which is to set the delay. The value "00" indicates that the time unit is nanoseconds (ns). The value "50 00" indicates that the delay is 0x0050 (decimal 80) time units. For subcommand 607, the operation code is "01", which indicates waiting for the memory module 102 to be ready. For subcommand 608, the operation code is "31", which indicates that the timer is stopped and the timing time is saved. For subcommand 609, the operation code is "14", which indicates that the row address is to be increased. This subcommand is used to repeatedly call this command sequence. If the object to be executed by calling this command sequence next time is on the same plane, the parameter field can be filled with the value "0040". If the object to be executed by calling this command sequence next time is on a different plane, the parameter field can be filled with "0010". Finally, for subcommand 610, the operation code is "FF", which indicates that this command sequence ends.

[0050] In the above example, the command sequence "FCL_SLC_ERASE" includes 10 sub-commands 601-610. However, in other storage devices 10, if the model of the memory module 102 is changed, the host system 11 will generate another command sequence list, in which the command sequence "FCL_SLC_ERASE" may include different sub-commands. Specifically, after the memory controller 103 transmits the identification information of the memory module 102 to the host system 11, if the host system 11 determines that the identification information is the first identification information (e.g., a certain model), the host system 11 will generate a first command sequence list and transmit the first command sequence list to the memory controller 103. If the host system 11 determines that the received identification information is the second identification information (e.g., another model), the host system 11 will generate a second command sequence list and transmit the second command sequence list to the memory controller 103. The above-mentioned first command sequence list is different from the second command sequence list. In some embodiments, the order of the command sequences in the first command sequence list may be different from the order of the command sequences in the second command sequence list, for example, the index value of the command sequence "FCL_SLC_ERASE" in the first command sequence list is 1, but the index value of the same command sequence list in the second command sequence list is 3. In some embodiments, the number of command sequences in the first command sequence list is different from the number of command sequences in the second command sequence list, for example, the first command sequence list includes 28 command sequences, while the second command sequence list includes 31 command sequences.

[0051] In some embodiments, the subcommands in the first command sequence table and the second command sequence table may have different parameters. Taking the command sequence "FCL_SLC_ERASE" as an example, the command sequence "FCL_SLC_ERASE" (also called the first command sequence) in the first command sequence table includes the subcommand "10 DA 00 00" (also called the first subcommand), which can be referred to Figure 6 However, in the second command sequence table, the command sequence "FCL_SLC_ERASE" (also called the second command sequence) may include the subcommand "10 3B 00 00" (also called the second subcommand), that is, the operation code of the first subcommand is the same as the operation code of the second subcommand, but the parameters of the first subcommand are different from the parameters of the second subcommand.

[0052] The memory controller 103 cannot add, modify or delete the command sequence in the command sequence table. In some embodiments, the host system 11 adds, modifies or deletes the command sequence in the current command sequence table, generates a new command sequence table and transmits it to the memory controller 103. After receiving the new command sequence table, the memory controller 103 stores the latest received command sequence table to replace the current command sequence table. For example, the current command sequence table contains 28 command sequences, and the new command sequence table contains 32 command sequences.

[0053] From another perspective, the third aspect of the embodiment of the present application provides a storage device 10, including a connection interface unit 101 for connecting to a host system 11; a memory module 102; and a memory controller 103 connected to the connection interface unit 101 and the memory module 102.

[0054] The memory controller 103 is used to respond to the identification instruction sent by the host system 11, obtain the identification information of the memory module 102 and transmit it to the host system 11; to receive and store the command sequence table corresponding to the memory module 102 generated by the host system 11, wherein the command sequence table includes multiple command sequences and their corresponding index values, and each of the multiple command sequences includes multiple sub-commands; to respond to the call instruction sent by the host system 11, select the corresponding command sequence in the command sequence table according to the index value in the call instruction; and to parse the corresponding command sequence to obtain the contained sub-commands, and control the memory module 102 according to the data parameters in the call instruction and the obtained sub-commands. The specific implementation details are as described above and will not be repeated here.

[0055] Through the above-mentioned means, for different models of memory modules 102, the host system 11 can generate a corresponding command sequence table and transmit it to the memory controller 103. In subsequent operations, the host system 11 can call the corresponding command sequence by simply transmitting the index value of the command sequence. In this way, the firmware of the memory controller 103 only needs to identify the predefined sub-command table to control different models of memory modules 102 according to the command sequence table transmitted by the host system 11. There is no need to burn different firmware in response to different models of memory modules 102, which can reduce the development cost and complexity of the firmware. The above-mentioned means can also be applied to different connection interface standards, such as USB, SATA, PCIE, etc. In addition, the memory module 102 may have different specifications, such as single-plane and multi-plane, and the above-mentioned means can be applied to various specifications.

[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory control method, characterized in that: For use in a host system, the host system being electrically connected to a memory controller, the method comprising: The host system sends an identification instruction to the memory controller to obtain identification information of a memory module transmitted by the memory controller; Generate a command sequence table corresponding to the memory module according to the identification information, wherein the command sequence table includes a plurality of command sequences and their corresponding index values, each of the plurality of command sequences includes a plurality of sub-commands; wherein the plurality of sub-commands are selected from a predefined sub-command table, the predefined sub-command table includes a plurality of predefined sub-commands, and the predefined sub-command table is a pre-set universal command set that can be recognized by the host system and the memory controller; wherein when the identification information is determined to be the first identification information, a first command sequence table is generated as the command sequence table; and when the identification information is determined to be the second identification information, a second command sequence table is generated as the command sequence table, the first command sequence table is different from the second command sequence table, wherein one of the command sequences in the first command sequence table and one of the command sequences in the second command sequence table implement the same function but contain different predefined sub-commands; transmitting the command sequence table to the memory controller; A corresponding call instruction is sent to the memory controller according to the execution requirement, wherein the call instruction includes an index value and a data parameter, and is used to call and execute one of the multiple command sequences in the command sequence table once or multiple times to control the memory module.

2. The memory control method according to claim 1, characterized in that: Generating a command sequence table corresponding to the memory module according to the identification information includes: Determine an operation command format corresponding to the memory module according to the identification information; One or more of the predefined sub-commands in the table of predefined sub-commands are selected to form each command sequence in the table of command sequences, and execution parameters in the predefined sub-commands are determined according to the operation command format.

3. The memory control method according to claim 1, characterized in that: The first command sequence list is different from the second command sequence list in that: The order of the command sequences in the first command sequence table is different from the order of the command sequences in the second command sequence table; or The number of the command sequences in the first command sequence table is different from the number of the command sequences in the second command sequence table.

4. The memory control method according to claim 1, characterized in that: The first command sequence list is different from the second command sequence list in that: The first command sequence in the first command sequence list includes a first subcommand, and the second command sequence in the second command sequence list includes a second subcommand; The operation code of the first subcommand is the same as the operation code of the second subcommand and the execution parameter of the first subcommand is different from the execution parameter of the second subcommand.

5. The memory control method according to claim 2, characterized in that: The predefined subcommand includes a command field and a parameter field: The command field includes an operation code to indicate the type of each predefined subcommand; The parameter field includes the execution parameter for indicating the execution format of each predefined subcommand.

6. The memory control method according to claim 1, characterized in that: Also includes: If the host system adds, modifies or deletes a command sequence in the current command sequence table, a new command sequence table is generated and transmitted to the memory controller to replace the current command sequence table.

7. A memory control method, characterized in that: For a storage controller, the storage controller is electrically connected to a host system and a memory module, the method comprising: The memory controller, in response to the identification instruction sent by the host system, obtains the identification information of the memory module and transmits it to the host system; Receive and store a command sequence table corresponding to the memory module generated by the host system, wherein the command sequence table includes multiple command sequences and their corresponding index values, each of the multiple command sequences includes multiple sub-commands, when the identification information is the first identification information, the command sequence table is a first command sequence table; when the identification information is the second identification information, the command sequence table is a second command sequence table, wherein The plurality of subcommands are selected from a predefined subcommand table, the predefined subcommand table comprising a plurality of predefined subcommands, the predefined subcommand table being a predefined universal command set that can be recognized by both the host system and the memory controller, wherein one of the command sequences in the first command sequence table and one of the command sequences in the second command sequence table implement the same function but comprise different predefined subcommands; In response to a call instruction sent by the host system, selecting a corresponding command sequence in the command sequence table according to an index value in the call instruction; and The corresponding command sequence is parsed to obtain the contained sub-commands, and the memory module is controlled according to the data parameters in the calling instruction and the obtained sub-commands.

8. The memory control method according to claim 7, characterized in that: After receiving and storing the command sequence table corresponding to the memory module generated by the host system, the method further includes: If a new command sequence list is received from the host system, the newly received command sequence list is stored to replace the current command sequence list.

9. The memory control method according to claim 7, characterized in that: Also includes: The memory controller cannot add, modify or delete the command sequence in the command sequence table.

10. A storage device, characterized in that: include: A connection interface unit for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface unit and the memory module; The memory controller is used to obtain the identification information of the memory module and transmit it to the host system in response to the identification instruction sent by the host system; for receiving and storing a command sequence table corresponding to the memory module generated by the host system, wherein the command sequence table includes a plurality of command sequences and their corresponding index values, each of the plurality of command sequences includes a plurality of sub-commands, when the identification information is the first identification information, the command sequence table is a first command sequence table; when the identification information is the second identification information, the command sequence table is a second command sequence table, the first command sequence table is different from the second command sequence table; wherein the plurality of sub-commands are selected from a predefined sub-command table, the predefined sub-command table includes a plurality of predefined sub-commands, the predefined sub-command table is a pre-set universal command set that can be commonly recognized by the host system and the memory controller, wherein one of the command sequences in the first command sequence table and one of the command sequences in the second command sequence table implement the same function but include different predefined sub-commands; In response to a call instruction sent by the host system, select a corresponding command sequence in the command sequence table according to an index value in the call instruction; and The method is used to parse the corresponding command sequence to obtain the contained sub-commands, and control the memory module according to the data parameters in the calling instruction and the obtained sub-commands.

11. The storage device according to claim 10, characterized in that: The first command sequence list is different from the second command sequence list in that: The order of the plurality of command sequences in the first command sequence list is different from the order of the plurality of command sequences in the second command sequence list; or The number of the plurality of command sequences in the first command sequence list is different from the number of the plurality of command sequences in the second command sequence list.

12. The storage device according to claim 10, characterized in that: The first command sequence list is different from the second command sequence list and further includes: The first command sequence in the first command sequence list includes a first subcommand, and the second command sequence in the second command sequence list includes a second subcommand; The operation code of the first subcommand is the same as the operation code of the second subcommand and the execution parameter of the first subcommand is different from the execution parameter of the second subcommand.

13. The storage device according to claim 10, characterized in that: Also includes: The memory controller cannot add, modify or delete the command sequence in the command sequence table.

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