Processor reliability testing methods, apparatus, computer equipment, and storage media

Abstract

The present application relates to the field of device testing technology, and in particular to a processor reliability testing method, device, computer equipment, computer-readable storage medium, and computer program product. The method comprises: building a test board for a digital signal processor to be tested, setting test parameters of the test board; obtaining a corresponding test program according to the test items; setting different test environment conditions, and running the corresponding test program to perform reliability testing on the digital signal processor to be tested; and obtaining reliability test evaluation results based on the obtained test data. This method can simulate harsh environments in real application scenarios, accurately evaluate the performance of devices, and improve test efficiency and reliability.

Description

Technical Field

[0001] The present application relates to the field of device testing technology, and in particular to a processor reliability testing method, apparatus, computer equipment, computer-readable storage medium, and computer program product. Background Art

[0002] With the rapid development of information technology, digital signal processors are increasingly used in communications, radar and other fields. However, under special environmental conditions, such as high and low temperatures, high humidity, vibration, etc., the performance evaluation of digital signal processors has become an important challenge.

[0003] At present, ATE testing is the main method for evaluating the performance of digital signal processors, but it has many shortcomings. First, the development cycle of ATE testing is long, the technology is difficult, and the cost is high. Second, ATE testing is usually performed in a fixed environment and cannot simulate the special environmental conditions in real application scenarios. In addition, ATE testing usually uses a test socket, which is quite different from the actual use environment and cannot accurately evaluate the performance of the device in actual applications.

[0004] Therefore, it is necessary to develop a new test method that can evaluate the performance of digital signal processors under special environmental conditions. Such a device should be able to simulate the harsh environment in real application scenarios, accurately evaluate the performance of the device, and improve test efficiency and reliability. Summary of the invention

[0005] Based on this, it is necessary to provide a processor reliability testing method, device, computer equipment, computer-readable storage medium and computer program product that can simulate the harsh environment in real application scenarios, accurately evaluate the performance of devices, and improve test efficiency and reliability in response to the above technical problems.

[0006] In a first aspect, the present application provides a processor reliability testing method, comprising:

[0007] Building a test board for the digital signal processor to be tested, and setting test parameters of the test board;

[0008] According to the test items, obtain the corresponding test procedures;

[0009] Set different test environment conditions and run corresponding test programs to perform reliability tests on the digital signal processor under test;

[0010] Based on the obtained test data, obtain the reliability test evaluation results.

[0011] In one embodiment, the test items include power-on timing test, reset timing test, serial peripheral interface test, IIC bus test, serial RapidIO interface test, PCI Express bus test, dynamic random access memory test, interrupt test and power consumption test.

[0012] In one embodiment, the test environment conditions include: temperature cycle conditions, temperature shock conditions, air pressure conditions, power supply pull conditions and vibration shock conditions.

[0013] In one embodiment, setting different test environment conditions and running corresponding test programs to perform reliability testing on the digital signal processor to be tested includes:

[0014] Connecting the digital signal processor to be tested to the test board for communication;

[0015] Determine the current test environment conditions, place the test board in a test module having the current test environment conditions, and establish a communication connection between the test board and a host computer;

[0016] Run the corresponding test program to perform reliability test on the digital signal processor under test.

[0017] In one embodiment, obtaining the reliability test evaluation result according to the obtained test data includes:

[0018] Acquiring test data of the digital signal processor to be tested through the field programmable logic gate array module in the test board;

[0019] The test data is displayed by the host computer, and the reliability test evaluation result is obtained.

[0020] In a second aspect, the present application also provides a processor reliability testing device, comprising:

[0021] The device comprises a preprocessing module, an acquisition module, a test module, a test board and a host computer;

[0022] The preprocessing module is used to build a test board for the digital signal processor to be tested and set test parameters of the test board;

[0023] The acquisition module is used to acquire the corresponding test program according to the test item;

[0024] The test module is used to set different test environment conditions and run corresponding test programs to perform reliability tests on the digital signal processor to be tested;

[0025] The host computer is used to obtain reliability test evaluation results based on the obtained test data.

[0026] In one of the embodiments, the test board includes a field programmable gate array module;

[0027] The field programmable logic gate array module is used to assemble different types of digital signal processors to be tested, and to transmit and receive data with the digital signal processor to be tested through the interface EMIF, the interface GPIO, the interface SRIO, and the interface PCIE.

[0028] In one of the embodiments, the test board includes a storage module and a clock distribution module;

[0029] The storage module includes DDR3 memory, EEPROM memory and FLASH memory, and reads and writes data through the interface EMIF, interface IIC and interface SPI;

[0030] The clock distribution module uses a crystal oscillator as a clock source, generates differential clock signals of different frequencies after frequency multiplication through a clock generation chip, and transmits the differential clock signals to the field programmable logic gate array module and the digital signal processor to be tested.

[0031] In one of the embodiments, the test module is further used to establish a communication connection between the digital signal processor to be tested and the test board;

[0032] Determine the current test environment conditions, place the test board in a test module having the current test environment conditions, and establish a communication connection between the test board and a host computer;

[0033] Run the corresponding test program to perform reliability test on the digital signal processor under test.

[0034] In one of the embodiments, the host computer is further used to obtain test data of the digital signal processor to be tested through the field programmable logic gate array module in the test board;

[0035] The test data is displayed by the host computer, and the reliability test evaluation result is obtained.

[0036] The above-mentioned processor reliability test method, device, computer equipment, computer-readable storage medium and computer program product can more accurately evaluate the performance of digital signal processors in practical applications by simulating harsh environments in real application scenarios, such as high and low temperatures, high humidity, vibration, etc. This is significantly improved compared to the traditional ATE test, which is carried out in a fixed environment and cannot simulate the limitations of real environmental conditions. By building a test board for the digital signal processor to be tested and obtaining the corresponding test program according to the test items, the reliability test of the device to be tested can be carried out in a targeted manner. This avoids the problems of long ATE test development cycle, high technical difficulty, high cost, etc., and improves the efficiency of the test. At the same time, due to the authenticity of the test environment and the pertinence of the test program, the reliability of the test results is also enhanced. By setting different test environment conditions and running the corresponding test program, a comprehensive reliability test can be carried out on the digital signal processor to be tested. This test method is suitable for performance testing under a single environmental condition and for comprehensive performance testing under multiple environmental conditions, and has high flexibility. Since this method does not require the use of special ATE test equipment, but is tested by building a test board and running the test program, the test process is simplified and the test cost is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 An application environment diagram of a processor reliability testing method in one embodiment;

[0039] Figure 2 is a flowchart of a processor reliability testing method in one embodiment;

[0040] Figure 3 is a flowchart of a processor reliability testing method in another embodiment;

[0041] Figure 4 is a structural block diagram of a processor reliability testing device in one embodiment;

[0042] Figure 5 A detailed structural diagram of the connection between the test board and the host computer in an embodiment;

[0043] Figure 6 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0045] The processor reliability testing method provided in the embodiment of the present application can be applied to Figure 1 In the application environment shown, the terminal 102 communicates with the server 104 through a network. The data storage system can store data that the server 104 needs to process. The data storage system can be integrated on the server 104, or placed on the cloud or other network servers.

[0046] The terminal 102 obtains the corresponding test program according to the test items, sets different test environment conditions, and runs the corresponding test program to perform reliability tests on the digital signal processor to be tested; and obtains the reliability test evaluation results according to the obtained test data. Among them, the terminal 102 can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, Internet of Things devices and portable wearable devices. The Internet of Things devices can be smart speakers, smart TVs, smart air conditioners, smart car-mounted devices, etc. Portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc. The server 104 can be implemented as an independent server or a server cluster consisting of multiple servers.

[0047] In an exemplary embodiment, Figure 2 As shown, a processor reliability testing method is provided, which is applied to Figure 1 The terminal (host computer) in is used as an example to illustrate, including the following steps S202 to S208. Among them:

[0048] Step S202: construct a test board for the digital signal processor to be tested, and set test parameters of the test board.

[0049] Specifically, first of all, the purpose of building a test board is to provide a dedicated and controllable test environment for performance testing of the digital signal processor to be tested. This test board is usually composed of a power supply, FPGA and other auxiliary devices, which together build a complete test system. In this system, FPGA, as the core control unit, is responsible for controlling the key operations such as the power-on timing and reset timing of the DSP (digital signal processor to be tested) to be tested, and monitoring key parameters such as the power consumption of the DSP. At the same time, other components on the test board, such as power modules and storage modules, also provide necessary support and guarantee for the normal operation of the DSP. Secondly, the test parameters of the test board are set to simulate various conditions in actual use scenarios to evaluate the performance of the digital signal processor under different conditions. These test parameters may include power supply voltage, operating temperature range, vibration intensity, etc., which directly affect the performance and stability of the DSP. By accurately setting these parameters, testers can simulate various environmental conditions that the DSP may encounter in actual applications, thereby comprehensively evaluating its performance.

[0050] In the process of building the test board, the communication interface and protocol between the board and the host computer (PC) must be considered to ensure real-time transmission and processing of test data. At the same time, the layout and wiring of the board must also be considered to reduce the impact of electromagnetic interference and noise on the test results.

[0051] Step S204: Obtain corresponding test program according to the test item.

[0052] Specifically, test items are usually formulated based on the functions, performance, compatibility, etc. of digital signal processors, such as testing the power-on timing, reset timing, interrupt function, power consumption, etc. of DSP. Each test item has its specific test objectives and requirements, so it is necessary to select or develop corresponding test programs in a targeted manner. Secondly, obtaining test programs requires considering the source and quality of the test programs. Test programs may be developed by a dedicated testing team, or they may come from an open source community or a third-party organization. When obtaining test programs, it is necessary to ensure that they are suitable for the current test environment and test object, and that they have been fully verified and debugged to ensure their accuracy and reliability.

[0053] Step S206, setting different test environment conditions and running corresponding test programs to perform reliability tests on the digital signal processor to be tested.

[0054] Specifically, different test environment conditions are set to simulate various actual application scenarios that the DSP may encounter. These environmental conditions may include factors such as temperature, humidity, vibration, etc., all of which may affect the performance and stability of the DSP. By testing under various conditions, the reliability of the DSP can be evaluated more comprehensively. Secondly, running the corresponding test program is to perform specific performance tests on the DSP under specific environmental conditions. These test programs may include various types such as bit error rate testing, spectrum analysis, eye diagram testing, etc., which are designed to evaluate key indicators such as the signal processing capability and anti-interference capability of the DSP under different conditions.

[0055] Step S208: Obtain reliability test evaluation results based on the obtained test data.

[0056] Specifically, the test data records various performance indicators of the digital signal processor when running the test program under different test environment conditions. These test data may include signal processing accuracy, power consumption changes, temperature stability and other aspects, which together constitute the basis for evaluating reliability. Next, these data need to be processed and analyzed. This includes data cleaning, sorting, statistics and comparison. By eliminating abnormal data, calculating statistics such as average and standard deviation, we can get a preliminary understanding of the performance of the digital signal processor. At the same time, the test data can also be compared with the standard value or expected value to determine whether the processor meets the design requirements. Based on the data analysis, the reliability test evaluation results can be further obtained. These results may include: 1. Whether the performance indicators of the digital signal processor meet the design requirements and actual application needs. 2. How stable is the processor under different environmental conditions, and whether there are obvious performance fluctuations or failure points. 3. Compared with similar products or previous versions of processors, what is the reliability level of the processor to be tested.

[0057] In the above-mentioned processor reliability test method, by simulating the harsh environment in the real application scenario, such as high and low temperature, high humidity, vibration, etc., the performance of the digital signal processor in the actual application can be more accurately evaluated. Compared with the traditional ATE test, which is carried out in a fixed environment and cannot simulate the limitations of the real environmental conditions, it has been significantly improved. By building a test board for the digital signal processor to be tested and obtaining the corresponding test program according to the test project, the reliability test of the device to be tested can be carried out in a targeted manner. This avoids the problems of long ATE test development cycle, high technical difficulty, high cost, etc., and improves the efficiency of the test. At the same time, due to the authenticity of the test environment and the pertinence of the test program, the reliability of the test results is also enhanced. By setting different test environment conditions and running the corresponding test program, a comprehensive reliability test can be carried out on the digital signal processor to be tested. This test method is suitable for performance testing under a single environmental condition and for comprehensive performance testing under multiple environmental conditions, and has high flexibility. Since this method does not require the use of special ATE test equipment, but is tested by building a test board and running the test program, the test process is simplified and the test cost is reduced.

[0058] In an exemplary embodiment, the test items include power-on timing test, reset timing test, serial peripheral interface test, IIC bus test, serial RapidIO interface test, PCI Express bus test, dynamic random access memory test, interrupt test and power consumption test.

[0059] Specifically, the test items cover power-on timing test, reset timing test, serial peripheral interface test, IIC bus test, serial RapidIO interface test, PCI Express bus test, dynamic random access memory test, interrupt test and power consumption test. These tests are all to ensure the stability and reliability of the product and meet the design requirements and usage scenarios.

[0060] Power-on sequence test: The power supply of DSP is composed of a separate power chip. The enablement of the DSP power supply chip is controlled by FPGA (field programmable gate array module) to achieve precise control of the power-on sequence and test of the power-on sequence. Mainly focus on the power-on sequence and stability to ensure that each component is powered at the right time to avoid current shock and component damage.

[0061] Reset timing test: The reset timing of DSP is generated by FPGA to achieve accurate control and test of reset timing. Check the timing correctness of reset operation to ensure that the system can correctly restore to the initial state under abnormal conditions.

[0062] Serial peripheral interface test (SPI test): The DSP's general SPI port is connected to an SPI NOR FLASH, and the DSP SPI function is tested by reading and writing data in the FLASH. The communication interface between the digital signal processor and the external serial device is tested to verify the correctness and stability of data transmission.

[0063] IIC bus test: The DSP's general IIC port is connected to an EEPORM chip, and the DSPIIC function is tested by reading and writing data from the chip. As a two-wire interface, the IIC bus is widely used in the communication between microcontrollers and sensors and other devices. During the test, the timing integrity of the IIC bus is mainly focused on to ensure that the signal transmission is correct.

[0064] Serial RapidIO interface test (SRIO test): The SRIO port of the DSP is connected to the FPGA, and the DSP SRIO function is verified by sending and receiving data with the FPGA's SRIO function and doorbell test. Test the interconnection technology of high-performance embedded systems to verify its stability and reliability in high-speed data transmission.

[0065] PCI Express bus test (PCIE test): The PCIE port of DSP is connected to FPGA, DSP is used as RC port, FPGA is used as EP port, and DSP PCIE function is tested by sending and receiving data with FPGA PCIE function. PCI Express is a new bus technology, mainly used to improve data transmission rate. When testing, you need to pay attention to its performance in high-speed data transmission.

[0066] Dynamic random access memory test (DDR3 test): The DDR port of DSP is connected to an external DDR3 chip, and the DSP DDR function is tested by reading and writing the data of the DDR3. Verify the performance and stability of the memory module, ensure that data is read and written correctly, and prevent data loss or damage.

[0067] Interrupt test: DSP interrupts can be generated by GPIO ports. GPIO is connected to an external FPGA, and the FPGA generates an excitation signal to test the DSP interrupt function. Check whether the processor's interrupt handling mechanism works properly to ensure that it can be handled in time when an external event is triggered.

[0068] Power consumption test: The power supply of DSP is composed of a separate power chip. The power supply current of each DSP is detected by detecting the current passing through the shunt detection chip to calculate the power consumption of DSP. Test the power consumption performance of the product under different working conditions to ensure that it meets the performance requirements while also meeting the design requirements.

[0069] In this embodiment, these test items comprehensively check the digital signal processor from multiple dimensions to ensure its stability and reliability in a complex working environment. Through these tests, potential problems can be discovered in a timely manner, providing a basis for product optimization and improvement.

[0070] In an exemplary embodiment, the test environment conditions include: temperature cycle conditions, temperature shock conditions, air pressure conditions, power pull conditions and vibration shock conditions.

[0071] Specifically, the temperature cycling condition simulates the repeated conversion of the product between extreme temperatures to test its durability and stability in different temperature environments. The temperature shock condition simulates the rapid change of the atmospheric temperature around the product, such as when the device is quickly transferred to a different temperature environment. This test is designed to test the adaptability and shock resistance of the product under extreme temperature changes to ensure its reliability in various practical application scenarios. Air pressure conditions are also an important part of the test. Under conditions such as high pressure, high temperature, high humidity or low temperature, low air pressure, operators may experience symptoms such as headaches, dizziness, nausea, and even personal injury accidents. Therefore, measuring the air pressure in the production environment helps to detect unsafe production environments in a timely manner and improve the safety of operations. The power pull condition simulates the unstable power supply to test the stability and reliability of the product under such conditions. The vibration shock condition simulates the use of the product in a vibration and shock environment to evaluate whether it can withstand various environmental factors in actual use.

[0072] In this embodiment, these test environment conditions together constitute an important part of the product reliability test. By testing under these conditions, the performance and reliability of the product can be fully evaluated, providing strong support for the design, optimization and production of the product.

[0073] In an exemplary embodiment, Figure 3 As shown, different test environment conditions are set and corresponding test programs are run to perform reliability tests on the digital signal processor to be tested, including:

[0074] Step S302, establishing a communication connection between the digital signal processor to be tested and the test board;

[0075] Step S304, determining the current test environment conditions, placing the test board in a test module having the current test environment conditions, and establishing a communication connection between the test board and the host computer;

[0076] Step S306: Run the corresponding test program to perform reliability test on the digital signal processor to be tested.

[0077] Specifically, determining the current test environment conditions involves selecting appropriate test environment conditions, such as temperature cycle conditions, temperature shock conditions, air pressure conditions, power supply pull-off conditions, or vibration shock conditions, according to the test plan or test requirements. The selection of these conditions should simulate as many environmental scenarios as possible that the processor may encounter in actual applications. Subsequently, the test board is placed in a test module with the current test environment conditions. The test module is a specially designed device that provides specific environmental conditions and ensures that the test board operates stably under these conditions. In this way, the digital signal processor to be tested can be tested under conditions similar to the actual use environment. At the same time, it is also necessary to communicate with the host computer. As the control center of the test system, the host computer is responsible for sending test instructions, receiving test data, and performing corresponding processing and analysis. Through the communication connection with the host computer, the tester can monitor the test progress in real time, obtain test data, and accurately evaluate the test results. Finally, according to the current test environment conditions, select or write a suitable test program to perform reliability testing on the digital signal processor to be tested. These test procedures may include power-on timing test, reset timing test, interface test, power consumption test and other aspects, aiming to comprehensively evaluate the performance and stability of the processor under different conditions.

[0078] In this embodiment, a comprehensive reliability test can be performed on the digital signal processor to be tested, thereby ensuring that it can work stably and reliably in practical applications. This not only helps to improve the quality and reliability of the product, but also provides strong support for product optimization and improvement.

[0079] In an exemplary embodiment, obtaining a reliability test evaluation result according to the obtained test data includes:

[0080] The test data of the digital signal processor to be tested is obtained by testing the field programmable logic gate array module in the board; the test data is displayed on the host computer, and the reliability test evaluation result is obtained.

[0081] Specifically, various test data of the digital signal processor to be tested can be captured in real time through the field programmable gate array (FPGA) module in the test board. Due to its programmability and high-speed processing capabilities, the FPGA module can accurately record the working status and performance indicators of the processor under different test conditions. These test data include but are not limited to timing information, signal quality, power consumption data, etc., which directly reflect the performance and reliability of the processor. Then, these test data are transmitted to the host computer through a specific communication interface. As the center of data processing and analysis, the host computer has powerful computing power and rich software resources. It can not only display the test data in real time, so that the tester can intuitively understand the performance status of the processor, but also conduct in-depth analysis and processing of the test data. On the host computer, special test software will process and analyze the test data according to preset algorithms and models. These software can automatically calculate various performance indicators, such as bit error rate, power efficiency, timing stability, etc., and compare them with preset standards or thresholds. Based on these comparison results, the software will generate a reliability test evaluation report, clearly indicating in which aspects the processor performs well and in which aspects there are potential problems or need to be improved.

[0082] In this embodiment, the test data is obtained through the FPGA module, and is displayed and analyzed through the host computer, and finally the reliability test evaluation result is obtained, which can not only comprehensively evaluate the reliability of the digital signal processor to be tested, but also provide strong data support for product optimization and improvement.

[0083] In an exemplary embodiment, the test board includes a field programmable gate array module;

[0084] The field programmable logic gate array module is used to assemble different types of digital signal processors to be tested, and to transmit and receive data with the digital signal processor to be tested through the interface EMIF, interface GPIO, interface SRIO, and interface PCIE.

[0085] In an exemplary embodiment, the test board includes a storage module and a clock distribution module;

[0086] The storage module includes DDR3 memory, EEPROM memory and FLASH memory, and reads and writes data through the interface EMIF, interface IIC and interface SPI;

[0087] The clock distribution module uses a crystal oscillator as the clock source, generates differential clock signals of different frequencies after frequency multiplication through a clock generation chip, and transmits the differential clock signals to the field programmable logic gate array module and the digital signal processor under test.

[0088] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0089] Based on the same inventive concept, the embodiment of the present application also provides a processor reliability test device for implementing the above-mentioned processor reliability test method. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above-mentioned method, so the specific limitations in one or more processor reliability test device embodiments provided below can refer to the above-mentioned limitations on the processor reliability test method, and will not be repeated here.

[0090] In an exemplary embodiment, Figure 4 As shown, a processor reliability testing device is provided, including: a preprocessing module 402, an acquisition module 404, a testing module 406, a testing board 408 and a host computer 410;

[0091] The preprocessing module 402 is used to build a test board 408 of the digital signal processor to be tested and set test parameters of the test board 408;

[0092] The acquisition module 404 is used to acquire the corresponding test program according to the test item;

[0093] The test module 406 is used to set different test environment conditions and run corresponding test programs to perform reliability tests on the digital signal processor to be tested;

[0094] The host computer 410 is used to obtain reliability test evaluation results based on the obtained test data.

[0095] In one embodiment, the test board 408 includes a field programmable gate array module;

[0096] The field programmable logic gate array module is used to assemble different types of digital signal processors to be tested, and to transmit and receive data with the digital signal processor to be tested through the interface EMIF, interface GPIO, interface SRIO, and interface PCIE.

[0097] In one embodiment, the test board 408 includes a storage module and a clock distribution module;

[0098] The storage module includes DDR3 memory, EEPROM memory and FLASH memory, and reads and writes data through the interface EMIF, interface IIC and interface SPI;

[0099] The clock distribution module uses a crystal oscillator as the clock source, generates differential clock signals of different frequencies after frequency multiplication through a clock generation chip, and transmits the differential clock signals to the field programmable logic gate array module and the digital signal processor under test.

[0100] In one embodiment, the test module 406 is further used to establish a communication connection between the digital signal processor to be tested and the test board 408;

[0101] Determine the current test environment conditions, place the test board 408 in the test module 406 having the current test environment conditions, and establish a communication connection between the test board 408 and the host computer 410;

[0102] Run the corresponding test program to perform reliability test on the digital signal processor under test.

[0103] In one embodiment, the host computer 410 is also used to obtain test data of the digital signal processor to be tested through the field programmable logic gate array module in the test board 408;

[0104] The host computer 410 displays the test data and obtains the reliability test evaluation results.

[0105] In one embodiment, the test items include power-on timing test, reset timing test, serial peripheral interface test, IIC bus test, serial RapidIO interface test, PCI Express bus test, dynamic random access memory test, interrupt test and power consumption test.

[0106] In one embodiment, the test environment conditions include: temperature cycle conditions, temperature shock conditions, air pressure conditions, power supply pull conditions and vibration shock conditions.

[0107] In a detailed embodiment, Figure 5 As shown, Figure 5 To test the connection between the board and the host computer, a detailed structural diagram is provided; the host computer (PC) is bidirectionally connected to the FPGA through a communication module, and the host computer is installed with display and control software, and the control program and data processing and storage are input through the host computer.

[0108] The power module uses a DC-DC circuit to provide the +3.3V, +1.0V, +1.8V, +2.5V, +0.9V and other voltages required by the DSP and peripheral devices. The input end of the DC-DC circuit is protected by a TVS diode to prevent the input voltage from being too high and damaging the devices on the board. At the same time, a filter network composed of magnetic beads and filter capacitors is installed to filter out the noise brought by the power line and prevent it from affecting the normal operation of the test board.

[0109] The power-on timing, reset timing, interrupt testing, power consumption monitoring, and communication with the industrial computer of the DSP under test are all completed by the control FPGA. The test results of the DSP device under test are fed back through the FPGA and returned to the host computer for display. The test status of the digital signal processor is monitored by the host computer.

[0110] DSP is the digital signal processor to be tested. It completes data transmission and reception with FPGA through EMIF, GPIO, SRIO, PCIE and other interfaces, and realizes the control and logic implementation of FPGA on digital signal processor testing. The device can be equipped with different models of digital signal processors.

[0111] The JTAG port is a debugging interface. DSP and FPGA download debugging programs through the JTAG interface to drive the normal operation of the device.

[0112] The status indicator is an LED display array, which indicates the working status of the FPGA and DSP, such as the hard reset status and program loading status, by turning the LED "on" or "off".

[0113] The storage module includes DDR3, EEPROM and FLASH memory, and the reading and writing of the memory are realized through EMIF, IIC and SPI interfaces.

[0114] The clock distribution uses a crystal oscillator as the clock source, and after frequency multiplication by the clock generation chip, differential clocks of different frequencies are generated and output to the external system.

[0115] The test software for writing software programs is mainly developed for FPGA. The human-computer interaction software part of the software is designed as a general-purpose automated test management platform software, which implements the test of digital signal processors by loading different test subroutines. The test program development software is built based on LabVIEW and Teststand, and supports third-party development tools such as VC. LabVIEW can be used to develop test subroutines, display interfaces or packaged drivers, and can also be used to develop complex or relatively independent test cases. Teststand is used to write test scripts, and test subroutines, interfaces or packaged drivers are organized into a test case using a scripting language. A group of test cases forms a test case set, which realizes the development of test items required for digital signal processors.

[0116] Each module in the above processor reliability test device can be implemented in whole or in part by software, hardware and their combination. Each module can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to each module above.

[0117] In an exemplary embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as shown in FIG. Figure 6 As shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a processor reliability test method is implemented. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse.

[0118] Those skilled in the art will understand that Figure 6 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0119] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented:

[0120] Build the test board of the digital signal processor to be tested and set the test parameters of the test board;

[0121] According to the test items, obtain the corresponding test procedures;

[0122] Set different test environment conditions and run corresponding test programs to perform reliability tests on the digital signal processor under test;

[0123] Based on the obtained test data, obtain the reliability test evaluation results.

[0124] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0125] The test items include power-on timing test, reset timing test, serial peripheral interface test, IIC bus test, serial RapidIO interface test, PCI Express bus test, dynamic random access memory test, interrupt test and power consumption test.

[0126] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0127] The test environment conditions include: temperature cycle conditions, temperature shock conditions, air pressure conditions, power supply pull conditions and vibration shock conditions.

[0128] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0129] Set different test environment conditions and run corresponding test programs to perform reliability tests on the digital signal processor under test, including:

[0130] Connecting the digital signal processor to be tested to the test board for communication;

[0131] Determine the current test environment conditions, place the test board in a test module having the current test environment conditions, and establish a communication connection between the test board and the host computer;

[0132] Run the corresponding test program to perform reliability test on the digital signal processor under test.

[0133] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0134] Based on the obtained test data, obtain reliability test evaluation results, including:

[0135] Acquire test data of the digital signal processor to be tested by testing the field programmable logic gate array module in the board;

[0136] The test data is displayed on the host computer, and the reliability test evaluation results are obtained.

[0137] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0138] The test board includes a field programmable logic gate array module;

[0139] The field programmable logic gate array module is used to assemble different types of digital signal processors to be tested, and to transmit and receive data with the digital signal processor to be tested through the interface EMIF, interface GPIO, interface SRIO, and interface PCIE.

[0140] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0141] The test board includes a storage module and a clock distribution module;

[0142] The storage module includes DDR3 memory, EEPROM memory and FLASH memory, and reads and writes data through the interface EMIF, interface IIC and interface SPI;

[0143] The clock distribution module uses a crystal oscillator as the clock source, generates differential clock signals of different frequencies after frequency multiplication through a clock generation chip, and transmits the differential clock signals to the field programmable logic gate array module and the digital signal processor under test.

[0144] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0145] Build the test board of the digital signal processor to be tested and set the test parameters of the test board;

[0146] According to the test items, obtain the corresponding test procedures;

[0147] Set different test environment conditions and run corresponding test programs to perform reliability tests on the digital signal processor under test;

[0148] Based on the obtained test data, obtain the reliability test evaluation results.

[0149] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0150] The test items include power-on timing test, reset timing test, serial peripheral interface test, IIC bus test, serial RapidIO interface test, PCI Express bus test, dynamic random access memory test, interrupt test and power consumption test.

[0151] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0152] The test environment conditions include: temperature cycle conditions, temperature shock conditions, air pressure conditions, power supply pull conditions and vibration shock conditions.

[0153] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0154] Set different test environment conditions and run corresponding test programs to perform reliability tests on the digital signal processor under test, including:

[0155] Connecting the digital signal processor to be tested to the test board for communication;

[0156] Determine the current test environment conditions, place the test board in a test module having the current test environment conditions, and establish a communication connection between the test board and the host computer;

[0157] Run the corresponding test program to perform reliability test on the digital signal processor under test.

[0158] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0159] Based on the obtained test data, obtain reliability test evaluation results, including:

[0160] Acquire test data of the digital signal processor to be tested by testing the field programmable logic gate array module in the board;

[0161] The test data is displayed on the host computer, and the reliability test evaluation results are obtained.

[0162] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0163] The test board includes a field programmable logic gate array module;

[0164] The field programmable logic gate array module is used to assemble different types of digital signal processors to be tested, and to transmit and receive data with the digital signal processor to be tested through the interface EMIF, interface GPIO, interface SRIO, and interface PCIE.

[0165] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0166] The test board includes a storage module and a clock distribution module;

[0167] The storage module includes DDR3 memory, EEPROM memory and FLASH memory, and reads and writes data through the interface EMIF, interface IIC and interface SPI;

[0168] The clock distribution module uses a crystal oscillator as the clock source, generates differential clock signals of different frequencies after frequency multiplication through a clock generation chip, and transmits the differential clock signals to the field programmable logic gate array module and the digital signal processor under test.

[0169] In one embodiment, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the following steps:

[0170] Build the test board of the digital signal processor to be tested and set the test parameters of the test board;

[0171] According to the test items, obtain the corresponding test procedures;

[0172] Set different test environment conditions and run corresponding test programs to perform reliability tests on the digital signal processor under test;

[0173] Based on the obtained test data, obtain the reliability test evaluation results.

[0174] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0175] The test items include power-on timing test, reset timing test, serial peripheral interface test, IIC bus test, serial RapidIO interface test, PCI Express bus test, dynamic random access memory test, interrupt test and power consumption test.

[0176] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0177] The test environment conditions include: temperature cycle conditions, temperature shock conditions, air pressure conditions, power supply pull conditions and vibration shock conditions.

[0178] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0179] Set different test environment conditions and run corresponding test programs to perform reliability tests on the digital signal processor under test, including:

[0180] Connecting the digital signal processor to be tested to the test board for communication;

[0181] Determine the current test environment conditions, place the test board in a test module having the current test environment conditions, and establish a communication connection between the test board and the host computer;

[0182] Run the corresponding test program to perform reliability test on the digital signal processor under test.

[0183] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0184] Based on the obtained test data, obtain reliability test evaluation results, including:

[0185] Acquire test data of the digital signal processor to be tested by testing the field programmable logic gate array module in the board;

[0186] The test data is displayed on the host computer, and the reliability test evaluation results are obtained.

[0187] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0188] The test board includes a field programmable logic gate array module;

[0189] The field programmable logic gate array module is used to assemble different types of digital signal processors to be tested, and to transmit and receive data with the digital signal processor to be tested through the interface EMIF, interface GPIO, interface SRIO, and interface PCIE.

[0190] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0191] The test board includes a storage module and a clock distribution module;

[0192] The storage module includes DDR3 memory, EEPROM memory and FLASH memory, and reads and writes data through the interface EMIF, interface IIC and interface SPI;

[0193] The clock distribution module uses a crystal oscillator as the clock source, generates differential clock signals of different frequencies after frequency multiplication through a clock generation chip, and transmits the differential clock signals to the field programmable logic gate array module and the digital signal processor under test.

[0194] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0195] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0196] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0197] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A processor reliability testing method, characterized in that: The method comprises: Building a test board for the digital signal processor to be tested, and setting test parameters of the test board; According to the test items, obtain the corresponding test procedures; Connecting the digital signal processor to be tested to the test board for communication; Determine the current test environment conditions, place the test board in a test module having the current test environment conditions, and establish a communication connection between the test board and a host computer; Run the corresponding test program to perform reliability test on the digital signal processor to be tested; Acquiring test data of the digital signal processor to be tested through the field programmable logic gate array module in the test board; The test data is displayed by the host computer, and the reliability test evaluation result is obtained.

2. The method according to claim 1, characterized in that The test items include power-on timing test, reset timing test, serial peripheral interface test, IIC bus test, serial RapidIO interface test, PCI Express bus test, dynamic random access memory test, interrupt test and power consumption test.

3. The method according to claim 1, characterized in that The test environment conditions include: temperature cycle conditions, temperature shock conditions, air pressure conditions, power supply pull conditions and vibration shock conditions.

4. A processor reliability testing device, characterized in that: The device comprises a preprocessing module, an acquisition module, a test module, a test board and a host computer; The preprocessing module is used to build a test board for the digital signal processor to be tested and set test parameters of the test board; The acquisition module is used to acquire the corresponding test program according to the test item; The test module is used to establish a communication connection between the digital signal processor to be tested and the test board; determine the current test environment conditions, place the test board in the test module with the current test environment conditions, and establish a communication connection between the test board and the host computer; run the corresponding test program to perform a reliability test on the digital signal processor to be tested; The host computer is used to obtain test data of the digital signal processor to be tested through the field programmable logic gate array module in the test board; it is also used to display the test data and obtain reliability test evaluation results.

5. The processor reliability testing device according to claim 4, characterized in that: The test board includes a field programmable logic gate array module; The field programmable logic gate array module is used to assemble different types of digital signal processors to be tested, and to transmit and receive data with the digital signal processor to be tested through the interface EMIF, the interface GPIO, the interface SRIO, and the interface PCIE.

6. The processor reliability testing device according to claim 5, characterized in that: The test board includes a storage module and a clock distribution module; The storage module includes DDR3 memory, EEPROM memory and FLASH memory, and reads and writes data through the interface EMIF, interface IIC and interface SPI; The clock distribution module uses a crystal oscillator as a clock source, generates differential clock signals of different frequencies after frequency multiplication through a clock generation chip, and transmits the differential clock signals to the field programmable logic gate array module and the digital signal processor to be tested.

7. The processor reliability testing device according to claim 4, characterized in that: The test module is also used to establish a communication connection between the digital signal processor to be tested and the test board; Determine the current test environment conditions, place the test board in a test module having the current test environment conditions, and establish a communication connection between the test board and a host computer; Run the corresponding test program to perform reliability test on the digital signal processor under test.

8. The processor reliability testing device according to claim 4, characterized in that: The host computer is also used to obtain test data of the digital signal processor to be tested through the field programmable logic gate array module in the test board; The test data is displayed by the host computer, and the reliability test evaluation result is obtained.

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