Circuit for transmitting end information of data stream, data transmission chip and electronic device

Abstract

The present disclosure provides a circuit, a data transmission chip, and an electronic device for transmitting end-of-data-stream information. The circuit includes a counting module that counts the length of a data stream received from the link layer and sends an indication to insert end-of-data-stream information when the count value reaches a preset value; an end-of-data-stream information generation module that, in response to the indication to insert end-of-data-stream information, rewrites the packet identifier of the link layer transmission unit at the boundary in the data stream, wherein the rewritten packet identifier of the link layer transmission unit at the boundary implies end-of-data-stream information, and the link layer transmission unit at the boundary corresponds to the boundary of the physical channel; and a physical channel interface that sends the data stream including the rewritten link layer transmission unit at the boundary to the physical channel. Through the circuit, the data transmission chip, and the electronic device for transmitting end-of-data-stream information provided by the present disclosure, a simple and effective implementation manner for inserting EDS in the manner required by the CXL protocol is provided.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of high-speed interfaces, and in particular, to a circuit for transmitting end-of-data-stream information, a data transmission chip, and an electronic device. Background Art

[0002] The Compute Express Link (CXL) protocol is a cache-coherent interconnect protocol for processors, memory expansion, and accelerators. The CXL protocol is built on top of PCIe (Peripheral Component Interconnect Express), and extends and optimizes memory coherence and high-speed data exchange capabilities by adding new protocol layers. The CXL protocol aims to provide higher data throughput and lower latency to meet the growing demands of computing and storage systems.

[0003] Since the CXL protocol is a protocol based on PCIe, the link training, establishment, and packet transmission basically follow the PCIe protocol. However, in order to reduce latency and improve bandwidth utilization, the CXL protocol has also made many updates and improvements compared to PCIe. Summary of the Invention

[0004] In a first aspect, at least one embodiment of the present disclosure provides a circuit for transmitting end-of-data-stream information, which is disposed in the physical layer. The circuit includes: a counting module, connected to the link layer, configured to count the length of the data stream received from the link layer, and send an indication to insert end-of-data-stream information when the count value reaches a preset value; an end-of-data-stream information generation module, connected to the counting module and the link layer, configured to receive the indication to insert end-of-data-stream information, and in response to the indication to insert end-of-data-stream information, rewrite the packet identifier of the link layer transmission unit at the boundary in the data stream, where the rewritten packet identifier of the link layer transmission unit at the boundary implies end-of-data-stream information, and the link layer transmission unit at the boundary corresponds to the boundary of the physical channel; a physical channel interface, connected to the end-of-data-stream information generation module and the physical channel, configured to send the data stream including the rewritten link layer transmission unit at the boundary to the physical channel to transmit the data stream via the physical channel.

[0005] For example, in the circuit provided by an embodiment of the present disclosure, the circuit further includes: a state machine, connected to the counting module, configured to receive an indication of the end of the inserted data stream and a first indication for generating a control sequence, perform a state transition according to the indication of the end of the inserted data stream and the first indication, and output a second indication for generating a control sequence, where the first indication is related to low power consumption or clock compensation, and the control sequence includes a high-speed serial interface clock compensation sequence and a sequence for the high-speed interface to enter electrical idle; a sequence generator, connected to the state machine, configured to receive the second indication and generate a control sequence according to the second indication; a selector, connected to the state machine, the sequence generator, the data stream end information generation module, and the physical channel interface, configured to receive a data stream or a control sequence, and send the data stream or the control sequence to the physical channel interface, where when the second indication is received, the control sequence is selected and sent to the physical channel interface.

[0006] For example, in the circuit provided by an embodiment of the present disclosure, the counting module includes: a link layer transmission unit counter, configured to count the number of link layer transmission units in the data stream, and the counting threshold of the link layer transmission unit counter is a first preset value; and a block counter, configured to count the data stream in units of blocks, and the counting threshold of the block counter is a second preset value; where the length of each link layer transmission unit is 68 characters or 256 characters, each block includes 16 characters, the length of each character is 8 bits, and the indication of the end of the inserted data stream is sent when the count value of the link layer transmission unit counter reaches the first preset value and the count value of the block counter reaches the second preset value.

[0007] For example, in the circuit provided by an embodiment of the present disclosure, when the sync header bypass mode is disabled, the first preset value is N * 88 and the second preset value is 374, and when the sync header bypass mode is enabled, the first preset value is N * 80 and the second preset value is 340, where N is the number of physical channels.

[0008] For example, in the circuit provided by an embodiment of the present disclosure, the counting module includes: an empty packet detector, configured to detect whether there is an empty link layer transmission unit in the data stream; a character counter, configured to count the data stream in units of characters, and the counting threshold of the character counter is a third preset value; where when the sync header bypass mode is disabled, the indication of the end of the inserted data stream is also sent when the empty packet detector detects an empty link layer transmission unit in the data stream and the count value of the character counter reaches the third preset value, and when the sync header bypass mode is enabled, the indication of the end of the inserted data stream is also sent when the empty packet detector detects an empty link layer transmission unit in the data stream and the count value of the block counter reaches the second preset value.

[0009] For example, in the circuit provided by an embodiment of the present disclosure, the third preset value is 16, and the second preset value is 340.

[0010] For example, in the circuit provided by an embodiment of the present disclosure, the circuit further includes: an empty packet generator, configured to generate an empty link layer transmission unit according to a second indication and insert the empty link layer transmission unit into a data stream before the counting module receives the data stream.

[0011] In a second aspect, at least one embodiment of the present disclosure provides a data transmission chip, including: a link layer connected to a physical layer, configured to send a data stream to the physical layer; the physical layer is configured to insert data stream end information and a control sequence into the data stream received from the link layer at intervals of a preset data length, and the control sequence includes a high-speed serial interface clock compensation sequence; wherein, the physical layer includes a circuit for transmitting data stream end information as described in any one of the first aspects above.

[0012] For example, in the chip provided by an embodiment of the present disclosure, the chip further includes a virtual link manager and a training and status manager. Among them, the link layer is connected to the virtual link manager and is further configured to respond to a low-power management indication and, when there is no link layer transmission unit waiting to be transmitted, send a power consumption management request to the virtual link manager, send a power consumption management data link layer control packet and an empty data link layer control packet to the physical layer, and then stop sending data link layer control packets to the physical layer; the virtual link manager is connected to the training and status manager and is configured to respond to the power consumption management request and send a first indication to enter low power to the training and status manager; the training and status manager is connected to the physical layer and is configured to respond to the first indication to enter low power from the virtual link manager and send an indication to generate a low-power control sequence to the physical layer; the circuit for transmitting data stream end information is connected to the training and status manager and is configured to receive the indication to generate a low-power control sequence and, in response to the indication to generate a low-power control sequence, insert data stream end information and a control sequence into the data stream received from the link layer, and the control sequence further includes a sequence for the high-speed interface to enter electrical idle.

[0013] For example, in the chip provided by an embodiment of the present disclosure, the chip further includes a transaction layer and a power consumption manager. Among them, the transaction layer is connected to the link layer and the power consumption manager and is configured to respond to a request to enter low power, stop sending link layer transmission units to the link layer, and send a second indication to enter low power to the power consumption manager, where the request to enter low power comes from a processor within the chip or other devices outside the chip; the power consumption manager is connected to the link layer and the training and status manager and is configured to monitor the transmission situation of link layer transmission units in the link layer and, when it is determined that there is no link layer transmission unit waiting to be transmitted in the link layer, send a low-power management indication to the link layer.

[0014] For example, in a chip provided by an embodiment of the present disclosure, one or more of a power consumption manager, a virtual link manager, and a training and status manager are implemented using a state machine.

[0015] In a third aspect, at least one embodiment of the present disclosure provides an electronic device, comprising a data transmission chip as described in any one of the second aspects above. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0017] Figure 1 A schematic diagram showing the relationship between physical channels, characters, and blocks.

[0018] Figure 2 A schematic diagram of a circuit for transmitting data stream end information provided according to an embodiment of the present disclosure is shown;

[0019] Figure 3 A schematic diagram showing another circuit for transmitting data stream end information provided according to an embodiment of the present disclosure is shown;

[0020] Figure 4 A schematic diagram showing another circuit for transmitting data stream end information provided according to an embodiment of the present disclosure is shown;

[0021] Figure 5 A schematic diagram showing another circuit for transmitting data stream end information provided according to an embodiment of the present disclosure is shown;

[0022] Figure 6 A schematic diagram of a data transmission chip provided according to an embodiment of the present disclosure is shown;

[0023] Figure 7a A schematic diagram of another data transmission chip provided according to an embodiment of the present disclosure is shown;

[0024] Figure 7b A schematic diagram of another data transmission chip provided according to an embodiment of the present disclosure is shown;

[0025] Figure 8 A schematic diagram of an electronic device provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following will clearly and completely describe the technical solutions of the embodiments of the present disclosure with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0027] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. Similarly, terms such as "a", "an", or "the" do not denote a quantity limitation, but mean that there is at least one. The terms "comprising" or "including" and similar terms mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. The terms "connected" or "coupled" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0028] Different from PCIe, the CXL protocol includes three sub-protocols, namely CXL.io, CXL.cache, and CXL.memory. The CXL.io sub-protocol is similar to PCIe, and the CXL.cache sub-protocol and the CXL.memory sub-protocol are new additions compared to PCIe. For example, for the End of Data Stream (EDS), in PCIe, EDS is specified to be explicitly inserted into the data stream, while in CXL, it is specified that EDS needs to be implicitly inserted. Although the insertion method of EDS is specified in the CXL protocol, in electronic devices that support the CXL protocol, there is still no relevant solution on how to implement the insertion of EDS in the data stream with a circuit.

[0029] To solve the above technical problems, embodiments of the present disclosure provide a circuit for transmitting end - of - data - stream information, a data transmission chip, and an electronic device. The circuit for transmitting end - of - data - stream information includes a counting module connected to the link layer, configured to count the length of the data stream received from the link layer, and send an indication to insert end - of - data - stream information when the count value reaches a preset value; an end - of - data - stream information generation module connected to the counting module and the link layer, configured to receive the indication to insert end - of - data - stream information, and in response to the indication to insert end - of - data - stream information, rewrite the packet identifier of the link - layer transmission unit at the boundary in the data stream, where the rewritten packet identifier of the link - layer transmission unit at the boundary implies end - of - data - stream information, and the link - layer transmission unit at the boundary corresponds to the boundary of the physical channel; a physical channel interface connected to the end - of - data - stream information generation module and the physical channel, configured to send the data stream including the rewritten link - layer transmission unit at the boundary to the physical channel to transmit the data stream via the physical channel. By using the counting module to determine whether the length of the data stream meets the condition for inserting EDS, and when it is determined to insert EDS, the end - of - data - stream information generation module rewrites the packet identifier, so that EDS is implied in the data stream. Through the circuit for transmitting end - of - data - stream information, the data transmission chip, and the electronic device provided by the present disclosure, a simple and effective implementation manner is provided for inserting EDS in the required manner in the CXL protocol.

[0030] Before describing the embodiments of the present disclosure, some terms used in the present disclosure are introduced for better understanding.

[0031] In PCIe, data is transmitted in the form of packets, and the packets include Transaction Layer Packets (TLPs) and Data Link Layer Packets (DLLPs).

[0032] The basic transmission unit of the CXL protocol is the Flit (Link Layer Unit of Transfer), and the Flit is also known as the flow control unit, etc. The length of the Flit is 68 Bytes (bytes) or 256 Bytes. For example, a 68 - Byte Flit can include 2 Bytes of protocol ID (Identity Document), 64 Bytes of payload, and 2 Bytes of Cyclic Redundancy Check (CRC). In the CXL protocol, the CXL.cache and CXL.mem sub - protocols use the full - data Flit layout, while CXL.io uses the PCIe's TLP and DLLP, and the TLP and DLLP are sent in the payload part of the Flit.

[0033] The data stream refers to the information or message transmitted within or between CXL devices. The data stream includes data and control sequences, etc. Transmitting information in the transaction layer, link layer, or physical layer all belongs to the data stream. The data in the data stream is transmitted in the form of Flits. The control sequence can also be called an ordered set, which is used for training, entering and exiting electrical idle, transitioning to data blocks, and clock tolerance compensation, etc. For example, the read - write requests transmitted in the transaction layer, link layer, and physical layer of a CXL device all belong to data. The control sequence is a preset digital sequence with a fixed pattern, for example, 00001111.

[0034] A symbol is a transmission unit in the CXL protocol, and its length is 8 bit.

[0035] A data block, also known as a Block, is a transmission unit on a physical lane, and its length is 16 symbols. The length of 1 Flit is 68 or 256 symbols.

[0036] The link - layer transmission unit at the boundary means that the link - layer transmission unit falls at the boundary of the physical lane. This boundary refers to the situation where the last physical lane among multiple physical lanes transmits the last 1 bit of data of the link - layer transmission unit.

[0037] Figure 1 Shows a schematic diagram of the relationship between the physical lane, symbol, and block.

[0038] In Figure 1Among them, the physical channel 100 includes 8 physical channels, namely lane 0, lane 1, lane 2, lane 3, lane 4, lane 5, lane 6, and lane 7. The 8 physical channels perform parallel data transmission. It can be understood that the physical channel 100 in the present disclosure may also include 1 physical channel, 2 physical channels, 4 physical channels, or other numbers of physical channels. One block 110 transmitted by the physical channel 100 includes 16 characters, namely symbol 0, symbol 1,..., symbol 15. Block 110 is Figure 1 represented by a dashed box in Figure 1 . As an illustration, in

[0039] , the 8-bit data in each character is filled with "0", and the specific content of the synchronization header is not shown, which does not limit the specific content of the characters and the synchronization header in actual applications. Figure 1 . According to different modes, the block may or may not include a synchronization header. For example, when the synchronization header bypass mode is disabled, the block includes a synchronization header, and when the synchronization header bypass mode is enabled, the block includes a 2-byte synchronization header. The situation where block 110 includes a 2-byte synchronization header Sync Hdr is shown. The 8 physical channels transmit 1 bit of data in each character in parallel. As

[0040] shown, the last bit of data of symbol 15 is exactly transmitted by lane 7, and the last bit of data of symbol 15 is also the last bit of data of block 110. The last bit of data of block 110 is at the boundary of the block, and the last bit of data of the block is usually also transmitted by the last physical channel among multiple physical channels. If the last bit of data of the block is exactly also the last bit of data of the link layer transmission unit, it can be considered that the link layer transmission unit is at the boundary of the block and also at the boundary of the physical channel.

[0040] Embodiments in the present disclosure will be described below with reference to the accompanying drawings.

[0041] Figure 2 shows a schematic diagram of a circuit for transmitting end-of-data-stream information according to an embodiment of the present disclosure.

[0042] As Figure 2 shown, the circuit 200 for transmitting end-of-data-stream information includes a counting module 210, an end-of-data-stream information generation module 220, and a physical channel interface 230. The circuit 200 for transmitting end-of-data information is disposed in the physical layer, which is connected to the link layer and the physical channel. Among them, the counting module 210 and the end-of-data-stream information generation module 220 are connected to the link layer, and the physical channel interface 230 is connected to the physical channel.

[0043] The counting module 210 is configured to count the length of the data stream received from the link layer, and when the count value reaches a preset value, send an indication to insert the end-of-data-stream information.

[0044] The end-of-data-stream information generation module 220, connected to the counting module 210, is configured to receive the indication to insert the end-of-data-stream information, and in response to the indication to insert the end-of-data-stream information, rewrite the packet identifier of the link layer transmission unit at the boundary in the data stream, where the rewritten packet identifier of the link layer transmission unit at the boundary implies the end-of-data-stream information, and the link layer transmission unit at the boundary corresponds to the boundary of the physical channel.

[0045] The physical channel interface 230, connected to the end-of-data-stream information generation module and the physical channel, is configured to send the data stream containing the rewritten link layer transmission unit at the boundary to the physical channel to transmit the data stream via the physical channel.

[0046] In this embodiment, the counting module 210 counts the length of the data stream sent by the link layer. For example, the data stream is counted in units of characters, blocks, link layer transmission units, or other lengths. Optionally, the counting module 210 may include one or more counters, and different counters may count the length of the data stream in different units. For example, when the link layer and the physical layer perform data transmission, the data is stored in the cache or memory of the physical layer and the link layer, and the counting module 210 may be connected to the cache in the physical layer to obtain the data stream sent by the link layer from the cache.

[0047] The counting threshold of the counting module 210 is a preset value, which can also be adjusted according to actual needs. In this embodiment, the counting threshold of the counting module 210 needs to satisfy that the link layer transmission unit is located at the boundary of the physical channel, that is, the count value of the counting module 210 reaches the preset value when the link layer transmission unit is located at the boundary of the physical channel. When the count value reaches the preset value, the counting module 210 generates and sends an indication to insert the end-of-data-stream information to the end-of-data-stream information generation module 220. The content or form of various indications in this disclosure can be set according to the application scenario and will not be limited here.

[0048] When the data stream end information generation module 220 receives an indication to insert data stream end information, it rewrites the packet identifier of the link layer transmission unit at the boundary so that the packet identifier of the link layer transmission unit at the boundary implicitly contains the data stream end information. For example, the normal packet identifier of CXL.io can be FFFFh, while the packet identifier implicitly containing EDS is D2D2h. The normal packet identifier of CXL.cache+mem can be 5555h, while the packet identifier implicitly containing EDS is 8787h. The specific setting method of the packet identifier and the packet identifier implicitly containing EDS can refer to the regulations in the CXL protocol or can be set according to the application.

[0049] After the data stream end information generation module 220 rewrites the packet identifier of the link layer transmission unit, it does not change the length of the link layer transmission unit. The rewritten link layer transmission unit is continuously sent to the physical channel interface 230, and the physical channel interface 230 sends it to the physical channel for continuous transmission.

[0050] Through the counting module 210 and the data stream end information generation module 220 in the circuit 200 for transmitting data stream end information provided by this embodiment, the implicit insertion of EDS can be simply implemented.

[0051] Figure 3 A schematic diagram showing another circuit for transmitting data stream end information according to an embodiment of the present disclosure is shown.

[0052] The circuit 300 for transmitting data stream end information includes a counting module 310, a data stream end information generation module 320, a physical channel interface 330, a state machine 340, a sequence generator 350, and a selector 360. The circuit 300 for transmitting data end information is provided in the physical layer, which is connected to the link layer and the physical channel. The counting module 310 and the data stream end information generation module 320 are connected to the link layer, and the physical channel interface 330 is connected to the physical channel.

[0053] The state machine 340, connected to the counting module 310, is configured to receive an indication to insert data stream end information and a first indication for generating a control sequence, perform state switching according to the indication to insert data stream end information and the first indication, and output a second indication for generating a control sequence, where the first indication is related to low power consumption or clock compensation, and the control sequence includes a high-speed serial interface clock compensation sequence and a sequence for the high-speed interface to enter electrical idle.

[0054] The sequence generator 350, connected to the state machine 340, is configured to receive the second indication and generate a control sequence according to the second indication.

[0055] Selector 360, connected to state machine 340, sequence generator 350, data stream end information generation module 320, and physical channel interface 330, is configured to receive a data stream or a control sequence and send the data stream or the control sequence to the physical channel interface. Among them, when receiving a second indication, it selects to receive the control sequence and sends the control sequence to the physical channel interface.

[0056] In this embodiment, counting module 310, data stream end information generation module 320, and physical channel interface 330 are respectively similar to or the same as Figure 2 counting module 210, data stream end information generation module 220, and physical channel interface 230 therein. For details, reference can be made to Figure 2 the description, which will not be elaborated herein.

[0057] State machine 340 receives an indication to insert data stream end information and a first indication for generating a control sequence. The indication to insert data stream end information comes from counting module 310, and the first indication for generating a control sequence can come from the link layer or other devices outside the link layer. The first indication is related to low power consumption or clock compensation. The control sequence includes a high-speed serial interface clock compensation sequence and a sequence for the high-speed interface to enter electrical idle.

[0058] According to the indication to insert data stream end information and the first indication, state machine 340 can perform state switching and output a second indication for generating a control sequence. In this embodiment, state machine 340 can include at least three states, such as an idle state, a state of generating a high-speed serial interface clock compensation sequence, and a state of generating a sequence for the high-speed interface to enter electrical idle. In the idle state, state machine 340 does not output a second indication for generating a control sequence. When receiving both the indication to insert data stream end information and the first indication for generating a control sequence, it switches to the state of generating a control sequence. For example, according to the different first indications for generating a control sequence received, it switches to the state of generating a high-speed serial interface clock compensation sequence or the state of generating a sequence for the high-speed interface to enter electrical idle. State machine 340 can generate different second indications according to different states. For example, the second indication corresponds to a high-speed serial interface clock compensation sequence or a sequence for the high-speed interface to enter electrical idle.

[0059] Sequence generator 350 receives the second indication from state machine 340 and generates a control sequence according to the second indication. Sequence generator 350 generates a high-speed serial interface clock compensation sequence or a sequence for the high-speed interface to enter electrical idle according to the second indication. The high-speed serial interface clock compensation sequence and the sequence for the high-speed interface to enter electrical idle usually have fixed patterns or formats. Sequence generator 350 can pre-store these two sequences and output the corresponding sequence when receiving the second indication.

[0060] Selector 360 receives a data stream or a control sequence and, according to the second indicated control, sends the data stream or the control sequence to the physical channel interface 330. When receiving the second indication, selector 360 receives the control sequence and sends the control sequence to the physical channel interface 330. When not receiving the second indication, selector 360 sends the data stream to the physical channel interface 330. Selector 360 may be a multiplexer, the second indication serves as the control signal of the multiplexer, and the data stream and the control sequence are the two inputs of the multiplexer.

[0061] Through the circuit for transmitting the end information of the data stream provided in this embodiment, in addition to being able to implicitly insert the EDS in the data stream, a control sequence following the EDS can be further inserted, thereby providing a hardware implementation for the EDS and the control sequence specified in the CXL protocol.

[0062] Optionally, the circuit for implicitly inserting the EDS and the circuit for inserting the control sequence can be implemented separately. Figure 2 The circuit 200 for transmitting the end information of the data stream in [description] is a circuit for separately implementing the implicit insertion of the EDS. Figure 3 The counting module 310, the physical channel interface 330, the state machine 340, the sequence generator 350, and the selector 360 inside the circuit 300 for transmitting the end information of the data stream in [description] can be used to separately implement the insertion of the control sequence.

[0063] Optionally, the above counting module may include: a link layer transmission unit counter configured to count the number of link layer transmission units in the data stream, the counting threshold of the link layer transmission unit counter being a first preset value; and a block counter configured to count the data stream in units of blocks, the counting threshold of the block counter being a second preset value; wherein the length of each link layer transmission unit is 68 characters or 256 characters, each block includes 16 characters, the length of each character is 8 bits, and the indication for inserting the end information of the data stream is sent when the count value of the link layer transmission unit counter reaches the first preset value and the count value of the block counter reaches the second preset value.

[0064] Optionally, when the sync header bypass mode is disabled, the first preset value is N*88 and the second preset value is 374; when the sync header bypass mode is enabled, the first preset value is N*80 and the second preset value is 340, where N is the number of physical channels.

[0065] Optionally, the above counting module may further include: an empty packet detector configured to detect whether there is an empty link layer transmission unit in the data stream; a character counter configured to count the data stream in terms of characters, and the counting threshold of the character counter is a third preset value; wherein, when the synchronization header bypass mode is disabled, the indication of inserting the data stream end information is also sent when the empty packet detector detects that there is an empty link layer transmission unit in the data stream and the count value of the character counter reaches the third preset value, and when the synchronization header bypass mode is enabled, the indication of inserting the data stream end information is also sent when the empty packet detector detects that there is an empty link layer transmission unit in the data stream and the count value of the block counter reaches the second preset value. For example, the third preset value is 16 and the second preset value is 340.

[0066] Figures 4 - 5 Schematic diagrams of circuits for transmitting data stream end information when the counting module includes different counters are respectively shown.

[0067] In Figures 4 - 5 circuit 400 for transmitting data stream end information and circuit 500 for transmitting data stream end information are specific implementation manners of circuit 300 for transmitting data stream end information, and their specific structures can be referred to the description in Figure 3 The difference between circuit 400 for transmitting data stream end information and circuit 500 for transmitting data stream end information is the different implementation manners of the counting module 310. And

[0068] As Figure 4 shown, the counting module 310 includes a link layer transmission unit counter 311 and a block counter 312. The link layer transmission unit counter 311 is not connected to the block counter 312, and the link layer transmission unit counter 311 and the block counter 312 independently count the data stream. The link layer transmission unit counter 311 counts the number of link layer transmission units in the data stream, and its counting threshold is a first preset value. The block counter 312 counts the data stream in terms of blocks, and its counting threshold is a second preset value. An indication of inserting data stream end information is sent when the count value of the link layer transmission unit counter reaches the first preset value and the count value of the block counter reaches the second preset value. For example, the counting module 310 further includes an indication generator, which is connected to the link layer transmission unit counter 311 and the block counter 312, and generates the indication of inserting the data stream end information when the count values of both the link layer transmission unit counter 311 and the block counter 312 reach the counting threshold. In this embodiment, the indication of inserting the data stream end information corresponds to the high-speed serial interface clock compensation sequence.

[0069] In this embodiment, the values of the first preset value and the second preset value are related to the transmission mode of the block and also related to the number of physical channels.

[0070] For example, when a device supporting the CXL protocol sends data normally, it needs to send a high-speed serial interface clock compensation sequence at regular intervals. Before the high-speed serial interface clock compensation sequence, there needs to be an EDS in the data stream. The interval time of the high-speed serial interface clock compensation sequence is different in different modes. In this embodiment, the interval time is replaced by the data length.

[0071] When the sync-header bypass mode is disabled, a high-speed serial interface clock compensation sequence is sent once every 374 blocks on one physical channel. When there are N physical channels in the link, the physical channels send a high-speed serial interface clock compensation sequence once every N * 374 blocks, and also need to send a high-speed serial interface clock compensation sequence once every N * 88 link layer transmission units. For the sync header, see Figure 1 。

[0072] When the sync-header bypass mode is enabled, a high-speed serial interface clock compensation sequence is sent once every 340 blocks on one physical channel. When there are N physical channels in the link, the physical channels send a high-speed serial interface clock compensation sequence once every N * 340 blocks, and also need to send a high-speed serial interface clock compensation sequence once every N * 80 link layer transmission units.

[0073] Optionally, when the sync-header bypass mode is disabled, the first preset value is N * 88 and the second preset value is 374; when the sync-header bypass mode is enabled, the first preset value is N * 80 and the second preset value is 340, where N is the number of physical channels.

[0074] As Figure 5As shown in the figure, the counting module 310 includes a link layer transmission unit counter 311, a block counter 312, an empty packet detector 313, and a character counter 314. The link layer transmission unit counter 311, the block counter 312, the empty packet detector 313, and the character counter 314 are not connected to each other. The link layer transmission unit counter 311, the block counter 312, and the character counter 314 independently count the data stream. The empty packet detector 313 detects whether there is an empty link layer transmission unit in the data stream. The counting threshold of the character counter 314 is the third preset value, and the counting threshold of the block counter 312 is still the above-mentioned second preset value. Among them, when the synchronization header bypass mode is disabled, the empty packet detector 313 also sends an indication to insert the end-of-data-stream information when it detects the existence of an empty link layer transmission unit in the data stream and the count value of the character counter 314 reaches the third preset value. When the synchronization header bypass mode is enabled, an indication to insert the end-of-data-stream information is sent when the empty packet detector 313 detects the existence of an empty link layer transmission unit in the data stream, the count value of the link layer transmission unit counter 311 reaches the first preset value, and the count value of the block counter 312 reaches the second preset value. For example, the third preset value is 16, the second preset value is 340, and the first preset value is N * 80.

[0075] In this embodiment, the indication to insert the end-of-data-stream information corresponds to the sequence in which the high-speed interface enters the electrical idle state.

[0076] When the synchronization header bypass mode is disabled, the length of the empty link layer transmission unit is variable. An empty link layer transmission unit that ends the implicit EDS can be selected at the boundary of the block, and a sequence in which the high-speed interface enters the electrical idle state is inserted into the next block. Therefore, when the empty packet detector 313 detects the existence of an empty link layer transmission unit and the count value of the character counter 314 reaches the third preset value, an indication to insert the end-of-data-stream information is sent to the state machine 340.

[0077] When the synchronization header bypass mode is enabled, the length of the empty link layer transmission unit is fixed, and the complete empty link layer transmission unit needs to be located at the boundary of the block when the transmission is completed. Therefore, when the empty packet detector 313 detects the existence of an empty link layer transmission unit, the count value of the link layer transmission unit counter 311 reaches the first preset value, and the count value of the block counter 312 reaches the second preset value, an indication to insert the end-of-data-stream information is sent to the state machine 340.

[0078] Optionally, the circuit for transmitting the end-of-data-stream information further includes: an empty packet generator configured to generate an empty link layer transmission unit according to a second indication for generating a control sequence and insert the empty link layer transmission unit into the data stream before the counting module receives the data stream.

[0079] Before sending the sequence for the high-speed interface to enter the electrical idle state, it is usually necessary to send an empty link layer transmission unit. However, the empty link layer transmission unit needs to be generated separately. This embodiment provides a method of setting an empty packet generator in the physical layer, which can make the insertion of the empty link layer transmission unit simpler and easier.

[0080] The above describes the circuit for implementing the insertion of the EDS and the corresponding control sequence. The generation and insertion of the sequence for the high-speed interface to enter the electrical idle state also involve operations outside the physical layer. For this, the present disclosure further provides a data transmission chip.

[0081] Figure 6 Shows a schematic diagram of a data transmission chip provided according to an embodiment of the present disclosure.

[0082] As Figure 6 shown, the data transmission chip 600 includes a link layer 610 and a physical layer 620. The link layer 610 is connected to the physical layer 620, and the physical layer 620 includes a circuit for transmitting the end-of-data-stream information as described in any of the above embodiments.

[0083] The link layer 610 sends a data stream to the physical layer 620, and this data stream is transmitted in the form of link layer transmission units. The physical layer 620 inserts the end-of-data-stream information and the control sequence into the data stream received from the link layer 610 at intervals of a preset data length. This control sequence is a high-speed serial interface clock compensation sequence. The circuit for transmitting the end-of-data-stream information in the physical layer 620 can be the circuit for transmitting the end-of-data-stream information as Figures 3 - 5 shown, and the manner in which the physical layer 620 inserts the end-of-data-stream information and the control sequence can be referred to the description in Figures 3 - 5 , and will not be elaborated here.

[0084] The data transmission chip 600 provided in this embodiment can implement the implicit insertion of the EDS and the insertion of the high-speed serial interface clock compensation sequence.

[0085] Figure 7a Shows a schematic diagram of another data transmission chip provided according to an embodiment of the present disclosure.

[0086] The data transmission chip 700 includes a link layer 710, a physical layer 720, a virtual link manager 730, and a training and status manager 740. The link layer 710 can be the Figure 6 shown link layer 610, and the physical layer 720 can be the Figure 6 link layer 620 in Figure 6 , and for the specific reference, see the description in

[0087] The link layer 710 is connected to the physical layer 720 and the virtual link manager 730, and the training and status manager 740 is connected to the physical layer 720 and the virtual link manager 730. Among them, the training and status manager 740 can be connected to the circuit for transmitting the end-of-data-stream information in the physical layer 720.

[0088] In response to the low-power management indication and when there is no link layer transmission unit waiting to be transmitted, the link layer 710 sends a power management request to the virtual link manager 730, and sends a power management data link layer control packet and an empty data link layer control packet to the physical layer 720, and then stops sending data link layer control packets to the physical layer 720.

[0089] In response to the power management request from the link layer 710, the virtual link manager 730 sends a first indication to enter the low-power state to the training and status manager 740.

[0090] In response to the first indication to enter the low-power state from the virtual link manager 730, the training and status manager 740 sends an indication to generate a low-power control sequence to the physical layer 720.

[0091] The circuit 721 for transmitting the end-of-data-stream information in the physical layer 720 receives the indication to generate a low-power control sequence from the training and status manager 740, and in response to the indication to generate a low-power control sequence, inserts the end-of-data-stream information and the control sequence into the data stream received from the link layer 710. The control sequence also includes a sequence for the high-speed interface to enter the electrical idle state.

[0092] For example, the indication to generate a low-power control sequence is the first indication for generating a control sequence in this application. After the circuit 721 for transmitting the end-of-data-stream information receives the indication to generate a low-power control sequence, it can generate a sequence for the high-speed interface to enter the electrical idle state and insert the end-of-data-stream information and the sequence for the high-speed interface to enter the electrical idle state into the data stream. For example, the circuit 721 for transmitting the end-of-data-stream information inserts the EDS into the empty link layer transmission unit and inserts the sequence for the high-speed interface to enter the electrical idle state after the empty data link transmission unit.

[0093] Figure 7b The schematic diagram of another data transmission chip provided according to an embodiment of the present disclosure is shown.

[0094] The data transmission chip 700' includes a link layer 710, a physical layer 720, a virtual link manager 730, a training and status manager / 40, a power manager 750, and a transaction layer 760.

[0095] The power consumption manager 750, connected to the link layer 710 and the training and status manager 740, is configured to monitor the transmission of link layer transmission units in the link layer 710, and when it is determined that there are no link layer transmission units waiting to be transmitted in the link layer 710, send a low power consumption management instruction to the link layer 710.

[0096] The transaction layer 760, connected to the link layer 710 and the power consumption manager 750, is configured to, in response to a request to enter low power consumption, stop sending link layer transmission units to the link layer 710 and send a second instruction to enter low power consumption to the power consumption manager 750, where the request to enter low power consumption comes from a processor within the chip or from other devices outside the chip.

[0097] The power consumption manager 740 is connected to the training and status manager 760, the transaction layer 730, the link layer 710, and the virtual link manager 750. The virtual link manager 750 is also connected to the link layer 710 and the training and status manager 760. The training and status manager 760 is also connected to the physical layer 720, specifically to the circuit in the physical layer 720 that transmits the end-of-transmission data stream information. The link layer 710 and the physical layer 720 can be implemented by the link layer 610 and the physical layer 620.

[0098] The transaction layer 730 receives a request to enter low power consumption, and the request to enter low power consumption comes from a processor within the chip or from other devices outside the chip. This request to enter low power consumption can be a request from the chip itself or an external request from other chips or devices.

[0099] In response to the request to enter low power consumption, the transaction layer 730 stops sending link layer transmission units to the link layer 710 and sends a first instruction to enter low power consumption to the power consumption manager 740. After receiving the request to enter low power consumption, the transaction layer 730 stops sending new link layer transmission units to the link layer 710, and the link layer transmission units that have been sent but for which a completion message has not yet been received still need to be sent.

[0100] The power consumption manager 740 monitors the transmission of link layer transmission units in the link layer 710, and when it is determined that there are no link layer transmission units waiting to be transmitted in the link layer 710, send a low power consumption management instruction to the link layer 710.

[0101] In response to the low power consumption management instruction from the power consumption manager, the link layer 710 sends a power consumption management request to the virtual link manager 750, sends a power consumption management data link layer control packet and an empty data link layer control packet to the physical layer 720, and then stops sending data link layer control packets to the physical layer 720. In this example, the power consumption management request, the power consumption management data link layer control packet, and the empty data link layer control packet are all included in the link layer transmission unit.

[0102] In response to a power consumption management request, the virtual link manager 750 sends a first indication to enter the low power state to the training and status manager 760.

[0103] In response to the first indication to enter the low power state from the virtual link manager 750, the training and status manager 760 sends an indication to the physical layer 720 to generate a control sequence for the low power state.

[0104] In response to the indication to generate a control sequence for the low power state, the physical layer 720 inserts end-of-data-stream information and a control sequence into the data stream received from the link layer 710, and the control sequence is a sequence for the high-speed interface to enter the electrical idle state.

[0105] Optionally, one or more of the power consumption manager, the virtual link manager, and the training and status manager may be implemented using a state machine.

[0106] When the data transmission chip in this embodiment needs to enter the low power state, after sending the control packet to enter the low power state, it can generate and send an empty link layer transmission unit, so as to ensure the continuity of the data stream and ensure that the EDS is inserted at the specified data length interval.

[0107] Figure 8 A schematic diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0108] The electronic device 800 includes a data transmission chip as described in any one of the above embodiments. For example, the electronic device 800 includes the data transmission chip 600 or the data transmission chip 700.

[0109] The electronic device in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Tablet Computers), PMPs (Portable Multimedia Players), vehicle terminals (such as vehicle navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 8 The electronic device shown is only an example and should not impose any limitations on the functions and usage scopes of the embodiments of the present disclosure.

[0110] The basic principles of the present application have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, advantages, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, advantages, effects, etc. are essential for each embodiment of the present application. In addition, the above-disclosed specific details are only for the purposes of illustration and easy understanding, rather than limitations, and the above details do not limit the present application to necessarily adopt the above specific details for implementation.

[0111] It should be noted that the step flowcharts and the above method descriptions in this application are only illustrative examples and do not aim to require or imply that the steps of each embodiment must be carried out in the given order. Some steps can be executed in parallel, independently of each other, or in other appropriate orders. Additionally, words such as "secondly", "then", "next", etc. do not aim to limit the order of the steps; these words are only used to guide the reader through the description of these methods.

[0112] The block diagrams of the devices, apparatuses, equipment, and systems involved in this application are only illustrative examples and do not intend to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. It should also be noted that in the devices and methods of this application, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be regarded as equivalent solutions of this application.

[0113] The following points need to be explained: (1) The drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure, and other structures can refer to the general design. (2) Without conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments. As described above, the above is only the specific implementation manner of this disclosure, but the protection scope of this disclosure is not limited thereto. The protection scope of this disclosure should be subject to the protection scope of the claims.

Claims

1. A circuit for transmitting data stream end information of a CXL protocol, arranged in a physical layer, comprising: A counting module connected to the link layer and configured to count the length of the data stream received from the link layer and send an indication of inserting the end information of the data stream when the count value reaches a preset value; a data stream end information generating module, connected to the counting module and the link layer, configured to receive the indication of inserting the data stream end information, and in response to the indication of inserting the data stream end information, rewrite the data packet identifier of the link layer transmission unit at the boundary of the data stream, wherein the rewritten data packet identifier of the link layer transmission unit at the boundary implies the data stream end information, and the link layer transmission unit at the boundary corresponds to the boundary of the physical channel; A physical channel interface is connected to the data stream end information generation module and the physical channel, and is configured to send the data stream including the rewritten link layer transmission unit at the boundary to the physical channel to transmit the data stream via the physical channel.

2. The circuit according to claim 1, wherein The circuit further comprises: a state machine connected to the counting module, configured to receive the indication of inserting the data stream end information and a first indication for generating a control sequence, perform state switching according to the indication of inserting the data stream end information and the first indication, and output a second indication for generating a control sequence, wherein the first indication is related to low power consumption or clock compensation, and the control sequence includes a high-speed serial interface clock compensation sequence and a high-speed interface entering electrical idle sequence; a sequence generator, connected to the state machine, configured to receive the second indication and generate the control sequence according to the second indication; A selector is connected to the state machine, the sequence generator, the data stream end information generation module and the physical channel interface, and is configured to receive the data stream or the control sequence and send the data stream or the control sequence to the physical channel interface, wherein when the second indication is received, the control sequence is selected to be received and sent to the physical channel interface.

3. The circuit according to claim 1 or 2, wherein: The counting module comprises: a link layer transmission unit counter configured to count the number of link layer transmission units in the data stream, wherein a counting threshold of the link layer transmission unit counter is a first preset value; and A block counter, configured to count the data stream in units of blocks, wherein a counting threshold of the block counter is a second preset value; Wherein, the length of each link layer transmission unit is 68 characters or 256 characters, each block includes 16 characters, the length of each character is 8 bits, and the indication of the end of the inserted data stream information is sent when the count value of the link layer transmission unit counter reaches the first preset value and the count value of the block counter reaches the second preset value.

4. The circuit according to claim 3, wherein: When the synchronization head bypass mode is disabled, the first preset value is N*88 and the second preset value is 374. When the synchronization head bypass mode is enabled, the first preset value is N*80 and the second preset value is 340, where N is the number of physical channels.

5. The circuit according to claim 3, wherein: The counting module comprises: a null packet detector configured to detect whether there is an empty link layer transmission unit in the data stream; A character counter, configured to count the data stream in units of characters, wherein a counting threshold of the character counter is a third preset value; Wherein, when the synchronization header bypass mode is disabled, the indication of the end of the data stream insertion is also sent when the empty packet detector detects the presence of an empty link layer transmission unit in the data stream and the count value of the character counter reaches the third preset value; and when the synchronization header bypass mode is enabled, the indication of the end of the data stream insertion is also sent when the empty packet detector detects the presence of an empty link layer transmission unit in the data stream and the count value of the block counter reaches the second preset value.

6. The circuit according to claim 5, wherein: The third preset value is 16, and the second preset value is 340.

7. The circuit according to claim 2, wherein: The circuit further comprises: The empty packet generator is configured to generate an empty link layer transmission unit according to the second indication and insert the empty link layer transmission unit into the data stream before the counting module receives the data stream.

8. A data transmission chip, comprising: A link layer, connected to the physical layer, configured to send a data stream to the physical layer; The physical layer is configured to preset the data length at intervals, insert data stream end information and a control sequence into the data stream received from the link layer, and the control sequence includes a high-speed serial interface clock compensation sequence; The physical layer includes a circuit for transmitting data stream end information according to any one of claims 1-7.

9. The chip according to claim 8, wherein: The chip also includes a virtual link manager and a training and status manager, wherein: The link layer, connected to the virtual link manager, is further configured to send a power management request to the virtual link manager in response to a low power management indication and when no link layer transmission unit is waiting to transmit, and to send a power management data link layer control packet and an empty data link layer control packet to the physical layer, and then stop sending data link layer control packets to the physical layer; The virtual link manager is connected to the training and state manager and is configured to send a first indication of entering low power consumption to the training and state manager in response to the power consumption management request; The training and state manager is connected to the physical layer and is configured to send an instruction to generate a low power consumption control sequence to the physical layer in response to a first instruction to enter low power consumption from the virtual link manager; The circuit for transmitting data stream end information is connected to the training and status manager, and is configured to receive an indication of the control sequence for generating low power consumption, and in response to the indication of the control sequence for generating low power consumption, insert data stream end information and the control sequence into the data stream received from the link layer, wherein the control sequence also includes a sequence for the high-speed interface to enter electrical idle.

10. The chip according to claim 9, wherein: The chip also includes a transaction layer and a power consumption manager, wherein: The transaction layer is connected to the link layer and the power consumption manager, and is configured to stop sending the link layer transmission unit to the link layer in response to a request to enter low power consumption, and send a second indication to the power consumption manager to enter low power consumption, wherein the request to enter low power consumption comes from a processor in the chip or from other devices outside the chip; The power consumption manager is connected to the link layer and the training and status manager, and is configured to monitor the transmission status of the link layer transmission unit in the link layer, and when it is determined that there is no link layer transmission unit in the link layer waiting for transmission, send the low power consumption management indication to the link layer.

11. The chip according to claim 10, wherein: One or more of the power consumption manager, the virtual link manager, and the training and state manager are implemented using a state machine.

12. An electronic device comprising the data transmission chip according to any one of claims 8 to 11.

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