Texturing pretreatment silicon wafer, preparation method thereof, texturing wafer and solar cell

Abstract

The application provides a texturing pretreatment silicon wafer, a preparation method thereof, a texturing wafer and a solar cell. The texturing pretreatment silicon wafer comprises a base layer and a pre-texturing layer arranged on at least one side surface of the base layer, wherein the pre-texturing layer comprises a plurality of protrusions, the protrusions are in the shape of a quadrangular pyramid, and the bottom side length of the protrusions is in the range of 2-8 μm. The texturing pretreatment silicon wafer can successfully obtain a texturing wafer with a high-quality texturing surface, and thus can be used to provide a solar cell with excellent performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cells, in particular to a texturing pretreatment silicon wafer, a preparation method thereof, a textured wafer and a solar cell. BACKGROUND

[0002] Solar cells are one of the important ways to alleviate global energy crisis and environmental pollution problems. Heterojunction cells gradually become the development direction of future solar cells because of their high photoelectric conversion efficiency, high double-sided rate, almost no light-induced degradation, good temperature characteristics and simple preparation process. Heterojunction is the deposition of amorphous silicon film on the silicon crystal layer, and the distribution of light trapping structure of the texturing surface of the silicon crystal layer directly affects the performance of the cell.

[0003] At present, the silicon wafer for heterojunction cells needs to go through rough polishing, texturing, smoothing and hydrofluoric acid passivation processes. Among them, the rough polishing process can sufficiently remove the damage layer on the surface of the silicon wafer caused by the cutting process, and the structure formed on the surface of the silicon wafer after rough polishing can guide the formation of light trapping structure during subsequent texturing. In the prior art, in order to sufficiently remove the above-mentioned damage layer, strong alkali with a concentration of about 5wt% is generally used for rough polishing of the silicon wafer, but this will result in that the size of the finally formed light trapping structure is large, the distribution density is low, and the size difference of multiple light trapping structures is large, which will increase the internal resistance of the final cell and affect the normal performance of the cell. SUMMARY

[0004] Therefore, the present application provides a texturing pretreatment silicon wafer and a preparation method thereof. The texturing pretreatment silicon wafer can successfully form a texturing wafer with a high flatness and a low contact resistance, and thus can be used to provide a solar cell with excellent performance.

[0005] The first aspect of the present application provides a texturing pretreatment silicon wafer, comprising a substrate layer and a pre-texturing layer arranged on at least one side surface of the substrate layer, wherein the pre-texturing layer comprises a plurality of protrusions, the protrusions are in the shape of a quadrangular pyramid, and the bottom edge length of the protrusions is in the range of 2μm-8μm.

[0006] The protrusion structure of the texturing pretreatment silicon wafer is in the shape of a quadrangular pyramid, and the bottom edge length thereof is controlled in the range of 2μm-8μm. In this way, in the subsequent texturing process, the protrusions can form light trapping structures with small size and dense arrangement, so as to improve the flatness of the texturing wafer and reduce its contact resistance, and thus can be used to provide a solar cell with small internal resistance.

[0007] The second aspect of the present application provides a preparation method of a texturing pretreatment silicon wafer, comprising the following steps:

[0008] The raw material of the texturing wafer is sequentially cleaned and subjected to alkali etching to obtain a texturing pretreated wafer; the texturing pretreated wafer comprises a substrate layer and a pre-texturing layer arranged on at least one side surface of the substrate layer, and the pre-texturing layer comprises a plurality of protrusions in the shape of a quadrangular pyramid.

[0009] The alkali etching conditions include: using a strong alkali solution with a concentration of 15wt%-30wt% to etch the silicon wafer; the alkali etching time is 40s-120s, and the alkali etching temperature is 50℃-80℃.

[0010] The preparation method has simple steps, high process reliability and high production efficiency, and is suitable for large-scale industrial production.

[0011] The third aspect of the present application provides a texturing wafer prepared from the texturing pretreated wafer provided in the first aspect of the present application. The texturing wafer has a high flatness of the texturing surface, which is conducive to the deposition of other film layers (such as non-silicon crystal film layers, transparent oxide layers, etc.) in the subsequent battery preparation process and the close contact between the subsequent other film layers and the grid lines.

[0012] The fourth aspect of the present application provides a solar cell comprising the texturing wafer provided in the third aspect of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 A schematic diagram showing the principle of gradually forming a light-trapping structure by the protrusions in the texturing process;

[0014] Figure 2A A scanning electron microscopy (SEM) photograph of the texturing pretreated wafer provided in Example 1 of the present application;

[0015] Figure 2B A cross-sectional SEM photograph of the texturing pretreated wafer provided in Example 1 of the present application;

[0016] Figure 2C A cross-sectional SEM photograph of the texturing wafer provided in Example 1 of the present application;

[0017] Figure 3A A cross-sectional SEM photograph of the texturing pretreated wafer provided in Example 5 of the present application;

[0018] Figure 3B A cross-sectional SEM photograph of the texturing wafer provided in Example 5 of the present application;

[0019] Figure 4A A cross-sectional SEM photograph of the texturing pretreated wafer provided in Comparative Example 1 of the present application;

[0020] Figure 4BThe cross-sectional SEM photo of the texturing wafer provided for Comparative Example 1 of the present application;

[0021] Figure 5 The electrode pattern diagram for testing the contact resistance between each texturing wafer and electrode provided by the present application. DETAILED DESCRIPTION

[0022] The embodiment of the present application provides a texturing pretreatment silicon wafer, which comprises a substrate layer and a pre-texturing layer arranged on at least one side surface of the substrate layer, and the pre-texturing layer comprises a plurality of protrusions, the protrusions are in the shape of quadrangular pyramid, and the bottom edge length of the protrusions is in the range of 2-8 μm. It can be understood that, in the present application, the bottom edge length of the protrusions refers to the intersection line of the protrusions and the substrate layer, that is, the maximum cross-sectional width of the protrusions.

[0023] Please refer to Figure 1 , the pre-texturing layer of the texturing pretreatment silicon wafer comprises a plurality of protrusions in the shape of quadrangular pyramid, in the subsequent texturing process, the texturing liquid will continue to corrode the protrusions to gradually form light-trapping structures, as shown in (a) of Figure 1 , wherein the profile depicted by the black dotted line in the figure represents the profile of the front view of the light-trapping structure that can be theoretically formed; by controlling the bottom edge length of the protrusions in the above range, in the process of further etching the protrusions to form light-trapping structures in the subsequent texturing, the merging of adjacent light-trapping structures is not easy to occur, so that the size of the light-trapping structures can be inhibited, the final light-trapping structures have small size, high distribution density and uniform size distribution, and therefore the texturing surface has high flatness and small contact resistance, so that the texturing surface can be used to provide a solar cell with small internal resistance and high photoelectric conversion efficiency.

[0024] As shown in (b) of Figure 1 , if the bottom edge length of the protrusions is too small (less than 2 μm), the adjacent light-trapping structures in the growth process are easy to merge to finally form light-trapping structures with excessively large size, resulting in that the final texturing surface has few light-trapping structures, low density, large fluctuation, low flatness, and large size difference between the light-trapping structures, which leads to excessively large internal resistance of the final solar cell; as shown in (c) of Figure 1 , if the bottom edge length of the protrusions is too large (greater than 8 μm), the growing light-trapping structures cannot receive steric hindrance from other growing light-trapping structures, which leads to that the final texturing surface has large size of light-trapping structures, few light-trapping structures, low density, and excessively large fluctuation of the surface of the texturing layer, which is also not conducive to the performance of the final solar cell.

[0025] Exemplarily, the bottom edge length of the protrusions can be 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, 7 μm, 7.5 μm, 8 μm, etc.

[0026] In some embodiments of the present application, the side wall of the protrusion is provided with nucleation sites. In this way, in the subsequent texturing process, the texturing solution is more likely to further etch the protrusion based on the nucleation sites to successfully form "small and dense, and uniform size distribution" light-trapping structures. In the present application, the nucleation site specifically refers to a small bump structure with a maximum cross-sectional width in the range of greater than 0 to less than or equal to 1 μm and a height in the range of greater than 0 to less than or equal to 0.75 μm. In some embodiments, the small bump is in the shape of a four-sided pyramid, that is, "small pyramid". In the scanning electron microscopy (SEM) photos of the pre-texturing silicon wafer, due to the obvious tip effect and edge effect of the secondary electron or backscattered electron contrast, the nucleation site appears as a "white dot" under a certain scale (e.g., 1 μm).

[0027] In some embodiments of the present application, the height of the protrusion is in the range of 0.5 μm to 2 μm. In this way, when the nucleation sites on the side wall start to "grow", controlling the height of the protrusion in the above range can make the distance between any two points on the two oppositely arranged side walls A and B of the protrusion be in a more appropriate range, that is, the distance between the nucleation site on the side wall A and the nucleation site on the side wall B is controlled to be in a more appropriate range, which is more conducive to obtaining a pre-texturing wafer with higher surface flatness. Exemplarily, the height of the protrusion can be 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 1.9 μm, 2 μm, etc.

[0028] In some embodiments of the present application, the cross-sectional dimension of the protrusion gradually decreases in the direction away from the base layer. In this way, the four-sided pyramid is upright on the base layer, and the light-trapping structure prepared thereby is also upright on the base layer, thereby being more conducive to multiple absorption of light.

[0029] In some embodiments of the present application, there are 2-11 protrusions per 100 μm 2 of the pre-texturing layer. In this way, the distribution of the protrusion structure on the pre-texturing layer is relatively dense, which can make the nucleation sites have a more appropriate distribution density, thereby being more conducive to obtaining a pre-texturing wafer with higher surface flatness. Exemplarily, the number of protrusions per 100 μm 2 of the pre-texturing layer can be 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, etc.

[0030] In some embodiments of the present application, when the silicon wafer raw material is (100) silicon crystal, the side wall of the protrusion exposes the (111) crystal plane of the silicon crystal; and the upper surface of the protrusion exposes the (100) crystal plane of the silicon crystal.

[0031] The embodiment of the present application provides a preparation method of a texturing pretreatment silicon wafer, which can be used for preparing the texturing pretreatment silicon wafer provided by the embodiment of the present application, and the preparation method comprises the following steps:

[0032] The texturing wafer raw material is sequentially subjected to cleaning and alkali etching treatment to obtain the texturing pretreatment silicon wafer; wherein the alkali etching conditions comprise: using a strong alkali with a concentration of 15wt%-30wt% to etch at least one side surface of the texturing wafer raw material; the alkali etching time is 40s-120s, and the temperature is 50°C-80°C. In this way, the prepared texturing pretreatment silicon wafer comprises a substrate layer and a pre-texturing layer arranged on at least one side surface of the substrate layer, and the pre-texturing layer comprises a plurality of protrusions in the shape of a quadrangular pyramid.

[0033] In the above alkali etching process, the strong alkali with a concentration of 15wt%-30wt% simultaneously etches the (100) crystal surface and the (111) crystal surface of the silicon crystal and has a comparable corrosion rate on the two crystal surfaces, which not only quickly etches the damage layer of the silicon crystal, but also makes the (100) crystal surface vertical and the (111) crystal surface have an inclination angle of about 54°, so that a tetrahedral structure is continuously formed on the surface of the silicon crystal in the alkali etching process, and the alkali solution continuously corrodes the top end of the tetrahedral structure to form a relatively flat top surface. In the continuous balance of the two corrosion directions, the protrusions in the shape of a quadrangular pyramid are engraved. If the concentration of the alkali etching solution is too small, the corrosion rates of different crystal surfaces of the silicon crystal will be different, so that the protrusions in the shape of a quadrangular pyramid cannot be obtained, which is not conducive to the preparation of the texturing wafer with high flatness. If the concentration of the alkali etching solution is too large, the corrosion is too strong, which will lead to the protrusions in the shape of a quadrangular pyramid with too long side length, and it is not conducive to obtaining a uniform texturing surface.

[0034] In addition, the alkali etching time and the alkali etching temperature are simultaneously controlled in the range of 40s-120s and 50°C-80°C respectively, and under the synergistic effect of the three factors of the concentration of the alkali etching solution, the alkali etching time and the temperature, the bottom side length of the protrusion (i.e. the maximum cross-sectional width of the protrusion) can be controlled in the range of 2μm-8μm, so that a texturing surface with high flatness can be prepared subsequently. If the alkali etching time is less than 40s, the etching amount is insufficient, which cannot sufficiently remove the damage layer (i.e. there are many cutting line marks remaining on the surface of the final texturing wafer), and the protrusions cannot be obtained. If the alkali etching time is more than 120s, the etching amount is excessive, which will finally lead to the bottom side length of each protrusion being too large, and a texturing surface with high flatness cannot be obtained. If the alkali etching temperature is too low, the protrusions in the shape of a quadrangular pyramid cannot be obtained, and the damage layer cannot be sufficiently removed. Understandably, the etching rate will increase with the increase of the alkali etching temperature, but if the alkali etching temperature is too high, the etching rate will be too fast, which will make the process conditions uncontrollable, and the shape and size of the protrusions cannot be controlled.

[0035] Exemplarily, the alkali etching time can be 40s, 50s, 60s, 70s, 80s, 90s, 100s, 110s, 120s, etc.

[0036] Exemplarily, the alkali etching temperature can be 50℃, 52℃, 55℃, 57℃, 60℃, 62℃, 65℃, 68℃, 70℃, 72℃, 75℃, 78℃, etc.

[0037] The preparation method has simple steps and strong process reliability, and can efficiently and sufficiently remove the damage layer of the silicon wafer. The "sufficient removal of the damage layer" means that the cutting line marks are hardly observed in the final product, and a raised structure with a suitable size can be prepared, so that the nucleation site can expand into a light-trapping structure with a suitable size.

[0038] In some embodiments of the present application, the alkaline solution also etches the side wall of the raised structure to form a nucleation site on the side wall of the raised structure. In this way, it is beneficial to make the pre-textured layer more smoothly to obtain a textured layer with higher flatness.

[0039] The embodiment of the present application also provides a textured wafer, which comprises a substrate and a textured surface arranged on at least one side surface of the substrate. The textured surface layer comprises densely arranged light-trapping structures, and the maximum cross-sectional width of the light-trapping structures is in the range of 1 μm-4 μm. Exemplarily, the maximum cross-sectional width of the light-trapping structures can be 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 3.8 μm, etc.

[0040] The above-mentioned textured wafer has densely arranged light-trapping structures on the surface. These light-trapping structures are densely arranged on the surface of the textured wafer like a mountainous area. After the incident light is incident on the first point on one side surface of the light-trapping structure, the reflected light is incident on the surface of another adjacent light-trapping structure again to form the second light absorption, and even n times of light absorption. Especially, the size of each light-trapping structure is small and the density is high, so the light is more likely to be reflected and absorbed between different light-trapping structures, so that the textured wafer can achieve a lower reflectivity. At the same time, the size of the light-trapping structure is small and the density is high, so the textured surface has small height difference and high flatness, which is beneficial to the deposition of other film layers (such as non-silicon crystal film layer, transparent oxide layer, etc.) in the subsequent battery preparation process and the close contact between the other film layers and the grid lines, thereby reducing the internal resistance of the battery and further improving the photoelectric conversion efficiency of the battery.

[0041] In the present application, the above-mentioned textured wafer can have a textured surface layer on both side surfaces, or have a textured surface layer on one side surface and a polished surface on the other side surface.

[0042] In some embodiments of the present application, the number of light-trapping structures per 100 μm 2The number of light-trapping structures in the rough surface layer is 60-100. In this way, the density of light-trapping structures in the rough surface layer is in a more suitable range, which is more conducive to improving the flatness of the rough surface, and thus is more conducive to further improving the photoelectric conversion efficiency of the solar cell. For example, the number of light-trapping structures in the rough surface layer per 100 μm 2 The number of light-trapping structures in the rough surface layer can be 60, 65, 70, 75, 80, 85, 90, 95, 100, etc.

[0043] In some embodiments of the present application, the adjacent light-trapping structures are arranged without spacing. It can be understood that there is a clear boundary between the bottom edge of the light-trapping structure and the bottom edge of the adjacent light-trapping structure, but there is almost no gap. In this way, the density of light-trapping structures in the rough surface layer is higher, and the flatness of the rough surface is higher, which is more conducive to improving the photoelectric conversion efficiency of the final solar cell.

[0044] In some embodiments of the present application, the light-trapping structure is in the shape of a quadrangular pyramid; the maximum cross-sectional dimension of the light-trapping structure gradually decreases in the direction away from the base layer. In this way, the light-trapping structure is in the shape of an upright "pyramid", which is more conducive to multiple absorption of light. In the present application, the "quadrangular pyramid" specifically refers to the overall shape of the light-trapping structure being in the shape of a quadrangular pyramid, but the side edges thereof can be straight edges or arc lines; the side walls thereof can be flat surfaces or curved surfaces; at this time, the maximum cross-sectional width of the light-trapping structure refers to the length of the bottom edge of the quadrangular pyramid, that is, the intersection line between the quadrangular pyramid and the base layer.

[0045] In some embodiments of the present application, the height of the light-trapping structure is in the range of 1.23 μm-1.58 μm. In this way, the height of the rough surface layer is also controlled in the above range, and the flatness of the rough surface layer is higher. In addition, taking the quadrangular pyramid-shaped light-trapping structure as an example, the length of the bottom edge of the light-trapping structure is in the range of 1 μm-4 μm, and the height thereof is also controlled in the above range, so the angle of the inclination angle between the side wall of the light-trapping structure and the base layer is also controlled in a more suitable range which is more conducive to multiple absorption of light. For example, the height of the light-trapping structure can be 1.23 μm, 1.25 μm, 1.27 μm, 1.3 μm, 1.32 μm, 1.35 μm, 1.37 μm, 1.4 μm, 1.42 μm, 1.45 μm, 1.47 μm, 1.5 μm, 1.52 μm, 1.55 μm, 1.58 μm, etc.

[0046] In some specific embodiments, the preparation of the texturing sheet includes the following steps:

[0047] S01, the silicon wafer is cleaned with No. 1 cleaning solution, the cleaning temperature is 60-90℃, and the cleaning time is 5-20min; wherein, No. 1 solution contains hydrogen peroxide and ammonia water, the ammonia water concentration is about 2-10wt%, and the hydrogen peroxide concentration is about 2-10wt%. Understandably, organic matter pollution will be inevitably introduced in the production, transportation and storage process of the silicon wafer, which will hinder the subsequent process. Hydrogen peroxide can oxidize and decompose organic matter into small molecules, and ammonia water can complex and dissolve small molecules, thereby removing organic matter.

[0048] S02, the silicon wafer is continuously cleaned with No. 2 cleaning solution. The cleaning temperature is 60-90℃, and the cleaning time is 5-20min; No. 2 cleaning solution is an aqueous solution of hydrochloric acid and hydrogen peroxide, and the concentration of hydrochloric acid and hydrogen peroxide is 2-10wt%. Understandably, there are metal contaminants remaining on the surface of the silicon wafer, and the metal will introduce intermediate energy levels in the single crystal silicon band gap, which is a strong carrier recombination center. Strong acid and strong oxidant can remove the above metal contaminants.

[0049] S03, alkali throwing. The silicon wafer is sequentially cleaned and alkali thrown to obtain a texturing pretreated silicon wafer; the texturing pretreated silicon wafer comprises a base layer and a pre-texturing layer arranged on at least one side surface of the base layer, and the pre-texturing layer comprises a plurality of protrusions, the protrusions are in the shape of a quadrangular pyramid, and at least the side wall of the protrusions is distributed with nucleation sites;

[0050] The conditions of the alkali throwing treatment include: using a strong alkali solution with a concentration of 15-30wt% to etch the silicon wafer; the duration of the alkali throwing treatment is 40-120s, and the alkali throwing temperature is 50-80℃.

[0051] S04, pre-cleaning. The pre-cleaning solution is a mixed solution of KOH and H2O2, wherein the concentration of KOH is about 0.5-5wt%, and the concentration of H2O2 is about 1-10wt%; the cleaning temperature is 40-80℃, and the cleaning time is about 120-360s. Understandably, due to the previous process, the surface of the silicon wafer will inevitably be contaminated with organic matter such as oil, which will affect the contact between the subsequent texturing solution and the silicon wafer, and needs to be removed. At this time, H2O2 can oxidize organic matter, and dilute KOH can dissolve the oxidized organic matter.

[0052] S05, texturing, the texturing temperature is about 60-90℃, and the texturing time is 6-15min. The texturing solution is a mixture of strong alkali and organic additive, wherein the concentration of the strong alkali (KOH and / or NaOH) is about 1-10wt%. In some embodiments, the texturing solution further comprises an organic additive (e.g., glycerol, ethylene glycol, propanol, etc.), wherein the mass percentage of the organic additive in the texturing solution is in the range of greater than 0 to less than or equal to 5wt%. The texturing solution in the concentration range can achieve anisotropic etching of the silicon wafer, and can etch the aforementioned convex structure into a "pyramid" structure of light-trapping structure, to obtain a textured layer.

[0053] S06, first post-cleaning. The process parameters are the same as those in S04, and a pre-cleaning solution is also used. The organic additive remaining from the above texturing process can be removed.

[0054] S07, rounding. The texturing process can cause sharp edges at the top and bottom of the "pyramid", which is not conducive to subsequent film plating and screen printing processes. The rounding process converts the sharp edges into rounded corners with a certain arc by acid etching. The etching solution used is an aqueous solution of concentrated nitric acid and hydrofluoric acid, wherein the volume ratio of hydrofluoric acid is less than 1%, and the process temperature used is 5-20℃, and the time is 1-10min.

[0055] S08, second post-cleaning. After the previous processes, metal contaminants may still remain on the surface of the silicon wafer and need to be removed. The cleaning temperature is 50-70℃, the cleaning time is 1-3min; the cleaning solution used is an aqueous solution of hydrochloric acid and hydrogen peroxide, and the concentration of both hydrochloric acid and hydrogen peroxide is 1-10wt%.

[0056] S09, hydrofluoric acid passivation. After the previous processes, the textured wafer has been prepared, but the silicon wafer will naturally oxidize to form a thin layer of silicon dioxide in the air, so hydrofluoric acid is used to form a protective film composed of a single layer of fluorine atoms on the surface of the silicon wafer to prevent oxidation of the silicon wafer. After treatment, the textured wafer is slowly lifted out of the water, taking away the water droplets.

[0057] S10, drying. After all the processes are completed, the textured wafer is dried with nitrogen.

[0058] The embodiments of the present application also provide a solar cell comprising the textured wafer provided by the embodiments of the present application. Since the textured wafer provided by the embodiments of the present application is used, the solar cell has a smaller internal resistance and a higher photoelectric conversion efficiency.

[0059] In some embodiments of the present application, the solar cell comprises a heterojunction cell. In some specific embodiments, the heterojunction cell comprises a conductive oxide layer, a P-type non-silicon thin film layer, an intrinsic hydrogen-rich amorphous silicon thin film layer, a texturing layer, an intrinsic hydrogen-rich amorphous silicon thin film layer, an N-type non-silicon thin film layer, and a conductive oxide layer, which are sequentially stacked.

[0060] In some embodiments, the conductive oxide layer is provided with a grid layer.

[0061] The technical solutions of the present application are further described in the following embodiments.

[0062] Embodiment 1

[0063] S01, the silicon wafer is cleaned with No. 1 cleaning solution, the cleaning temperature is 80℃, and the cleaning time is 10min; wherein No. 1 cleaning solution contains hydrogen peroxide and ammonia water, the concentration of ammonia water is 3wt%, and the concentration of hydrogen peroxide is 6wt%.

[0064] S02, the silicon wafer is further cleaned with No. 2 cleaning solution. The cleaning temperature is 80℃, and the cleaning time is 10min; No. 2 cleaning solution is an aqueous solution of hydrochloric acid and hydrogen peroxide, and the concentration of hydrochloric acid is 4wt%, and the concentration of hydrogen peroxide is 6wt%.

[0065] S03, 44mL of 50wt% KOH solution is mixed with 106mL of water to prepare an alkali etching solution (the concentration of KOH is about 20wt%); the silicon wafer cleaned in S02 is placed in the above-mentioned alkali etching solution and treated at 80℃ for 60s to obtain a texturing pretreated silicon wafer, which has a pre-texturing layer with a plurality of densely arranged four-pyramid-shaped protrusions on the surface.

[0066] S04, the texturing pretreated silicon wafer prepared in S03 is cleaned with a mixed solution of KOH and H2O2, wherein the concentration of KOH is about 1wt%, and the concentration of H2O2 is about 5wt%; the cleaning temperature is 65℃, and the cleaning time is about 240s.

[0067] S05, the above-mentioned cleaned texturing pretreated silicon wafer is placed in a texturing solution and treated at 80℃ for 480s. The texturing solution is a mixed solution of KOH and TS53 (trade name), wherein the concentration of KOH is 2wt%, and the concentration of TS53 is about 1wt%.

[0068] S06, the first post-cleaning. The process parameters are the same as those of S04, and the same pre-cleaning solution is used.

[0069] S07, rounding. The etching solution used is a concentrated nitric acid, hydrofluoric acid aqueous solution, wherein the volume ratio of hydrofluoric acid is less than 1%, and the process temperature is 12℃, and the time is 4min.

[0070] S08, second post-cleaning. The cleaning temperature is 60℃, the cleaning time is 2min; the cleaning solution used is a hydrochloric acid and hydrogen peroxide aqueous solution, and the concentration of hydrochloric acid and hydrogen peroxide is 5wt%.

[0071] S09, hydrofluoric acid passivation.

[0072] S10, dry the texturing wafer by nitrogen blowing, to obtain the texturing wafer of example 1.

[0073] Example 2

[0074] The difference from example 1 is that in S03, the alkali etching solution is 15wt% KOH, the alkali etching time is 60s, and the temperature is 65℃; the obtained texturing pretreated silicon wafer has a pre-texturing layer, and the surface of the pre-texturing layer has a plurality of densely arranged four-pyramid-shaped protrusions.

[0075] Example 3

[0076] The difference from example 1 is that in S03, the alkali etching solution is 30wt% KOH, the alkali etching time is 60s, and the temperature is 65℃; the obtained texturing pretreated silicon wafer has a pre-texturing layer, and the surface of the pre-texturing layer has a plurality of densely arranged four-pyramid-shaped protrusions.

[0077] Example 4

[0078] The difference from example 1 is that in S03, the alkali etching time is 40s; the obtained texturing pretreated silicon wafer has a pre-texturing layer, and the surface of the pre-texturing layer has a plurality of densely arranged four-pyramid-shaped protrusions; and in S05, the obtained texturing pretreated silicon wafer is placed in the texturing solution and treated at 80℃ for 360s to obtain the texturing wafer provided in example 5.

[0079] Example 5

[0080] The difference from example 1 is that in S03, the alkali etching time is 100s; the obtained texturing pretreated silicon wafer has a pre-texturing layer, and the surface of the pre-texturing layer has a plurality of densely arranged four-pyramid-shaped protrusions.

[0081] Example 6

[0082] The difference from example 1 is that in S03, the alkali etching temperature is 55℃; the obtained texturing pretreated silicon wafer has a pre-texturing layer, and the surface of the pre-texturing layer has a plurality of densely arranged four-pyramid-shaped protrusions.

[0083] Example 7

[0084] The difference from Example 1 is that in S03, the time for alkali etching is 75°C; the obtained texturing pretreated silicon wafer has a pre-texturing layer, and the surface of the pre-texturing layer has a plurality of densely arranged four-pyramid-shaped protrusions.

[0085] To highlight the beneficial effects of the embodiments of the present application, the following comparative examples are provided.

[0086] Comparative Example 1

[0087] The difference from Example 1 is only that in S03, the alkali etching solution is 35wt% KOH; the obtained texturing pretreated silicon wafer has a pre-texturing layer, and the surface of the pre-texturing layer has a plurality of four-pyramid-shaped protrusions.

[0088] Comparative Example 2

[0089] The difference from Example 1 is only that in S03, the time for alkali etching is 600s; the obtained texturing pretreated silicon wafer has a pre-texturing layer, and the surface of the pre-texturing layer has four-pyramid-shaped protrusions.

[0090] Comparative Example 3

[0091] The difference from Example 1 is only that in S03, the temperature is 35°C, and the obtained texturing pretreated silicon wafer.

[0092] Performance characterization test

[0093] (1) The texturing wafer prepared in each example and comparative example was subjected to scanning electron microscope test.

[0094] (2) The surface of the texturing wafer prepared in each example and comparative example was printed with a special electrode pattern (see Figure 5 ), and the contact resistance of the texturing wafer and the grid line was tested according to the following steps:

[0095] An AT510Pro direct current resistance tester was used, the 5th measurement range and large current (670μA) signal source mode were selected, the maximum range was 300Ω, and the resolution was 10mΩ. First, the resistance R1 between the 1st and 2nd electrodes was measured, wherein the 1st and 2nd electrodes were 1mm apart, and it can be understood that R1 is equal to the contact resistance of each of the two electrodes plus the resistance of 1mm of the silicon wafer itself. Next, the resistance R2 between the 2nd and 3rd electrodes was measured, wherein the 2nd and 3rd electrodes were 2mm apart, and it can be understood that R2 is equal to the contact resistance of each of the two electrodes plus the resistance of 2mm of the silicon wafer itself. In this way, R3, R4 and R5 can be measured. Using R1-R5 to plot the electrode distance, half of the Y-axis intercept is the contact resistance.

[0096] Table 1: Summary of the parameters of the texturing pretreated silicon wafer and the texturing wafer prepared in each example and comparative example

[0097]

[0098]

[0099] Figure 2A is a SEM photo of the texturing pretreated silicon wafer prepared in Example 1 of the present application, Figure 2B is a cross-sectional SEM photo thereof. It can be seen from Figure 2A that the base edge length of each protrusion is about 5 μm, and the white small dots (nucleation sites) are distributed on the side wall of each protrusion; it can be seen from Figure 2B that the height of the protrusion is small, and the protrusion tends to be a flat structure, and the damage layer of the silicon wafer has also been completely removed. The texturing wafer prepared therefrom (see Figure 2C ) has a dense arrangement of light-trapping structures with a base edge length of about 2 μm in the texturing layer, and the size distribution of each light-trapping structure is also relatively uniform, and the flatness of the texturing layer is high, which can also be seen from the contact resistance data in Table 1.

[0100] Figure 3A and Figure 3B are SEM photos of the texturing pretreated silicon wafer and the texturing wafer prepared in Example 5 of the present application, respectively, it can be seen that the base edge length of the protrusion of the texturing pretreated silicon wafer is about 8 μm, the base edge length of the light-trapping structure is about 3 μm, and the distribution of the base edge length of the plurality of light-trapping structures is relatively uniform.

[0101] The texturing pretreated silicon wafer and the texturing wafer prepared in the comparative example are obviously inferior to those of the examples, Figure 4A and Figure 4B are SEM photos of the texturing pretreated silicon wafer and the texturing wafer prepared in Comparative Example 1, respectively, the base edge length of the protrusion of the texturing pretreated silicon wafer is about 20 μm, the base edge length of the light-trapping structure is distributed within 1-5 μm, the distribution of the base edge length of the plurality of light-trapping structures is very uneven, and the surface flatness of the texturing layer is low, and the contact resistance with the gate line is also larger (see the data in Table 1).

[0102] The above is an exemplary embodiment of the present application, it should be noted that for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, which are also considered to be within the scope of protection of the present application.

Claims

1. A pre-treatment silicon wafer for texturing, characterized in that, A method for preparing a texturing wafer; the texturing wafer includes a substrate layer and a pre-texturing layer arranged on at least one side surface of the substrate layer, any 100 μm 2 of the pre-texturing layer includes 2-11 protrusions, the protrusions are in the shape of a quadrangular pyramid, the bottom side length of the protrusions is in the range of 2 μm-8 μm, and the height of the protrusions is in the range of 0.5-2 μm; The side wall of the protrusion is distributed with nucleation sites, which are small bump structures with a maximum cross-sectional width in the range of greater than 0 to less than or equal to 1 μm and a height in the range of greater than 0 to less than or equal to 0.75 μm.

2. The etch-preparation pretreated silicon wafer of claim 1, wherein, The cross-sectional size of the protrusion gradually decreases in a direction away from the base layer.

3. A method of preparing a pre-textured silicon wafer, characterized by, The preparation method comprises the following steps: The silicon wafer is sequentially cleaned and alkali-etched to obtain a texturing pretreated silicon wafer; the texturing pretreated silicon wafer comprises a substrate layer and a pre-texturing layer arranged on at least one side surface of the substrate layer, and any 100μm 2 The pre-texturing layer comprises 2-11 protrusions, the protrusions are in the shape of a quadrangular pyramid, the bottom side length of the protrusions is in the range of 2μm-8μm, and the height of the protrusions is in the range of 0.5μm-2μm; the sidewall of the protrusions is distributed with nucleation sites, which are small bump structures with a maximum cross-sectional width in the range of greater than 0 to less than or equal to 1μm and a height in the range of greater than 0 to less than or equal to 0.75μm. The alkali-throwing treatment conditions include: using a strong alkali solution with a concentration of 15 wt%-30 wt% to etch the silicon wafer; the duration of the alkali-throwing treatment is 40 s-120 s, and the temperature of the alkali-throwing treatment is 50 °C-80 °C.

4. A wafer texturing apparatus characterized by, The texturing wafer is prepared from the texturing pretreated silicon wafer according to any one of claims 1-2. The suede sheet comprises a base layer and a suede layer arranged on at least one side surface of the base layer, any 100 μm 2 The suede layer has 60-100 light-trapping structures, the maximum cross-sectional width of the light-trapping structures is in the range of 1 μm-4 μm; the light-trapping structures are in the shape of quadrangular pyramids; the maximum cross-sectional size of the light-trapping structures gradually decreases in the direction away from the base layer.

5. The etch tab of claim 4, wherein, The height of the light-trapping structure is in the range of 1.23 μm-1.58 μm.

6. A solar cell, characterized by, The solar cell comprises the texturing wafer according to claim 4 or 5.

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