A control method, bare chip and system for bare chip transmission

Abstract

The present disclosure relates to the field of integrated circuits, and more particularly to a control method, die, and system for die-to-die transmission. The method comprises: when a first die needs to send data, it sends data to a second die, and the second die has a memory space for receiving data by default; the first die receives a data packet carrying first backpressure information sent by the second die at a preset time interval; the first die determines whether to stop sending data to the second die based on the first backpressure information in the data packet. In the method provided by the embodiment of the present disclosure, since the second die (receiving end) has a memory space for receiving data by default, the first die (transmitting end) can directly send data to the second die when it needs to send data, thereby reducing data transmission delay; and the second die will feedback the first backpressure information to the first die along with the data packet at a preset time interval. The above-mentioned instant feedback mechanism can ensure that the backpressure feedback delay is minimized.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and more particularly to a back-voltage control method, die, and system in die-to-die (D2D) transmission. Background Art

[0002] Currently, standard protocols are commonly used to implement end-to-end data transmission between dies. These protocols primarily employ a credit-based flow control mechanism. Examples of these protocols include the high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe) or the Universal Chip Interconnect Express (UCIe).

[0003] In the current flow control mechanism, the sender cannot send data by default. Before sending a data packet, it must first check whether the receiving end has enough space to accommodate the data. After the communication between the sender and the receiving end is completed, it will determine whether to send the data packet. This causes a certain waiting time for the sender to send the data packet, resulting in a large data transmission delay. Summary of the Invention

[0004] In view of this, the present disclosure proposes a control method, die, and system for die-to-die transmission.

[0005] According to one aspect of the present disclosure, a control method for die-to-die transmission is provided, which is used in a first die. The method includes:

[0006] When data needs to be sent, the data is sent to the second bare chip, and the second bare chip has a memory space for receiving data by default;

[0007] receiving a data packet carrying the first back pressure information sent by the second bare chip in a timely manner according to a preset time interval (the default setting is 1 clock cycle, the minimum value, and the fastest feedback);

[0008] Determine whether to stop sending data to the second die according to the first back pressure information in the data packet.

[0009] In a possible implementation, the first back pressure information includes a first back pressure flag corresponding to each of the plurality of second cache queues of the second die, where the first back pressure flag is used to indicate whether the amount of data in the second cache queue is greater than a first back pressure threshold.

[0010] In another possible implementation, there is a one-to-one correspondence between the multiple first cache queues of the first die and the multiple second cache queues of the second die;

[0011] The determining, according to the first back pressure information in the data packet, whether to stop sending data to the second die includes:

[0012] According to each first back pressure flag in the data packet, it is determined whether the first cache queue corresponding to each first back pressure flag stops sending data to the corresponding second cache queue.

[0013] In another possible implementation, the first cache queue is a channel first-in-first-out (FIFO) memory of a transmitting interface of the first die, and the second cache queue is a channel FIFO memory of a receiving interface of the second die.

[0014] In another possible implementation, before determining whether to stop sending data to the second die according to the first back pressure information in the data packet, the method further includes:

[0015] The receiving interface of the first bare chip unpacks the received data packet and extracts the first back pressure information from the data packet;

[0016] The receiving interface of the first die feeds back the first back pressure information to the sending interface of the first die, and the sending interface of the first die is used to determine whether to stop sending data to the receiving interface of the second die according to the first back pressure information.

[0017] In another possible implementation, the first die includes a target module and an upstream module of the target module, and the method further includes:

[0018] The target module sends second back pressure information to an upstream module of the target module according to its own cache occupancy, where the second back pressure information is used to instruct the upstream module of the target module whether to stop outputting data.

[0019] In another possible implementation, the second back pressure information includes a back pressure signal, and the target module sends the second back pressure information to an upstream module of the target module based on its own cache occupancy, including:

[0020] When the data volume of the target module is greater than a second back pressure threshold, the target module sends the back pressure signal to the upstream module of the target module, where the back pressure signal is used to instruct the upstream module of the target module to stop outputting data.

[0021] In another possible implementation, the target module and the upstream module of the target module include any one or more combinations of the following:

[0022] The target module is a retry buffer (English: Retry Buffer), and the upstream module of the target module is a FIFOs matrix;

[0023] The target module is a FIFOs matrix, and the upstream module of the target module is an arbitrator; and

[0024] The target module is a FIFOs matrix, and the upstream module of the target module is a plurality of channel FIFO memories of a transmitting interface.

[0025] In another possible implementation, the target module is a plurality of channel FIFO memories of a receiving interface, the upstream module of the target module is a plurality of types of synchronous first-in-first-out (SFIFO) matrices, and the plurality of channel FIFO memories of the receiving interface and the plurality of types of SFIFO matrices have a one-to-one correspondence;

[0026] The second back pressure information includes a second back pressure flag bit corresponding to each of the multiple channel FIFO memories of the receiving interface, and the second back pressure flag bit is used to indicate whether the corresponding type SFIFO matrix stops outputting data.

[0027] According to another aspect of the present disclosure, a control method for die-to-die transmission is provided, which is used in a second die, and the method includes:

[0028] receiving data sent by the first bare chip, wherein the second bare chip has a memory space for receiving the data by default;

[0029] A data packet carrying first back pressure information is sent to the first die at a preset time interval, so that the first die determines whether to stop sending data to the second die according to the first back pressure information in the data packet.

[0030] In a possible implementation, the first back pressure information includes a first back pressure flag corresponding to each of the plurality of second cache queues of the second die, where the first back pressure flag is used to indicate whether the amount of data in the second cache queue is greater than a first back pressure threshold.

[0031] In another possible implementation, there is a one-to-one correspondence between the multiple first cache queues of the first die and the multiple second cache queues of the second die, so that the first die determines whether the first cache queue corresponding to each first back pressure flag bit stops sending data to the corresponding second cache queue based on each first back pressure flag bit in the data packet.

[0032] In another possible implementation, the first cache queue is a channel FIFO memory of a transmitting interface of the first die, and the second cache queue is a channel FIFO memory of a receiving interface of the second die.

[0033] In another possible implementation, sending the data packet carrying the first back pressure information to the first die at a preset time interval includes:

[0034] The receiving interface of the second bare chip inserts the first back pressure information into the data packet of the sending interface of the second bare chip according to the preset time interval;

[0035] The sending interface of the second bare chip transmits the data packet carrying the first back pressure information to the receiving interface of the first bare chip at the preset time interval.

[0036] In another possible implementation, the second die includes a target module and an upstream module of the target module, and the method further includes:

[0037] The target module sends second back pressure information to an upstream module of the target module according to its own cache occupancy, where the second back pressure information is used to instruct the upstream module of the target module whether to stop outputting data.

[0038] In another possible implementation, the second back pressure information includes a back pressure signal, and the target module sends the second back pressure information to an upstream module of the target module based on its own cache occupancy, including:

[0039] When the data volume of the target module is greater than a second back pressure threshold, the target module sends the back pressure signal to the upstream module of the target module, where the back pressure signal is used to instruct the upstream module of the target module to stop outputting data.

[0040] In another possible implementation, the target module and the upstream module of the target module include any one or more combinations of the following:

[0041] The target module is a retry buffer, and the upstream module of the target module is a FIFOs matrix;

[0042] The target module is a FIFOs matrix, and the upstream module of the target module is an arbitrator; and

[0043] The target module is a FIFOs matrix, and the upstream module of the target module is a plurality of channel FIFO memories of a transmitting interface.

[0044] In another possible implementation, the target module is a plurality of channel FIFO memories of a receiving interface, the upstream module of the target module is a plurality of types of SFIFO matrices, and there is a one-to-one correspondence between the plurality of channel FIFO memories of the receiving interface and the plurality of types of SFIFO matrices;

[0045] The second back pressure information includes a second back pressure flag bit corresponding to each of the multiple channel FIFO memories of the receiving interface, and the second back pressure flag bit is used to indicate whether the corresponding type SFIFO matrix stops outputting data.

[0046] According to another aspect of the present disclosure, a control method in die-to-die transfer is provided, for use in a die-to-die transfer system including a first die and a second die, the method comprising:

[0047] When the first die needs to send data, it sends the data to the second die, and the second die has a memory space for receiving data by default;

[0048] The second die receives data sent by the first die;

[0049] The second die sends a data packet carrying the first back pressure information to the first die at a preset time interval;

[0050] The first die receives a data packet carrying the first back pressure information and sent by the second die according to the clock cycle;

[0051] The first die determines whether to stop sending data to the second die according to the first back pressure information in the data packet.

[0052] According to another aspect of the present disclosure, there is provided a first die, the first die comprising: a transmitting interface and a receiving interface;

[0053] The sending interface is used to send data to the second bare chip when data needs to be sent, and the second bare chip has a memory space for receiving data by default;

[0054] The receiving interface is configured to receive a data packet carrying first back pressure information sent by the second die at a preset time interval, and feed back the first back pressure information in the data packet to the sending interface;

[0055] The sending interface is further configured to determine whether to stop sending data to the second die according to the first back pressure information.

[0056] In a possible implementation, the first back pressure information includes a first back pressure flag corresponding to each of the plurality of second cache queues of the second die, where the first back pressure flag is used to indicate whether the amount of data in the second cache queue is greater than a first back pressure threshold.

[0057] In another possible implementation, there is a one-to-one correspondence between the multiple first cache queues of the first die and the multiple second cache queues of the second die;

[0058] The sending interface is further used for:

[0059] According to each first back pressure flag in the data packet, it is determined whether the first cache queue corresponding to each first back pressure flag stops sending data to the corresponding second cache queue.

[0060] In another possible implementation, the first cache queue is a channel FIFO memory of a transmitting interface of the first die, and the second cache queue is a channel FIFO memory of a receiving interface of the second die.

[0061] In another possible implementation, the first die further includes a target module and an upstream module of the target module;

[0062] The target module is configured to send second back pressure information to an upstream module of the target module according to its own cache occupancy, where the second back pressure information is used to instruct the upstream module of the target module whether to stop outputting data.

[0063] In another possible implementation, the second back pressure information includes a back pressure signal;

[0064] The target module is further configured to send the back pressure signal to the upstream module of the target module when the data volume of the target module is greater than a second back pressure threshold, wherein the back pressure signal is configured to instruct the upstream module of the target module to stop outputting data.

[0065] In another possible implementation, the target module and the upstream module of the target module include any one or more combinations of the following:

[0066] The target module is a retry buffer, and the upstream module of the target module is a FIFOs matrix;

[0067] The target module is a FIFOs matrix, and the upstream module of the target module is an arbitrator; and

[0068] The target module is a FIFOs matrix, and the upstream module of the target module is a plurality of channel FIFO memories of a transmitting interface.

[0069] In another possible implementation, the receiving interface of the first bare chip is further configured to:

[0070] Unpacking the received data packet and extracting the first back pressure information from the data packet;

[0071] The first back pressure information is fed back to the sending interface of the first die, and the sending interface of the first die is used to determine whether to stop sending data to the receiving interface of the second die according to the first back pressure information.

[0072] In another possible implementation, the target module is a plurality of channel FIFO memories of a receiving interface, the upstream module of the target module is a plurality of types of SFIFO matrices, and there is a one-to-one correspondence between the plurality of channel FIFO memories of the receiving interface and the plurality of types of SFIFO matrices;

[0073] The second back pressure information includes a second back pressure flag bit corresponding to each of the multiple channel FIFO memories of the receiving interface, and the second back pressure flag bit is used to indicate whether the corresponding type SFIFO matrix stops outputting data.

[0074] According to another aspect of the present disclosure, there is provided a second die, the second die comprising: a receiving interface and a transmitting interface;

[0075] The receiving interface is used to receive data sent by the first bare chip, and the second bare chip has a memory space for receiving data by default;

[0076] The sending interface is used to send a data packet carrying first back pressure information to the first bare chip at a preset time interval, and the first bare chip is used to determine whether to stop sending data to the second bare chip based on the first back pressure information in the data packet.

[0077] In a possible implementation, the first back pressure information includes a first back pressure flag corresponding to each of the plurality of second cache queues of the second die, where the first back pressure flag is used to indicate whether the amount of data in the second cache queue is greater than a first back pressure threshold.

[0078] In another possible implementation, there is a one-to-one correspondence between the multiple first cache queues of the first die and the multiple second cache queues of the second die, so that the first die determines whether the first cache queue corresponding to each first back pressure flag bit stops sending data to the corresponding second cache queue based on each first back pressure flag bit in the data packet.

[0079] In another possible implementation, the first cache queue is a channel FIFO memory of a transmitting interface of the first die, and the second cache queue is a channel FIFO memory of a receiving interface of the second die.

[0080] In another possible implementation,

[0081] The receiving interface of the second bare chip is further configured to insert the first back pressure information into a data packet of the sending interface of the second bare chip according to the preset time interval;

[0082] The sending interface of the second bare chip is further configured to transmit the data packet carrying the first back pressure information to the receiving interface of the first bare chip according to the preset time interval.

[0083] In another possible implementation, the second die further includes a target module and an upstream module of the target module;

[0084] The target module is configured to send second back pressure information to an upstream module of the target module according to its own cache occupancy, where the second back pressure information is used to instruct the upstream module of the target module whether to stop outputting data.

[0085] In another possible implementation, the second back pressure information includes a back pressure signal;

[0086] The target module is further configured to send the back pressure signal to the upstream module of the target module when the data volume of the target module is greater than a second back pressure threshold, wherein the back pressure signal is configured to instruct the upstream module of the target module to stop outputting data.

[0087] In another possible implementation, the target module and the upstream module of the target module include any one or more combinations of the following:

[0088] The target module is a retry buffer, and the upstream module of the target module is a FIFOs matrix;

[0089] The target module is a FIFOs matrix, and the upstream module of the target module is an arbitrator; and

[0090] The target module is a FIFOs matrix, and the upstream module of the target module is a plurality of channel FIFO memories of a transmitting interface.

[0091] In another possible implementation, the target module is a plurality of channel FIFO memories of a receiving interface, the upstream module of the target module is a plurality of types of SFIFO matrices, and there is a one-to-one correspondence between the plurality of channel FIFO memories of the receiving interface and the plurality of types of SFIFO matrices;

[0092] The second back pressure information includes a second back pressure flag bit corresponding to each of the multiple channel FIFO memories of the receiving interface, and the second back pressure flag bit is used to indicate whether the corresponding type SFIFO matrix stops outputting data.

[0093] According to another aspect of the present disclosure, there is provided a die-to-die transfer system, the system comprising a first die and a second die;

[0094] The first bare chip is the first bare chip described in the fourth aspect or any possible implementation of the fourth aspect;

[0095] The second bare chip is the second bare chip described in the fifth aspect or any possible implementation of the fifth aspect.

[0096] An embodiment of the present disclosure provides a control method for die-to-die transmission. When a first die (transmitter) needs to send data, it can directly send the data to a second die (receiver). This is because the second die has memory space for receiving data by default. In this way, the first die does not need to check whether the memory space of the second die is sufficient before sending the data. This avoids the need for communication between the sender and the receiver before sending data in the related art, saves communication time, and reduces data transmission delay. In this implementation, the second die will feedback first back pressure information to the first die along with the data packet at a preset time interval. This instant feedback mechanism allows the first die to determine whether it needs to stop sending data based on the first back pressure information in the received data packet. Through the above-mentioned instant feedback mechanism, the back pressure feedback delay can be minimized, thereby improving the efficiency and reliability of data transmission.

[0097] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0098] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0099] Figure 1 A schematic structural diagram of a die-to-die transmission system provided by an exemplary embodiment of the present disclosure is shown.

[0100] Figure 2A flowchart of a control method in die-to-die transmission provided by an exemplary embodiment of the present disclosure is shown.

[0101] Figure 3 A schematic structural diagram of a bare chip provided by an exemplary embodiment of the present disclosure is shown.

[0102] Figure 4 A schematic diagram showing the principle of a control method in die-to-die transmission provided by an exemplary embodiment of the present disclosure is shown.

[0103] Figure 5 A flowchart of a control method in die-to-die transmission provided by another exemplary embodiment of the present disclosure is shown.

[0104] Figure 6 A schematic structural diagram of a first die provided by an exemplary embodiment of the present disclosure is shown.

[0105] Figure 7 FIG. 1 shows a schematic structural diagram of a second die provided by an exemplary embodiment of the present disclosure.

[0106] Figure 8 The present invention is a block diagram showing a device for performing back-pressure control in die-to-die transmission according to an exemplary embodiment. DETAILED DESCRIPTION

[0107] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0108] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0109] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0110] The AXI4 bus interface, the fourth version of the Advanced eXtensible Interface (AEXI), is a high-performance bus interface protocol standard widely used in the high-performance interconnect architecture of system-on-chips (SoCs). To achieve inter-die communication, the die typically use the AXI bus interface as the sender or receiver of valid data. After converting between standard or custom protocols, data is transmitted between the die at the physical layer. To meet the specific transmission requirements, specific methods such as back pressure are required to achieve effective and timely flow control, both end-to-end and between protocol transport layers.

[0111] In related technologies, the core idea of credit-based flow control mechanisms is that before a data packet is sent, it must first check whether the receiving end has sufficient space to accommodate the data before it can be sent. For example, in the PCIe protocol, before a data packet is sent, the receiving end sends a Data Link Layer Packet (DLLP) to the sending end. The DLLP contains the latest credit score, which indicates the available space in the receiving end's buffer. After the sending end parses the DLLP, it determines whether to send the data packet in the buffer based on the credit score. In other words, in this credit-based flow control mechanism, the sending end cannot send data by default. Before a data packet is sent, it must first check whether the receiving end has sufficient space to accommodate the data. After the sending end and the receiving end have completed communication, it can determine whether to send the data packet. This results in a certain waiting time for the sending end to send the data packet. In addition, standard protocol stacks such as PCIe and UCIe typically contain multiple layers, and the more complex design and implementation also increases the overall transmission delay before back pressure takes effect.

[0112] The present embodiment provides a method for controlling die-to-die transmission. Based on the combined considerations of high bandwidth and low latency, it employs a simplified transport layer structure and a custom protocol packet format, introducing a multi-layered fast backpressure mechanism for flow control. The backpressure control principle provided by the present embodiment is designed as follows: Within a certain end (a first die or a second die), a downstream module sends backpressure information to an upstream module based on its own buffer occupancy, instructing the upstream module to stop outputting data. This internally generated backpressure information is directly transmitted through the connection, either step by step or across steps, to take effect. Between the two ends of the physical layer (a first die and a second die), the first backpressure information of the second die's receiving interface (updated at a preset interval, with a default minimum of one clock cycle) is inserted into the data packet of the second die's transmitting interface. This information is then continuously transmitted through the physical layer to the first die's receiving interface. The first die's receiving interface decompresses and extracts the first backpressure information, which is then fed back to the first die's transmitting interface. The first die's transmitting interface then identifies the first backpressure information and determines whether to stop transmitting data. This overall backpressure control principle design minimizes the latency of backpressure feedback.

[0113] First, the application scenarios involved in the embodiment of the present disclosure are introduced. The die-to-die transmission system provided by the embodiment of the present disclosure includes multiple die, and the multiple die include at least a first die and a second die. Figure 1 , which shows a structural schematic diagram of a die-to-die transmission system provided by an exemplary embodiment of the present disclosure.

[0114] The system 10 includes a first die 12 and a second die 14. The first die 12 and the second die 14 can be two different dies, or can be two identical dies. A die is also called a bare chip, a bare crystal or a wafer, etc., and refers to a chip that has been cut from a wafer and has not been packaged. Each die is an independent functional chip that has not yet been packaged. These chips have not yet undergone the final packaging process and cannot be directly used in actual circuits. They are usually very small, only a few millimeters in size, and have pads or small holes for connecting to external circuits. Die-to-die transmission refers to a data transmission technology between multiple dies in the same package. This transmission method takes advantage of the extremely short connection distance between chips to achieve high-efficiency and high-bandwidth data exchange.

[0115] The first die 12 and the second die 14 are interconnected via a die-to-die interface. This interface, comprised of a physical layer (PHY) and a controller module, establishes a seamless connection between the die's internal interconnect structures, supporting a variety of advanced 2D, 2.5D, and 3D packaging technologies. The physical layer is the hardware component that implements data transmission, converting data signals into a format suitable for transmission between the two dies.

[0116] In the embodiment of the present disclosure, die-to-die transmission is performed between the first die 12 and the second die 14. The first die 12 is used to send data to the second die when data needs to be sent, and the second die has memory space for receiving data by default; the second die 14 is used to receive data sent by the first die; a data packet carrying first back pressure information is sent to the first die at a preset time interval; the first die 12 is also used to receive a data packet carrying first back pressure information sent by the second die at a preset time interval; and based on the first back pressure information in the data packet, it is determined whether to stop sending data to the second die.

[0117] Below, exemplary embodiments are used to introduce the control method for die-to-die transmission provided by the embodiments of the present disclosure.

[0118] Please refer to Figure 2 , which shows a flow chart of a control method for die-to-die transmission provided by an exemplary embodiment of the present disclosure. This embodiment uses this method for the above Figure 1 The die-to-die transfer system shown in FIG.

[0119] Step 201 : When a first die needs to send data, the first die sends the data to a second die. The second die has a memory space for receiving data by default.

[0120] When the first die needs to send data to the second die, it can send the data directly to the second die. Because the second die has memory space to receive data by default, the first die can send data to the second die without checking the memory space of the second die, that is, without communicating with the second die.

[0121] Step 202: The second die receives data sent by the first die.

[0122] Correspondingly, the second die can directly receive data sent by the first die without communicating with the first die in advance.

[0123] Step 203 : When the first die sends data to the second die, the second die sends a data packet carrying the first back pressure information to the first die at a preset time interval.

[0124] When the first die sends data to the second die, the second die updates the first back pressure information at a preset time interval, inserts the updated first back pressure information into the data packet to be sent, and sends the data packet carrying the first back pressure information to the first die.

[0125] Optionally, the first back pressure information includes a first back pressure flag corresponding to each of the multiple second cache queues of the second die, that is, each second cache queue corresponds to a first back pressure flag, and each first back pressure flag is used to indicate whether the data volume of the second cache queue is greater than the first back pressure threshold.

[0126] Since the second bare chip generally queues the data packets in the cache according to certain rules to form multiple second cache queues, and the data packets in each second cache queue are output in order, when the data volume of a second cache queue exceeds a certain threshold value, namely the first back pressure threshold, it indicates that the second cache queue is about to be full. At this time, corresponding back pressure control is required to stop the first cache queue in the corresponding first bare chip from sending data.

[0127] Illustratively, when the first backpressure flag is a first value, it indicates that the amount of data in the second cache queue is greater than the first backpressure threshold, indicating that the second cache queue is about to be full and that corresponding backpressure control is required to cause the corresponding first cache queue to stop sending data to the second cache queue. When the first backpressure flag is a second value, it indicates that the amount of data in the second cache queue is less than or equal to the first backpressure threshold, indicating that the second cache queue is not at risk of being full and that corresponding backpressure control is not required, and the corresponding first cache queue can continue to send data to the second cache queue. The first value is different from the second value. For example, the first backpressure flag is a 1-bit value, the first value is 1, and the second value is 0. This is not limited in the present embodiment.

[0128] Optionally, each channel of the receiving interface of the second bare chip has a FIFO memory, namely the channel FIFO memory of the receiving interface, and the channel FIFO memory of the receiving interface is used to store received data. The above-mentioned second cache queue is the channel FIFO memory of the receiving interface of the second bare chip.

[0129] Optionally, the second bare chip inserts the updated first back pressure information into the data packet to be sent, and sends the data packet carrying the first back pressure information to the first bare chip, which may include: the receiving interface of the second bare chip inserts the first back pressure information into the data packet of the sending interface of the second bare chip at a preset time interval, and the sending interface of the second bare chip transmits the data packet carrying the first back pressure information to the receiving interface of the first bare chip through the physical layer at a preset time interval.

[0130] Optionally, the preset time interval includes one or more clock cycles. That is, the second die may send a data packet carrying the first back pressure information once per clock cycle, or may send a data packet carrying the first back pressure information once every multiple clock cycles. The clock cycle may be fixed. A clock cycle is the minimum time unit for internal system operations and is determined by the frequency of the system clock. If the system clock frequency is 500 megahertz (MHz), then each clock cycle is the reciprocal of the clock frequency, that is, 2 nanoseconds (ns).

[0131] Among them, the data packet carrying the first back pressure information can be a Flit data packet. In network communications, messages are usually divided into smaller units for transmission, and these smaller units are called data packets. The data packet is further divided into smaller fixed-length units, called Flit data packets. In the PCIe6.0 standard protocol flit mode, the data packet is defined as a Flit data packet. Each Flit data packet contains a certain amount of data and necessary control information such as verification. For example, the receiving interface of the second bare chip includes 5 channel FIFO memories. The second bare chip inserts the 1-bit first back pressure flag of each channel FIFO memory of the receiving interface into the target field of the Flit data packet at a preset time interval, and sends the Flit data packet carrying the first back pressure information (i.e., the 5-bit first back pressure flag) to the first bare chip.

[0132] Step 204 : The first die receives a data packet carrying first back pressure information sent by the second die at a preset time interval.

[0133] When the first die sends data to the second die, the first die receives data packets carrying first back pressure information sent by the second die at preset time intervals.

[0134] Step 205 : The first die determines whether to stop sending data to the second die based on the first back pressure information in the data packet.

[0135] After receiving the data packet, the first die decapsulates the packet, extracts the first back pressure information from the packet, and determines whether to stop sending data to the second die based on the extracted first back pressure information. Optionally, the receiving interface of the first die decapsulates the received data packet and extracts the first back pressure information from the packet; the receiving interface of the first die feeds the first back pressure information back to the sending interface of the first die; and the sending interface of the first die determines whether to stop sending data to the receiving interface of the second die based on the first back pressure information.

[0136] Optionally, there is a one-to-one correspondence between the multiple first cache queues of the first die and the multiple second cache queues of the second die, and the first back pressure information includes a first back pressure flag corresponding to each of the multiple second cache queues of the second die. Determining whether to stop sending data to the second die based on the first back pressure information in the data packet may include: determining, based on each first back pressure flag in the data packet, whether the first cache queue corresponding to each first back pressure flag stops sending data to the corresponding second cache queue. That is, for each first back pressure flag in the data packet, if the first back pressure flag indicates that the amount of data in the second cache queue is greater than a first back pressure threshold, determining that the first cache queue corresponding to the first back pressure flag stops sending data to the corresponding second cache queue; and if the first back pressure flag indicates that the amount of data in the second cache queue is less than or equal to the first back pressure threshold, determining that the first cache queue corresponding to the first back pressure flag continues sending data to the corresponding second cache queue.

[0137] Illustratively, each channel of the transmitting interface of the first bare chip has a FIFO memory, namely the channel FIFO memory of the transmitting interface, which is used to store data to be sent. The above-mentioned first cache queue is the channel FIFO memory of the transmitting interface of the first bare chip.

[0138] In summary, the embodiments of the present disclosure provide a control method for die-to-die transmission. Since the second die (receiving end) has memory space for receiving data by default, the first die (transmitting end) can directly send data to the second die when it needs to send data. In this way, the first die does not need to check whether the memory space of the second die is sufficient before sending the data, thereby avoiding the need for communication between the transmitting end and the receiving end before sending data in the related art, saving communication time, and reducing data transmission delay. In this implementation, the second die will feedback first back pressure information to the first die along with the data packet at a preset time interval. This instant feedback mechanism enables the first die to determine whether it needs to stop sending data based on the first back pressure information in the received data packet. Through the above-mentioned instant feedback mechanism, the back pressure feedback delay can be minimized, thereby improving the efficiency and reliability of data transmission.

[0139] In a possible implementation, both the first die and the second die in the die-to-die transmission system include a transmitting channel and a receiving channel. The following takes a die (either the first die or the second die) as an example to introduce the transmitting channel and the receiving channel of the die. Figure 3 , which shows a schematic diagram of the die structure provided by an exemplary embodiment of the present disclosure. The die's transmit channel is used to send data from one end to the other end. The transmit channel may include a transmit interface (TX interface), a format conversion generator (FMT Gen), an arbitrator (Arbitrator), a synchronous data packet first-in-first-out controller (Flit SFIFO Ctrl), and a data packet transmit controller (Flit TXCtrl).

[0140] 1. Transmit interface: Responsible for receiving and caching the interface signals of the AXI channel, which is the starting point for data to enter the transmit channel. Each type of channel of the transmit interface has a FIFO memory, namely the channel FIFO memory of the transmit interface. The channel FIFO memory of the transmit interface is used to store the AXI type data to be sent. The multiple channel FIFO memories of the transmit interface include a write address FIFO memory, a write data FIFO memory, a read address FIFO memory, a read data FIFO memory, and a write response FIFO memory. For example, the figure only schematically shows the five types of channel FIFO memories of the transmit interface, namely the write address FIFO memory "AW_FIFO", the write data FIFO memory "W_FIFO", the read address FIFO memory "AR_FIFO", the read data FIFO memory "R_FIFO" and the write response FIFO memory "B_FIFO".

[0141] Among them, "AW" represents write address, and the write address FIFO memory "AW_FIFO" is used to store the address information of write operations; "W" represents write data, and the write data FIFO memory "W_FIFO" is a FIFO memory used for data writing; "AR" represents read address, and the read address FIFO memory "AR_FIFO" is used to store the address information of read operations; "R" represents read data, and the read data FIFO memory "R_FIFO" is a FIFO memory used for data reading; "B" represents buffering, and the write response FIFO memory "B_FIFO" is a FIFO memory for write operation response feedback.

[0142] The multiple channel FIFO memories of the sending interface are also used to output data packets of corresponding channel types to the format conversion generator according to preset time slots. Among them, 1 time slot is a unit of 8 bytes. The data packets of the channel types corresponding to the multiple channel FIFO memories are: write address channel packet "AW_PKT", write data channel packet "W_PKT", read address channel packet "AR_PKT", read data channel packet "R_PKT" and write response channel packet "B_PKT". This is not limited in the present embodiment.

[0143] 2. Format conversion generator: used to format data packets of different channel types and convert them into data packets with a custom fixed format (English: Fix Format) to maintain the uniformity of the format in subsequent processing.

[0144] 3. Arbiter: This uses round-robin arbitration to read and transmit packets from various cached data types, ensuring that data is processed in the order of established priority. Optionally, the arbiter can also output data using time-division multiplexing.

[0145] 4. Data Packet Synchronization FIFO Controller: This controller caches Flit packets and outputs valid Flit packets according to a custom protocol format, providing data buffering and control. The controller includes a matrix of FIFOs, a data buffer used to cache data output by the arbitrator. A Flit packet can optionally consist of multiple time slots; for example, eight time slots constitute a Flit packet.

[0146] 5. Packet Transmit Controller: This buffers valid Flit packets and, based on the ACK / NAK feedback mechanism, initiates retransmissions or inserts idle Flit packets as needed to control flow and maintain normal data flow. The packet transmit controller includes a retry buffer, which stores data that has not yet been confirmed successfully transmitted. This buffer is used to temporarily store failed packets so that they can be retransmitted in sequence.

[0147] The receiving channel of the bare chip is used to receive data sent by the other end to the local end. The receiving channel may include a data packet receiving controller (English: Flit RX Ctrl), a type synchronous first-in-first-out controller (English: Type SFIFO Ctrl), and a receiving interface (English: RX interface).

[0148] 1. Packet Receive Controller: This component is responsible for aligning data across multiple lanes to ensure correct data ordering. It also performs data validation for valid Flit packets, checks for errors during transmission, and performs depacketization, converting data from Flit format back to its original form. Because data may be transmitted concurrently across multiple lanes, the packet receive controller must ensure that the data is correctly reassembled and synchronized for subsequent processing.

[0149] 2. Type-synchronous FIFO controller: It classifies and caches the type data units of the unpacked Flit data packets, reads these data units according to their full length, and converts them back into AXI channel type data packets for output. The type-synchronous FIFO controller acts as an intermediate buffer and conversion layer, converting the data received by the physical layer into a format that can be understood by the transaction layer, preparing for further data processing. The type-synchronous FIFO controller includes multiple type SFIFO matrices. There is a one-to-one correspondence between the multiple type SFIFO matrices and the multiple channel FIFO memories of the receiving interface. Each type SFIFO matrix is used to store the data output by the corresponding channel FIFO memory. The multiple type SFIFO matrices mainly include a write address FIFOs matrix, a write data FIFOs matrix, a read address FIFOs matrix, a read data FIFOs matrix, and a write response FIFOs matrix. For example, the figure only schematically shows six types of SFIFO matrices, namely the data link layer packet FIFOs matrix "DLLP FIFOs matrix", the write address FIFOs matrix "AW FIFOs matrix", the write data FIFOs matrix "W FIFOs matrix", the read address FIFOs matrix "AR FIFOs matrix", the read data FIFOs matrix "R FIFOs matrix", and the buffer FIFOs matrix "BFIFOs matrix". Among them, the write address FIFOs matrix "AW FIFOs matrix" corresponds to the write address FIFO memory "AW_FIFO", and is used to store the write address channel package "AW_PKT" output by the write address FIFO memory "AW_FIFO"; the write data FIFOs matrix "WFIFOs matrix" corresponds to the write data FIFO memory "W_FIFO", and is used to store the write data channel package "W_PKT" output by the write data FIFO memory "W_FIFO"; the read address FIFOs matrix "AR FIFOs matrix" corresponds to the read address FIFO memory "AR_FIFO", and is used to store the read address channel package "AR_PKT" output by the read address FIFO memory "AR_FIFO"; the read data FIFOs matrix "R FIFOs matrix" corresponds to the read data FIFO memory "R_FIFO", and is used to store the read data channel package "R_PKT" output by the read data FIFO memory "R_FIFO"; the write response FIFOs matrix "B The FIFOs matrix "corresponds to the write response FIFO memory "B_FIFO" and is used to store the write response channel packet "B_PKT" output by the buffer FIFO memory "B_FIFO".

[0150] 3. Receive interface: This buffers AXI channel-type data packets and converts them into AXI channel interface signals through a handshake mechanism, outputting them to the High Bandwidth Fabric (HBF) bus. The receive interface is the final stage before data enters system memory or the processor, ensuring efficient data interaction with other components within the system.

[0151] Each type of channel of the receiving interface has a FIFO memory, namely the channel FIFO memory of the receiving interface. The channel FIFO memory of the receiving interface is used to store received data. The multiple channel FIFO memories of the receiving interface may include at least two of the write address FIFO memory, the write data FIFO memory, the read address FIFO memory, the read data FIFO memory, and the buffer FIFO memory. For example, the figure only schematically shows five types of channel FIFO memories of the receiving interface, namely the write address FIFO memory "AW_FIFO", the write data FIFO memory "W_FIFO", the read address FIFO memory "AR_FIFO", the read data FIFO memory "R_FIFO", and the buffer FIFO memory "B_FIFO". The relevant details can be referred to in the relevant description of the channel FIFO memory of the transmitting interface and will not be repeated here.

[0152] It should be noted that the aforementioned transmission and reception channels are merely illustrated by the division of the aforementioned functional modules when implementing their functions. In actual applications, the aforementioned functions can be assigned to different functional modules based on actual needs. That is, the content structure of the die can be divided into different functional modules to complete all or part of the functions described above. The functional modules in the aforementioned transmission and reception channels can be deleted, added, or replaced based on actual needs, and the present disclosure does not limit this.

[0153] The back pressure control method provided by the embodiment of the present disclosure, in addition to the back pressure control method between the two bare chips (the first bare chip and the second bare chip) mentioned above, also includes a back pressure control method within a bare chip (which can be the first bare chip or the second bare chip), that is, within the end. A bare chip includes multiple modules with cache (including a target module and an upstream module of the target module), and the back pressure control method within the end includes: the target module within a bare chip sends second back pressure information to the upstream module of the target module within the bare chip through the internal transmission link of the sending channel or the receiving channel, step by step or across levels, thereby performing back pressure control on the upstream module of the target module. That is, within a bare chip, the target module sends second back pressure information to the upstream module of the target module based on its own cache occupancy. The second back pressure information is used to indicate whether the upstream module of the target module stops outputting data. The target module is one of the multiple modules with cache in the bare chip, and the upstream module of the target module is a module with cache at the upper level or n levels above the target module in the internal transmission link of the bare chip, where n is a positive integer greater than 1.

[0154] In one possible implementation, the second back pressure information includes a back pressure signal. The target module sends the second back pressure information to the upstream module of the target module based on its own cache occupancy. This may include: when the amount of data in the target module is greater than the second back pressure threshold, it indicates that the target module is about to be fully loaded and it is necessary to stop outputting data to the target module. Therefore, the target module sends a back pressure signal to the upstream module of the target module step by step or across levels, and the back pressure signal instructs the upstream module of the target module to stop outputting data. Thereby, the upstream module of the target module receives the back pressure signal and stops outputting data to the target module according to the received back pressure signal. When the amount of data in the target module is less than or equal to the second back pressure threshold, it indicates that the target module is not at risk of being fully loaded and there is no need to perform corresponding back pressure control.

[0155] The target module can be one or more modules. When there are multiple target modules, the second back pressure thresholds of the multiple target modules can be the same, or different, or there can be at least two target modules whose second back pressure thresholds are the same. For each target module, there can be one or more upstream modules that can perform back pressure control. When there are multiple upstream modules of the target module, the target module can set the same second back pressure threshold for the multiple upstream modules, or can set corresponding second back pressure thresholds for the multiple upstream modules. For example, the target module sets a first threshold for the upstream module of the previous level and a second threshold for the upstream module of the previous n levels. When the data volume of the target module is greater than its own first threshold, the target module sends a back pressure signal to the upstream module of the previous level; when the data volume of the target module is greater than its own second threshold, the target module sends a back pressure signal to the upstream module of the previous n levels, where n is a positive integer greater than 1. The first threshold is different from the second threshold. Schematically, the first threshold is greater than the second threshold. The embodiments of the present disclosure are not limited to this.

[0156] Optionally, the target module and the upstream module of the target module include any one or more combinations of the following: the target module is a retry buffer, and the upstream module of the target module is a FIFOs matrix; the target module is a FIFOs matrix, and the upstream module of the target module is an arbitrator; and the target module is a FIFOs matrix, and the upstream module of the target module is a plurality of channel FIFO memories of a sending interface.

[0157] Schematically, the FIFOs matrix is the upstream module of the retry buffer, the arbiter is the upstream module of the FIFOs matrix, and the multiple channel FIFO memories of the sending interface are the upstream modules of the FIFOs matrix at the upper n levels, for example, n is 3.

[0158] That is, when the amount of data in the retry buffer is greater than its own second back pressure threshold, the retry buffer sends a back pressure signal to the FIFOs matrix, and the back pressure signal instructs the FIFOs matrix to stop outputting data; and / or, when the amount of data in the FIFOs matrix is greater than its own second back pressure threshold, the FIFOs matrix sends a back pressure signal to the arbiter, and the back pressure signal instructs the arbiter to stop outputting data; and / or, when the amount of data in the FIFOs matrix is greater than its own second back pressure threshold, the FIFOs matrix sends a back pressure signal to the multiple channel FIFO memories of the sending interface, and the back pressure signal instructs the multiple channel FIFO memories of the sending interface to stop outputting data. The above three possible implementation methods can be executed one by one, or any two of them can be executed, or all three can be executed. The embodiments of the present disclosure are not limited to this.

[0159] When the back pressure control method includes the second and third possible implementation methods mentioned above, that is, for the FIFOs matrix, the upstream module that can perform back pressure control can be the arbitrator of the previous level, or it can be the multiple channel FIFO memories of the sending interface of the previous multiple levels. Therefore, the same second back pressure threshold can be set for these two upstream modules, or different second back pressure thresholds can be set for these two upstream modules. Schematically, the FIFOs matrix sets a first threshold for the arbitrator and sets a second threshold for the multiple channel FIFO memories of the sending interface, and the first threshold is different from the second threshold.

[0160] In another possible implementation, the above-mentioned target module sends the second back pressure information to the upstream module of the target module based on its own cache occupancy, which may include: the target module updates the second back pressure information at a preset time interval, and sends the updated second back pressure information to the upstream module of the target module, so that the upstream module of the target module determines whether to stop outputting data based on the second back pressure information.

[0161] Optionally, the target module is a plurality of channel FIFO memories of a receiving interface, and the upstream module of the target module is a plurality of types of SFIFO matrices. The second back pressure information includes a second back pressure flag corresponding to each of the plurality of channel FIFO memories of the receiving interface, and the second back pressure flag corresponding to each channel FIFO memory is used to indicate whether the amount of data in the channel FIFO memory is greater than a third back pressure threshold. It should be noted that the description of the second back pressure flag can be analogously referred to the relevant description of the first back pressure flag above and is not repeated here.

[0162] Optionally, there is a one-to-one correspondence between the multiple channel FIFO memories of the receiving interface and the multiple types of SFIFO matrices, and the second back pressure flag corresponding to each channel FIFO memory is also used to indicate whether the corresponding type SFIFO matrix stops outputting data. That is, for each second back pressure flag, when the second back pressure flag indicates that the amount of data in the channel FIFO memory is greater than the third back pressure threshold, it indicates that the channel FIFO memory is about to be full, that is, it indicates that the type SFIFO matrix corresponding to the second back pressure flag stops outputting data; when the second back pressure flag indicates that the amount of data in the channel FIFO memory is less than or equal to the third back pressure threshold, it indicates that the second cache queue is not at risk of being full, that is, it indicates that the type SFIFO matrix corresponding to the second back pressure flag continues to output data.

[0163] Optionally, continuing to output data includes continuing to read and output data, and stopping outputting data includes stopping reading data and stopping outputting data.

[0164] Optionally, the first back pressure threshold, the second back pressure threshold, and the third back pressure threshold are default settings or custom settings. The values of the first back pressure threshold, the second back pressure threshold, and the third back pressure threshold can be the same, different, or at least two of them can be the same, which is not limited in the present embodiment.

[0165] It should be noted that when the die is the first die, the back pressure control method within the end refers to the back pressure control method within the first die, and the target module and the upstream module of the target module are both modules within the first die. For example, the multiple channel FIFO memories of the die's transmit interface are the multiple channel FIFO memories of the die's transmit interface, and the multiple channel FIFO memories of the die's receive interface are the multiple channel FIFO memories of the die's receive interface. Similarly, when the die is the second die, the back pressure control method within the end refers to the back pressure control method within the second die, and the target module and the upstream module of the target module are both modules within the second die. The multiple channel FIFO memories of the die's transmit interface are the multiple channel FIFO memories of the die's transmit interface, and the multiple channel FIFO memories of the die's receive interface are the multiple channel FIFO memories of the die's receive interface.

[0166] The embodiment of the present disclosure adopts a multi-level back pressure mechanism to control the flow, including the back pressure control method within the end and the back pressure control method between the two ends. In an illustrative example, based on Figure 3 Provided bare die, such as Figure 4 As shown, it shows a schematic diagram of the principle of the control method for die-to-die transmission provided by an exemplary embodiment of the present disclosure. Taking the local end as the first die and the opposite end as the second die as an example, the back pressure control method within the local end is: multiple modules with caches each set a back pressure threshold, and when the data volume of a module is greater than its own back pressure threshold, a back pressure signal is generated. The generated back pressure signal is transmitted to the upstream module step by step or across the internal transmission link of the sending channel or the receiving channel to take effect. The back pressure control method within the end includes but is not limited to the following possible paths:

[0167] Path 1: When the retry buffer is about to be full, backpressure control is performed on the read enable (English: rd_en) of the FIFOs matrix.

[0168] Optionally, when the amount of data in the retry buffer is greater than its own second back pressure threshold, it indicates that the retry buffer is about to be full, and the retry buffer sends a back pressure signal to the FIFOs matrix. The back pressure signal instructs to stop the read enable of the FIFOs matrix. The FIFOs matrix stops reading data and stops outputting data according to the received back pressure signal.

[0169] Path 2: When the FIFO matrix is about to be fully loaded, back-pressure control is performed on the work enable (English: work_enable) of the arbitrator.

[0170] Optionally, when the amount of data in the FIFOs matrix is greater than its own second back pressure threshold, it indicates that the FIFOs matrix is about to be fully loaded, and the FIFOs matrix sends a back pressure signal to the arbitrator. The back pressure signal instructs to stop the arbitrator's operation. The arbitrator stops reading data and stops outputting data according to the received back pressure signal.

[0171] Path 3: When the FIFO matrix is about to be fully loaded, backpressure control is performed on the read enable of all channel FIFO memories of the transmit interface.

[0172] Optionally, when the amount of data in the FIFOs matrix is greater than its own second back pressure threshold, it indicates that the FIFOs matrix is about to be fully loaded, and the FIFOs matrix sends a back pressure signal to multiple channel FIFO memories of the sending interface. The back pressure signal instructs to stop reading enable of all channel FIFO memories of the sending interface. All channel FIFO memories of the sending interface stop reading data and stop outputting data according to the received back pressure signal.

[0173] Path 4: Based on the first back pressure flag bits corresponding to the multiple channel FIFO memories of the receiving interface, back pressure control is performed on the read enable of multiple types of SFIFO matrices respectively.

[0174] Optionally, the receiving interface updates the first backpressure flag corresponding to each of the multiple channel FIFO memories of the receiving interface at a preset time interval, and sends the first backpressure flag corresponding to each of the multiple channel FIFO memories to the multiple types of SFIFO matrices. For each first backpressure flag, if the first backpressure flag indicates that the amount of data in the channel FIFO memory is greater than a third backpressure threshold, it indicates that the channel FIFO memory is about to be full, and instructs the type SFIFO matrix corresponding to the first backpressure flag to stop reading data and stop outputting data.

[0175] It should be noted that for the details of the above-mentioned paths, reference can be made to the relevant descriptions in the above-mentioned embodiments, which will not be repeated here.

[0176] The backpressure control method between the two ends is as follows: the first backpressure flag bit of each channel FIFO memory of the receiving interface of the second die (i.e., the opposite end) is inserted into the Flit data packet sent to each channel FIFO memory of the transmitting interface of the first die (i.e., the local end), thereby controlling the reading and output of data from the corresponding channel FIFO memory of the first die at a preset time interval. The backpressure control method between the two ends includes but is not limited to the following possible paths:

[0177] Path 5: The second die inserts the first back pressure flag of each channel FIFO memory of the receiving interface into the Flit data packet according to the clock cycle, and sends the inserted Flit data packet to the receiving interface of the first die.

[0178] It should be noted that path 5 is a step executed by the other end. For the convenience of explanation, the figure only schematically marks the direction of the information flow on the local end. The steps executed by the other end can be analogously referred to the direction of the information flow.

[0179] For example, the second die's receive interface includes five channel FIFO memories. The second die inserts the first backpressure flag bit (a total of five bits) of each channel FIFO memory in the receive interface into the destination field of the Flit packet at the clock cycle. This way, when the Flit packet arrives at the first die's transmit interface, the first die's transmit interface is aware of the status of each of the multiple channel FIFO memories in the second die's receive interface.

[0180] Path 6: The receiving interface of the first bare chip depackets the received Flit data packet, extracts the first back pressure information in the Flit data packet, and feeds the first back pressure information back to the sending interface of the first bare chip.

[0181] The sending interface of the first die determines whether to stop sending data to the receiving interface of the second die according to the first back pressure information.

[0182] It should be noted that for the details of the above-mentioned paths, reference can be made to the relevant descriptions in the above-mentioned embodiments, which will not be repeated here.

[0183] In summary, the disclosed embodiments employ a multi-level backpressure mechanism for flow control, including an intra-end backpressure control method and an inter-end backpressure control method. In the intra-end backpressure control method, the target module sends second backpressure information to the upstream module of the target module step by step or across levels based on its own cache occupancy. The second backpressure information is used to indicate whether the upstream module of the target module stops outputting data, thereby avoiding the risk of data overflow / loss. In the inter-end backpressure control method, the second die (receiving end) feeds back the first backpressure information to the first die (sending end) along with the data packet at a preset time interval. This instant feedback mechanism enables the first die to determine whether it needs to stop sending data based on the first backpressure information in the received data packet. Through the above-mentioned instant feedback mechanism, the backpressure feedback delay can be minimized, thereby improving the efficiency and reliability of data transmission. Moreover, when the first die needs to send data, it can directly send data to the second die, reducing the waiting time for data transmission at the sending end and improving the effective utilization of transmission bandwidth.

[0184] Please refer to Figure 5, which shows a flowchart of a control method for die-to-die transmission provided by another exemplary embodiment of the present disclosure. This embodiment uses this method for the above Figure 1 The die-to-die transfer system shown in FIG.

[0185] Step 501 : When a first die needs to send data, the first die sends the data to a second die. By default, the second die has a memory space for receiving data.

[0186] Step 502: The first die receives a data packet carrying first back pressure information sent by the second die at a preset time interval.

[0187] Step 503: The first die determines whether to stop sending data to the second die according to the first back pressure information in the data packet.

[0188] It should be noted that the relevant details of each step in this embodiment can be referred to the relevant description in the above embodiment and will not be repeated here.

[0189] The following is an apparatus embodiment of the present disclosure. For parts not described in detail in the apparatus embodiment, reference may be made to the technical details disclosed in the above method embodiment.

[0190] Please refer to Figure 6 , which shows a schematic structural diagram of a first die provided by an exemplary embodiment of the present disclosure. The first die includes: a transmitting interface 62 and a receiving interface 64.

[0191] A sending interface 62, used to send data to the second die when data needs to be sent. The second die has a memory space for receiving data by default.

[0192] The receiving interface 64 is configured to receive a data packet carrying the first back pressure information sent by the second die at a preset time interval, and feed the first back pressure information in the data packet back to the sending interface 62;

[0193] The sending interface 62 is further configured to determine whether to stop sending data to the second die according to the first back pressure information.

[0194] In a possible implementation, the first back pressure information includes a first back pressure flag corresponding to each of the plurality of second cache queues of the second die, where the first back pressure flag is used to indicate whether the amount of data in the second cache queue is greater than a first back pressure threshold.

[0195] In another possible implementation, there is a one-to-one correspondence between the plurality of first cache queues of the first die and the plurality of second cache queues of the second die;

[0196] The sending interface 62 is further used for:

[0197] According to each first back pressure flag in the data packet, it is determined whether the first cache queue corresponding to each first back pressure flag stops sending data to the corresponding second cache queue.

[0198] In another possible implementation, the first cache queue is a channel FIFO memory of the transmitting interface 62 of the first die, and the second cache queue is a channel FIFO memory of the receiving interface of the second die.

[0199] In another possible implementation, the receiving interface 64 of the first die is further configured to:

[0200] Depacketizing the received data packet and extracting the first back pressure information in the data packet;

[0201] The first back pressure information is fed back to the sending interface 62 of the first die. The sending interface 62 of the first die is used to determine whether to stop sending data to the receiving interface of the second die according to the first back pressure information.

[0202] In another possible implementation, the first die further includes a target module and an upstream module of the target module;

[0203] The target module is configured to send second back pressure information to an upstream module of the target module according to its own cache occupancy, where the second back pressure information is used to instruct the upstream module of the target module whether to stop outputting data.

[0204] In another possible implementation, the second backpressure information includes a backpressure signal;

[0205] The target module is further configured to send a back pressure signal to an upstream module of the target module when the data volume of the target module is greater than a second back pressure threshold, wherein the back pressure signal is configured to instruct the upstream module of the target module to stop outputting data.

[0206] In another possible implementation, the target module and the upstream module of the target module include any one or more combinations of the following:

[0207] The target module is a retry buffer, and the upstream module of the target module is a FIFOs matrix;

[0208] The target module is a FIFOs matrix, and the upstream module of the target module is an arbitrator; and

[0209] The target module is a FIFOs matrix, and the upstream module of the target module is a plurality of channel FIFO memories of the transmitting interface.

[0210] In another possible implementation, the target module is a plurality of channel FIFO memories of a receiving interface, the upstream module of the target module is a plurality of types of SFIFO matrices, and there is a one-to-one correspondence between the plurality of channel FIFO memories of the receiving interface and the plurality of types of SFIFO matrices;

[0211] The second back pressure information includes a second back pressure flag bit corresponding to each of the multiple channel FIFO memories of the receiving interface, and the second back pressure flag bit is used to indicate whether the corresponding type SFIFO matrix stops outputting data.

[0212] It should be noted that, when the device provided in the above embodiment realizes its function, it only uses the division of the above-mentioned functional modules as an example. In actual application, the above-mentioned functions can be assigned to different functional modules according to actual needs, that is, the content structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0213] Regarding the apparatus in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0214] Please refer to Figure 7 , which shows a schematic structural diagram of a second die provided by an exemplary embodiment of the present disclosure. The second die includes: a receiving interface 72 and a transmitting interface 74.

[0215] A receiving interface 72, configured to receive data sent by the first die, and the second die has memory space for receiving data by default;

[0216] The sending interface 74 is used to send a data packet carrying the first back pressure information to the first die at a preset time interval. The first die is used to determine whether to stop sending data to the second die according to the first back pressure information in the data packet.

[0217] In a possible implementation, the first back pressure information includes a first back pressure flag corresponding to each of the plurality of second cache queues of the second die, where the first back pressure flag is used to indicate whether the amount of data in the second cache queue is greater than a first back pressure threshold.

[0218] In another possible implementation, there is a one-to-one correspondence between the multiple first cache queues of the first die and the multiple second cache queues of the second die, so that the first die determines, based on each first back pressure flag in the data packet, whether the first cache queue corresponding to each first back pressure flag bit stops sending data to the corresponding second cache queue.

[0219] In another possible implementation, the first cache queue is a channel FIFO memory of a transmitting interface of the first die, and the second cache queue is a channel FIFO memory of a receiving interface of the second die.

[0220] In another possible implementation,

[0221] The receiving interface 72 of the second die is further configured to insert the first back pressure information into the data packet of the sending interface 74 of the second die according to a preset time interval;

[0222] The sending interface 74 of the second bare chip is further configured to transmit the data packet carrying the first back pressure information to the receiving interface of the first bare chip at a preset time interval.

[0223] In another possible implementation, the second die further includes a target module and an upstream module of the target module;

[0224] The target module is configured to send second back pressure information to an upstream module of the target module according to its own cache occupancy, where the second back pressure information is used to instruct the upstream module of the target module whether to stop outputting data.

[0225] In another possible implementation, the second backpressure information includes a backpressure signal;

[0226] The target module is further configured to send a back pressure signal to an upstream module of the target module when the data volume of the target module is greater than a second back pressure threshold, wherein the back pressure signal is configured to instruct the upstream module of the target module to stop outputting data.

[0227] In another possible implementation, the target module and the upstream module of the target module include any one or more combinations of the following:

[0228] The target module is a retry buffer, and the upstream module of the target module is a FIFOs matrix;

[0229] The target module is a FIFOs matrix, and the upstream module of the target module is an arbitrator; and

[0230] The target module is a FIFOs matrix, and the upstream module of the target module is a plurality of channel FIFO memories of the transmitting interface.

[0231] In another possible implementation, the target module is a plurality of channel FIFO memories of a receiving interface, the upstream module of the target module is a plurality of types of SFIFO matrices, and there is a one-to-one correspondence between the plurality of channel FIFO memories of the receiving interface and the plurality of types of SFIFO matrices;

[0232] The second back pressure information includes a second back pressure flag bit corresponding to each of the multiple channel FIFO memories of the receiving interface, and the second back pressure flag bit is used to indicate whether the corresponding type SFIFO matrix stops outputting data.

[0233] It should be noted that, when the device provided in the above embodiment realizes its function, it only uses the division of the above-mentioned functional modules as an example. In actual application, the above-mentioned functions can be assigned to different functional modules according to actual needs, that is, the content structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0234] Regarding the apparatus in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0235] Figure 8 1 is a block diagram of an apparatus for back pressure control in die-to-die transmission according to an exemplary embodiment. For example, the apparatus 1900 may be provided as a die. Figure 8 The apparatus 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions, such as an application, that can be executed by the processing component 1922. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute the instructions to perform the above-described method.

[0236] The device 1900 may also include a power supply component 1926 configured to perform power management of the device 1900, a wired or wireless network interface 1950 configured to connect the device 1900 to a network, and an input / output interface 1958 (I / O interface). The device 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server 2003. TM , MacOS X TM , Unix TM ,Linux TM , FreeBSD TM or similar.

[0237] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by the processing component 1922 of the apparatus 1900 to perform the above-described method.

[0238] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems and methods according to multiple embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and the part of the module, program segment or instruction contains one or more executable instructions for realizing the prescribed logical function. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a special hardware-based system that performs the prescribed function or action, or can be implemented by a combination of special hardware and computer instructions.

[0239] While various embodiments of the present disclosure have been described above, the foregoing description is intended to be illustrative, non-exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or technological improvements in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A control method for die-to-die transmission, characterized in that: In a first die, the method includes: When data needs to be sent, the data is sent to the second die, the second die having a memory space for receiving data by default, and the data is sent without the first die checking the memory space of the second die; receiving a data packet carrying first back pressure information sent by the second bare chip at a preset time interval; determining, according to the first back pressure information in the data packet, whether to stop sending data to the second die; The first back pressure information includes a first back pressure flag corresponding to each of the plurality of second cache queues of the second die, the first back pressure flag being used to indicate whether the amount of data in the second cache queue is greater than a first back pressure threshold; There is a one-to-one correspondence between the plurality of first cache queues of the first die and the plurality of second cache queues of the second die; The determining, according to the first back pressure information in the data packet, whether to stop sending data to the second die includes: According to each first back pressure flag in the data packet, it is determined whether the first cache queue corresponding to each first back pressure flag stops sending data to the corresponding second cache queue.

2. The method according to claim 1, characterized in that The first cache queue is a channel FIFO memory of a transmitting interface of the first die, and the second cache queue is a channel FIFO memory of a receiving interface of the second die.

3. The method according to claim 1 or 2, characterized in that Before determining whether to stop sending data to the second die according to the first back pressure information in the data packet, the method further includes: The receiving interface of the first bare chip unpacks the received data packet and extracts the first back pressure information from the data packet; The receiving interface of the first die feeds back the first back pressure information to the sending interface of the first die, and the sending interface of the first die is used to determine whether to stop sending data to the receiving interface of the second die according to the first back pressure information.

4. The method according to claim 1 or 2, characterized in that The first die includes a target module and an upstream module of the target module, and the method further includes: The target module sends second back pressure information to an upstream module of the target module according to its own cache occupancy, where the second back pressure information is used to instruct the upstream module of the target module whether to stop outputting data.

5. The method according to claim 4, characterized in that The second back pressure information includes a back pressure signal, and the target module sends the second back pressure information to the upstream module of the target module according to its own cache occupancy, including: When the data volume of the target module is greater than a second back pressure threshold, the target module sends the back pressure signal to the upstream module of the target module, where the back pressure signal is used to instruct the upstream module of the target module to stop outputting data.

6. The method according to claim 5, characterized in that The target module and the upstream module of the target module include any one or more combinations of the following: The target module is a retry buffer, and the upstream module of the target module is a FIFOs matrix; The target module is a FIFOs matrix, and the upstream module of the target module is an arbitrator; and The target module is a FIFOs matrix, and the upstream module of the target module is a plurality of channel FIFO memories of a transmitting interface.

7. The method according to claim 4, characterized in that The target module is a plurality of channel FIFO memories of a receiving interface, the upstream module of the target module is a plurality of types of SFIFO matrices, and there is a one-to-one correspondence between the plurality of channel FIFO memories of the receiving interface and the plurality of types of SFIFO matrices; The second back pressure information includes a second back pressure flag bit corresponding to each of the multiple channel FIFO memories of the receiving interface, and the second back pressure flag bit is used to indicate whether the corresponding type SFIFO matrix stops outputting data.

8. A control method for die-to-die transmission, characterized in that: For use in a second die, the method includes: receiving data sent by the first die, the second die having a memory space for receiving the data by default, the data being sent by the first die without checking the memory space of the second die; sending a data packet carrying first back pressure information to the first die at a preset time interval, so that the first die determines whether to stop sending data to the second die based on the first back pressure information in the data packet; The first back pressure information includes a first back pressure flag corresponding to each of the multiple second cache queues of the second die, and the first back pressure flag is used to indicate whether the data volume of the second cache queue is greater than a first back pressure threshold; there is a one-to-one correspondence between the multiple first cache queues of the first die and the multiple second cache queues of the second die, so that the first die determines, based on each first back pressure flag in the data packet, whether the first cache queue corresponding to each first back pressure flag stops sending data to the corresponding second cache queue.

9. The method according to claim 8, characterized in that The first cache queue is a channel FIFO memory of a transmitting interface of the first die, and the second cache queue is a channel FIFO memory of a receiving interface of the second die.

10. The method according to claim 8 or 9, characterized in that The step of sending the data packet carrying the first back pressure information to the first die at a preset time interval includes: The receiving interface of the second bare chip inserts the first back pressure information into the data packet of the sending interface of the second bare chip according to the preset time interval; The sending interface of the second bare chip transmits the data packet carrying the first back pressure information to the receiving interface of the first bare chip at the preset time interval.

11. The method according to claim 8 or 9, characterized in that The second die includes a target module and an upstream module of the target module, and the method further includes: The target module sends second back pressure information to an upstream module of the target module according to its own cache occupancy, where the second back pressure information is used to instruct the upstream module of the target module whether to stop outputting data.

12. The method according to claim 11, characterized in that The second back pressure information includes a back pressure signal, and the target module sends the second back pressure information to the upstream module of the target module according to its own cache occupancy, including: When the data volume of the target module is greater than a second back pressure threshold, the target module sends the back pressure signal to the upstream module of the target module, where the back pressure signal is used to instruct the upstream module of the target module to stop outputting data.

13. The method according to claim 12, characterized in that The target module and the upstream module of the target module include any one or more combinations of the following: The target module is a retry buffer, and the upstream module of the target module is a FIFOs matrix; The target module is a FIFOs matrix, and the upstream module of the target module is an arbitrator; and The target module is a FIFOs matrix, and the upstream module of the target module is a plurality of channel FIFO memories of a transmitting interface.

14. The method according to claim 11, characterized in that The target module is a plurality of channel FIFO memories of a receiving interface, the upstream module of the target module is a plurality of types of SFIFO matrices, and there is a one-to-one correspondence between the plurality of channel FIFO memories of the receiving interface and the plurality of types of SFIFO matrices; The second back pressure information includes a second back pressure flag bit corresponding to each of the multiple channel FIFO memories of the receiving interface, and the second back pressure flag bit is used to indicate whether the corresponding type SFIFO matrix stops outputting data.

15. A first bare chip, characterized in that: The first bare chip includes: a transmitting interface and a receiving interface; The sending interface is used to send data to the second die when data needs to be sent, the second die has a memory space for receiving data by default, and the data is sent without the first die checking the memory space of the second die; The receiving interface is configured to receive a data packet carrying first back pressure information sent by the second die at a preset time interval, and feed back the first back pressure information in the data packet to the sending interface; The sending interface is further configured to determine whether to stop sending data to the second die according to the first back pressure information; The first back pressure information includes a first back pressure flag corresponding to each of the plurality of second cache queues of the second die, the first back pressure flag being used to indicate whether the amount of data in the second cache queue is greater than a first back pressure threshold; There is a one-to-one correspondence between the multiple first cache queues of the first die and the multiple second cache queues of the second die; the sending interface is further used to: According to each first back pressure flag in the data packet, it is determined whether the first cache queue corresponding to each first back pressure flag stops sending data to the corresponding second cache queue.

16. A second bare chip, characterized in that: The second bare chip includes: a receiving interface and a transmitting interface; The receiving interface is configured to receive data sent by the first die, the second die having a memory space for receiving the data by default, and the data is sent by the first die without checking the memory space of the second die; The sending interface is configured to send a data packet carrying first back pressure information to the first die at a preset time interval, and the first die is configured to determine whether to stop sending data to the second die based on the first back pressure information in the data packet; The first back pressure information includes a first back pressure flag corresponding to each of the multiple second cache queues of the second die, and the first back pressure flag is used to indicate whether the data volume of the second cache queue is greater than a first back pressure threshold; there is a one-to-one correspondence between the multiple first cache queues of the first die and the multiple second cache queues of the second die, so that the first die determines, based on each first back pressure flag in the data packet, whether the first cache queue corresponding to each first back pressure flag stops sending data to the corresponding second cache queue.

17. A die-to-die transmission system, characterized in that: The system includes a first die and a second die; The first die is the first die according to claim 15; The second die is the second die according to claim 16.

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