Intelligent decoding method for UART serial signals

Abstract

The application discloses an intelligent decoding method for UART serial signals, which comprises the following steps: firstly, automatically recognizing unknown baud rate, data bit number, stop bit length and whether the UART protocol signal contains a parity check bit and other key parameters by using a large amount of data; and secondly, decoding and processing subsequent UART protocol signals according to cascaded decoding modules. Through the intelligent decoding of the UART protocol signal, the correct data information and baud rate can be accurately parsed without manually configuring or trying various decoding settings, so that the decoding process of the UART protocol signal can be greatly simplified, and the operation burden of the user can be reduced.

Description

Technical Field

[0001] This invention belongs to the field of communication signal testing technology, and more specifically, relates to an intelligent decoding method for UART serial signals. Background Technology

[0002] In current communication technologies, serial communication, especially UART (Universal Asynchronous Receiver / Transmitter) communication, plays a crucial role in various applications. Serial UART communication is a widely used asynchronous serial transceiver protocol. It consists of a transmitter and a receiver; data transmission and reception are accomplished by connecting the transmitting and receiving ends, requiring only two transmission lines for data exchange. Serial UART plays a vital role in various applications, enabling data exchange and command transmission between various sensors, actuators, and controllers, thereby achieving automated control and intelligent management. Serial UART communication offers advantages such as simplicity, reliability, and low cost, making it suitable for various power and automatic control applications, providing a simple and reliable solution for data communication. The frame structure of the UART communication protocol includes a start bit, data bits, parity bit (optional), and stop bits, which together constitute the basic format for data transmission in serial communication. There are usually a certain number of idle bits between each two frames to provide inter-frame spacing and synchronization signals.

[0003] When performing real-time decoding of UART in a digital oscilloscope, the user must accurately know and manually set various parameters of the communication protocol, and needs to know the format of the data frame to be decoded in advance, including the number of data bits, stop bits, and parity bits. This traditional decoding method not only increases the complexity of parameter setting, but also may lead to decoding failure or data errors if the parameter settings are mismatched, thus affecting the reliability and stability of UART decoding in the digital oscilloscope. Therefore, the UART decoding method in digital oscilloscopes suffers from drawbacks such as dependence on fixed frame formats, sensitivity to signal quality, and lack of flexibility.

[0004] It is evident that current UART decoding methods in digital oscilloscopes have some limitations, failing to flexibly adapt to varying signal conditions and changing requirements. Intelligent decoding methods, by dynamically analyzing the received signal and allowing the decoding module to learn, train, detect, and determine the frame structure, can perform real-time decoding of the transmitted UART protocol signal, thereby improving the versatility and adaptability of the decoding. This intelligent decoding method can better handle issues such as signal format changes, making UART communication more reliable and flexible in various application scenarios. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide an intelligent decoding method for UART serial signals. By dynamically analyzing and intelligently processing the received signals, efficient decoding and data transmission of UART serial signals can be achieved.

[0006] To achieve the above-mentioned objective, the present invention provides an intelligent decoding method for UART serial signals, characterized by comprising the following steps:

[0007] (1) Digital oscilloscopes use a sampling rate f s The serial signal of the UART is acquired, and the acquired data sequence is denoted as x(n), where n = 1, 2, ..., N, and N is the number of sampling points;

[0008] In UART's serial signal, the length of each frame is typically between 7 and 13 bits. The specific frame format is as follows: The start bit of the frame contains a falling edge marker, which is 1 bit long and represented by logic "0". The number of falling edges in a frame typically does not exceed 7. The data bits are 5 to 9 bits. The parity bits are 0 to 1 bits, representing no parity, odd parity, even parity, flag bit, or blank bit. The frame stop bit is 1, 1.5, or 2 bits long and represented by logic "1". There is an idle state between frames, during which the signal level remains high and represented by logic "1".

[0009] (2) Preprocess the data x(n);

[0010] (2.1) Construct a histogram of the data sequence x(n);

[0011] (2.2) Obtain the threshold level V based on the histogram of x(n). t ;

[0012] (2.3) Calculate the minimum pulse width W min ;

[0013] The data sequence x(n) is compared and shaped, and x(n) is compared with the threshold level V. t Compare and find the minimum pulse width W in the data sequence. min ;

[0014] (2.4) Frame data segmentation;

[0015] Using minimum pulse width W min Cut the data sequence x(n), separate the UART protocol signal, and store it in the sequence A(n);

[0016] (3) Decode the UART protocol signal in A(n) through the decoding module;

[0017] (3.1) Let the minimum frame length of the UART protocol signal be L; set the array D(j) and initialize it to empty;

[0018] (3.2) Identify all falling edges of the UART protocol signal and index and store them.

[0019] (3.3) Find the starting frame of the UART protocol signal from the index of the first falling edge until L is greater than 13. If the analysis fails, exit.

[0020] (3.4) Extract the UART protocol signal D of the j-th frame. j Confirm D j Are the last two digits both logical "1"? If they are logical "1", then set D... j Add to array D(j), then proceed to (3.5); if D j If the last two bits are logic "0", then the search for frame D will continue from the next falling edge. j If the requirement is still not met even after using 7 falling edges as the starting frame, L = L + 1, and the process jumps back to step (3.3).

[0021] (3.5) From D j Starting from the first falling edge after the end, search for the next frame. If the logic state of the last two bits of the next frame is "0", then the starting frame becomes the next falling edge, and return to step (3.4); otherwise, repeat step (3.4) until all signals of A(n) have been analyzed, and then output the decoded array D(j) to the second decoding module.

[0022] (4) The second decoding module checks whether the frame signal in D(j) contains a parity bit. After the parity check is completed, the frame number and the data bit length of the UART protocol signal are output. The data bit length is: L-start bit-stop bit-parity bit; finally, the data bits of the UART protocol signal are output.

[0023] The objective of this invention is achieved as follows:

[0024] This invention discloses an intelligent decoding method for UART serial signals. First, it automatically identifies UART protocol signals with unknown baud rates, data bits, stop bit lengths, and whether they contain parity bits using a large amount of data. Then, it decodes subsequent UART protocol signals using cascaded decoding modules. In this way, through intelligent decoding of UART protocol signals, the correct data information and baud rate can be accurately parsed without manual configuration or trying various decoding settings. This greatly simplifies the decoding process of UART protocol signals and reduces the user's operational burden.

[0025] Meanwhile, the intelligent decoding method for UART serial signals of the present invention also has the following beneficial effects:

[0026] (1) This method can accurately identify the frame structure, including start bit, data bit, parity bit and stop bit, ensuring accurate extraction of data information without needing to know the fixed format of the frame in advance. It meets the requirements of modern communication technology for high precision and high reliability data decoding and has important practical value for improving the quality and efficiency of serial communication technology.

[0027] (2) The intelligent decoding method designed in this invention enables the digital oscilloscope to adaptively adjust the decoding parameters of the UART when facing different signal conditions and communication environments, including baud rate, data bits, stop bit length and the presence of parity bits, thereby improving the versatility and reliability of decoding, reducing the complexity of decoding function, avoiding tedious manual settings by users, speeding up data processing, and better adapting to different application needs.

[0028] (3) The method of the present invention can adapt to different UART signal formats and can intelligently identify and decode without knowing the specific parameters of the signal in advance. This greatly improves the compatibility and flexibility of the system and provides strong support for users to handle uncertain and variable signals. Attached Figure Description

[0029] Figure 1 This is a flowchart of an intelligent decoding method for UART serial signals according to the present invention;

[0030] Figure 2 It is a UART signal frame format;

[0031] Figure 3 This is the decoding flowchart for the first decoding module;

[0032] Figure 4 This is a decoding example diagram of the second decoding module. Detailed Implementation

[0033] The specific embodiments of the present invention will now be described with reference to the accompanying drawings to enable those skilled in the art to better understand the invention. It should be particularly noted that in the following description, detailed descriptions of known functions and designs that might obscure the main content of the invention will be omitted here.

[0034] Example

[0035] Figure 1 This is a flowchart of an intelligent decoding method for UART serial signals according to the present invention.

[0036] In this embodiment, as Figure 1 As shown, the present invention provides an intelligent decoding method for UART serial signals, comprising the following steps:

[0037] S1, Digital oscilloscope with sampling rate f s The serial signal of the UART is acquired, and the acquired data sequence is denoted as x(n), where n = 1, 2, ..., N, and N is the number of sampling points;

[0038] In this embodiment, the length of the UART serial signal is typically between 7 and 13 bits, such as... Figure 2 As shown, its specific frame format is as follows: The start bit of the frame contains a falling edge marker, which is 1 bit long and represented by logic "0". The number of falling edges in a frame typically does not exceed 7. The data bits are 5 to 9 bits. The parity bits are 0 to 1 bits, representing no parity, odd parity, even parity, a flag bit, or a blank bit. The frame stop bit is 1, 1.5, or 2 bits long and represented by logic "1". There is an idle state between frames, during which the signal level remains high and represented by logic "1".

[0039] For example, consider a protocol signal consisting of 100 frames. The start bit is 1 bit (fixed), the data bits are 6 bits, the stop bits are 2 bits, and the parity bit is 1 bit (even parity). Therefore, a complete frame is 1 + 6 + 2 + 1 = 10 bits. Assume a frame is 0110001111, its data format is: 0 (start bit) 110001 (data bits) 1 (even parity bit) 11 (stop bit). All valid information is in the data bits. The 100 frames are grouped together, with high-level empty bits between frames. At the start of decoding, the composition of this UART protocol signal is not yet known; only the basic characteristics of the UART signal are known.

[0040] S2. Preprocess the data x(n);

[0041] S2.1 Construct a histogram of the data sequence x(n), which reflects the frequency of different level values ​​in the signal;

[0042] S2.2 Find the highest and lowest frequency level points on the histogram, and calculate their average as the high / low level threshold V. t ;

[0043] S2.3 Calculate the minimum pulse width W min ;

[0044] The sampled value of each sampling point in the data sequence x(n) is compared with the threshold level V. t Comparison, such as when the sampled value at a certain sampling point is less than the threshold level V. t If the value at that sampling point is 0, then the value is set to 0; otherwise, it is set to 1, resulting in a binary sequence consisting of 0s and 1s. Then, the shortest duration of either 0 or 1 in the binary sequence is calculated and denoted as the minimum pulse width W. min ;

[0045] S2.4, Frame data segmentation;

[0046] Using minimum pulse width W min Cut the data sequence x(n), separate the UART protocol signal, and store it in the sequence A(n);

[0047] In this embodiment, the initial sampling rate is f s When acquiring the serial signal from a UART, because the sampling rate f s Typically, the values ​​are very large, and the acquired protocol signals are not just 0s and 1s, so comparison shaping is required. The comparison shaping process is based on V. t Compared to x(n), the signal after the comparison rounding is entirely transformed into a binary sequence of 0s and 1s. For example, 0110001111, after sampling, might become 0000001111111111110000000000000000001111111111111111111111111111111. However, what's needed is the protocol signal, so the shortest duration of 0s or 1s needs to be calculated as the minimum pulse width W for segmentation. min Furthermore, the UART protocol signal is extracted from the data sequence x(n) and stored in the sequence A(n);

[0048] S3, such as Figure 3 As shown, the UART protocol signal in A(n) is decoded by the first decoding module;

[0049] In this embodiment, the first decoding module starts decoding the UART protocol signal in A(n), but the data may be incomplete in the first frame, so it is necessary to find the location of the specific complete first frame. The total frame length L is also uncertain, so according to the characteristics of the UART signal, it starts to traverse from the smallest possible frame length to find the specific frame. After this process is completed, the total frame length and the specific number of frames that constitute this protocol signal can be determined. The specific decoding process is described in detail below.

[0050] S3.1 Identify all falling edges of the UART protocol signal and store them by index;

[0051] S3.2. Let the minimum frame length of the UART protocol signal be L. Select the index of the first falling edge as the index of the starting falling edge of the frame, and at the same time set this index as the falling edge index of the next frame.

[0052] S3.3 Verify whether the frame length L does not exceed the maximum allowed value. If it does, interrupt the process and prompt "decoding failed"; otherwise, proceed to step S3.4.

[0053] S3.4 Determine whether the index of the starting falling edge of the current frame is less than or equal to the index of the seventh falling edge among all falling edge indices. If yes, proceed to step S3.5; otherwise, increase the frame length L by setting L = L + 1, then reset the indices of the starting falling edge of the frame and the falling edge of the next frame to the index of the first falling edge, and then return to step S3.3.

[0054] S3.5 Set the current falling edge index to the first falling edge index;

[0055] S3.6 Extract frame data D using the current falling edge index and frame length L. j ;

[0056] S3.7 Calculate the index of the end position of the current frame: current falling edge index + L – 1;

[0057] S3.8. Check whether the index of the end position of the current frame does not exceed the total length of array A(n). If it does not exceed the total length, proceed to step S3.9; otherwise, jump to step S3.12.

[0058] S3.9, Confirm D j If the last two digits are both logic "1", the verification passes and step S3.10 is executed; otherwise, the frame start falling edge index is updated to the next falling edge index and the process returns to step S3.4.

[0059] S3.10, Confirm D j For a valid frame, each frame is saved to the decoding array D(j), and the falling edge index of the next frame is updated to the index of the first falling edge after the end position of the current frame;

[0060] S3.11. Check if the falling edge index of the next frame is empty. If it is not empty, update the starting falling edge index of the current frame to the falling edge index of the next frame and return to step (3.6); if it is empty, execute step S3.12.

[0061] S3.12. The decoding operation of the first decoding module ends, and the decoded array D(j) is output and sent to the second decoding module;

[0062] S4, such as Figure 4 As shown, the second decoding module checks whether the frame signal in D(j) contains a parity bit. This algorithm only contains one parity check method, but other algorithms can also be used to implement parity check.

[0063] S4.1. Initialize two variables: one variable to store the total number of decoded frames, and the other variable to store a logical array of length equal to the total number of frames. The initial value of the logical array is set to "1".

[0064] S4.2. Traverse each frame signal in the decoding array D(j). In each frame signal, except for the start bit and stop bit of the frame, continue to traverse the other bits of the frame. If a logical "1" appears in another bit of a frame, invert the corresponding element in the logical array of the frame, and then continue to traverse the next bit until all bits of the frame have been traversed.

[0065] After all frame signals in the decoding array D(j) have been traversed, the logic array is checked. If all elements of the logic array are 1, it indicates that the number of logical "1"s in each frame is even, and there is 1 parity bit, displaying "Data contains even parity". If all elements of the logic array are 0, it indicates that the number of logical "1"s in each frame is odd, and there is 1 parity bit, displaying "Data contains odd parity". If the elements in the logic array contain both 1 and 0, it indicates that the data does not contain a parity bit, displaying "Data does not contain a parity bit".

[0066] S4.3 The decoding operation of the second decoding module ends, and the number of frames and the data bit length of the UART protocol signal are output. The data bit length is: L - start bit - stop bit - parity bit; finally, the data bits of the UART protocol signal are output.

[0067] In this embodiment, the second decoding module checks whether the frame signal in D(j) contains a parity bit. The parity bit is generally the third to last bit, which is the bit before the stop bit. Assuming the total frame length is 100, a logic matrix with a width of 100 bits and a logic value of 1 is defined. Each frame is processed. Taking the example 0110001111 as the i-th frame, the number of 1s is counted, except for the first bit 0 (start bit) and the last two bits 11 (stop bit). For the data bits of 1100011, there are four 1s. Therefore, the value of the i-th logic 1 in the corresponding array is flipped four times: 1-0-1-0-1. Thus, the i-th bit in the logic array is still 1 and is saved. Finally, check the entire logic array to see if it all conforms to 1 or 0. This will verify the complete format of the data. Output the data bits as 0110001111, which means that the protocol signal is output in 100 frames with 6 data bits, including even parity. The first frame is……………… The i-th frame is 1100011………… The 100th frame is……….

[0068] Although the illustrative specific embodiments of the present invention have been described above to enable those skilled in the art to understand the invention, it should be understood that the invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the invention as defined and determined by the appended claims, and all inventions utilizing the concept of the present invention are protected.

Claims

1. A smart decoding method for UART serial signals, characterized in that, Includes the following steps: (1) Digital oscilloscopes use a sampling rate f s The serial signal of the UART is acquired, and the acquired data sequence is denoted as x(n), where n = 1, 2, ..., N, and N is the number of sampling points; In UART's serial signal, each frame is between 7 and 13 bits long. The specific frame format is as follows: The start bit of the frame contains a falling edge marker, which is 1 bit long and represented by logic "0". The number of falling edges in a frame typically does not exceed 7. The data bits are 5 to 9 bits. The parity bits are 0 to 1 bits, representing no parity, odd parity, even parity, flag bit, or blank bit. The frame stop bit is 1, 1.5, or 2 bits long and represented by logic "1". There is an idle state between frames, during which the signal level remains high and represented by logic "1". (2) Preprocess the data x(n); (2.1) Construct a histogram of the data sequence x(n); (2.2) Obtain the threshold level V based on the histogram of x(n). t ; (2.3) Calculate the minimum pulse width W min ; The data sequence x(n) is compared and shaped, and x(n) is compared with the threshold level V. t Compare and find the minimum pulse width W in the data sequence. min ; (2.4) Frame data segmentation; Using minimum pulse width W min Cut the data sequence x(n), separate the UART protocol signal, and store it in the sequence A(n); (3) Decode the UART protocol signal in A(n) through the decoding module; (3.1) Let the minimum frame length of the UART protocol signal be L; set the array D(j) and initialize it to empty; (3.2) Identify all falling edges of the UART protocol signal and store them by index; (3.3) Find the starting frame of the UART protocol signal from the index of the first falling edge until L is greater than 13. If the analysis fails, exit. (3.4) Extract the UART protocol signal D of the j-th frame. j Confirm D j Are the last two digits both logical "1"? If they are logical "1", then set D... j Add to array D(j), then proceed to (3.5); if D j If the last two bits are logic "0", then the search for frame D will continue from the next falling edge. j If the requirement is still not met even after using 7 falling edges as the starting frame, L = L + 1, and the process jumps back to step (3.3). (3.5) From D j Starting from the first falling edge after the end, search for the next frame. If the logic state of the last two bits of the next frame is "0", then the starting frame becomes the next falling edge, and return to step (3.4); otherwise, repeat step (3.4) until all signals of A(n) have been analyzed, and then output the decoded array D(j) to the second decoding module. (4) The second decoding module checks whether the frame signal in D(j) contains a parity bit. After the parity check is completed, the frame number and the data bit length of the UART protocol signal are output. The data bit length is: L-start bit-stop bit-parity bit; finally, the data bits of the UART protocol signal are output.

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