A method for authenticating universal parallel ports

Abstract

The embodiment of the application provides a method for verifying a universal parallel port, which comprises: configuring a clock rollover interval in a comprehensive top layer, so that the clock signal frequency of the universal parallel port to be verified is a set frequency value; configuring a reset signal to be pulled high after a plurality of clock cycles, so that the universal parallel port ends the reset; reading the reset value of a register and a memory after the reset ends, and confirming that the reset value is correct; performing a write-first-read-later operation on the register and the memory, and detecting the read-write function; and verifying the sending and receiving function in a double-machine connection mode. The embodiment of the application utilizes the UVM characteristics, improves the reusability and standardization of the verification environment, realizes highly randomized testing of test cases, makes up for the test points that cannot be found by manpower of the verification personnel, improves the function coverage rate, and realizes comprehensive verification of the uPP module level.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip front-end verification field, in particular, the embodiment of the present application relates to a method for verifying a universal parallel port. BACKGROUND

[0002] With the rapid development of SOC integrated circuits, the complexity of the system itself increases, and the number and functions of integrated peripherals in the chip are increasing. The chip front-end verification stage is responsible for discovering defects in chip functions and ensuring the completion of the chip, which is an indispensable part of the chip development process. The traditional verification method is to use System Verilog (SV) to build a verification environment, perform directional excitation or simple random excitation to complete the test. Although this method can complete the test of the basic functions of the module, the reusability of the verification environment is low, a large number of test cases need to be written, and only some superficial defects can be found. SUMMARY

[0003] The purpose of the embodiment of the present application is to provide a method for verifying a universal parallel port. The embodiment of the present application uses UVM features to improve the reusability and standardization of the verification environment, enables highly randomized testing of test cases, makes up for the test points that cannot be found by human verification personnel, improves the functional coverage, and realizes comprehensive verification of the uPP module level.

[0004] In a first aspect, the embodiment of the present application provides a method for verifying a universal parallel port, the method comprising: configuring a clock rollover interval in a synthesizable top layer, so that the clock signal frequency of the universal parallel port to be verified is a set frequency value; configuring a reset signal to be pulled high after a plurality of clock cycles, so that the universal parallel port ends the reset; reading the reset value of the register and the memory after the reset ends, and confirming that the reset value is correct; performing a write-before-read operation on the register and the memory to detect the read-write function; and verifying the sending and receiving function in a dual-machine connection mode.

[0005] In some embodiments, the method for verifying the sending and receiving function by using the dual-machine connection mode comprises: configuring the universal parallel port master as a sending end and the universal parallel port slave as a receiving end; monitoring the signals transmitted between the interface of the universal parallel port master and the universal parallel port slave by a universal parallel port monitor, wherein the signals comprise: the clock signal, the start signal, the enable signal, the multi-bit data signal sent from the universal parallel port master to the universal parallel port slave, and the wait signal returned from the universal parallel port slave to the universal parallel port master; if the universal parallel port monitor monitors a complete data transmission, the universal parallel port monitor sends the monitored result to a score board; detecting the data quantity and value and the clock frequency by the score board according to the master configuration; and further detecting whether the data received by the universal parallel port slave is correct under the condition that the sending result of the universal parallel port master is correct.

[0006] In some embodiments, the further detecting whether the data received by the universal parallel port slave is correct comprises: judging the RAM address of the data to be received by a configured receiving descriptor, reading the data from the receiving data storage unit RX-DATARAM, and verifying whether the receiving function is correct.

[0007] In some embodiments, the method for verifying the sending and receiving function by connecting the host and the slave includes: setting the universal parallel port host to a sending mode, and writing an array in the universal parallel port environment configuration module uPP env config into the sending data storage unit TX-DATARAM; configuring the universal control register to determine the sending mode of the universal parallel port host in this time; opening the enable signal of the universal parallel port to be tested, and configuring a sending descriptor by random constraint, wherein the sending descriptor includes a transmission start address, a transmission line number, a transmission byte number, and a transmission line interval number; starting the sending of data by the universal parallel port host; monitoring the data sending process by the universal parallel port monitor, and sending a captured universal parallel port sequence item upp sequence item to the score board when a complete data transmission is monitored; generating a reference result according to the received transaction level information by the reference model in the score board; comparing the reference result with the sending result of the universal parallel port host monitored by the universal parallel port monitor by the score board, and confirming the correctness of the data sent by the universal parallel port host; wherein the sending data storage unit TX-DATARAM is used for storing the data to be sent by the universal parallel port host, the universal control register is used for configuring the sending mode type in this time, and the universal parallel port sequence item upp sequence item is used for recording the data value and the control signal value of a complete transmission sent by the universal parallel port host to the universal parallel port slave.

[0008] In some embodiments, the method for verifying the sending and receiving function by connecting the host and the slave includes: setting the universal parallel port host to a sending mode, and writing an array in the universal parallel port environment configuration module uPP env config into the sending data storage unit TX-DATARAM; configuring the universal control register to determine the sending mode of the universal parallel port host in this time; opening the enable signal of the universal parallel port to be tested, and configuring a sending descriptor by random constraint, wherein the sending descriptor includes a transmission start address, a transmission line number, a transmission byte number, and a transmission line interval number; starting the sending of data by the universal parallel port host; monitoring the data sending process by the universal parallel port monitor, and sending a captured universal parallel port sequence item upp sequence item to the score board when a complete data transmission is monitored; generating a reference result according to the received transaction level information by the reference model in the score board; comparing the reference result with the sending result of the universal parallel port host monitored by the universal parallel port monitor by the score board, and confirming the correctness of the data sent by the universal parallel port host; wherein the sending data storage unit TX-DATARAM is used for storing the data to be sent by the universal parallel port host, the universal control register is used for configuring the sending mode type in this time, and the universal parallel port sequence item upp sequence item is used for recording the data value and the control signal value of a complete transmission sent by the universal parallel port host to the universal parallel port slave.

[0009] In some embodiments, the method further includes: after the universal parallel port host and the universal parallel port slave are configured with the corresponding descriptors, waiting for the transmission of data, and then configuring a descriptor for the universal parallel port host and the universal parallel port slave respectively to obtain a queuing descriptor; and after the first transmission is completed, the universal parallel port host and the universal parallel port slave perform a second data transmission according to the queuing descriptor.

[0010] In some embodiments, the method further comprises: when the number of transmission bytes corresponding to the universal parallel port host is greater than a transmission threshold, then the data to be transmitted is transmitted to the general input / output port (GPIO); when the number of reception bytes configured by the reception descriptor corresponding to the universal parallel port slave is greater than a reception threshold, then the data of the general input / output port (GPIO) is received and stored into the reception data memory (RX-DATARAM).

[0011] In some embodiments, the method further comprises: randomly configuring the clock division value of the universal parallel port host output clock into the interface configuration register; the universal parallel port monitor monitors the clock frequency emitted by the universal parallel port host when transmitting data and judges the frequency in the score board.

[0012] In some embodiments, the method further comprises: configuring the enablement and polarity of the control signals of the universal parallel port protocol, verifying that each control signal can be correctly transmitted when enabled and disabled, wherein the polarity can be configured as high active or low active.

[0013] In some embodiments, the method further comprises: first enabling the event interrupt and generating a trigger event, detecting whether an interrupt is generated and verifying whether the generated interrupt meets the event trigger condition, and then clearing the interrupt flag and detecting whether the clearing is successful. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0015] Figure 1 The composition architecture diagram of the verification platform for verifying the universal parallel port provided by the embodiments of the present application is shown in the figure.

[0016] Figure 2 The schematic diagram of the communication monitoring signal of the universal parallel port uPP to be verified provided by the embodiments of the present application is shown in the figure.

[0017] Figure 3 The sequence structure and calling schematic diagram provided by the embodiments of the present application is shown in the figure.

[0018] Figure 4 The flowchart of the method for verifying the universal parallel port provided by the embodiments of the present application is shown in the figure.

[0019] Figure 5Flowchart two of the method for verifying universal parallel port provided by the embodiments of the present application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

[0021] It should be noted that similar reference numerals and letters refer to similar items in the following drawings, and therefore, once an item is defined in one drawing, it need not be further defined and explained in subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second", and the like are merely used to distinguish description, and cannot be understood as indicating or implying relative importance.

[0022] At least to overcome the problems in the background art section, the embodiments of the present application provide a more advanced verification method, which can improve the multiplicity of the verification environment and the verification efficiency, and can perform more complex constraints and random test to find deep-seated defects. This method is based on the universal verification method UVM.

[0023] Universal parallel port (uPP) is a high-speed parallel interface with a dedicated data bus and minimal control signals. It can be connected with high-speed digital-to-analog (DAC) or analog-to-digital (ADC) converters with eight-bit data width, or can be interconnected with field programmable gate array (FPGA) or other universal parallel port uPP devices to realize high-speed digital data transmission. The transmission mode of the universal parallel port uPP module is various, the control signal is complex, and the timing has strict requirements. The traditional verification method is difficult to find defects caused by the configuration mode and queuing function of the universal parallel port uPP to be verified. Therefore, the embodiments of the present application provide a more comprehensive verification environment and verification method for verifying universal parallel port.

[0024] Please refer to Figure 1 , Figure 1 The verification platform for verifying universal parallel port is a uPP verification environment structure diagram based on UVM (Universal Verification Methodology), and the related components required in the environment are shown in the diagram. The detailed functions of each component of the verification platform will be described below. Figure 1

[0025] ​The verification environment of the embodiment of the present application needs two top layers as follows: a synthesizable part top layer hdl_top, which is used to instantiate an interface and a design under test (DUT), generate a clock and a reset signal, and pass a virtual interface to a corresponding agent; and a start verification environment top layer hvl_top, which is used to start the whole UVM verification platform by calling a built-in task run_test().

[0026] A basic test case upp_test_base is used to instantiate a universal parallel port environment upp env, a universal parallel port environment configuration module upp env config, an upp agent configuration upp agent config, an advanced high performance bus (AHB) agent configuration ahb agent config, a register memory model, and an interrupt utility. General variables, structure variables, and mode variables are controlled by configuring variables in the upp env config, so as to control the whole verification environment. The upp env config contains the upp agent config and the ahb agent config, and is responsible for hierarchical configuration of the agents. The register model is instantiated, reset, configured, and passed to the upp env config after a backdoor access path is passed. The class is a base class of all test cases, and all test cases inherit from the class. Different verification environments can be generated in different test cases to meet different test requirements. A function of passing the upp env config is declared in the base class, which is used to pass two sequencers and the register model to a virtual sequence, so as to facilitate calling of the virtual sequence and the sequence.

[0027] A basic environment upp_env_base is used to instantiate an ahb agent, an upp agent, a scoreboard, a functional coverage, an adapter, and a register predictor. An analysis port of the ahb agent is connected to the reg predictor, the functional coverage, and the scoreboard, and an analysis port of the upp agent is connected to the scoreboard. A monitor of the two agents sends monitored thing level information to a receiving end through the analysis port.

[0028] Environment configuration upp_env_config: used to control the verification environment, contains multiple structure variables, used as switches of components. At the same time, a 32-bit random array with a depth of 128 is declared, and a function for randomizing the array is declared, which can be called by the sequence and the score board. In the initialization of the ahb sequence of TX-DATARAM, the random function is called, and the array is written into the TX-DATARAM of the host. The reference model of the score board also uses the same random array for processing. In the ahb sequence for reading and detecting data received by the slave RX-DATARAM, the random array after randomization is also needed for comparison.

[0029] Advanced high-performance bus agent ahb_agent: used to instantiate ahb driver, ahb monitor, ahb sequencer and analysis port. Responsible for connecting the analysis port in the agent and the analysis port in the minitor, connecting the seq_item_port in the driver to the seq_item_export in the sequencer. By configuring the ahb agent config, it can be determined whether each component in the ahb agent is created and used. This agent is mainly responsible for operations related to the AHB protocol, including reading and writing registers, reading and writing memories, and monitoring AHB buses to collect functional coverage, etc.

[0030] Universal Parallel Port Agent (UPP Agent): used to instantiate the UPP driver, UPP monitor, UPP sequencer and analysis port. It is responsible for connecting the analysis port in the agent and the analysis port in the monitor, and connecting the seq_item_port in the driver to the seq_item_export in the sequencer. By configuring the UPP agent config, it can be determined whether each component in the UPP agent is created and used. For example, by configuring the value of UVM_ACTIVE, it can be controlled whether to instantiate and connect the UPP driver and the UPP sequencer. This agent is mainly responsible for driving and monitoring the remaining signals of the UPP module except for the AHB signal, the interrupt signal, the clock and the reset signal, including the debug mode signal, the host number signal, the initialization completion signal, the general purpose input / output port (GPIO) output enable signal and the UPP transmission protocol signal. The UPP monitor sends the monitored data packet to the scoreboard for result judgment.

[0031] Interrupt Service Program (Intr Utils): used to monitor the interrupt signal, in which the task of waiting for the interrupt and the function of detecting the interrupt clearing are declared, which can be called by the scoreboard and the sequence to detect the interrupt signal.

[0032] Scoreboard: used to process the transaction-level data packet received, send it to the reference model, compare the results output by the reference model and the to-be-tested module, and judge whether the GPIO output enable is correct, whether the sent clock is correctly divided, and whether the data corresponds to the configuration. At the same time, the interrupt service program is set to wait for the interrupt signal to be generated. After detecting the interrupt signal, the interrupt handling program is triggered immediately to detect the type of interrupt triggered, whether the triggering condition is met, and clear the interrupt. It should be noted that the sending function of the universal parallel port (UPP) to be tested in some embodiments of the present application can generate the data and control information and clock packet to be sent according to the configured register information (including sending mode, descriptor or interface control information), but there is no timing output. The reference model can generate a complete transmission reference UPP_seq_item, so the comparator in the scoreboard compares the UPP_aeq_item sent by the host monitored by the UPP monitor with the result output by the reference model to judge whether the sending function is correct.

[0033] Functional Coverage: According to the verification plan, the corresponding functional coverage group is written, and the ahb_seq_item written back by the ahb monitor is sampled to collect the coverage of the functional points.

[0034] Register and memory model: The registers and two built-in RAMs of the general-purpose parallel port uPP module to be verified are modeled, and the corresponding register access mode, offset address and backdoor access path are configured. The size of each memory is configured as 512 bytes, which is the same as the size of the internal RAM of the uPP module, facilitating the access to the registers and RAM. The bus register information ahb_seq_item monitored by the AHB monitor is sent to the predictor Predictor, and the predictor updates the mirror value of the register model. When the register model is used to configure the registers, the configured register information is converted into ahb_aeq_item information that can be sent by the AHB sequencer through the adapter Adapter, completing the sending of the register configuration.

[0035] Bus functional model (BFM): The interface actually connected to the design under test, which internally contains tasks or functions for driving or monitoring signals, and has three BFM: AHB BFM, UPP BFM and INTR BFM, which are connected to the corresponding agents, respectively. The monitor and the driver are not directly connected to the interface of the design under test, but realize the driving and monitoring of the signals by calling the tasks or functions of the BFM. In this way, the transaction-level verification platform and the pin-level signal transmission part can be separated, which is conducive to the transplantation of the verification environment to the hardware acceleration platform.

[0036] Design under test (DUT): The two UPPs instantiated at the top level, upp1 is configured as the master for sending, and upp2 is configured as the slave for receiving, and the DUT is connected with the test platform through the BFM.

[0037] Figure 2This diagram illustrates the monitoring signals for dual-machine communication using the Universal Parallel Port (uPP) in some embodiments of this application. To simplify the verification environment and improve verification efficiency, embodiments of this application employ a dual-machine connection to verify the sending and receiving functions. The uPP master (or universal parallel port master) is configured as the sending end, used to send data, and the uPP slave (or universal parallel port slave) is configured as the receiving end, used to receive data. The universal parallel port master's sending data is stored in the sending data storage unit TX-DATARAM, and the slave's receiving start address is the mapping address of the master's sending address in RX-DATARAM. This configuration makes detecting the received data value simpler and more convenient, eliminating the need to write drivers in the environment and avoiding environmental errors that could interfere with the verification results. Figure 2 As shown, the Universal Parallel Port Monitor (uPP monitor) monitors the interface sent from the master to the slave via the Universal Parallel Port Bus Functions (UPP) module (to monitor the data, control signals, and clock of a complete UPP transmission), including the output clock signal (e.g., Figure 2 The signal connecting the CLKOUT pin on the host and the CLK IN pin on the slave), and the start signal (e.g., Figure 2 The signal connecting the START OUT pin on the host and the START IN pin on the slave, and the enable signal (e.g., Figure 2 The signal connecting the ENABLE OUT pin on the host and the ENABLE IN pin on the slave), and the wait signal returned by the slave to the host (e.g., Figure 2 The signal connecting the WAIT IN pin on the host and the WAIT OUT pin on the slave) and an eight-bit data signal (e.g., Figure 2 (This refers to the signal between the DATA OUT pin on the host and the DATA IN pin on the slave). After detecting a complete data transmission, the Universal Parallel Port Monitor (UPP) sends the detected result to the Scoreboard. The Scoreboard performs data quantity and value detection and clock frequency division detection according to the host configuration to verify whether the host's transmission result is correct. Once the transmission function is confirmed to be accurate, it then checks whether the data received by the slave receiver in the RX-DATARAM is correct. It determines the RAM address where the data should be received using the configured descriptor, reads the slave's RX-DATARAM, and verifies whether the reception function is completely correct.

[0038] Figure 3 This application provides a sequence structure and call diagram for some embodiments, verifying the existence of two agent modules in the environment, namely... Figure 3The ahb agent and the upp agent each send a respective sequence item. The ahb sequence completes operations related to the AHB protocol, such as configuring registers, reading and writing memory, etc., and sends the generated ahb sequence item to the ahb driver through the ahb sequencer; the upp sequence completes operations of the remaining signals, such as setting the host number, monitoring the upp protocol signal, etc., and sends the generated upp sequence item to the upp driver through the upp sequencer. The two sequences are invoked in the test sequence to cooperate to complete the test function. The test sequence connects the sequence to the corresponding sequencer, and this function is implemented through the xxx_seq.start(xxx_sqr, this) statement. The sequencer in the test sequence is passed by calling the function in the upp test base.

[0039] The following will be described in conjunction with Figure 4 The method for verifying a universal parallel port provided by some embodiments of the present application is exemplarily described, and the method exemplarily includes:

[0040] S101, configuring a clock rollover interval in a synthesizable top layer, so that the clock signal frequency of the universal parallel port to be verified is a set frequency value.

[0041] S102, configuring a reset signal to be pulled high after a plurality of clock cycles, so that the universal parallel port ends the reset.

[0042] S103, reading the reset value of a register and a memory after the reset ends, and confirming that the reset value is correct.

[0043] S104, performing a write-first-read-later operation on the register and the memory, and detecting the read-write function.

[0044] S105, verifying the sending-receiving function in a dual-machine connection mode.

[0045] In some embodiments of the present application, the process of verifying the sending and receiving function in S105 employs a double machine connection mode, which includes: configuring the universal parallel port host as a sending end and the universal parallel port slave as a receiving end; storing the data to be sent by the universal parallel port host in a sending data storage unit TX-DATARAM, and storing the data to be received by the universal parallel port slave in a receiving data storage unit RX-DATARAM; monitoring the signals transmitted between the interface of the universal parallel port host and the universal parallel port slave by a universal parallel port monitor, wherein the signals include: a clock signal, a start signal start, an enable signal enable, a multi-bit data signal sent from the universal parallel port host to the universal parallel port slave, and a wait signal wait returned from the universal parallel port slave to the universal parallel port host; if the universal parallel port monitor monitors a complete data transmission, the universal parallel port monitor sends the detected result to a score board; detecting the number and value of data and clock frequency by the score board according to the host configuration; and further detecting whether the data received by the universal parallel port slave is correct under the condition that the sending result of the universal parallel port host is correct.

[0046] In some embodiments of the present application, the further detection of whether the data received by the universal parallel port slave is correct includes: judging the RAM address of the data to be received by a configured receiving descriptor, reading the data from the receiving data storage unit RX-DATARAM, and verifying whether the receiving function is correct.

[0047] In some embodiments of the present application, the sending and receiving function verification in the dual-machine connection mode comprises: setting the universal parallel port host in a sending mode, and writing an array in the universal parallel port environment configuration module uPP env config into the sending data storage unit TX-DATARAM after randomization; configuring the universal control register to determine the sending mode of the universal parallel port host in this time; opening the enable signal of the universal parallel port under test, and configuring a sending descriptor through randomization, wherein the sending descriptor comprises a transmission start address, a transmission line number, a transmission byte number, and a transmission line interval number; starting data sending by the universal parallel port host; detecting the data sending process by the universal parallel port monitor, and sending a captured universal parallel port sequence item upp sequence item to the score board when a complete data transmission is monitored by the universal parallel port monitor; generating a reference result according to the received transaction level information by the reference model in the score board; comparing the reference result with the sending result of the universal parallel port host monitored by the universal parallel port monitor by the score board, and confirming the correctness of the data sent by the universal parallel port host; wherein the sending data storage unit TX-DATARAM is used for storing the data to be sent by the universal parallel port host, the universal control register is used for storing the sending mode type in this time, and the universal parallel port sequence item upp sequence item is used for recording the data value and the control signal value of a complete transmission sent by the universal parallel port host to the universal parallel port slave.

[0048] In some embodiments of the present application, the sending and receiving function verification in the dual-machine connection mode comprises: configuring the universal parallel port slave in a receiving mode, wherein the receiving mode corresponds to the sending mode of the universal parallel port host in this time; storing the data received by the universal parallel port slave into the receiving data storage unit RX-DATARAM; after the universal parallel port slave completes data receiving, performing a read operation on the RX-DATARAM corresponding address according to the content of the receiving descriptor to obtain the to-be-verified receiving data; comparing the to-be-verified receiving data with the corresponding data of the randomly generated array to determine whether the receiving function is correct.

[0049] In some embodiments of the present application, the method further comprises: in the phase of waiting for transmission data after the universal parallel port host and the universal parallel port slave are configured with corresponding descriptors, respectively configuring a descriptor for the universal parallel port host and the universal parallel port slave again and queuing, to obtain a queued descriptor; after the first transmission is completed, performing a second data transmission according to the queued descriptor by the universal parallel port host and the universal parallel port slave.

[0050] In some embodiments of the present application, the method further comprises: when the number of transmission bytes corresponding to the universal parallel port host is greater than a transmission threshold, the data to be transmitted is transmitted to a general input / output port (GPIO); and when the number of reception bytes configured by the reception descriptor corresponding to the universal parallel port slave is greater than a reception threshold, the data of the general input / output port (GPIO) is received and stored into the reception data memory (RX-DATARAM).

[0051] In some embodiments of the present application, the method further comprises: randomly constraining the clock frequency of the universal parallel port host output clock, and determining in the scoreboard.

[0052] In some embodiments of the present application, the method further comprises: configuring the enablement and polarity of the control signals of the universal parallel port protocol, and verifying that each control signal can be correctly transmitted when enabled or disabled, wherein the polarity can be configured as high active or low active.

[0053] In some embodiments of the present application, the method further comprises: first enabling the event interrupt and generating a trigger event, detecting whether an interrupt is generated and verifying whether the generated interrupt meets the event trigger condition, and then clearing the interrupt flag and detecting whether the clearing is successful. In some embodiments of the present application, the data to be transmitted is written into the transmission data storage unit (TX-DATARAM), the master-slave descriptor is configured, and the data is transmitted to the slave, and the slave receives the data into the reception data storage unit (RX-DATARAM).

[0054] The following will be described in detail with reference to the accompanying drawings. Figure 5 An exemplary method for verifying a universal parallel port is described.

[0055] First, the uPP module UVM verification environment is built.

[0056] Second, two upp modules are instantiated in the top layer as a host and a slave.

[0057] Third, the register and RAM read-write verification is performed.

[0058] The universal parallel port uPP module verification flowchart, the module-level verification of the uPP module, and the detailed method of using the above UVM verification environment are as follows:

[0059] The clock rollover interval is configured in the synthesizable top layer, so that the module clock signal frequency of the uPP is 300 MHz. The reset signal is pulled high from low after a short period of time at the beginning of running, so that the module ends the reset. The reset value of the register and the memory is read after the reset ends, to detect whether the reset value is correct; then all the registers and the memory are written and then read, to detect the read-write function.

[0060] Fourthly, the four basic sending modes are verified respectively. The uPP master (i.e. universal parallel port master) is set as the sending mode, the array in the env config is written into the TX-DATARAM (i.e. the TX-DATARAM stores the data to be sent by the universal parallel port master) after randomization, the universal control register is configured to configure the specific mode of sending, the uPP module is enabled, the valid sending descriptor is generated through random constraint, including the transmission start address, the transmission row number, the byte number and the row interval number. After the valid descriptor is configured, the uPP module starts sending data, and the upp monitor monitors a complete data transmission and sends the captured upp sequence item to the scoreboard. The reference model in the scoreboard generates the reference result through the received thing level information, and compares the received host sending result to judge whether the sent data is correct.

[0061] Fifthly, the four basic receiving modes are verified respectively. After ensuring that the host sending mode is correct, the uPP slave is configured as the receiving mode, and the specific receiving mode corresponds to the host sending mode. The receiving address of the slave receiving descriptor is the mapping address of the host sending address, and the rest is the same as the host, so that the receiving data can be easily detected. After the slave completes the receiving, the address of the received data is read through the descriptor, and the corresponding data of the randomly generated array is compared to judge whether the receiving function is correct.

[0062] Sixthly, the queuing function verification. After the uPP is configured with the descriptor, the waiting transmission phase can be configured with the descriptor again for queuing. After the first transmission is completed, the second queuing descriptor transmission will be performed immediately. Only one queuing descriptor can exist at the same time, if the descriptor is written again, the DMA programming error interrupt event will be triggered and the configured descriptor will not take effect, and the third transmission will not be performed. The sending end and the receiving end are configured with a queuing descriptor during the verification, and two complete transmissions can be completed.

[0063] Step 7, interrupt verification. Channel I and channel Q can each generate four interrupt events: end-of-line interrupt, end-of-window interrupt, DMA programming error interrupt, and underflow or overflow interrupt, for a total of eight interrupt types. End-of-line event: this event occurs when the DMA channel reaches the end of a line of the data window. End-of-window event: this event occurs when the DMA channel reaches the end of the data window. DMA programming error event: this event occurs when a descriptor has already been queued and a descriptor is written again. Underflow or overflow event: this event occurs when the number of bytes configured by the descriptor is less than the threshold or greater than 512 bytes. When testing the interrupt event, first enable the event interrupt and generate a trigger event, detect whether an interrupt is generated and whether the trigger condition of the event is met when the interrupt is generated, and then clear the interrupt flag to detect whether the clearing is successful.

[0064] Step 8, send / receive threshold verification. When the number of bytes configured by the host descriptor for sending is greater than the sending threshold, the data is sent to the GPIO port; when the number of bytes configured by the slave descriptor for receiving is greater than the receiving threshold, the GPIO port data is received into the RX-DATA RAM. When the number of bytes configured by the descriptor is less than the threshold or greater than 512 bytes, the underflow or overflow interrupt event is triggered.

[0065] Step 9, clock division verification

[0066] Randomly constrain the clock division of the uPP host output clock, and determine in the score board. Monitor how many module clocks there are in the time of an output clock, and compare with the configured division. When the mode is single-data-rate (SDR), the highest support is four divisions; when double-data-rate (DDR), the highest support is eight divisions. Here, the highest transmission rate of uPP is tested.

[0067] Step 10, control signal enable and polarity control verification

[0068] Configure the enable and polarity of the control signals of the uPP protocol, verify that each control signal can be correctly transmitted when enabled and disabled, and the polarity of the signal can be configured as high active or low active. Different polarity situations are generated by randomly constraining the polarity configuration, and it is required to ensure that the signal polarity of the host uPP and the slave uPP should be configured in the same way to achieve normal transmission.

[0069] Step 11, soft reset function verification: by configuring the soft reset function bit of the register, the uPP can be soft reset. Soft reset only resets the uPP internal and state machine and the signals related to it, and does not reset the register. When the uPP runs an error, the uPP module can be reset by soft reset to avoid uPP module dead.

[0070] Twelfth step, verification end, change random SEED value, regression.

[0071] uPP function verification end, because the test case uses random constraint to produce register value and signal, so by changing the SEED value of the Makefile script, different excitation conditions can be produced. Change the SEED value several times, use the regression script to perform regression verification, and can more comprehensively cover the function points.

[0072] It should be noted that the UPP, upp or uPP of some embodiments of the application are all representations of the universal parallel port. The data to be sent of the universal parallel port is stored in the sending data storage unit TX-DATARAM, and the received data is stored in the receiving data storage unit RX-DATARAM.

[0073] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can also be implemented in other ways. The apparatus embodiments described above are only schematic, for example, the flowcharts and block diagrams in the drawings show the possible implementation architectures, functions and operations of the apparatus, method and computer program product according to the embodiments of the present application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment or a part of code, which contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur in different orders than that shown in the figure. For example, two consecutive blocks can actually be executed substantially in parallel, and sometimes they can be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0074] In addition, each functional module in the various embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0075] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts of the prior art that make contributions or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0076] The above merely provides an example of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that similar reference numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0077] The above merely provides an example of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that similar reference numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0078] It should be noted that, in this document, the terms such as first and second are used merely to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the processes, methods, articles or devices including a series of elements not only include those elements, but also include other elements not explicitly listed or inherent to such processes, methods, articles or devices. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or device including the element.

Claims

1. A method for authenticating a universal parallel port, characterized by, The method comprises: configuring a clock rollover interval in a synthesizable top layer, so that the clock signal frequency of the universal parallel port to be verified is a set frequency value; configuring a reset signal to be pulled high after a plurality of clock cycles, so that the universal parallel port ends the reset; reading the reset values of the registers and the memory after the reset ends, and confirming that the reset values are correct; performing a write-before-read operation on the registers and the memory, and detecting the read-write function; verifying the sending and receiving function in a dual-machine connection mode; wherein: the verifying the sending and receiving function in the dual-machine connection mode comprises: configuring the universal parallel port master as a sending end and configuring the universal parallel port slave as a receiving end; the universal parallel port monitor monitors the signals transmitted between the interfaces of the universal parallel port master and the universal parallel port slave, wherein the signals comprise: the clock signal, the start signal, the enable signal, the multi-bit data signal sent from the universal parallel port master to the universal parallel port slave, and the wait signal returned by the universal parallel port slave to the universal parallel port master; if the universal parallel port monitor monitors a complete data transmission, the universal parallel port monitor sends the monitored result to the score board; the score board detects the number and value of the data according to the master configuration and detects the clock frequency; under the condition that the sending result of the universal parallel port master is confirmed to be correct, further detecting whether the data received by the universal parallel port slave is correct.

2. The method of claim 1, wherein, the further detecting whether the data received by the universal parallel port slave is correct comprises: judging the RAM address of the data to be received through the configured receiving descriptor, reading the data from the receiving data storage unit RX-DATARAM, and verifying whether the receiving function is correct.

3. The method of claim 1, wherein, the verifying the sending and receiving function in the dual-machine connection mode comprises: setting the universal parallel port master as a sending mode, and writing the array in the universal parallel port environment configuration module uPP env config into the sending data storage unit TX-DATARAM after randomization; configuring the universal control register to determine the sending mode adopted by the universal parallel port master in this time; opening the enable signal of the universal parallel port to be tested, and configuring the sending descriptor through random constraint, wherein the sending descriptor comprises a transmission start address, a transmission row number, a transmission byte number, and a transmission row interval number; starting the data sending by the universal parallel port master; monitoring the data sending process by the universal parallel port monitor, and when the universal parallel port monitor monitors a complete data transmission, sending the captured universal parallel port sequence item upp sequence item to the score board; generating a reference result according to the received transaction level information through the reference model in the score board; comparing the reference result with the sending result of the universal parallel port master monitored by the universal parallel port monitor through the score board, and confirming that the data sent by the universal parallel port master is correct. The sending data storage unit TX-DATARAM is configured to store the data to be sent by the universal parallel port host, the universal control register is configured to configure the sending mode type of this time, and the universal parallel port sequence item uppsequence item is configured to record the data value and control signal value of one complete transmission of the universal parallel port host to the universal parallel port slave.

4. The method of claim 2, wherein, The sending and receiving function is verified by using the double-machine connection mode, which comprises the following steps: The universal parallel port slave is configured to be in a receiving mode, wherein the receiving mode corresponds to the sending mode of the universal parallel port host in this time; The universal parallel port slave stores the received data into the receiving data storage unit RX-DATARAM; After the universal parallel port slave completes the data receiving, the receiving data storage unit RX-DATARAM is read according to the content of the receiving descriptor to obtain the to-be-verified receiving data; The to-be-verified receiving data is compared with the corresponding data of the randomly generated array to determine whether the receiving function is correct.

5. The method of claim 4, wherein, The method further comprises the following steps: After the universal parallel port host and the universal parallel port slave are configured with the corresponding descriptors, the universal parallel port host and the universal parallel port slave are respectively configured with a descriptor again to obtain a queuing descriptor in a phase of waiting for transmission data; After the first transmission is completed, the universal parallel port host and the universal parallel port slave perform a second data transmission according to the queuing descriptor.

6. The method of claim 5, wherein, The method further comprises the following steps: When the transmission byte number corresponding to the universal parallel port host is greater than a sending threshold value, the to-be-sent data is sent to a general input / output port GPIO; When the receiving byte number configured by the receiving descriptor corresponding to the universal parallel port slave is greater than a receiving threshold value, the data of the general input / output port GPIO is received and stored into the receiving data storage unit RX-DATARAM.

7. The method of claim 6, wherein, The method further comprises the following steps: The clock division value of the universal parallel port host output clock is randomly configured into an interface configuration register; The universal parallel port monitor monitors the clock frequency emitted by the universal parallel port host during the transmission of data and judges the frequency in the score board.

8. The method of claim 6, wherein, The method further comprises the following steps: The control signal enable and polarity of the universal parallel port protocol are configured, and it is verified that each control signal can be correctly transmitted when enabled and disabled, wherein the polarity can be configured as high-level active or low-level active.

9. The method of claim 8, wherein, The method further comprises the following steps: An event interrupt is enabled first to generate a trigger event, and it is detected whether an interrupt is generated and whether the generated interrupt meets the event trigger condition, and then the interrupt flag is cleared and it is detected whether the clearing is successful.

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