A semiconductor power device and a method of manufacturing the same

Abstract

A semiconductor power device and a method for manufacturing the same. The semiconductor power device comprises: a plurality of first pillar regions arranged in the extension direction of the gate structure in the drift layer; the drift layer between adjacent first pillar regions as a second pillar region; the first pillar region and the second pillar region both extend from below the well region on one side of the gate structure to below the well region on the other side of the gate structure; the first pillar region comprises a first region and a plurality of second regions arranged in the direction perpendicular to the surface of the semiconductor substrate layer, adjacent second regions are arranged at intervals, each layer of second regions in any one first pillar region comprises a second sub-region extending in the length direction of the gate structure, the second sub-region is connected with the second pillar region, the first region surrounds the second sub-region, the conductivity type of the first region is opposite to that of the second pillar region, and the conductivity type of the second region is the same as that of the second pillar region. The reverse recovery performance of the semiconductor power device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor power device and its fabrication method. Background Technology

[0002] Wide bandgap materials, especially 4H-SiC, have been used in the fabrication of power electronic devices, such as SiC MOSFETs, and are considered one of the most promising technologies for next-generation power electronic converters.

[0003] To fully realize the potential of this technology, special attention must be paid to the analysis of switching transitions caused by voltage stresses generated during rapid switching, which involves parasitic elements related to package and printed circuit board (PCB) layout. The state of the third-quadrant body diode of SiC MOSFETs during operation is of particular concern. In this case, the reverse recovery of the body diode plays a critical role during switching transitions, as it affects the performance of the power converter. Specifically, reverse recovery occurs when the body diode transitions from freewheeling to turn-off. When the reverse recovery process is too rapid, the resonant circuit formed by the parasitic circuit inductance and diode depletion layer capacitance can generate severe voltage spikes, and if a critical voltage value is reached, the voltage surge can cause the body diode to fail, severely impacting the performance of the power device. Summary of the Invention

[0004] The technical problem to be solved by this invention is how to improve the reverse recovery performance of semiconductor power devices in related technologies and increase the softness factor.

[0005] To address the aforementioned technical problems, this invention provides a semiconductor power device, comprising: a semiconductor substrate; a drift layer on the semiconductor substrate; a gate structure on a portion of the drift layer; a well region located in drift layers on both sides of the gate structure and extending to the bottom of a portion of the gate structure; a plurality of spaced first pillar regions arranged in the drift layer along the extension direction of the gate structure; a drift layer between adjacent first pillar regions serving as a second pillar region; both the first pillar region and the second pillar region extending from below the well region on one side of the gate structure to below the well region on the other side of the gate structure; the first pillar region includes a first region and a plurality of second regions arranged in a direction perpendicular to the surface of the semiconductor substrate, with adjacent second regions spaced apart, each second region in any first pillar region including a second sub-region extending along the length direction of the gate structure, the second sub-region being connected to the second pillar region, the first region surrounding the second sub-region, the conductivity type of the first region being opposite to that of the second pillar region, and the conductivity type of the second region being the same as that of the second pillar region.

[0006] Optionally, each layer of the second region in any first pillar region includes a plurality of second sub-regions extending along the length direction of the gate structure, and the plurality of second sub-regions in the second region are arranged at intervals along the length direction of the channel.

[0007] Optionally, the second sub-regions in the second regions of adjacent layers in any first pillar region are arranged in a direction perpendicular to the surface of the semiconductor substrate layer.

[0008] Optionally, the second sub-regions in the second region of any adjacent layer in the first column region are staggered along the length of the channel.

[0009] Optionally, the orthographic projection patterns of the second sub-regions in the second region of an adjacent layer in any first pillar region partially overlap on the surface of the semiconductor substrate; or, the orthographic projection patterns of the second sub-regions in the second region of an adjacent layer in any first pillar region do not overlap on the surface of the semiconductor substrate.

[0010] Optionally, the dimension of the second sub-region along the channel length direction is larger than the dimension along the direction perpendicular to the surface of the semiconductor substrate.

[0011] Optionally, the cross-sectional pattern of the second sub-region along the length direction perpendicular to the gate structure is a feature pattern, which is a circle, ellipse, rectangle or square; or, the feature pattern includes a main pattern and sub-patterns located on both sides of the main pattern along the channel length direction, the sub-patterns having feature edges protruding away from the main pattern in the direction parallel to the channel length direction, and the two ends of the feature edges being connected to the main pattern.

[0012] Optionally, it further includes: a source region located in the well region; and an ohmic contact region located in the well region and in contact with the source region, wherein the ohmic contact region has the same conductivity type as the well region.

[0013] The present invention also provides a method for fabricating a semiconductor power device, comprising: providing a semiconductor substrate; forming a drift layer on the semiconductor substrate, wherein during the formation of the drift layer, a plurality of first pillar regions arranged at intervals along a first direction are formed in the drift layer, and the drift layer between adjacent first pillar regions serves as a second pillar region; the first pillar region includes a first region and a plurality of second regions arranged along a direction perpendicular to the surface of the semiconductor substrate, the second regions of adjacent layers are spaced apart, each second region in any first pillar region includes a second sub-region extending along the first direction, the second sub-region is connected to the second pillar region, the first region surrounds the second sub-region, the conductivity type of the first region is opposite to the conductivity type of the second pillar region, and the conductivity type of the second region is the same as the conductivity type of the second pillar region; forming a well region in the drift layer; forming a gate structure extending along the first direction on the drift layer, the gate structure covering the drift layer between adjacent well regions and a portion of the surface of adjacent well regions; the first pillar region and the second pillar region both extend from below the well region on one side of the gate structure to below the well region on the other side of the gate structure.

[0014] Optionally, the step of forming the drift layer, the first pillar region, and the second pillar region includes: forming a first epitaxial layer on the semiconductor substrate; forming a plurality of first doped regions arranged at intervals along a first direction in the first epitaxial layer, wherein the first epitaxial layer between adjacent first doped regions serves as a first connection region, and the conductivity type of the first connection region is opposite to that of the first doped region; forming a second epitaxial layer on the first doped region and the first connection region, wherein the second epitaxial layer located above and in contact with the first connection region serves as a second connection region, and the conductivity type of the second epitaxial layer is the same as that of the first epitaxial layer; forming a plurality of second doped regions in the second epitaxial layer on both sides of the second connection region along the first direction, wherein the second doped regions are located above a portion of the first doped regions; the plurality of second doped regions on any side of the second connection region along the first direction are arranged at intervals along a second direction, and the second epitaxial layer between adjacent second doped regions along the second direction serves as a second sub-region, wherein the second sub-region is connected to the second connection region, and the second direction... The conductivity type of the second doped region is opposite to that of the second connection region, which intersects with the first direction. A third epitaxial layer is formed on the second connection region, the second sub-region, and the second doped region. The conductivity type of the third epitaxial layer is the same as that of the first epitaxial layer. A plurality of third doped regions are formed in the third epitaxial layer at intervals along the first direction. The third doped regions are located above the second doped region and the second sub-region. The third epitaxial layer between adjacent third doped regions serves as a third connection region. The third connection region is located above the second connection region, and the conductivity type of the third connection region is opposite to that of the third doped region. A top drift region is formed above the third doped region and the third connection region. The conductivity type of the top drift region is the same as that of the first epitaxial layer. The first connection region, the second connection region, and the third connection region constitute the second pillar region. The first doped region, the second doped region, and the third doped region constitute the first region. The step of forming a well region in the drift layer is: forming a well region in the top drift region.

[0015] Optionally, it further includes: forming a source region in the well region; and performing an annealing process after forming the source region.

[0016] Optionally, it may also include repeating the steps of forming the first epitaxial layer, forming the first doped region, forming the second epitaxial layer, and forming the second doped region before forming the third epitaxial layer.

[0017] Optionally, the second doped regions of the adjacent layers on either side of the second pillar region are arranged in a direction perpendicular to the surface of the semiconductor substrate; or, the second doped regions of the adjacent layers on either side of the second pillar region are staggered along a second direction.

[0018] The technical solution of this invention has the following technical effects:

[0019] The semiconductor power device provided by this invention, when the gate structure is turned off and the potential of the source region is greater than that of the drain electrode layer, almost no current flows through the channel. The PN junction formed by the well region and the second pillar region at the bottom of the well region is turned on, and the PN junction formed by the well region and the second sub-region at the bottom of the well region is turned on, so that electrons from the second sub-region and the second pillar region are injected into the first region, and holes from the first region are injected into the second sub-region and the second pillar region. Reverse recovery includes a first recovery stage and a second recovery stage performed sequentially. In the first recovery stage, electrons in the first region are extracted into the second sub-region and the second pillar region, and holes in the second sub-region and the second pillar region are extracted into the first region. The second recovery stage needs to restore to the reverse breakdown voltage state. In the second recovery stage, holes in the first region are extracted to the front electrode through the well region, and electrons in the second sub-region and the second pillar region are extracted to the drain electrode layer. In the second recovery stage, the second sub-region blocks the transmission of holes from the first region to the front electrode, forming a potential barrier. Holes in the first region below the second sub-region need to pass through the second sub-region to reach the first region above the second sub-region, which makes the second recovery stage slower and longer, reduces dV / dt, reduces the peak voltage of the reverse recovery process, improves the reverse recovery performance of semiconductor power devices, and increases the softness factor.

[0020] Furthermore, it also includes an ohmic contact region. When the gate structure is turned off and the potential of the source region is greater than that of the drain electrode layer, the PN junction formed by the well region and the second pillar region at the bottom of the well region, as well as the PN junction formed by the ohmic contact region and the second pillar region at the bottom of the ohmic contact region, are turned on. In the second recovery phase, holes in the first region are drawn to the front electrode through the well region and the ohmic contact region. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of the present invention, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 A three-dimensional structural schematic diagram of a semiconductor power device provided in an embodiment of the present invention;

[0023] Figure 2 for Figure 1 A schematic diagram of the middle section structure;

[0024] Figure 3 A schematic diagram of a feature graphic;

[0025] Figures 4 to 20 This is a schematic diagram of the semiconductor power device fabrication process provided in another embodiment of the present invention. Detailed Implementation

[0026] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0028] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0029] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0030] One embodiment of the present invention provides a semiconductor power device, in conjunction with reference to [reference needed]. Figure 1 and Figure 2 ,include:

[0031] Semiconductor substrate layer 100;

[0032] Drift layer 110 located on semiconductor substrate 100;

[0033] Gate structure 170 located on part of drift layer 110;

[0034] Well region 140 is located in drift layer 110 on both sides of gate structure 170 and extends to the bottom of drift layer 110 of gate structure 170.

[0035] A plurality of first pillar regions 130 are arranged at intervals in the drift layer 110 along the extension direction of the gate structure 170; the drift layer 110 between adjacent first pillar regions 130 serves as a second pillar region 120; both the first pillar region 130 and the second pillar region 120 extend from below the well region 140 on one side of the gate structure 170 to below the well region 140 on the other side of the gate structure 170; the first pillar region 130 includes a first region 132 and a plurality of second regions arranged in a direction perpendicular to the surface of the semiconductor substrate layer 100, the second regions of adjacent layers are spaced apart, each second region in any first pillar region 130 includes a second sub-region 131 extending along the length direction of the gate structure 170, the second sub-region 131 is connected to the second pillar region 120, the first region 132 surrounds the second sub-region 131, the conductivity type of the first region 132 is opposite to the conductivity type of the second pillar region 120, and the conductivity type of the second region is the same as the conductivity type of the second pillar region 120.

[0036] In this embodiment, next-generation SiC-based semiconductor power devices, represented by SiC, exhibit higher reverse voltage withstand capability, lower forward conduction loss, faster switching frequency, and stronger environmental tolerance compared to Si-based semiconductor power devices, and are therefore considered a new hope in the field of power conversion. It should be noted that in this embodiment, the semiconductor substrate 100 is silicon carbide (SiC) doped with conductive ions. In one embodiment, the conductive ions in the semiconductor substrate 100 are N-type ions. In other embodiments, the conductivity type of the semiconductor substrate 100 is not limited.

[0037] In one embodiment, the drift layer 110 has the same conductivity type as the semiconductor substrate 100, and the doping concentration of the drift layer 110 is lower than that of the semiconductor substrate 100. In one embodiment, the drift layer is made of silicon carbide doped with N-type conductive ions. The N-type conductive ions can be phosphorus ions or nitrogen ions.

[0038] The conductivity type of the well region 140 is opposite to that of the drift layer 110. In this embodiment, when the conductivity type of the drift layer 110 is N-type, the conductivity type of the well region 140 is P-type.

[0039] In this embodiment, the semiconductor power device further includes: a source region 150 located in the well region 140, wherein the conductivity type of the source region 150 is opposite to that of the well region 140. In this embodiment, when the conductivity type of the well region 140 is P-type, the conductivity type of the source region 150 is N-type; and an ohmic contact region 160 located in the well region 140 and in contact with the source region 150. The ohmic contact region 160 has the same conductivity type as the well region 140, and the doping concentration of the ohmic contact region 160 is greater than that of the well region 140.

[0040] In this embodiment, the gate structure 170 covers the drift layer 110 between adjacent well regions 140 and a portion of the surface of the adjacent well regions 140. The gate structure 170 includes a gate dielectric layer 171 and a gate electrode layer 172, with the gate electrode layer 172 located on the gate dielectric layer 171. The gate dielectric layer 171 is made of silicon oxide, and the gate electrode layer 172 is made of polysilicon. The well regions 140 are located in the drift layers 110 on both sides of the width direction of the gate structure 170.

[0041] In this embodiment, the semiconductor power device further includes: a front electrode 190, which contacts the source region 150 and, more specifically, an ohmic contact region 160; and an isolation dielectric layer 180, surrounding the side and top surfaces of the gate electrode layer 172. The front electrode 190 covers the gate structure 170, and the isolation dielectric layer 180 isolates the front electrode 190 and the gate electrode layer 172. The material of the isolation dielectric layer 180 includes silicon oxide. In this embodiment, a drain electrode layer 101 is also included, located on the side surface of the semiconductor substrate layer 100 facing away from the drift layer 110.

[0042] When the gate structure 170 is turned off and the potential of the source region 150 is greater than that of the drain electrode layer 101, the channel almost no longer conducts current. The PN junction formed by the well region 140 and the second pillar region 120 at the bottom of the well region 140 is turned on. The PN junction formed by the ohmic contact region 160 and the second pillar region 120 at the bottom of the ohmic contact region 160 is turned on. The PN junction formed by the well region 140 and the second sub-region 131 at the bottom of the well region 140 is turned on. This allows electrons from the second sub-region and the second pillar region to be injected into the first region 132, and holes from the first region to be injected into the second sub-region 131 and the second pillar region 120. The reverse recovery includes a first recovery stage and a second recovery stage performed sequentially. In the first recovery stage, electrons in the first region 132 are extracted into the second sub-region 131 and the second pillar region 120, and holes in the second sub-region 131 and the second pillar region 120 are extracted into the first region 132. The second recovery stage requires recovery to the reverse withstand voltage state. In the second recovery stage, holes in the first region 132 are extracted to the front electrode 190 through the well region 140 and the ohmic contact region 160, and electrons in the second sub-region 131 and the second pillar region 120 are extracted to the drain electrode layer 101. In the second recovery stage, the second sub-region 131 blocks the transmission of holes from the first region 132 to the front electrode 190, forming a potential barrier. The holes in the first region 132 below the second sub-region 131 need to pass through the second sub-region 131 to reach the first region 132 above the second sub-region 131, which makes the second recovery stage slower and longer, reduces dV / dt, reduces the peak voltage of the reverse recovery process, improves the reverse recovery performance of the semiconductor power device, and increases the softness factor.

[0043] In one embodiment, the first region 132 has a P-type conductivity, the second sub-region 131 has an N-type conductivity, and the second pillar region 120 has an N-type conductivity.

[0044] In one embodiment, the doping concentration of the first region 132 is less than the doping concentration of the well region 140.

[0045] In one embodiment, the doping concentration of the first region is 2E16atom / cm. 3 ~7E16 atom / cm 3 The doping concentration of well region 140 is 9E16 atom / cm³. 3 ~2E17 atom / cm 3 .

[0046] In one embodiment, the doping concentration of the first region 132 is greater than the doping concentration of the second sub-region 131 and also greater than the doping concentration of the second pillar region 120. This is because when the volumes of the second sub-region 131 and the second pillar region 120 are larger than the volume of the first region, the charge balance is better, resulting in better reverse breakdown voltage performance. In other embodiments, there are no limitations on the doping concentrations of the first region, the second sub-region, and the second pillar region.

[0047] In one embodiment, the doping concentration of the second sub-region 131 is the same as that of the drift layer 110, and the doping concentration of the second pillar region 120 is the same as that of the drift layer 110.

[0048] In other embodiments, the doping concentration of the second sub-region 131 is greater than the doping concentration of the drift layer 110, and the doping concentration of the second pillar region is greater than the doping concentration of the drift layer 110.

[0049] In other embodiments, there are no restrictions on the concentration relationship between the doping concentration of the second sub-region 131, the drift layer 110, and the doping concentration of the second pillar region.

[0050] In this embodiment, the distance between the bottom surface of the first region 132 and the top surface of the semiconductor substrate 100 is greater than zero. In other embodiments, the distance between the bottom surface of the first region 132 and the top surface of the semiconductor substrate 100 is zero.

[0051] In this embodiment, each layer of the second region in any first pillar region 130 includes a plurality of second sub-regions 131 extending along the length direction of the gate structure 170, and the plurality of second sub-regions 131 in the second region are arranged at intervals along the channel length direction. In other embodiments, each layer of the second region in any first pillar region includes a second sub-region extending along the length direction of the gate structure.

[0052] In this embodiment, the second sub-regions 131 of the second regions in adjacent layers of any first pillar region 130 are staggered along the channel length direction. This has the advantage of increasing the degree to which the second sub-regions 131 block the transmission of holes from the first region 132 to the front electrode 190. Furthermore, the orthographic projection patterns of the second sub-regions 131 of the second regions in adjacent layers of any first pillar region 130 partially overlap on the surface of the semiconductor substrate layer 100. This further increases the degree to which the second sub-regions 131 block the transmission of holes from the first region 132 to the front electrode 190. In other embodiments, the orthographic projection patterns of the second sub-regions 131 of the second regions in adjacent layers of any first pillar region 130 do not overlap on the surface of the semiconductor substrate layer.

[0053] In other embodiments, the second sub-regions in the second regions of adjacent layers in any first pillar region 130 are arranged in a direction perpendicular to the surface of the semiconductor substrate layer 100.

[0054] In one embodiment, the dimension of the second sub-region 131 along the channel length direction is larger than the dimension along the direction perpendicular to the surface of the semiconductor substrate 100. The advantage is that, during the second recovery phase, the second sub-region 131 is more effective at blocking the transport of holes from the first region 132 to the front electrode.

[0055] In other embodiments, the dimension of the second sub-region along the channel length direction is less than or equal to the dimension along the direction perpendicular to the surface of the semiconductor substrate layer.

[0056] In one embodiment, the cross-sectional pattern of the second sub-region 131 along the length direction perpendicular to the gate structure is a characteristic pattern, which is a circle, ellipse, rectangle, or square; or, referring to Figure 3 The feature pattern includes a main pattern 1301 and sub-patterns 1302 located on both sides of the main pattern 1301 along the length of the channel. The main pattern 1301 is rectangular, and the sub-patterns 1302 have feature edges 1303 protruding from the main pattern 1301 in a direction parallel to the length of the channel. The two ends of the feature edges 1303 are connected to the main pattern 1301.

[0057] In this embodiment, the length extension direction of the gate structure is parallel to the first direction Z, and the length direction of the channel is parallel to the second direction X.

[0058] Another embodiment of the present invention provides a method for fabricating a semiconductor power device, comprising: providing a semiconductor substrate layer; forming a drift layer on the semiconductor substrate layer, wherein during the formation of the drift layer, a plurality of first pillar regions arranged at intervals along a first direction are formed in the drift layer, and the drift layer between adjacent first pillar regions serves as a second pillar region; the first pillar region includes a first region and a plurality of second regions arranged along a direction perpendicular to the surface of the semiconductor substrate layer, the second regions of adjacent layers are spaced apart, each second region in any first pillar region includes a second sub-region extending along the first direction, the second sub-region is connected to the second pillar region, the first region surrounds the second sub-region, the conductivity type of the first region is opposite to the conductivity type of the second pillar region, and the conductivity type of the second region is the same as the conductivity type of the second pillar region; forming a well region in the drift layer; forming a gate structure extending along the first direction on the drift layer, the gate structure covering the drift layer between adjacent well regions and a portion of the surface of adjacent well regions; the first pillar region and the second pillar region both extend from below the well region on one side of the gate structure to below the well region on the other side of the gate structure.

[0059] The steps of forming the drift layer, the first pillar region, and the second pillar region include: forming a first epitaxial layer on the semiconductor substrate; forming a plurality of first doped regions arranged at intervals along a first direction in the first epitaxial layer, wherein the first epitaxial layer between adjacent first doped regions serves as a first connection region, and the conductivity type of the first connection region is opposite to that of the first doped region; forming a second epitaxial layer on the first doped region and the first connection region, wherein the second epitaxial layer located above and in contact with the first connection region serves as a second connection region, and the conductivity type of the second epitaxial layer is the same as that of the first epitaxial layer; forming a plurality of second doped regions in the second epitaxial layer on both sides of the second connection region along the first direction, wherein the second doped regions are located above a portion of the first doped regions; the plurality of second doped regions along any side of the second connection region along the first direction are arranged at intervals along a second direction, and the second epitaxial layer between adjacent second doped regions along the second direction serves as a second sub-region, wherein the second sub-region... The second doped region is connected to the second connection region, and the second direction intersects the first direction. The conductivity type of the second doped region is opposite to that of the second connection region. A third epitaxial layer is formed on the second connection region, the second sub-region, and the second doped region. The conductivity type of the third epitaxial layer is the same as that of the first epitaxial layer. Several third doped regions are formed in the third epitaxial layer at intervals along the first direction. The third doped regions are located above the second doped region and the second sub-region. The third epitaxial layer between adjacent third doped regions serves as a third connection region. The third connection region is located above the second connection region. The conductivity type of the third connection region is opposite to that of the third doped region. A top drift region is formed above the third doped region and the third connection region. The conductivity type of the top drift region is the same as that of the first epitaxial layer. The first connection region, the second connection region, and the third connection region constitute the second pillar region. The first doped region, the second doped region, and the third doped region constitute the first region.

[0060] The following is for reference. Figures 4 to 20 This document provides a detailed introduction to the fabrication process of semiconductor power devices.

[0061] refer to Figure 4 and Figure 5 , Figure 5 for Figure 4 A top view shows a semiconductor substrate 100; a first epitaxial layer 201 is formed on the semiconductor substrate.

[0062] In one embodiment, the conductivity type of the first epitaxial layer 201 is the same as that of the semiconductor substrate layer 100.

[0063] In this embodiment, the method further includes: before forming the first epitaxial layer 201, forming a bottom drift region 200 on the semiconductor substrate layer 100, wherein the conductivity type of the bottom drift region 200 is the same as that of the semiconductor substrate layer 100, and the doping concentration of the bottom drift region 200 is less than that of the semiconductor substrate layer 100.

[0064] In other embodiments, the bottom drift region 200 is not formed before the formation of the first epitaxial layer 201, and the first epitaxial layer is in contact with the semiconductor substrate layer.

[0065] refer to Figure 6 and Figure 7 , Figure 7 for Figure 6 Top view, Figure 6 In order to be in Figure 4 A basic diagram. Figure 7 In order to be in Figure 5 Based on the schematic diagram, a plurality of first doped regions 202 arranged along the first direction Z are formed in the first epitaxial layer 201 at intervals. The first epitaxial layer 201 between adjacent first doped regions 202 serves as a first connection region 203. The conductivity type of the first connection region 203 is opposite to that of the first doped region 202.

[0066] The conductivity type of the first connection region 203 is the same as that of the first epitaxial layer 201.

[0067] The process of forming a plurality of first doped regions 202 arranged along the first direction Z in the first epitaxial layer 201 at intervals is an ion implantation process.

[0068] refer to Figure 8 and Figure 9 , Figure 9 for Figure 8 Top view, Figure 8 In order to be in Figure 6 A basic diagram. Figure 9 In order to be in Figure 7 The schematic diagram shows that a second epitaxial layer 204 is formed on the first doped region 202 and the first connection region 203. The second epitaxial layer 204, located above and in contact with the first connection region 203, serves as the second connection region 205. The conductivity type of the second epitaxial layer 204 is the same as that of the first epitaxial layer 201.

[0069] refer to Figure 10 and Figure 11 , Figure 11 for Figure 10 Top view, Figure 10 In order to be in Figure 8 A basic diagram. Figure 11 In order to be in Figure 9Based on the schematic diagram, a plurality of second doped regions 206 are formed in the second epitaxial layers 204 on both sides of the second connection region 205 along the first direction Z. The second doped regions 206 are located above a portion of the first doped regions 202. The plurality of second doped regions 206 on any side of the second connection region 205 along the first direction Z are arranged at intervals along the second direction X. The second epitaxial layer 204 between adjacent second doped regions 206 along the second direction X serves as a second sub-region 207. The second sub-region 207 is connected to the second connection region 205. The second direction X intersects the first direction. The conductivity type of the second doped regions 206 is opposite to that of the second connection region 205.

[0070] In one embodiment, the second direction X is perpendicular to the first direction Z.

[0071] The process of forming a plurality of second doped regions 206 in the second epitaxial layer 204 on both sides of the second connection region 205 along the first direction Z includes an ion implantation process.

[0072] refer to Figure 12 and Figure 13 , Figure 13 for Figure 12 Top view, Figure 12 In order to be in Figure 10 A basic diagram. Figure 13 In order to be in Figure 11 Based on the schematic diagram, the steps of forming the first epitaxial layer 201, forming the first doped region 202, forming the second epitaxial layer 204, and forming the second doped region 206 are repeated.

[0073] refer to Figure 14 and Figure 15 , Figure 15 for Figure 14 Top view, Figure 14 In order to be in Figure 12 A basic diagram. Figure 15 In order to be in Figure 13 Based on the schematic diagram, a third epitaxial layer 208 is formed on the second connection region 205, the second sub-region 207, and the second doped region 206. The conductivity type of the third epitaxial layer 208 is the same as that of the first epitaxial layer 201.

[0074] refer to Figure 16 and Figure 17 , Figure 17 for Figure 16 Top view, Figure 16 In order to be in Figure 14 A basic diagram. Figure 17 In order to be in Figure 15Based on the schematic diagram, a plurality of third doped regions 209 arranged along the first direction Z are formed in the third epitaxial layer 208. The third doped regions 209 are located above the second doped region 206 and the second sub-region 207. The third epitaxial layer 208 between adjacent third doped regions 209 serves as a third connection region 210. The third connection region 210 is located above the second connection region 205. The conductivity type of the third connection region 210 is opposite to that of the third doped region 209.

[0075] The process of forming a plurality of spaced third doped regions 209 arranged along the first direction Z in the third epitaxial layer 208 includes an ion implantation process.

[0076] The first connection region 203, the second connection region 205, and the third connection region 210 constitute the second pillar region; the first doped region 202, the second doped region 206, and the third doped region 209 constitute the first region. The first region and the second sub-region 207 located on any side of the second pillar region along the first direction Z constitute the first pillar region.

[0077] In this embodiment, the second doped regions of adjacent layers on either side of the second pillar region are staggered along the second direction. Correspondingly, the second sub-regions of the second regions of adjacent layers in any first pillar region are staggered along the channel length direction. The orthographic projection patterns of the second sub-regions of the second regions of adjacent layers on the semiconductor substrate surface partially overlap; or, the orthographic projection patterns of the second sub-regions of the second regions of adjacent layers on the semiconductor substrate surface do not overlap.

[0078] In other embodiments, the second doped regions of adjacent layers on either side of the second pillar region are arranged in a direction perpendicular to the surface of the semiconductor substrate layer, and correspondingly, the second sub-regions of the second regions of adjacent layers in any first pillar region are arranged in a direction perpendicular to the surface of the semiconductor substrate layer.

[0079] refer to Figure 18 , Figure 18 In order to be in Figure 16 Based on the schematic diagram, a top drift region 211 is formed above the third doped region 209 and the third connection region 210. The conductivity type of the top drift region 211 is the same as that of the first epitaxial layer.

[0080] In this embodiment, after repeating the steps of forming the first epitaxial layer, forming the first doped region, forming the second epitaxial layer, and forming the second doped region, the third epitaxial layer is formed. In other embodiments, it is not necessary to repeat the steps of forming the first epitaxial layer, forming the first doped region, forming the second epitaxial layer, and forming the second doped region before forming the third epitaxial layer.

[0081] refer to Figure 19 , Figure 19 In order to be in Figure 18The schematic diagram shows that a trap region 140 is formed in the drift layer 110. Specifically, the trap region 140 is formed in the top drift region 211.

[0082] In this embodiment, the method further includes: forming a source region 150 in the well region 140; forming an ohmic contact region 160 in the well region 140, wherein the ohmic contact region 160 contacts the sidewall of the source region 150.

[0083] In this embodiment, the process further includes: after forming the source region 150 and the ohmic contact region 160, an annealing process is performed.

[0084] Continue to refer to Figure 19 and Figure 20 , Figure 20 for Figure 19 The corresponding three-dimensional structural diagram shows that a gate structure 170 extending along a first direction is formed on the drift layer. The gate structure 170 covers the drift layer between adjacent well regions 140 and a portion of the surface of the adjacent well regions 140. Both the first pillar region and the second pillar region extend from below the well region on one side of the gate structure to below the well region on the other side of the gate structure. The gate structure 170 includes a gate electrode layer 172 and a gate dielectric layer 171.

[0085] This embodiment further includes: forming an isolation dielectric layer 180, which surrounds the side surface and top surface of the gate electrode layer 172; forming a front electrode 190, which contacts the source region 150 and, further, contacts the ohmic contact region 160; the front electrode 190 covers the gate structure 170, and the isolation dielectric layer 180 isolates the front electrode 190 and the gate electrode layer 172. The material of the isolation dielectric layer 180 includes silicon oxide. This embodiment also includes: forming a drain electrode layer 101 on the side surface of the semiconductor substrate layer 100 opposite to the drift layer 110.

[0086] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A semiconductor power device, characterized in that, include: Semiconductor substrate layer; A drift layer located on a semiconductor substrate; Gate structure located on part of the drift layer; The well regions are located in the drift layers on both sides of the gate structure and extend to the bottom of the gate structure portion. The drift layer comprises several spaced first pillar regions arranged along the extension direction of the gate structure; the drift layer between adjacent first pillar regions serves as a second pillar region; both the first pillar region and the second pillar region extend from below the well region on one side of the gate structure to below the well region on the other side of the gate structure; the first pillar region includes a first region and several layers of second regions arranged along a direction perpendicular to the surface of the semiconductor substrate layer, with adjacent layers of second regions spaced apart, each layer of second region in any first pillar region includes a second sub-region extending along the length direction of the gate structure, the second sub-region being connected to the second pillar region, the first region surrounding the second sub-region, the second sub-regions in adjacent layers of second regions in any first pillar region being staggered along the channel length direction, the conductivity type of the first region being opposite to that of the second pillar region, and the conductivity type of the second region being the same as that of the second pillar region.

2. The semiconductor power device according to claim 1, characterized in that, Each layer of the second region in any first pillar region includes a plurality of second sub-regions extending along the length direction of the gate structure, and the plurality of second sub-regions in the second region are arranged at intervals along the length direction of the channel.

3. The semiconductor power device according to claim 1, characterized in that, The orthographic projection patterns of the second sub-regions in the second region of any adjacent layer in the first pillar region partially overlap on the surface of the semiconductor substrate; or, the orthographic projection patterns of the second sub-regions in the second region of any adjacent layer in the first pillar region do not overlap on the surface of the semiconductor substrate.

4. The semiconductor power device according to claim 1, characterized in that, The dimension of the second sub-region along the channel length direction is greater than the dimension along the direction perpendicular to the surface of the semiconductor substrate.

5. The semiconductor power device according to claim 1, characterized in that, The cross-sectional pattern of the second sub-region along the length direction perpendicular to the gate structure is a feature pattern, which is a circle, ellipse, rectangle or square; or, the feature pattern includes a main pattern and sub-patterns located on both sides of the main pattern along the channel length direction, the main pattern is a rectangle, and the sub-patterns have feature edges protruding away from the main pattern in the direction parallel to the channel length direction, and the two ends of the feature edges are connected to the main pattern.

6. The semiconductor power device according to claim 1, characterized in that, Also includes: The source region is located within the well region; An ohmic contact region is located in the well region and in contact with the source region, and the ohmic contact region has the same conductivity type as the well region.

7. A method for fabricating a semiconductor power device, characterized in that, include: Provide semiconductor substrate layer; A drift layer is formed on the semiconductor substrate. During the formation of the drift layer, a plurality of first pillar regions arranged at intervals along a first direction are formed in the drift layer. The drift layer between adjacent first pillar regions serves as a second pillar region. The first pillar region includes a first region and a plurality of second regions arranged along a direction perpendicular to the surface of the semiconductor substrate. The second regions of adjacent layers are spaced apart. Each second region in any first pillar region includes a second sub-region extending along the first direction. The second sub-region is connected to the second pillar region. The first region surrounds the second sub-region. The second sub-regions of the second regions of adjacent layers in any first pillar region are staggered along the channel length direction. The conductivity type of the first region is opposite to that of the second pillar region, and the conductivity type of the second region is the same as that of the second pillar region. A trap region is formed in the drift layer; A gate structure extending in a first direction is formed on the drift layer, the gate structure covering the drift layer between adjacent well regions and a portion of the surface of adjacent well regions; both the first pillar region and the second pillar region extend from below the well region on one side of the gate structure to below the well region on the other side of the gate structure.

8. The method for fabricating a semiconductor power device according to claim 7, characterized in that, The steps of forming the drift layer, the first pillar region, and the second pillar region include: forming a first epitaxial layer on the semiconductor substrate; forming a plurality of first doped regions arranged at intervals along a first direction in the first epitaxial layer, wherein the first epitaxial layer between adjacent first doped regions serves as a first connection region, and the conductivity type of the first connection region is opposite to that of the first doped region; forming a second epitaxial layer on the first doped region and the first connection region, wherein the second epitaxial layer located above and in contact with the first connection region serves as a second connection region, and the conductivity type of the second epitaxial layer is the same as that of the first epitaxial layer; forming a plurality of second doped regions in the second epitaxial layer on both sides of the second connection region along the first direction, wherein the second doped regions are located above a portion of the first doped regions; the plurality of second doped regions along any side of the second connection region along the first direction are arranged at intervals along a second direction, and the second epitaxial layer between adjacent second doped regions along the second direction serves as a second sub-region, wherein the second sub-region... The second doped region is connected to the second connection region, and the second direction intersects the first direction. The conductivity type of the second doped region is opposite to that of the second connection region. A third epitaxial layer is formed on the second connection region, the second sub-region, and the second doped region. The conductivity type of the third epitaxial layer is the same as that of the first epitaxial layer. Several third doped regions are formed in the third epitaxial layer at intervals along the first direction. The third doped regions are located above the second doped region and the second sub-region. The third epitaxial layer between adjacent third doped regions serves as a third connection region. The third connection region is located above the second connection region, and the conductivity type of the third connection region is opposite to that of the third doped region. A top drift region is formed above the third doped region and the third connection region. The conductivity type of the top drift region is the same as that of the first epitaxial layer. The first connection region, the second connection region, and the third connection region constitute the second pillar region. The first doped region, the second doped region, and the third doped region constitute the first region. The step of forming a trap region in the drift layer is as follows: forming a trap region in the top drift region.

9. The method for fabricating a semiconductor power device according to claim 8, characterized in that, Also includes: A source region is formed in the well region; after the source region is formed, an annealing process is performed.

10. The method for fabricating a semiconductor power device according to claim 8, characterized in that, Also includes: Before forming the third epitaxial layer, the steps of forming the first epitaxial layer, forming the first doped region, forming the second epitaxial layer, and forming the second doped region are repeated.

11. The method for fabricating a semiconductor power device according to claim 10, characterized in that, The second doped regions of the adjacent layers on either side of the second column region are offset along the second direction.

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