Micro light emitting element and micro display device thereof

Abstract

The application discloses a micro light emitting element and a micro display device thereof, comprising a semiconductor layer sequence, a first electrode and a second electrode, the semiconductor layer sequence has a first semiconductor layer, a second semiconductor layer and an active layer between the two, the first electrode is electrically connected with the first semiconductor layer, the second electrode is electrically connected with the second semiconductor layer, an insulating layer is arranged on the sidewall of the semiconductor layer sequence, the semiconductor layer sequence has a light emitting surface, the top of the insulating layer, the top of the semiconductor layer sequence and the light emitting surface are in the same level, and the influence of the edge of the insulating layer on the light emitting performance is reduced in the display unit with an ultra-small size.

Description

Technical Field

[0001] This application relates to the field of semiconductor display technology, and more specifically to micro light-emitting elements and display devices thereof. Background Technology

[0002] Among the existing display solutions used in the augmented reality (AR) field, LEDoS (MicroLED on Silicon) has attracted widespread attention due to its high brightness, high PPI, and long lifespan, and is known in the industry as the "ultimate display solution".

[0003] Currently, MicroLEDs on LEDoS are mainly fabricated using a vertical electrode structure, with a typical pixel pitch of <10um and pixel size of <5um. They are generally fabricated by transferring the entire epitaxial surface to CMOS, and then performing chip fabrication after the epitaxial transfer to reduce the difficulty of the process.

[0004] Improving the luminous efficacy of micro-light-emitting elements has become a major technical challenge of concern in the industry. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a micro-light-emitting element, comprising a semiconductor layer sequence, a first electrode, and a second electrode. The semiconductor layer sequence has a first semiconductor layer, a second semiconductor layer, and an active layer between them. The first electrode and the first semiconductor layer are electrically connected, and the second electrode and the second semiconductor layer are electrically connected. An insulating layer is disposed on the sidewall of the semiconductor layer sequence, and the height difference between the top of the insulating layer and the top of the semiconductor layer sequence is within ±0.2 micrometers to avoid the insulating layer from adversely affecting the light efficiency of the micro-light-emitting element.

[0006] The technical effects of this application include improving the overall light efficiency through the layer design of the micro-light-emitting elements. Attached Figure Description

[0007] Figure 1 This is a cross-sectional schematic diagram of a micro-light-emitting element in the prior art;

[0008] Figures 2-5 This is a cross-sectional schematic diagram of the micro-light-emitting element in Embodiments 1 and 2 of this application;

[0009] Figure 6 This is a cross-sectional schematic diagram of the micro-light-emitting element in Embodiment 2 of this application;

[0010] Figure 7 and Figure 8 This is a partially enlarged schematic diagram of the top of the insulating layer in the micro-light-emitting element of Embodiment 2 of this application;

[0011] Figure 9 This is a cross-sectional schematic diagram of the micro-light-emitting element in Embodiment 3 of this application;

[0012] Figure 10 This is a top view schematic diagram of the micro-display device in this application.

[0013] Explanation of reference numerals in the figures: 110, Semiconductor layer sequence; 111, First semiconductor layer; 112, Second semiconductor layer; 113, Active layer; 121, First electrode; 122, Second electrode; 130, Transparent conductive layer; 140, Metal reflective layer; 150, Metal barrier layer; 210, Insulating layer; 211, First portion of insulating layer; 212, Second portion of insulating layer; 310, Substrate; 311, Groove; 312, Conductive region; 320, Electrical connection layer; 330, Isolation trench; 410, Bonding layer; 510, Frame;

[0014] 110a, 111a, 112a, 210a, 311a, 410a, sidewalls; 110b, 111b, 210b, top surface; 210c, protrusion. Detailed Implementation

[0015] This application will be further described in detail with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0016] To enable those skilled in the art to better understand the technical solution of this application, this application provides a detailed explanation of the problems existing in the prior art.

[0017] See Figure 1 In the prior art, in micro-light-emitting elements, the insulating layer 210 extends from the sidewall 110a of the semiconductor layer sequence 110 to cover the top surface 110b. Due to process limitations, a protrusion 210c is typically formed on the surface of the top surface 110b, which adversely affects the light pattern and / or luminous efficiency. The top surface 110b of the semiconductor layer sequence 110 has a top-view area of ​​100 square micrometers to 500 square micrometers. The insulating layer 210 is a dielectric material such as silicon oxide, silicon nitride, aluminum oxide, or titanium oxide.

[0018] In some embodiments of this application, a micro-light-emitting element is provided, comprising a semiconductor layer sequence, a first electrode, and a second electrode. The semiconductor layer sequence has a first semiconductor layer, a second semiconductor layer, and an active layer between them. The first electrode and the first semiconductor layer are electrically connected, and the second electrode and the second semiconductor layer are electrically connected. An insulating layer is disposed on the sidewall of the semiconductor layer sequence. The semiconductor layer sequence has a light-emitting surface. The top of the insulating layer and the top of the semiconductor layer sequence are at the same height, and the height difference between the top of the insulating layer and the top of the semiconductor layer sequence is within ±0.2 micrometers to avoid affecting the light pattern and / or light efficiency. The micro-light-emitting element includes a micro-light-emitting diode.

[0019] In some embodiments of this application, the top of the semiconductor layer sequence is a first semiconductor layer, the material of the first semiconductor layer is gallium nitride-based, and the top of the insulating layer surrounds the top of the semiconductor layer sequence and goes around it.

[0020] In some embodiments of this application, the insulating layer is made of silicon oxide, silicon nitride, aluminum nitride, or titanium oxide.

[0021] In some embodiments of this application, the insulating layer includes a distributed Bragg reflector (DBR). This improves side light utilization.

[0022] In some embodiments of this application, a transparent conductive layer is disposed on top of the insulating layer and on top of the semiconductor layer sequence. The transparent conductive layer serves as a first electrode and extends from the top of the insulating layer to the top of the semiconductor layer sequence, thereby improving the continuity of the transparent conductive layer. The transparent conductive layer enhances light efficiency.

[0023] In some embodiments of this application, the size of the micro-light-emitting element, viewed from top view, is 0.5 micrometers to 10 micrometers, or 10 micrometers to 50 micrometers. The smaller the size, the greater the impact of the insulating layer on the light efficiency.

[0024] In some embodiments of this application, the semiconductor layer sequence has a light-emitting surface, and the height difference between the light-emitting surface and the top of the insulating layer is ±0.2 micrometers. Viewed from above, the light-emitting surface of the semiconductor layer sequence is completely disposed within the top of the insulating layer.

[0025] In some embodiments of this application, a substrate is also included, wherein a semiconductor layer sequence is disposed on the side away from the first semiconductor layer, serving to connect with the control circuit.

[0026] In some embodiments of this application, the second electrode is disposed between the substrate and the second semiconductor layer.

[0027] In some embodiments of this application, the insulating layer has a first opening when viewed from projection, the top of the insulating layer is the edge of the insulating layer and surrounds the first opening, and the area of ​​the first opening is 95% to 120% of the light-emitting surface area of ​​the semiconductor layer sequence, so as to minimize the influence of the edge of the insulating layer on the light emission.

[0028] In some embodiments of this application, the thickness of the insulating layer is 0.1 to 5 micrometers.

[0029] In some embodiments of this application, the insulating layer consists of two parts: one on the light-emitting surface and the other on the sidewall. The thickness of the insulating layer on the sidewall is greater than the thickness of the insulating layer on the light-emitting surface, and the thickness of the insulating layer on the light-emitting surface is no more than 0.5 micrometers. By limiting the thickness differently, the impact on the light emission effect is reduced.

[0030] In another aspect of this application, a micro-display device is also provided, including a bracket and a micro-light-emitting element as described above, with the bracket providing support for the micro-light-emitting element.

[0031] In the first embodiment of this application, a micro-light-emitting element structure and a method for fabricating the same are provided, comprising:

[0032] See Figure 2 Step 1: A micro-light-emitting element is provided, including a substrate 310 and a plurality of micro-light-emitting element units. Starting from the substrate 310 and from bottom to top, the micro-light-emitting element sequentially includes a second electrode 122 and a semiconductor layer sequence 110. The semiconductor layer sequence 110 consists of a first semiconductor layer 111, a second semiconductor layer 112 on the second electrode 122, and an active layer 113 between them. The second electrode 122 includes a metal reflective layer 140 and a metal blocking layer 150. The metal reflective layer 140 is, for example, silver or aluminum. The micro-light-emitting element is fixed to the substrate 310 by a bonding layer 410. The material of the bonding layer 410 includes gold, tin, a nickel-tin mixture, or a gold-tin mixture. The size of the micro-light-emitting element is 0.5 micrometers to 10 micrometers, or 10 micrometers to 50 micrometers.

[0033] The semiconductor layer sequence 110 can be formed on a growth substrate by means of metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD) or ion plating, and then bonded to the substrate 310 by substrate peeling and transfer technology.

[0034] The micro-light-emitting elements are electrically isolated from each other by isolation trenches 330 and / or insulating layers 210. The insulating layer 210 is made of silicon oxide, silicon nitride, aluminum nitride, or titanium oxide. The insulating layer 210 extends at least from the sidewall 112a of the second semiconductor layer 112 to the upper surface of the first semiconductor layer. Due to the manufacturing process, a ring of insulating layer 210 protrusions 210c is formed at the edge of the top surface 111b of the first semiconductor layer 111.

[0035] See Figure 3 Step 2 involves chemically or physically thinning one side of the first semiconductor layer 111, for example, by polishing to remove part or all of the protrusions 210c of the insulating layer 210. The top 210b of the insulating layer 210 and the top 110b of the semiconductor layer sequence 110 are at the same height, i.e., the height difference d between the top 210b of the insulating layer 210, the top 110b of the semiconductor layer sequence 110, and the light-emitting surface L is within ±0.2 micrometers. The top 210b of the insulating layer 210 surrounds the top 110b of the semiconductor layer sequence 110 and completes a full circumference.

[0036] See Figure 4 Step 3: A transparent conductive layer 130 is deposited on the surface of the micro-light-emitting element. The transparent conductive layer 130 extends at least from the top 110b of the semiconductor layer sequence 110 to the sidewall 210a of the insulating layer 210. The transparent conductive layer 130 serves as the first electrode 121 and makes electrical contact with the semiconductor layer sequence 110.

[0037] See Figure 5 Step 4: An electrical connection layer 320 is provided between the micro-light-emitting elements. The electrical connection layer 320 serves as a common electrode to provide current to the micro-light-emitting elements.

[0038] Continue reading Figure 5 and Figure 6In a second embodiment of this application, a micro-light-emitting element is disclosed, comprising a semiconductor layer sequence 110, a first electrode 121, and a second electrode 122. The semiconductor layer sequence 110 has a first semiconductor layer 111, a second semiconductor layer 112, and an active layer 113 between them. The first electrode 121 is electrically connected to the first semiconductor layer 111, and the second electrode 121 is electrically connected to the second semiconductor layer 112. An insulating layer 210 is disposed on a sidewall 110a of the semiconductor layer sequence 110. The semiconductor layer sequence 110 has a light-emitting surface. The top 210b of the insulating layer 210, the top 110b of the semiconductor layer sequence 110, and the light-emitting surface are at the same height, i.e., the height difference d between the top 210b of the insulating layer 210, the top 110b of the semiconductor layer sequence 110, and the light-emitting surface is within ±0.2 micrometers. The material of the insulating layer 210 includes silicon oxide, silicon nitride, aluminum nitride, or titanium oxide. A transparent conductive layer 130 is disposed on the top 210b of the insulating layer 210 and the top 110b of the semiconductor layer sequence 110. The transparent conductive layer 130 is a first electrode or a part of a first electrode, and the thickness of the transparent conductive layer 130 is from 10 angstroms to 10,000 angstroms. The transparent conductive layer 130 includes at least one of ITO, IZO, ZnO, AZO, IGZO, or any combination of these materials. The transparent conductive layer 130 extends from the top 210b of the insulating layer 210 to the top 110b of the semiconductor layer sequence 110. The thickness of the insulating layer 210 is from 0.1 to 5 micrometers. A groove 311 is disposed on the substrate 310 between the micro-light-emitting elements. The sidewalls of the micro-light-emitting elements are covered by the insulating layer 210 and extend into the groove 311. The groove 311 serves as a current blocking groove. The insulating layer 210 covers the groove 311, improving device reliability in the field of ultra-small pitch displays.

[0039] The insulating layer 210 contacts the groove 311, which has a depth greater than 100 nanometers and less than 1000 nanometers, improving the sealing properties of the insulating layer 210. The groove 311 has a V-shaped or U-shaped cross-section, and the insulating layer extends through the smooth sidewalls of the groove 311. The minimum spacing between the micro-light-emitting elements is 0.1 micrometers to 2 micrometers, improving the display pixel density. Maintaining smooth groove sidewalls helps improve the blocking properties of the insulating layer 210. Isolation grooves 330 are provided between the micro-light-emitting elements, and the groove 311 is disposed within the isolation grooves 330, for example, the groove 311 is located in the middle of adjacent micro-light-emitting elements.

[0040] The semiconductor layer sequence 110 has a sidewall 110a with an angle α between itself and the horizontal plane, the angle α being 30° to 90°. The insulating layer 210 also has an angle with the horizontal plane, the angle being 30° to 90°.

[0041] The top 110b of the semiconductor layer sequence 110 is the first semiconductor layer 111, and the material of the first semiconductor layer 111 is gallium nitride-based. The top 210b of the insulating layer 210 surrounds the top 110b of the semiconductor layer sequence 110 and completes a circumference. From a top view, the light-emitting surface of the semiconductor layer sequence 110 is completely disposed within the top 210b of the insulating layer 210.

[0042] Viewed from above, the size of the micro-light-emitting elements ranges from 0.5 micrometers to 10 micrometers, or from 10 micrometers to 50 micrometers.

[0043] The micro-light-emitting element also includes a substrate 310. The substrate 310 has a semiconductor layer sequence 110 disposed on the side away from the first semiconductor layer 111. A second electrode 122 and a bonding layer 410 are disposed between the second semiconductor layer 112 and the substrate 310. A conductive region 312 is disposed on the substrate 310. The semiconductor layer sequence 110 is electrically connected to the substrate 310 through the bonding layer 410 and the conductive region 312 on the substrate 310. In this embodiment, the first semiconductor layer 111 is an N-type semiconductor layer, the second semiconductor layer 112 is a P-type semiconductor layer, the first electrode 121 is an N-type electrode, and the second electrode 122 is a P-type electrode. The second electrode 122 includes a metal reflective layer 140 and a metal blocking layer 150. During use in display products, reliability is prone to decrease; therefore, the insulating layer 210 laying method of this embodiment is preferred.

[0044] The spacing between the bonding layers 410 between two adjacent micro-light-emitting elements is 0.1 micrometers to 2 micrometers, or 2 micrometers to 5 micrometers. In this embodiment's reliability design, reducing the spacing of the bonding layers 410 within the 0.1-2 micrometer range can improve display pixel density, but it also necessitates improving the reliability of the insulating layer 210. The bonding layer 410 is made of a metallic material.

[0045] The edge of the bonding layer 410 contacts the opening of the groove 311, and at the contact position, the sidewall 410a of the bonding layer 410 and the sidewall 311a of the groove 311 form a continuous surface. The difference in the tilt angle between the sidewall 410a of the bonding layer 410 and the sidewall 311a of the groove 311 about the horizontal plane is no greater than 20°, which improves the adhesion of the insulating layer 210 and avoids large-angle bends in the insulating layer 210 on the surface of the substrate 310. The substrate 310 is a metal oxide semiconductor substrate, a silicon-based liquid crystal substrate, or a thin-film transistor substrate.

[0046] Viewed from the projection, the insulating layer 210 has a first opening 211, the top 210b of the insulating layer 210 is the edge of the insulating layer 210 and surrounds the first opening 211, and the area of ​​the first opening 211 is 95% to 120% of the light-emitting surface area of ​​the semiconductor layer sequence 110.

[0047] See Figure 7 and Figure 8Due to limitations in process precision, it is difficult to ensure that the light-emitting surfaces of the insulating layer and the semiconductor layer sequence 110 are completely at the same height. In this embodiment, a height difference d within ±0.2 micrometers is sufficient to improve the light pattern to some extent. From an optical path perspective, light can be emitted directly from the top surface of the semiconductor layer sequence 110 of the micro-light-emitting element.

[0048] In some embodiments, the insulating layer 210 is disposed lower than the top of the semiconductor layer sequence 110 and lower than the light-emitting surface of the semiconductor layer sequence 110. The top 210b of the insulating layer 210 contacts the sidewall 111a of the first semiconductor layer 111 of the semiconductor layer sequence 110. The insulating layer 210 extends at least from the sidewall 112a of the second semiconductor layer 112 to the sidewall 111a of the first semiconductor layer 111.

[0049] See Figure 5 In the third embodiment of this application, the insulating layer 210 includes a distributed Bragg reflector (DBR), utilizing the reflective properties of the insulating layer 210 to reflect light originally emitted from the side back into the chip, thereby increasing the light intensity emitted from the front of the chip. The DBR in the insulating layer 210 extends from the sidewall of the first semiconductor layer to cover the bottom of the isolation trench 330.

[0050] See Figure 9 In the fourth embodiment of this application, the difference from other embodiments is that the insulating layer 210 consists of a first insulating layer 211 on the light-emitting surface and a second insulating layer 212 on the sidewall. The thickness of the sidewall insulating layer is greater than the thickness of the insulating layer on the light-emitting surface. For example, the thickness of the insulating layer on the light-emitting surface is 1.5 to 100 times the thickness of the insulating layer on the sidewall, and the thickness of the insulating layer on the light-emitting surface is no greater than 0.5 micrometers. For example, the DBR in the insulating layer 210 is only disposed on the sidewall of the semiconductor layer sequence, that is, the sidewall of the semiconductor layer sequence is covered with the first insulating layer and the second insulating layer (DBR). In this embodiment, the thickness of the second insulating layer 212 is 0.1 to 5 micrometers, and the second insulating layer 212 extends at least from the first semiconductor layer 111 to the bottom of the second semiconductor layer 112, which significantly reduces the thickness of the insulating layer 210 on the light-emitting surface.

[0051] In some embodiments of this example, the insulating layer 210 is a single layer of silicon oxide, aluminum oxide, or silicon nitride, and the DBR is a composite stacked material, such as a periodic stack of silicon dioxide and titanium dioxide.

[0052] See Figure 10In the fifth embodiment of this application, a micro-display device is provided, including a support 510 and micro-light-emitting elements as described in the above embodiments. Each micro-light-emitting element unit independently serves as a pixel of the micro-display device. An electrical connection layer 320 provides current to the micro-light-emitting elements. The micro-light-emitting elements are dispersedly disposed on the substrate 310, and each micro-light-emitting element constitutes a pixel. The micro-display device can be a micro-light-emitting element display (Micro LED Display).

[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A micro-light-emitting element, comprising a semiconductor layer sequence, a first electrode and a second electrode, and a substrate, wherein the semiconductor layer sequence has a first semiconductor layer, a second semiconductor layer and an active layer between them, the first electrode and the first semiconductor layer are electrically connected, the second electrode and the second semiconductor layer are electrically connected, the substrate is disposed on the side of the semiconductor layer sequence away from the first semiconductor layer, a groove is disposed on the substrate, and an insulating layer is disposed on the sidewall of the semiconductor layer sequence and extends into the groove, characterized in that: The top of the insulating layer is lower than the top of the semiconductor layer sequence, and the height difference between the top of the insulating layer and the top of the semiconductor layer sequence is within 0.2 micrometers.

2. The micro-light-emitting element according to claim 1, characterized in that: The top of the semiconductor layer sequence is the first semiconductor layer, which is made of gallium nitride. The top of the insulating layer surrounds the top of the semiconductor layer sequence and goes around it once.

3. The micro-light-emitting element according to claim 1, characterized in that: The insulating layer is made of materials such as silicon oxide, silicon nitride, aluminum nitride, or titanium oxide.

4. The micro-light-emitting element according to claim 1, characterized in that: The insulating layer includes a distributed Bragg reflector (DBR).

5. The micro-light-emitting element according to claim 1, characterized in that: A transparent conductive layer is disposed on top of the insulating layer and on top of the semiconductor layer sequence. The transparent conductive layer is a first electrode and extends from the top of the insulating layer to the top of the semiconductor layer sequence.

6. The micro-light-emitting element according to claim 1, characterized in that: Viewed from above, the size of the micro-light-emitting elements ranges from 0.5 micrometers to 10 micrometers, or from 10 micrometers to 50 micrometers.

7. The micro-light-emitting element according to claim 1, characterized in that: The semiconductor layer sequence has a light-emitting surface, and the height difference between the insulating layer and the light-emitting surface is within 0.2 micrometers. From a top view, the light-emitting surface of the semiconductor layer sequence is completely located inside the top of the insulating layer.

8. The micro-light-emitting element according to claim 1, characterized in that: The second electrode is disposed between the substrate and the second semiconductor layer.

9. The micro-light-emitting element according to claim 1, characterized in that: The thickness of the insulating layer is 0.1 to 5 micrometers.

10. A micro-display device, comprising a support, characterized in that: It also includes the micro-light-emitting element as described in any one of claims 1 to 9.

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