A CSP lamp bead packaging structure of embedded coplanar welding
By constructing a mutually compatible three-dimensional geometric structure between the metal substrate and the chip electrode to form a coplanar welding plane, the problems of insufficient welding area and difficult mounting in CSP technology are solved, and efficient and reliable CSP LED chip packaging is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- MLS CO LTD
- Filing Date
- 2025-08-13
- Publication Date
- 2026-06-23
Smart Images
Figure CN224402027U_ABST
Abstract
Description
[Technical Field]
[0002] This utility model relates to the field of semiconductor light-emitting device packaging technology, and in particular to a CSP lamp bead packaging structure with embedded coplanar bonding. [Background Technology]
[0004] With the rapid development of LED lighting and display technologies, the market has placed increasingly stringent demands on the miniaturization, high luminous efficiency, and high reliability of LED devices. Driven by this trend, CSP (chip-scale packaging) technology has emerged and is gradually becoming one of the mainstream technologies for high-performance LED devices. The core advantage of CSP technology lies in the fact that its package size is basically the same as the size of the chip itself, eliminating the need for traditional brackets and wire bonding, thereby achieving extremely high packaging density and excellent performance.
[0005] Among various CSP (Chip-on-Package) technologies, the flip-chip structure is highly favored due to its unique advantages. Flip-chips place both their P and N electrodes on the same side of the chip and connect them directly to the substrate via solder bumps, eliminating the need for electrical interconnects via gold wires. This structure not only fundamentally eliminates the light obstruction and potential breakage risks associated with gold wires, but more importantly, it provides the chip with an extremely short and efficient heat dissipation path. This allows heat generated by the light-emitting layer to be rapidly conducted away directly through the electrodes and solder joints, significantly improving the device's heat dissipation performance and long-term operational reliability.
[0006] However, despite the enormous potential of flip-chip CSP technology, a serious technological bottleneck has become increasingly apparent in its evolution towards smaller sizes (such as Mini-LED and even Micro-LED), hindering its mass production. As the size of LED chips shrinks to the micrometer level, the area of their P / N electrodes also decreases dramatically. This directly leads to the following series of technical challenges:
[0007] 1. Insufficient welding area and poor reliability. The tiny electrodes provide extremely limited contact area for subsequent surface mount soldering processes. Traditional planar-to-planar soldering methods, at this microscopic scale, not only result in solder joints with low mechanical strength but also require extremely stringent control of the process window. Even minor imperfections can lead to cold solder joints or open circuits, posing a significant challenge to the long-term reliability of the final product.
[0008] 2. The mounting and positioning accuracy requirements are extremely high, resulting in low production yield. Precisely picking up chips, each only tens to hundreds of micrometers in size, and placing them onto corresponding tiny pads on a substrate using automated equipment is an extremely challenging task. Any minute misalignment can lead to electrode misalignment with the pad, causing soldering failure. This extreme reliance on precision directly results in low production efficiency and low product yield throughout the packaging process, significantly increasing manufacturing costs.
[0009] 3. Poor pre-soldering stability and easy displacement. Before the chip is placed and enters the reflow oven for soldering, the tiny chip is only attached to the substrate by the adhesiveness of the solder paste. During the transfer and heat treatment process on the production line, the chip is very prone to slight displacement, rotation, or even tilting. These uncertain positional deviations are one of the main reasons for poor final soldering quality and high product failure rate. [Utility Model Content]
[0011] The purpose of this invention is to provide an embedded coplanar soldering CSP LED chip packaging structure, which aims to solve the technical problems in the prior art such as insufficient soldering area, difficult mounting, poor pre-soldering stability, and consequently low production yield and poor long-term reliability caused by chip miniaturization.
[0012] This utility model is achieved through the following technical solution:
[0013] An embedded coplanar soldering CSP LED chip package structure includes:
[0014] Metal substrate;
[0015] An LED chip, wherein the LED chip has a first electrode and a second electrode;
[0016] The metal substrate has a mutually compatible three-dimensional geometric structure with the first electrode and the second electrode, such that the first electrode and the second electrode form a docking structure with the metal substrate through the compatible three-dimensional geometric structure, and the bottom surface of the first electrode, the bottom surface of the second electrode and the bottom surface of the metal substrate together form a coplanar welding plane.
[0017] As described above, the embedded coplanar soldering CSP LED chip packaging structure includes a docking structure with docking holes on the metal substrate corresponding to the first electrode and the second electrode, wherein both the first electrode and the second electrode are stepped electrodes.
[0018] In the embedded coplanar soldered CSP LED chip package structure described above, the stepped electrode includes:
[0019] An electrode base, which is disposed on the LED chip; and
[0020] A stepped portion extends from the electrode base and has a thickness greater than that of the electrode base;
[0021] The stepped portion is embedded in the corresponding mating hole.
[0022] In the embedded coplanar soldering CSP LED chip package structure described above, the size of the mating hole is larger than the size of the step portion, so as to form a gap for accommodating solder between the sidewall of the mating hole and the sidewall of the step portion.
[0023] In the embedded coplanar soldered CSP LED chip packaging structure described above, the thickness of the electrode base is 0.42 μm to 1.22 μm, and the thickness of the stepped portion is 3.42 μm to 121.32 μm.
[0024] As described above, the embedded coplanar soldered CSP LED chip packaging structure consists of, from bottom to top, a chromium layer of 50-150 nm, an aluminum layer of 100-300 nm, a chromium layer of 50-150 nm, a platinum layer of 20-50 nm, and a top copper layer of 200-600 nm.
[0025] As described above, the embedded coplanar soldered CSP LED chip packaging structure consists of, from bottom to top, a chromium layer of 50-150 nm, an aluminum layer of 100-300 nm, a titanium layer of 30-50 nm, a nickel layer of 80-120 nm, a titanium layer of 30-50 nm, a platinum layer of 20-50 nm, and a top copper layer of 200-600 nm.
[0026] As described above, in the embedded coplanar soldered CSP LED chip packaging structure, the stepped portion is composed of the electrode base and a copper layer further deposited on the top copper layer of the electrode base. The total thickness of the final copper layer formed by the further deposited copper layer and the top copper layer is 3000nm to 120μm.
[0027] The embedded coplanar soldered CSP LED chip packaging structure described above further includes an encapsulating adhesive layer, which covers the upper surface of the LED chip and the metal substrate.
[0028] In the embedded coplanar soldered CSP lamp bead packaging structure described above, the LED chip 2 is a flip chip.
[0029] Compared with the prior art, the present invention has the following advantages:
[0030] 1. This invention cleverly combines the bottom surface of the tiny electrodes (originally part of the chip) with the bottom surface of the external metal substrate by constructing a mutually compatible three-dimensional docking structure between the metal substrate and the chip electrodes. This forms a unified, coplanar welding plane with an area far larger than that of traditional electrodes. This fundamentally solves the problem of insufficient welding area caused by chip miniaturization, resulting in solder joints with higher mechanical strength and more uniform current distribution, thereby significantly improving the long-term operational reliability of the product.
[0031] 2. The aforementioned three-dimensional geometric structure, such as the fit between the stepped portion and the mating hole, provides a physical self-alignment and self-locking function during automated placement. This not only significantly reduces the stringent requirements for the absolute positioning accuracy of the die bonding equipment, but also provides a stable mechanical support for the chip before soldering, effectively preventing positional shifts during production line transfer and heat treatment. This effectively solves the core pain points of difficult microchip placement and low yield in existing technologies.
[0032] 3. The packaging structure of this invention is perfectly compatible with flip-chip technology. The heat generated by the light-emitting layer can be efficiently conducted away through the wide coplanar bonding plane via the shortest path, resulting in better heat dissipation performance than traditional structures. Simultaneously, the gold-wire-free structure maximizes the effective light-emitting area, improving light extraction efficiency, and enabling the final product to possess both high luminous efficacy and long lifespan. [Attached Image Description]
[0034] To more clearly illustrate the technical solutions in the embodiments of the utility model, the accompanying drawings used in the description of the embodiments will be briefly introduced below.
[0035] Figure 1 This is a three-dimensional structural diagram of Example 1 viewed from below;
[0036] Figure 2 for Figure 1 A perspective structural diagram;
[0037] Figure 3 This is a top view of Example 1;
[0038] Figure 4 This is a schematic diagram of the exploded structure of Example 1;
[0039] Figure 5 for Figure 3 A sectional view along line AA.
[0040] Figure 6 This is a front view of the LED chip in Example 1;
[0041] Figure 7 This is a front view of the stepped electrode in Example 1;
[0042] Figure 8 This is a schematic diagram of the LED chip arrangement during step S1 of Example 5;
[0043] Figure 9 This is a schematic diagram of the array-type metal substrate structure in step S2 of Example 5;
[0044] Figure 10 This is a schematic diagram of the connection between the array-type metal substrate and the temporary support substrate in step S3 of embodiment 5.
[0045] Figure 11 This is a schematic diagram of the structure after the LED chip mounting and docking is completed in step S4 of Example 5;
[0046] Figure 12 This is a schematic diagram of the structure after the LED chip encapsulation adhesive layer is set in step S5 of Example 5;
[0047] Figure 13 This is a schematic diagram of step S6 in Example 5, in which the entire array of metal substrates with the encapsulation layer already formed is cut into individual CSP LEDs.
Detailed Implementation Methods
[0049] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0050] Example 1:
[0051] This embodiment provides an embedded coplanar soldering CSP LED chip packaging structure, which aims to solve the technical problems of low production yield and poor reliability caused by the small soldering area and difficult surface mount of existing CSP LED chips.
[0052] Please see the appendix Figures 1 to 7 The core of the CSP LED chip packaging structure in this embodiment lies in a metal substrate 1 and an LED chip 2 disposed within the structure. The LED chip 2 has a first electrode 21 and a second electrode 22 spaced apart from each other. The key aspect of this embodiment is that the metal substrate 1 and the first electrode 21 and second electrode 22 of the LED chip 2 have a specially designed, mutually compatible three-dimensional geometric structure. Through this ingenious structure, the first electrode 21 and the second electrode 22 can each form a stable docking structure 3 with the metal substrate 1. The final result of this docking is that the bottom surfaces of the first electrode 21, the second electrode 22, and the metal substrate 1 together form a flat, substantially coplanar welding plane. The formation of this coplanar welding plane greatly increases the total area available for welding, allowing the solder to simultaneously and uniformly wet and connect the chip electrodes and the metal substrate in subsequent surface mount technology (SMT) processes, thereby significantly improving the reliability and strength of the welding.
[0053] Furthermore, as a preferred embodiment, the mutually adaptable three-dimensional geometric structure and the formed docking structure 3 are specifically implemented as follows: docking holes 31 corresponding to the positions of the first electrode 21 and the second electrode 22 are pre-set on the metal substrate 1; at the same time, the first electrode 21 and the second electrode 22 are both designed as stepped electrodes with special morphology.
[0054] More specifically, the stepped electrode comprises two main parts: a relatively thin electrode base 211 directly disposed on the LED chip 2; and a thicker stepped portion 212 integrally extending from the electrode base 211. This base-stepped structure brings several significant technical advantages. First, it greatly simplifies the mounting and positioning process of microchips. During automated assembly, the thicker stepped portion 212 can act as a physical self-aligning structure, guiding the chip to accurately fall into the corresponding mating hole 31 on the metal substrate 1, effectively solving the industry problem of micron-sized chips being difficult to position accurately and prone to displacement due to their small size.
[0055] Secondly, it provides excellent pre-soldering mechanical stability. When the step portion 212 is inserted into the mating hole 31, the interlocking relationship formed between the two provides a stable mechanical support for the chip before soldering, preventing the chip from shifting or tilting during subsequent transportation and heat treatment, thus laying a solid foundation for high-quality soldering.
[0056] Ultimately, it is through this ingenious embedded connection that the core concept of this embodiment—forming a coplanar welding plane—is realized. This structure not only fundamentally solves the problem of insufficient welding area in traditional CSP LED chips, but also directly improves the production yield of the entire packaging process and the reliability of the final product through the simplification of the process and the structural stability it brings.
[0057] Furthermore, to further improve the reliability of the soldering, as a preferred design, the lateral dimension of the mating hole 31 is designed to be slightly larger than the lateral dimension of the step portion 212. This way, when the step portion 212 is inserted into the mating hole 31, an annular gap 32 is naturally formed between the sidewall of the mating hole 31 and the sidewall of the step portion 212. Crucially, since the step portion 212 is located in the middle region of the chip, the sidewall of the step and the formed gap 32 in this region can be effectively prevented from being covered or contaminated by the encapsulant layer during the subsequent encapsulation layer application process. This characteristic ensures that when the CSP LED is finally mounted onto the external substrate, the solder can adhere easily and without obstruction to the clean metal surface, and partially fill and climb the gap 32 using capillary effect, thereby forming a solder joint on the sidewall of the electrode as well. This allows the metal sheet to easily connect to the chip, forming a robust electrical and mechanical connection. This method creates a three-dimensional solder joint that is far stronger than traditional planar soldering, greatly enhancing the package structure's resistance to mechanical stress and thermal shock.
[0058] In this embodiment, the dimensions of each core component have been carefully designed and optimized to achieve the unique embedded coplanar welding structure described above. As a preferred feasible solution, the thickness of the electrode base 211 is controlled within the range of 0.42 μm to 1.22 μm. This thickness range represents a delicate balance between conductivity, process stability, and cost. For example, in a specific embodiment, the thickness of the electrode base can be selected as 0.8 μm. If the thickness is less than 0.42 μm, it may affect the lateral spread of current within the base, leading to current congestion; conversely, if the thickness is greater than 1.22 μm, it will unnecessarily increase material costs and deposition time. Correspondingly, the thickness of the step portion 212 is controlled within the range of 3.42 μm to 121.32 μm. For example, in a specific embodiment, its thickness can be selected as 15 μm. This thickness needs to be sufficient to ensure that the step portion provides robust mechanical support and a sufficiently large sidewall area to form a reliable three-dimensional weld after being embedded in the mating hole, but not so thick as to impose excessive mechanical stress on the chip. It is these precisely calculated dimensions at the microscopic scale that ensure the feasibility of the packaging structure in this embodiment and its ultimate performance stability.
[0059] To achieve excellent adhesion, conductivity, and chemical stability of the electrode itself, the electrode base 211 is formed by stacking multiple layers of metal sequentially from bottom to top using a deposition or vapor deposition process. Here, "from bottom to top" means starting from the metal layer closest to the LED chip semiconductor layer and continuing to the outermost exposed metal layer.
[0060] As an optional implementation, the multilayer metal structure can be composed from bottom to top as follows: First, a 50-150nm chromium layer serves as an adhesion layer to ensure a strong bond between the entire electrode structure and the chip semiconductor layer; next, a 100-300nm aluminum layer serves as the main reflective and conductive layer to improve light extraction efficiency and conductivity; then, a 50-150nm chromium layer and a 20-50nm platinum layer serve as a barrier layer to provide excellent chemical stability and prevent diffusion reactions between the upper and lower metal layers; the outermost layer is a 200-600nm thick top copper layer, which is the base layer for subsequent step formation and welding.
[0061] As an alternative implementation, the multilayer metal structure can also be composed from bottom to top as follows: first, a chromium layer of 50-150nm and an aluminum layer of 100-300nm, followed by a titanium layer of 30-50nm, a nickel layer of 80-120nm, and another titanium layer of 30-50nm to form a stronger barrier layer system, which is used to further improve the reliability of the electrode at high temperatures; then a platinum layer of 20-50nm, and the outermost layer is also a top copper layer with a thickness of 200-600nm.
[0062] Based on the structure of the electrode base 211 described above, the formation of the stepped portion 212 embodies a design with advantages in process integration and cost-effectiveness. It is not a separately manufactured component that is then combined with the base, but rather an additional copper layer integrally deposited on top of the top copper layer of the electrode base 211 through selective thickening processes such as electroplating. This formation method ensures that the stepped portion and the electrode base are continuous homogeneous materials without a physical interface, thereby achieving optimal electrical and thermal conductivity. The final copper layer formed by the additionally deposited copper layer and the original top copper layer can reach a total thickness of 3000 nm to 120 μm, thus forming a stepped structure with a significant height difference and clearly defined functions at the microscopic level.
[0063] To form a complete, light-emitting CSP LED chip, the encapsulation structure of this embodiment further includes an encapsulating adhesive layer 4. This encapsulating adhesive layer 4 covers the upper surface of the LED chip 2 and the metal substrate 1, serving to protect the internal chip and circuitry and perform light color conversion. Further, the encapsulating adhesive layer 4 may contain phosphor particles to convert the blue or ultraviolet light emitted by the LED chip 2 into white light or other colors. The phosphor particles can be made of one or more combinations of nitrides, aluminates, silicates, nitrides, sulfides, or fluorides commonly found in the art.
[0064] In this embodiment, the metal substrate 1 can be made of copper foil, aluminum foil, or tin foil, or an alloy thereof, which have good electrical and thermal conductivity, and its thickness typically ranges from 3 μm to 120 μm. As a preferred option, using copper foil with a thickness of 8 μm to 35 μm achieves the best balance between cost and performance.
[0065] Finally, the LED chip 2 in this embodiment preferably adopts a flip-chip structure. This choice is also a key step in achieving the high-efficiency and high-reliability packaging goal of this embodiment, and it brings many beneficial effects.
[0066] First, the structure of the flip chip works in synergy with the coplanar bonding plane of this embodiment. The P and N electrodes of the flip chip are both located on the same side of the chip and are directly connected to the external circuitry facing downwards during packaging. This perfectly aligns with the design concept of this application, which uses the metal substrate 1 and the electrodes to construct a large, flat coplanar bonding plane. This face-to-face connection method, compared to traditional upright chips that require gold wire connections, not only simplifies the packaging process but also fundamentally eliminates the risk of failure caused by poor soldering, breakage, or contact of the gold wires, greatly improving the long-term reliability of the product.
[0067] Secondly, flip-chip technology significantly optimizes the heat dissipation path, substantially improving the product's heat dissipation performance. In flip-chip technology, the heat generated by the light-emitting layer can be rapidly conducted to the metal substrate 1 and dissipated through the shortest path, directly via the wide first electrode 21 and second electrode 22, and through the coplanar bonding plane with a large thermal conductivity area in the packaging structure of this embodiment. Compared to the path of traditional flip-chip technology, which requires passing through a sapphire substrate with extremely poor thermal conductivity, this heat dissipation channel is several orders of magnitude more efficient. Excellent heat dissipation performance means that the chip can operate at a lower junction temperature, which directly translates to lower light decay, higher luminous efficiency, and longer operating life.
[0068] Finally, the gold-wire-free structure of flip chips also brings about improved optical performance. Since there are no gold wires or electrodes obstructing the light-emitting surface of the chip, its effective light-emitting area is maximized, significantly improving light extraction efficiency. This allows the final packaged CSP LED to achieve higher luminous flux output under the same electrical input.
[0069] It should be understood that the core idea of this application is to form a stable mating structure and a final coplanar welding plane by setting a mutually compatible three-dimensional geometric structure between the metal substrate and the electrodes of the LED chip, and should not be limited to the specific form of the stepped portion embedded in the mating hole described in Embodiment 1 above. Those skilled in the art can design a variety of alternative structures that can achieve the same purpose of this application. Several feasible extended embodiments are listed below:
[0070] Example 2: This example provides an alternative structure different from Example 1, specifically a groove-type mating structure. In this example, the first electrode 21 and the second electrode 22 of the LED chip 2 are not designed as stepped, but as ordinary block electrodes with flat bottom surfaces. Correspondingly, the mutually adaptable three-dimensional geometry is set on the metal substrate 1. Specifically, the upper surface of the metal substrate 1 is processed by processes such as stamping, etching, or milling to create grooves (not shown in the figure) that precisely correspond to the shape and position of the first electrode 21 and the second electrode 22. The depth of the groove is precisely controlled to be equal to the height of the LED chip electrode.
[0071] During assembly, the two block electrodes of the LED chip 2 are respectively embedded into corresponding grooves (not shown in the figure) on the metal substrate 1. At this time, the bottom surface of the LED chip electrode and the bottom surface of the metal substrate 1 outside the groove together form a flat, coplanar welding plane. This combination of flat electrode and grooved substrate also realizes the core concept of this application.
[0072] Example 3:
[0073] This embodiment provides another, more complex alternative with higher mechanical locking strength compared to Embodiment 1. In this embodiment, the cross-sectional shape of the first electrode 21 and the second electrode 22 of the LED chip 2 is designed as a non-rectangular interlocking shape, such as a "T-shaped" or "L-shaped".
[0074] Correspondingly, on the metal substrate 1, a "T-shaped groove" or "L-shaped groove" matching the "T-shaped" or "L-shaped" cross-section of the electrode is formed by precision cutting or etching process.
[0075] During assembly, the T-shaped (or L-shaped) electrodes of the LED chip can be laterally slid in or embedded from above to form a dovetail-like interlocking connection with the T-shaped (or L-shaped) grooves on the metal substrate 1. This structure not only creates a coplanar welding plane at the bottom, but also further enhances the stability and shear resistance of the mechanical connection compared to a simple vertical embedding structure. This design scheme...
[0076] Example 4:
[0077] This embodiment provides a combined alternative that incorporates some features of the aforementioned embodiments. In this solution, the LED chip 2 may design only one electrode, such as the first electrode 21 which serves as the main heat dissipation channel, as a stepped shape, while keeping the other electrode, such as the second electrode 22, as a regular block electrode.
[0078] Correspondingly, only one mating hole corresponding to the stepped portion of the first electrode 21 is provided on the metal substrate 1. For the second electrode 22, the metal substrate 1 reserves a flat area for it, and positions and electrically isolates it by setting an insulating dam (not shown in the figure) around the area, such as a resin dam formed by printing or dispensing processes.
[0079] During assembly, the stepped portion of the first electrode 21 is embedded in the mating hole, while the second electrode 22 is directly attached to the reserved area of the metal substrate 1, with its bottom naturally coplanar with the bottom of the metal substrate 1. This hybrid structure, in which one electrode uses embedded mating and the other uses planar mating, also realizes the core concept that the bottom surfaces of multiple electrodes and the bottom surface of the metal substrate together form a coplanar welding plane.
[0080] Example 5: The following describes a CSP LED chip packaging method based on the packaging structure of Example 1. The core advantage of this method lies in its array-based, high-throughput process flow. This not only enables efficient and large-scale manufacturing of the packaging structure described in Example 1, but also achieves significant technological advancements in production efficiency, processing accuracy, and product consistency compared to traditional packaging methods. Those skilled in the art should understand that the core process concept embodied in this method is also applicable to manufacturing the packaging structures described in Examples 2 to 4, requiring only appropriate adjustments to the specific preparation steps of the metal substrate and LED chip. Please refer to the appendix. Figures 8 to 13 The specific steps of this method are as follows:
[0081] S1. Raw material preparation. First, multiple LED chips 2 are provided as core light-emitting units. These chips are pre-produced through a series of standard semiconductor processes such as epitaxial growth, photolithography, etching, and electrode fabrication. Their key feature is that they have a stepped first electrode 21 and a second electrode 22 as described in Example 1 above.
[0082] S2. Fabrication of the array-type metal substrate 10. An array-type metal substrate 10 is fabricated from a single sheet of metal foil (such as copper foil) using etching or laser cutting processes. Here, the "array-type metal substrate" is an intermediate carrier for mass production, on which multiple structurally identical and repeatedly arranged unit regions are defined. Each independent unit region structurally pre-forms the complete morphology of the metal substrate 1 in the final single CSP LED product. Specifically, in each unit region, mating holes 31 corresponding to the stepped portions 212 of the first electrode 21 and the second electrode 22 of the LED chip are precisely machined. Therefore, the array-type metal substrate 10 can be understood as an assembly composed of multiple future, interconnected metal substrates 1 before final cutting and separation.
[0083] S3. Temporary Fixing. To facilitate subsequent automated mounting, the prepared array of metal substrates is smoothly fixed onto a transparent temporary support substrate 20 using a layer of high-temperature double-sided adhesive. This temporary support substrate 20 (which can be a glass substrate) acts as a jig during the production process. The key benefit of this step is that it provides a highly rigid and flat temporary platform for the originally soft and easily deformable thin metal foil, effectively preventing warping and deformation during subsequent processing and heat treatment. This is a core process guarantee for achieving large-scale, high-precision automated mounting.
[0084] S4. Chip Mounting and Assembly. Using an automated die bonder, multiple prepared LED chips 2 are precisely mounted one by one onto each unit area of the array-type metal substrate. During the mounting process, the die bonder ensures that the stepped portions 212 of the first electrode 21 and the second electrode 22 of each LED chip are accurately embedded into the corresponding mating holes 31 in the unit area. The beneficial effect of this step is that, thanks to the stable platform provided by step S3 and the self-alignment characteristics of the product structure itself, the automated die bonder can complete the precise placement of a large number of chips at extremely high speed and with an extremely low error rate. This directly solves the pain points of high requirements and low production yield of micro CSP chip mounting technology in the background technology, making high-efficiency and high-precision mass production possible. After mounting is completed, the core structure in Example 1—a welding plane where the bottom surface of the chip electrode and the bottom surface of the metal substrate 1 are coplanar—is formed in each unit area.
[0085] S5. Encapsulation Layer Application. Using powder spraying or molding processes, an integral and uniform encapsulation layer 4 is applied over the entire array-type metal substrate on which all LED chips have been mounted. This layer completely covers all LED chips 2 and their internal structure, forming a unified protective and optical conversion layer. The advantage of this array-type encapsulation method is that it ensures extremely high consistency in the thickness, shape, and phosphor concentration of the encapsulation layer obtained by each individual CSP LED unit in the array. This guarantees a high degree of uniformity in the final product's optical characteristics such as emission color, brightness, and angle, which is difficult to achieve with traditional single-chip dispensing processes.
[0086] S6. Cutting and Separation. Finally, using high-precision laser cutting or waterjet cutting, the entire array-type metal substrate with the encapsulating adhesive layer is cut along a preset cutting path. Through this step, the macroscopic array structure is separated into multiple independent, microscopic CSP LED beads. Each cut-off individual CSP LED bead contains a metal substrate 1 from its corresponding unit region, and an LED chip 2 encapsulated on it.
[0087] In summary, the above methods can efficiently and in large quantities manufacture CSP LEDs with the embedded coplanar welding structure described in Example 1. The entire process demonstrates the comprehensive advantages of high efficiency, high precision, high yield, and high consistency, providing a solid and reliable technical path for the commercial mass production of this innovative packaging structure.
[0088] The above are implementation methods provided in conjunction with specific content, and it is not intended that the specific implementation of this application is limited to these descriptions. Any methods or structures that are similar to those of this application, or any technical deductions or substitutions made based on the concept of this application, should be considered within the scope of protection of this application.
Claims
1. An embedded coplanar soldering CSP LED chip packaging structure, characterized in that, include: Metal substrate (1); LED chip (2), the LED chip (2) having a first electrode (21) and a second electrode (22); The metal substrate (1) has a mutually compatible three-dimensional geometric structure with the first electrode (21) and the second electrode (22), such that the first electrode (21) and the second electrode (22) respectively form a docking structure (3) with the metal substrate through the compatible three-dimensional geometric structure, and the bottom surface of the first electrode (21), the bottom surface of the second electrode (22) and the bottom surface of the metal substrate (1) together form a coplanar welding plane.
2. The embedded coplanar soldering CSP LED chip packaging structure according to claim 1, characterized in that, The docking structure (3) includes docking holes (31) disposed on the metal substrate (1) corresponding to the first electrode (21) and the second electrode (22), and the first electrode (21) and the second electrode (22) are both stepped electrodes.
3. The embedded coplanar soldering CSP LED chip packaging structure according to claim 2, characterized in that, The stepped electrode includes: An electrode base (211) is disposed on the LED chip (2); and A stepped portion (212) extends from the electrode base (211) and has a thickness greater than that of the electrode base (211); The stepped portion (212) is embedded in the corresponding docking hole (31).
4. The embedded coplanar soldering CSP LED chip packaging structure according to claim 3, characterized in that, The size of the mating hole (31) is larger than the size of the step portion (212) so as to form a gap (32) for accommodating solder between the sidewall of the mating hole (31) and the sidewall of the step portion (212).
5. The embedded coplanar soldering CSP LED chip packaging structure according to claim 3, characterized in that, The thickness of the electrode base (211) is 0.42 μm to 1.22 μm, and the thickness of the stepped portion (212) is 3.42 μm to 121.32 μm.
6. The embedded coplanar soldering CSP LED chip packaging structure according to claim 3, characterized in that, The electrode base (211) is composed of a chromium layer of 50-150 nm, an aluminum layer of 100-300 nm, a chromium layer of 50-150 nm, a platinum layer of 20-50 nm, and a top copper layer of 200-600 nm, from bottom to top.
7. The embedded coplanar soldering CSP LED chip packaging structure according to claim 3, characterized in that, The electrode base (211) is composed of a chromium layer of 50-150 nm, an aluminum layer of 100-300 nm, a titanium layer of 30-50 nm, a nickel layer of 80-120 nm, a titanium layer of 30-50 nm, a platinum layer of 20-50 nm, and a top copper layer of 200-600 nm, from bottom to top.
8. The embedded coplanar soldering CSP LED chip packaging structure according to claim 6 or 7, characterized in that, The stepped portion (212) is composed of the electrode base (211) and a copper layer that is deposited on the top copper layer of the electrode base (211). The total thickness of the final copper layer formed by the deposited copper layer and the top copper layer is 3000 nm to 120 μm.
9. The embedded coplanar soldering CSP LED chip packaging structure according to claim 1, characterized in that, It also includes an encapsulating adhesive layer (4), which covers the upper surface of the LED chip (2) and the metal substrate (1).
10. The embedded coplanar soldering CSP LED chip packaging structure according to claim 1, characterized in that, The LED chip 2 is a flip chip.