Memory access method, computing system, and electronic device

Abstract

Embodiments of the present application disclose a memory access method, a computing system, and an electronic device. The method is applied to a first computing device in a computing system, the computing system including a memory pool and multiple computing devices, the memory pool including multiple Computing Interconnect Protocol (CXL) memory devices, each CXL memory device including multiple CXL ports, and each computing device including multiple CXL ports; wherein the multiple CXL ports on each CXL memory device are respectively connected to different computing devices, the multiple CXL ports on each computing device are respectively connected to different CXL memory devices, and any two computing devices in the multiple computing devices are connected via at least one CXL memory device. The method includes: in response to a communication request sent by a second computing device, sending a memory access request to the first CXL memory device to request access to the memory space of the first CXL memory device.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of server technology, and in particular to a memory access method, a computing system, and an electronic device. Background Art

[0002] Compute Express Link (CXL) is a high-speed interconnect technology that supports multiple computing devices to share remote pooled memory, reducing the memory gap between computing devices. It enables high-speed data transmission and memory sharing, providing higher data throughput and lower latency, thus meeting the needs of modern computing and storage systems.

[0003] Currently, related technologies plan to connect multiple computing devices and multiple CXL memory devices through a CXL switch, so that multiple computing devices can share a memory pool formed by multiple CXL memory devices.

[0004] However, the development of CXL switches is not yet mature, and the above technical solution needs to rely on CXL switches to form a memory pool. When computing devices access memory space based on CXL switches, it may cause long memory access latency. When facing the situation of crossing multiple levels of CXL switches, it will bring even greater latency, seriously affecting the performance of the memory pool. Summary of the Invention

[0005] Embodiments of the present application provide a memory access method, a computing system, and an electronic device for effectively reducing the latency of memory access, thereby ensuring the performance of a memory pool.

[0006] To achieve the above objectives, the present invention adopts the following technical solutions:

[0007] In one aspect, a memory access method is provided, which is applied to a first computing device in a computing system. The computing system includes a memory pool and multiple computing devices. The memory pool includes multiple Compute Interconnect Protocol (CXL) memory devices. Each CXL memory device includes multiple CXL ports. Each computing device includes multiple CXL ports. The multiple CXL ports on each CXL memory device are respectively connected to different computing devices. The multiple CXL ports on each computing device are respectively connected to different CXL memory devices. Any two computing devices among the multiple computing devices are connected via at least one CXL memory device. The method includes:

[0008] In response to a communication request sent by a second computing device, a memory access request is sent to the first CXL memory device, where the communication request is used to request access to the memory space of the first CXL memory device, and the memory access request is used to request access to the memory space of the first CXL memory device; wherein the first computing device is a computing device connected to a CXL port of the first CXL memory device; and the second computing device is a computing device connected to the first computing device via the second CXL memory device.

[0009] In the above technical solution, multiple computing devices are connected to multiple CXL memory devices, wherein each computing device is connected to multiple different CXL memory devices, so that each computing device can access one or more CXL memory devices connected to it. Moreover, each CXL memory device is connected to multiple different computing devices, wherein any two computing devices are connected to a common CXL memory device, so that each computing device has at least one memory space with which data can be shared between the other computing devices. On this basis, each computing device can not only access the CXL memory device connected to it, but also access the CXL memory devices connected to other computing devices through other computing devices that are connected to a common CXL memory device, thereby realizing memory sharing among multiple computing devices in the memory pool. Among them, through the network communication between the first computing device and the second computing device, the process of the second computing device accessing the first CXL memory device through the first computing device can be completed quickly and efficiently. In this way, there is no need to rely on CXL switches to form a memory pool, which can effectively reduce the latency of memory access, and can not only ensure the performance of the memory pool, but also effectively ensure the access performance of the computing devices.

[0010] In some possible implementations, the memory access request is a data read request, which is used to request a read operation to be performed on a memory space of the first CXL memory device. After sending the memory access request to the first CXL memory device, the method further includes: writing the read first data to the second CXL memory device.

[0011] In the above implementation, the read first data is written to the second CXL memory device, so that the second CXL memory device can subsequently read the first data by accessing the second CXL memory device.

[0012] In some possible implementations, the memory access request is a data write request, which is used to request a write operation to be performed in the memory space of the first CXL memory device. Before sending the memory access request to the first CXL memory device, the method further includes: reading second data from the second CXL memory device; and generating the memory access request based on the read second data.

[0013] In the above implementation, a memory access request is generated based on the read second data to request writing the second data into the first CXL memory device.

[0014] In another aspect, a memory access method is provided, which is applied to a management device, the management device being used to perform memory management on a memory pool in a computing system. The computing system includes a memory pool and multiple computing devices, the memory pool including the multiple CXL memory devices, each CXL memory device including multiple CXL ports, and each computing device including multiple CXL ports. The multiple CXL ports on each CXL memory device are respectively connected to different computing devices, the multiple CXL ports on each computing device are respectively connected to different CXL memory devices, and any two computing devices among the multiple computing devices are connected via at least one CXL memory device. The method comprises:

[0015] In response to a memory allocation request from a second computing device, a memory requirement of the second computing device is obtained; if the memory of the multiple CXL memory devices connected to the second computing device does not meet the memory requirement of the second computing device, but the memory of the multiple CXL memory devices connected to the first computing device meets the memory requirement of the second computing device, memory of a first CXL memory device that meets the memory requirement is allocated to the second computing device from the multiple CXL memory devices connected to the first computing device; wherein the first computing device is a computing device connected to a CXL port of the first CXL memory device; and the second computing device is a computing device connected to the first computing device via the second CXL memory device.

[0016] In the above technical solution, multiple computing devices are connected to multiple CXL memory devices, wherein each computing device is connected to multiple different CXL memory devices, so that each computing device can access one or more CXL memory devices connected to it. Moreover, each CXL memory device is connected to multiple different computing devices, wherein any two computing devices are connected to a common CXL memory device, so that each computing device has at least one memory space for sharing data with other computing devices. On this basis, each computing device can not only access the CXL memory device connected to it, but also access the CXL memory devices connected to other computing devices through other computing devices that are connected to a common CXL memory device, thereby realizing memory sharing among multiple computing devices in the memory pool. In particular, by deploying a management device, the management device is used to manage the memory of multiple CXL memory devices in the memory pool. If the memory requirements of multiple CXL memory devices connected to a second computing device are insufficient, but the memory requirements of multiple CXL memory devices connected to a first computing device are sufficient, the memory of a first CXL memory device that meets the requirements can be allocated to the second computing device. This allows the second computing device to quickly and efficiently access the first CXL memory device through the first computing device via network communication between the first and second computing devices. This eliminates the need to rely on CXL switches to form a memory pool, effectively reducing memory access latency and ensuring both the performance of the memory pool and the access performance of the computing devices.

[0017] In some possible implementations, the memory requirement indicates that the memory type is a target type and the memory size is a target capacity;

[0018] The method further includes: if the sum of remaining available capacities of the target type of memory in the plurality of CXL memory devices connected to the second computing device is greater than or equal to the target capacity, determining that the memory of the plurality of CXL memory devices connected to the second computing device meets the memory requirement of the second computing device; and if the sum of remaining available capacities of the target type of memory in the plurality of CXL memory devices connected to the second computing device is less than the target capacity, determining that the memory of the plurality of CXL memory devices connected to the second computing device does not meet the memory requirement of the second computing device.

[0019] In the above implementation, a method is provided for determining whether the memory requirement of the second computing device is met based on the memory type and memory size. In this way, it is possible to ensure that the memory required by the second computing device is allocated, thereby ensuring the accuracy of memory allocation.

[0020] In some possible implementations, allocating memory of a first CXL memory device that meets the memory requirement to a second computing device from among multiple CXL memory devices connected to the first computing device includes sending device information of the first computing device and a memory address of the first CXL memory device to the second computing device, so that the second computing device can send a communication request to the first computing device, where the communication request is for requesting access to memory space of the first CXL memory device.

[0021] In the above implementation, the device information of the first computing device and the memory address of the first CXL memory device are sent to the second computing device, so that the second computing device can subsequently implement network communication with the first computing device based on the device information of the first computing device and the memory address of the first CXL memory device, thereby ensuring smooth memory access.

[0022] In another aspect, a memory pool is provided, the memory pool being configured to provide memory resources for multiple computing devices. The memory pool includes multiple CXL memory devices, each of which includes multiple CXL ports. The multiple CXL ports on each CXL memory device are respectively configured to connect to different computing devices, and any two computing devices among the multiple computing devices are connected via at least one CXL memory device.

[0023] a first CXL memory device configured to receive a memory access request sent by a first computing device, the memory access request being configured to request access to memory space of the first CXL memory device; the first computing device being a computing device connected to a CXL port of the first CXL memory device; and the second computing device being a computing device connected to the first computing device via the second CXL memory device;

[0024] The first CXL memory device is further configured to perform, based on the memory access request, a memory access operation indicated by the memory access request.

[0025] In the above-mentioned memory pool, each CXL memory device includes multiple CXL ports so as to connect to multiple different computing devices respectively, wherein any two computing devices among the multiple computing devices are connected through at least one CXL memory device, so that each computing device has at least one CXL memory device that can share data with other computing devices. On this basis, each computing device can not only access the CXL memory device connected to it, but also access the CXL memory devices connected to other computing devices through other computing devices that share a CXL memory device with it, thereby realizing memory sharing among multiple computing devices in the memory pool. Among them, through the network communication between the first computing device and the second computing device, the process of the second computing device accessing the first CXL memory device through the first computing device can be completed quickly and efficiently. In this way, there is no need to rely on a CXL switch to form a memory pool, which can effectively reduce the latency of memory access, and can not only ensure the performance of the memory pool, but also effectively ensure the access performance of the computing device.

[0026] In some possible implementations, the CXL port is at least one of a multi-channel input / output (MCIO) port, a universal serial bus (USB-C) port, or other ports supporting the CXL protocol.

[0027] In the above implementation, multiple types of CXL ports are provided, enriching the types of CXL ports. Furthermore, by setting CXL ports that support the CXL protocol, memory sharing between different computing devices based on multiple CXL memory devices can be achieved based on the CXL protocol.

[0028] In some possible implementations, the multiple CXL ports are multiple physical ports, i.e., one CXL port corresponds to one physical port, or the multiple CXL ports are multiple ports formed by splitting one physical port, i.e., one CXL port can be split into two or more CXL ports via a CXL adapter cable for connecting two or more different computing devices.

[0029] In the above implementation, one CXL port can be flexibly split into two or more CXL ports, thereby improving the flexibility of CXL port settings.

[0030] In some possible implementations, each CXL memory device includes a memory medium, where the memory medium includes at least one of a dynamic random access memory (DRAM) chip or a dual inline memory module (DIMM) memory stick.

[0031] In the above implementation, multiple types of memory media are provided, enriching the types of memory media.

[0032] In some possible implementations, the number of the plurality of CXL memory devices is determined based on the number of the plurality of computing devices, a first number of CXL ports in each computing device, and a second number of CXL ports in each CXL memory device; wherein the number of the plurality of CXL memory devices is positively correlated with the number of the plurality of computing devices and the first number, and negatively correlated with the second number.

[0033] In the above implementation, a method for calculating the number of multiple CXL memory devices is provided. The method determines the number of CXL memory devices based on the number of computing devices, the number of CXL ports in each computing device, and the number of CXL ports in each CXL memory device, such that the determined number of CXL memory devices meets the number of CXL memory devices required for subsequent memory pool establishment.

[0034] In some possible implementations, the memory access operation includes a read operation or a write operation.

[0035] In the above implementation, a memory access solution based on read operations or write operations is provided, so that a computing device can implement read operations or write operations based on a CXL memory device by accessing the memory space of the CXL memory device in the memory pool.

[0036] In another aspect, a computing system is provided, comprising a memory pool and a plurality of computing devices. The memory pool comprises a plurality of CXL memory devices, each CXL memory device comprises a plurality of CXL ports, and each computing device comprises a plurality of CXL ports. The plurality of CXL ports on each CXL memory device are respectively connected to different computing devices, the plurality of CXL ports on each computing device are respectively connected to different CXL memory devices, and any two computing devices among the plurality of computing devices are connected via at least one CXL memory device.

[0037] The first computing device is configured to send a memory access request to the first CXL memory device in response to a communication request sent by the second computing device, wherein the communication request is used to request access to a memory space of the first CXL memory device, and the memory access request is used to request access to the memory space of the first CXL memory device; the first computing device is a computing device connected to a CXL port of the first CXL memory device; and the second computing device is a computing device connected to the first computing device via the second CXL memory device.

[0038] The first CXL memory device is configured to receive a memory access request sent by the first computing device, and based on the memory access request, perform a memory access operation indicated by the memory access request.

[0039] In the above-mentioned computing system, multiple computing devices are connected to multiple CXL memory devices, wherein each computing device is connected to multiple different CXL memory devices, so that each computing device can access one or more CXL memory devices connected to it. Furthermore, each CXL memory device is connected to multiple different computing devices, wherein any two computing devices are connected to a common CXL memory device, so that each computing device has at least one memory space with which data can be shared between the other computing devices. On this basis, each computing device can not only access the CXL memory device connected to it, but also access the CXL memory devices connected to other computing devices through other computing devices that are connected to the common CXL memory device, thereby realizing memory sharing among multiple computing devices in the memory pool. In particular, through network communication between the first computing device and the second computing device, the process of the second computing device accessing the first CXL memory device through the first computing device can be completed quickly and efficiently. In this way, there is no need to rely on CXL switches to form a memory pool, which can effectively reduce the latency of memory access, and can not only ensure the performance of the memory pool, but also effectively ensure the access performance of the computing devices.

[0040] In some possible implementations, a first number of CXL ports in each computing device is determined based on the number of the plurality of computing devices and a second number of CXL ports in each CXL memory device; wherein the first number is positively correlated with the number of the plurality of computing devices and negatively correlated with the second number.

[0041] In the above implementation, by deploying a first number of CXL ports, each computing device can connect to a first number of CXL memory devices through the first number of CXL ports, thereby enabling interconnection between multiple computing devices and multiple CXL memory devices, thereby ensuring that each computing device can access the memory space of any CXL memory device.

[0042] In some possible implementations, the CXL port is at least one of a multi-channel input / output (MCIO) port, a universal serial bus (USB-C) port, or other ports supporting the CXL protocol.

[0043] In the above implementation, multiple types of CXL ports are provided, enriching the types of CXL ports. Furthermore, by setting CXL ports that support the CXL protocol, memory sharing between different computing devices based on multiple CXL memory devices can be achieved based on the CXL protocol.

[0044] In some possible implementations, the number of the plurality of CXL memory devices is determined based on the number of the plurality of computing devices, a first number of CXL ports in each computing device, and a second number of CXL ports in each CXL memory device; wherein the number of the plurality of CXL memory devices is positively correlated with the number of the plurality of computing devices and the first number, and negatively correlated with the second number.

[0045] In the above implementation, the number of multiple CXL memory devices is determined based on the number of the multiple computing devices, the number of CXL ports in each computing device, and the number of CXL ports in each CXL memory device. This number of CXL memory devices determined can meet the number requirement of CXL memory devices for subsequently establishing a memory pool, thereby enabling interconnection between the multiple computing devices and the multiple CXL memory devices, thereby ensuring that each computing device can access the memory space of any CXL memory device.

[0046] In some possible implementations, the memory access operation includes a read operation or a write operation.

[0047] In the above implementation, a memory access solution based on read operations or write operations is provided, so that a computing device can implement read operations or write operations based on a CXL memory device by accessing the memory space of the CXL memory device in the memory pool.

[0048] In another aspect, a memory access method is provided, which is applied to a first CXL memory device in the aforementioned memory pool, wherein the memory pool is configured to provide memory resources for multiple computing devices. The memory pool includes multiple CXL memory devices, each of which includes multiple CXL ports. The multiple CXL ports on each CXL memory device are respectively configured to connect to different computing devices, and any two computing devices in the multiple computing devices are connected via at least one CXL memory device. The method comprises:

[0049] The first CXL memory device receives a memory access request sent by a first computing device, the memory access request indicating a request to access memory space of the first CXL memory device; the first computing device is a computing device connected to a CXL port of the first CXL memory device; and the second computing device is a computing device connected to the first computing device via a second CXL memory device.

[0050] The first CXL memory device performs a memory access operation indicated by the memory access request based on the memory access request.

[0051] In the above technical solution, each CXL memory device includes multiple CXL ports so as to respectively connect to multiple different computing devices, wherein any two computing devices among the multiple computing devices are connected through at least one CXL memory device. In this way, there is at least one CXL memory device that can share data between each computing device and other computing devices. On this basis, each computing device can not only access the CXL memory device connected to it, but also access the CXL memory devices connected to other computing devices through other computing devices that are connected to a CXL memory device, thereby realizing memory sharing among multiple computing devices in the memory pool. Among them, through the network communication between the first computing device and the second computing device, the process of the second computing device accessing the first CXL memory device through the first computing device can be completed quickly and efficiently. In this way, there is no need to rely on a CXL switch to form a memory pool, which can effectively reduce the latency of memory access, and can not only ensure the performance of the memory pool, but also effectively ensure the access performance of the computing device.

[0052] In some possible implementations, the memory access operation includes a read operation or a write operation.

[0053] In the above implementation, a memory access solution based on read operations or write operations is provided, so that a computing device can implement read operations or write operations based on a CXL memory device by accessing the memory space of the CXL memory device in the memory pool.

[0054] In another aspect, a CXL memory device is provided. The CXL memory device includes a CXL controller and a memory medium, wherein the CXL controller and the memory medium are coupled. The memory medium is configured to store computer program instructions, and the CXL controller is configured to invoke the computer program instructions in the memory medium to execute the contents executed by the CXL memory device in the memory access method described in the above embodiment.

[0055] In another aspect, an electronic device is provided, comprising a processor and a memory, the processor and the memory being coupled. The memory is configured to store computer program instructions, and the processor is configured to invoke the computer program instructions in the memory to execute the contents executed by the computing device or management device in the memory access method described in the above embodiment. In the embodiments of the present application, the computing device or the management device may be an electronic device.

[0056] On the other hand, a computer-readable storage medium is provided. The computer-readable storage medium stores computer program instructions. The computer program instructions are used to enable a CXL memory device or an electronic device to execute the memory access method shown in the above embodiment.

[0057] On the other hand, a computer program product is provided, including computer program instructions. When the computer program instructions are executed on a CXL memory device or an electronic device, the CXL memory device or the electronic device executes the memory access method as shown in the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 A schematic diagram of the architecture of a data center system provided for related technologies;

[0059] Figure 2 A schematic diagram of another data center system architecture provided for related technologies;

[0060] Figure 3 A schematic diagram of the architecture of a memory pool based on a CXL switch is provided for related technologies;

[0061] Figure 4 A schematic diagram of the architecture of a computing system provided in an embodiment of the present application;

[0062] Figure 5 A schematic diagram of the hardware structure of a CXL memory expansion card provided in an embodiment of the present application;

[0063] Figure 6 A schematic diagram of the hardware structure of a computing device provided in an embodiment of the present application;

[0064] Figure 7 A schematic diagram of the hardware structure of a management device provided in an embodiment of the present application;

[0065] Figure 8 A schematic diagram of a memory access method provided in an embodiment of the present application;

[0066] Figure 9 A schematic diagram of a memory access method provided in an embodiment of the present application;

[0067] Figure 10 A schematic diagram of the structure of a memory access device provided in an embodiment of the present application;

[0068] Figure 11 A schematic structural diagram of a memory access device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0069] In the description of the embodiments of the present application, unless otherwise specified, " / " means "or", for example, A / B can mean A or B. "And / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, "at least one" means one or more, and "a plurality" means two or more. Words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not limit them to be necessarily different.

[0070] It should be noted that in the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0071] With the increasing prevalence of big data processing scenarios such as large artificial intelligence (AI) models, computing devices typically run resource-intensive applications, such as compute-intensive, memory-intensive, and communication-intensive. Compute-intensive applications refer to applications where the central processing unit (CPU) prioritizes computation. Memory-intensive applications refer to applications where the CPU prioritizes reading or writing data from memory. Communication-intensive applications refer to applications where the CPU prioritizes reading or writing data from network interfaces (NICs).

[0072] When computing data for these resource-intensive applications, computing devices typically require storing large amounts of data in memory before performing further computations. However, current data center systems cannot provide the massive memory required for computing data in these resource-intensive applications.

[0073] For example, Figure 1 A schematic diagram of the architecture of a data center system provided for related technologies. Figure 1 ,In the data center systems of related technologies, such as Figure 1The traditional data center system shown is connected to a network of general-purpose computing nodes, dedicated computing nodes, heterogeneous computing nodes, and storage nodes via a top-of-rack (TOR) switch. General-purpose computing nodes may include computing devices designed for a variety of application areas and algorithms, such as general-purpose computers such as personal computers, laptops, and servers. In some possible implementations, general-purpose computing nodes may be deployed with CPUs. Dedicated computing nodes may include computing devices specifically designed for a specific application area or algorithm, such as dedicated computers such as automated teller machines (ATMs), medical equipment, and industrial control systems. In some possible implementations, dedicated computing nodes may be deployed with xPUs, such as graphics processing units (GPUs), tensor processing units (TPUs), neural network processing units (NPUs), data processing units (DPUs), and so on. Heterogeneous computing nodes refer to a special type of parallel distributed computing system that can efficiently utilize computing resources to effectively achieve high computing power. In some possible implementations, heterogeneous computing nodes may be deployed with CPUs and xPUs. A storage node may include a computing device for storing and managing data, such as a storage server.

[0074] See also Figure 1 For any type of computing node in the data center system, including general computing nodes, dedicated computing nodes, and heterogeneous computing nodes, each node has its own memory deployed separately, and the memory cannot be further expanded, so that each computing node can only access its own memory space, which is limited.

[0075] For example, Figure 2 Another data center system architecture diagram provided for related technologies. Figure 2 ,In the data center systems of related technologies, such as Figure 2The next-generation data center system shown in the figure connects general-purpose compute nodes, specialized compute nodes, memory pooling nodes, and storage nodes via a high-bandwidth ibnetwork connected by top-of-rack switches. General-purpose and specialized compute nodes don't inherently contain much memory (such as local memory). Instead, memory pooling nodes are deployed to pool the massive memory space of multiple CXL memory devices. Memory pooling is achieved by connecting general-purpose compute nodes, specialized compute nodes, memory pooling nodes, and storage nodes in the data center via low-latency CXL.

[0076] Among them, CXL is a high-speed interconnection technology that supports multiple computing devices to share a remote pooled memory pool, reducing the memory gap between computing devices, enabling high-speed data transmission and memory sharing, and providing higher data throughput and lower latency, thereby meeting the needs of modern computing and storage systems.

[0077] For example, Figure 3 A schematic diagram of the architecture of a memory pool based on a CXL switch is provided for related technologies. Figure 3 , usually need to connect multiple computing devices through CXL switches (such as Figure 3 Host 1, host 2, ..., host n (where n is a positive integer greater than or equal to 2) and multiple CXL memory devices are shown, thereby enabling multiple computing devices to share a memory pool formed by the multiple CXL memory devices.

[0078] However, the related technology relies on CXL switches to form memory pools. On the one hand, due to the low technical maturity of CXL switches, it is difficult to promote and use them widely in the short term. On the other hand, when computing devices access memory space based on CXL switches, it may cause long memory access latency. When facing the situation of crossing multiple levels of CXL switches, the latency will be even greater, seriously affecting the performance of the memory pool.

[0079] In view of this, an embodiment of the present application provides a memory pool, and provides a computing system based on the memory pool. In the computing system provided by the embodiment of the present application, multiple computing devices are connected to multiple CXL memory devices via CXL cables, wherein each computing device is respectively connected to multiple different CXL memory devices, so that each computing device can access one or more CXL memory devices connected to it via the CXL cable. Moreover, each CXL memory device is respectively connected to multiple different computing devices, wherein any two computing devices are commonly connected to at least one CXL memory device, so that each computing device and other computing devices have at least one memory space for sharing data. On this basis, each computing device can not only access the CXL memory device connected to it via the CXL cable, but also access the CXL memory device connected to other computing devices via other computing devices that are commonly connected to a CXL memory device, thereby realizing memory sharing between multiple computing devices in the memory pool. In this way, there is no need to rely on a CXL switch to form a memory pool, which can effectively reduce the latency of memory access, and can not only ensure the performance of the memory pool, but also effectively ensure the access performance of the computing device.

[0080] Figure 4 This is a schematic diagram of the architecture of a computing system provided in an embodiment of the present application. Figure 4 The computing system 400 includes a memory pool 401 and multiple computing devices 402 .

[0081] The memory pool 401 includes multiple CXL memory devices, which may also be referred to as a CXL memory pool, and is used to provide memory resources for multiple computing devices 402. Figure 4 , multiple CXL memory devices can be Figure 4 The CXL memory device ①, CXL memory device ②, ..., CXL memory device ⑥, etc. shown in FIG. The plurality of computing devices 402 may be Figure 4 The computing devices shown are ①, ②, ③, and ④.

[0082] In some possible implementations, the CXL memory device may be a CXL memory expansion card. For example, Figure 5 This is a hardware structure diagram of a CXL memory expansion card provided in an embodiment of the present application. Figure 5 Each CXL memory expansion card may include a CXL controller and a memory medium connected to the CXL controller. For example, the CXL controller may be referred to as a CXL memory expander chip or a CXL memory expander controller. In some possible implementations, the CXL controller may be connected to multiple CXL ports of a CXL memory device.

[0083] Exemplarily, the memory medium may include at least one of dynamic random access memory (DRAM) particles or dual inline memory modules (DIMM) memory sticks. Of course, in other embodiments, the memory medium may also include flash memory particles. Thus, multiple types of memory media are provided, enriching the types of memory media. It should be understood that by accessing a connected CXL memory device, a computing device can access the memory space of the memory medium connected to the CXL memory device.

[0084] Each CXL memory device includes multiple CXL ports, where a plurality is two or more. The CXL ports of the CXL memory device can be access ports of a computing device. In some possible implementations, the CXL ports are at least one of a multi-channel input / output (MCIO) port, a universal serial bus type-C (USB-C) port, or other ports that support the CXL protocol.

[0085] The embodiments of this application do not limit the type of CXL port. Thus, multiple types of CXL ports are provided, enriching the types of CXL ports. Furthermore, by providing CXL ports that support the CXL protocol, memory sharing between different computing devices based on multiple CXL memory devices can be achieved based on the CXL protocol.

[0086] In some possible implementations, the CXL memory device may be a dual-port CXL memory expansion card, that is, the CXL memory device includes two CXL ports.

[0087] For example, see Figure 5 Figure 5-1 shows the internal architecture of a dual-port CXL memory expansion card, where the dual-port CXL memory expansion card may include port 1 and port 2. In this case, two computing devices connected to the two CXL ports of the dual-port CXL memory expansion card can access the memory space of the dual-port CXL memory expansion card.

[0088] In some further possible implementations, the CXL memory device may be a multi-port CXL memory expansion card, that is, the CXL memory device includes multiple CXL ports.

[0089] For example, see Figure 5Figure 5-2 shows the internal architecture of a multi-port CXL memory expansion card, where the multi-port CXL memory expansion card may include port 1, port 2, port 3, etc. In this case, multiple computing devices connected to the multiple CXL ports of the multi-port CXL memory expansion card can access the memory space of the multi-port CXL memory expansion card.

[0090] It should be noted that the multiple CXL ports involved in the embodiments of the present application can be multiple physical ports, that is, one CXL port corresponds to one physical port, or can be multiple ports formed by splitting one physical port. For example, an x16 port can be split into two x8 ports, that is, multiple CXL ports correspond to one physical port.

[0091] In some possible implementations, a physical port can be split into two or more ports via a CXL adapter cable to connect two or more different computing devices. Figure 5 In Figure 5-2, taking physical port 3 as an example, you can split port 3 into two ports, such as port 3.1 and port 3.2. This allows you to flexibly split a physical port into two or more CXL ports, increasing the flexibility of CXL port configuration.

[0092] In some possible implementations, when the CXL memory device is a CXL memory expansion card, the memory pool 401 can be in the form of a chassis (or box). For example, in some possible implementations, multiple CXL memory expansion cards can be arranged and deployed (or called parallel deployment) in a chassis (or box) so as to centrally manage multiple CXL memory expansion cards. Exemplarily, the chassis can be provided with multiple slots for inserting CXL memory expansion cards. In this way, a memory pool can be formed based on multiple CXL memory expansion cards. In this way, by centrally deploying the massive memory devices of multiple CXL memory expansion cards in one chassis, not only can high scalability and high utilization of memory be achieved, but also high maintainability and high management rationality of memory can be achieved.

[0093] When memory pool 401 is in the form of a chassis, multiple CXL memory expansion cards can be powered by the same power supply or by multiple power supplies. This embodiment of the present application is not limited to this. It should be noted that when multiple CXL memory expansion cards are actually deployed in the chassis, some of the CXL memory expansion cards can be used to connect computing devices, such as connecting some CXL memory expansion cards to multiple computing devices 402 to form a memory pool, while the remaining CXL memory expansion cards can be used for other purposes, such as implementing other functions of the computing device.

[0094] The above embodiment describes memory pool 401 using a CXL memory device as a CXL memory expansion card as an example. In other possible implementations, the CXL memory device can also be a server equipped with a CXL memory expansion card. Accordingly, memory pool 401 can be a server cluster composed of multiple servers equipped with CXL memory expansion cards. In this way, a memory pool can also be formed based on multiple servers equipped with CXL memory expansion cards.

[0095] The computing device can be an independent physical server, such as a general-purpose server, a graphics processing server, a data processing server, an artificial intelligence server, etc., or a server cluster or distributed file system composed of multiple physical servers, or at least one of the cloud servers that provide basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content distribution networks, and big data or artificial intelligence platforms. The embodiments of the present application are not limited to this.

[0096] For example, Figure 6 This is a hardware structure diagram of a computing device provided in an embodiment of the present application. Figure 6 , Figure 6 The computing device 600 shown may include a processor 601 , a memory 602 , a communication interface 603 , multiple CXL ports 604 , and a bus 605 . The processor 601 , the memory 602 , the communication interface 603 , and the multiple CXL ports 604 may be connected via the bus 605 .

[0097] The processor 601 is the control center of the computing device 600, and can be a general-purpose central processing unit such as a CPU, or other general-purpose processors. Among them, the general-purpose processor can be a microprocessor or any conventional processor. In the embodiment of the present application, the content executed by the computing device in the memory access method can be executed by the processor 601 in the computing device 600. As an example, the processor 601 can include one or more CPUs, such as Figure 6 CPU 0 and CPU 1 are shown in Figure 1.

[0098] The memory 602 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program codes in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. In an embodiment of the present application, the memory 602 may be connected to the processor 601 via a bus 604 for storing data, instructions or program codes. When the processor 601 calls and executes the instructions or program codes stored in the memory 602, the memory access method provided in the embodiment of the present application can be implemented.

[0099] The communication interface 603 is used to connect the computing device 600 to other devices via a communication network. The communication interface 603 may include a receiving unit for receiving data and a sending unit for sending data.

[0100] The number of the plurality of CXL ports 604 may be two or more. In some possible implementations, the CXL port is at least one of an MCIO port, a USB-C port, or other ports that support the CXL protocol. The embodiment of the present application does not limit the type of the CXL port.

[0101] It should be pointed out that Figure 6 The structure shown in the figure does not constitute a limitation on the computing device 600, except Figure 6 In addition to the components shown, the computing device 600 may include more or fewer components than shown, or combine certain components, or arrange the components differently.

[0102] In computing system 400 , multiple CXL ports on each CXL memory device are connected to different computing devices, multiple CXL ports on each computing device are connected to different CXL memory devices, and any two computing devices in computing devices 402 are connected through at least one CXL memory device.

[0103] Among them, the computing device can be connected to the CXL port of the CXL memory device via a CXL cable. In some possible implementations, the CXL cable is a cable that supports the CXL protocol. Exemplarily, the CXL cable can be a high-speed serial computer expansion bus (Peripheral Component Interconnect Express, PCIE) cable. It is worth noting that the CXL cable can also be other types of cables that support the CXL protocol. The embodiment of the present application does not limit the type of CXL cable. In this way, by setting a CXL cable that supports the CXL protocol, memory sharing based on multiple CXL memory devices of different computing devices can be achieved based on the CXL protocol.

[0104] In the embodiment of the present application, any two computing devices are connected to a CXL memory device. In this way, each computing device has at least one CXL memory device that can share data with other computing devices, so that data can be shared through the commonly connected CXL memory device. For example, see Figure 4 Taking computing device ① and computing device ② as an example, since computing device ① and computing device ② are both connected to CXL memory device ①, computing device ① and computing device ② can share data through the commonly connected CXL memory device ①. Other computing devices are similar and will not be described in detail.

[0105] Each computing device includes a first number of CXL ports, which are used to connect to different CXL memory devices. It should be noted that each computing device includes the same number of CXL ports. It should also be noted that each computing device's first number of CXL ports is connected to a different CXL memory device. This allows each computing device to access the memory space of one or more connected CXL memory devices via a CXL cable, effectively meeting the memory and bandwidth requirements of a single computing device.

[0106] Each CXL memory device includes a second number of CXL ports, which are used to connect to different computing devices. It should be noted that each CXL memory device includes the same number of CXL ports. It should also be noted that the second number of CXL ports included in each CXL memory device are respectively connected to different computing devices. This prevents CXL memory devices from being repeatedly connected to the same computing device, thereby reducing the problem of memory waste. Furthermore, by deploying the second number of CXL ports, each CXL memory device can connect to the second number of computing devices via the second number of CXL ports, thereby achieving the effect of the second number of computing devices sharing the same CXL memory device.

[0107] In some possible implementations, the first number of CXL ports in each computing device is determined based on the number of the plurality of computing devices 402 and the second number of CXL ports in each CXL memory device.

[0108] The first number is positively correlated with the number of the plurality of computing devices 402 and negatively correlated with the second number.

[0109] For example, taking a dual-port CXL memory expansion card as an example, that is, the second quantity is 2, the process of determining the first quantity can be: determining the first quantity based on the number of multiple computing devices 402, the second quantity and the following formula (1).

[0110] Q≥N-P+1 (1)

[0111] In the formula, Q represents a first quantity, i.e., the number of CXL ports included in each computing device; N represents the number of computing devices 402; and P represents a second quantity, i.e., the number of CXL ports included in each CXL memory device. It should be noted that the first quantity specifically refers to the number of CXL memory devices connected to each computing device, and does not mean that the computing device only includes the first number of CXL ports. For example, the computing device may include more than the first number of CXL ports.

[0112] In this way, by deploying the first number of CXL ports, each computing device can connect to the first number of CXL memory devices through the first number of CXL ports, so as to achieve interconnection between multiple computing devices and multiple CXL memory devices, thereby ensuring that each computing device can access the memory space of any CXL memory device.

[0113] In some possible implementations, the number of the plurality of CXL memory devices is determined based on the number of the plurality of computing devices 402 , a first number of CXL ports in each computing device, and a second number of CXL ports in each CXL memory device.

[0114] The number of the plurality of CXL memory devices is positively correlated with the number of the plurality of computing devices 402 and the first number, and negatively correlated with the second number.

[0115] For example, taking a dual-port CXL memory device as an example, that is, the second number is 2, the process of determining the number of multiple CXL memory devices may be as follows: the number of multiple CXL memory devices may be determined based on the number of multiple computing devices 402, the first number, the second number, and the following formula (2).

[0116] M≥N*Q / P (2)

[0117] Wherein, M represents the number of the plurality of CXL memory devices; N represents the number of the plurality of computing devices 402; Q represents a first number, ie, the number of CXL ports included in each computing device; and P represents a second number, ie, the number of CXL ports included in each CXL memory device.

[0118] Regarding formula (2), it can be understood that the value obtained by N*Q indicates the total number of CXL cables connected to the plurality of computing devices 402. Considering that the total number of CXL cables connected to the plurality of computing devices 402 should be consistent with the total number of CXL cables connected to the plurality of CXL memory devices, dividing by P can quickly determine the number of the plurality of CXL memory devices. Thus, based on the number of computing devices 402, the number of CXL ports in each computing device, and the number of CXL ports in each CXL memory device, the number of CXL memory devices is determined. This number of CXL memory devices can meet the number of CXL memory devices required for subsequent memory pool establishment, enabling interconnection between the plurality of computing devices and the plurality of CXL memory devices, thereby ensuring that each computing device can access the memory space of any CXL memory device.

[0119] Taking the first computing device and the first CXL memory device as an example, the first computing device is a computing device connected to a CXL port of the first CXL memory device via a CXL cable.

[0120] In an embodiment of the present application, a first computing device is configured to, in response to a communication request sent by a second computing device, send a memory access request to a first CXL memory device, wherein the communication request is for accessing memory space of the first CXL memory device, and the memory access request is for accessing memory space of the first CXL memory device. The second computing device is a computing device connected to the first computing device via the second CXL memory device.

[0121] In an embodiment of the present application, the first CXL memory device is configured to: receive a memory access request sent by the first computing device, and based on the memory access request, perform a memory access operation indicated by the memory access request.

[0122] For example, see Figure 4 Taking computing device ① as an example, since computing device ① is connected to CXL memory device ①, CXL memory device ②, and CXL memory device ③, computing device ① can access the memory space of one or more of CXL memory device ①, CXL memory device ②, and CXL memory device ③ through the CXL cable.

[0123] For example, see Figure 4For example, computing device ① and computing device ④ are both connected to CXL memory device ③. Based on this, computing device ① can share its connected CXL memory device ① or CXL memory device ② with computing device ④. For example, if computing device ① shares its connected CXL memory device ① with computing device ④, computing device ④ can write data to CXL memory device ③ and notify computing device ①. Computing device ① can then read the data from CXL memory device ③ and then write the data to CXL memory device ①. Alternatively, computing device ① can read data from CXL memory device ① and then write the data to CXL memory device ③ for computing device ④ to use.

[0124] Similarly, computing device ④ can also share its connected CXL memory device ④ or CXL memory device ⑤ with computing device ① for use. For example, computing device ④ can share its connected CXL memory device ④ with computing device ①. Computing device ① can write data to CXL memory device ③ and notify computing device ④. Computing device ④ can then read the data from CXL memory device ③ and write it to CXL memory device ④. Alternatively, computing device ④ can read data from CXL memory device ④ and write it to CXL memory device ③ for use by computing device ①.

[0125] In this way, by ensuring that any two computing devices are connected to a CXL memory device, the foundation is laid for subsequent access to the memory space of the CXL memory device connected to other computing devices. Then, through network communication between computing devices, the memory space of the CXL memory device connected to other computing devices can be accessed.

[0126] In such Figure 4 In the example shown, using a dual-port CXL memory device and a three-port computing device as examples, any two computing devices are connected through at least one CXL memory device. Furthermore, each CXL memory device is connected to two different computing devices, and each computing device is connected to three different CXL memory devices. This creates a fully interconnected network topology of CXL memory devices and computing devices, allowing each computing device to access the memory space of any CXL memory device in the memory pool, with at most one computing device hop. For example, a computing device can access the memory space of CXL memory devices connected to other computing devices by communicating with them through the same CXL memory device. This reduces the latency of memory access, thereby ensuring stable memory pool performance.

[0127] In some possible implementations, the computing system may further include: a management device 403 .

[0128] The management device 403 may be a server independently deployed from the plurality of computing devices 402, or may be any one (or any number) of the plurality of computing devices 402. Figure 4 The management device 403 is described by taking a server that is independently deployed from the plurality of computing devices 402 as an example.

[0129] For example, Figure 7 This is a hardware structure diagram of a management device provided in an embodiment of the present application. Figure 7 , Figure 7 The management device 700 shown may include: a processor 701, a memory 702, a communication interface 703, and a bus 704. The processor 701, the memory 702, and the communication interface 703 may be connected via the bus 704. Figure 6 The contents of the processor 601, memory 602, communication interface 603, and bus 605 are not repeated here. Figure 7 The structure shown in the figure does not constitute a limitation on the management device 700, except Figure 7 In addition to the components shown, the management device 700 may also include more or fewer components than shown, or combine certain components, or arrange the components differently.

[0130] In some possible implementations, the management device 403 runs a FM process for managing memory resources provided by each CXL memory device in the memory pool 401 . Accordingly, the management device 403 is configured to perform memory management, such as memory allocation, on the multiple CXL memory devices.

[0131] In some possible implementations, the management device 403 may maintain information related to the memory resources of multiple CXL memory devices, such as memory type, memory size, or memory address. In still other possible implementations, the management device 403 may also maintain the connection relationships between multiple computing devices and multiple CXL memory devices. In other possible implementations, the management device 403 may also maintain the memory allocation status of multiple CXL memory devices. For example, the management device 403 may use a table to maintain the information related to the memory resources of the multiple CXL memory devices, the connection relationships between the multiple computing devices and the multiple CXL memory devices, and the memory allocation status of the multiple CXL memory devices.

[0132] In an embodiment of the present application, the management device 403 is configured to obtain the memory requirements of the first computing device or the second computing device, and allocate memory resources in multiple CXL memory devices to the first computing device or the second computing device based on the memory requirements of the first computing device or the second computing device.

[0133] Figure 8 A schematic diagram of a memory access method provided by an embodiment of the present application. The scheme is described by taking the interaction between a first computing device and a first CXL memory device as an example, wherein the first computing device is a computing device connected to a CXL port of the first CXL memory device. Figure 8 , the memory access method may include:

[0134] S801: A first computing device sends a memory access request to a first CXL memory device in response to a communication request sent by a second computing device.

[0135] The second computing device is a computing device connected to the first computing device via a second CXL memory device. The communication request is used to request access to the memory space of the first CXL memory device. The memory access request is used to request access to the memory space of the first CXL memory device.

[0136] In some possible implementations, a first computing device receives a communication request from a second computing device and, based on the communication request, sends a memory access request to the first CXL memory device. In this implementation, network communication between the first and second computing devices allows the second computing device to quickly and efficiently access the first CXL memory device through the first computing device.

[0137] Specifically, the memory access request may be a data read request or a data write request. Accordingly, in S801, the first computing device sending the memory access request to the first CXL memory device may include: the first computing device sending a data read request or a data write request to the first CXL memory device. The data read request is used to request a read operation to be performed on the memory space of the first CXL memory device. The data write request is used to request a write operation to be performed on the memory space of the first CXL memory device.

[0138] For example, taking a data read request as an example, the communication request may include the storage location of the first data in the first CXL memory device. Accordingly, the process of triggering the first computing device to send a memory access request to the first CXL memory device may include: the first computing device generating a memory access request based on the storage location of the first data in the first CXL memory device, requesting to read the first data from the first CXL memory device.

[0139] In the above example, through network communication between the first computing device and the second computing device, and carrying the storage location of the first data in the first CXL memory device in the communication request, the second computing device can quickly and efficiently complete the process of performing a read operation in the first CXL memory device through the first computing device.

[0140] For example, using a data write request as an example, the communication request may include the storage location of the second data in the second CXL memory device. Accordingly, triggering the first computing device to send a memory access request to the first CXL memory device includes: the first computing device reading the second data from the second CXL memory device based on the storage location of the second data in the second CXL memory device; and generating a memory access request based on the read second data to request writing the second data to the first CXL memory device.

[0141] In the above example, by using network communication between the first and second computing devices and including the storage location of the second data in the second CXL memory device in the communication request, the second computing device can quickly and efficiently complete the process of performing a write operation in the first CXL memory device via the first computing device. Furthermore, by performing data transmission via the second CXL memory device, which is commonly connected between the first and second computing devices, data transmission based on shared memory is implemented, effectively reducing memory access latency. Furthermore, by including the storage location of the second data in the second CXL memory device in the communication request, rather than the stored data itself, the data size of the communication request can be greatly reduced, allowing the communication request to be quickly sent to the first computing device, effectively reducing data write latency and improving data write efficiency.

[0142] S802: A first CXL memory device receives a memory access request sent by a first computing device.

[0143] S803: The first CXL memory device performs a memory access operation indicated by the memory access request based on the memory access request.

[0144] Wherein, based on the fact that the memory access request is a data read request or a data write request, the memory access operation may be a read operation or a write operation.

[0145] In some possible implementations, when the memory access request indicates a read operation, the first CXL memory device performs a read operation to read the first data and returns the read first data to the first computing device. For example, the first CXL memory device may obtain the storage location of the first data carried in the memory access request in the first CXL memory device and, based on the storage location of the first data in the first CXL memory device, perform a read operation to read the first data.

[0146] For example, after the first computing device obtains the first data, it can write the first data to the second CXL memory device for reading by the second computing device. In this way, by writing the first data to the second CXL memory device, the second CXL memory device can subsequently access the second CXL memory device to read the first data.

[0147] Furthermore, in some possible implementations, after writing the read first data into the second CXL memory device, the first computing device may return a successful write notification to the second computing device to notify the second computing device that the first data has been successfully written into the second CXL memory device.

[0148] In some possible implementations, when the memory access request indicates a write operation, the first CXL memory device performs the write operation to write the second data. For example, the first CXL memory device may obtain the second data carried in the memory access request and write the second data to the first CXL memory device.

[0149] Furthermore, in some possible implementations, after writing the second data to the first CXL memory device, the first CXL memory device may also return a successful write notification to the first computing device, notifying the first computing device that the second data has been written to the first CXL memory device. Furthermore, after receiving the successful write notification, the first computing device may also return a successful write notification to the second computing device, notifying the second computing device that the second data has been successfully written to the first CXL memory device.

[0150] In this way, a memory access solution based on read operations or write operations is provided, so that a computing device can implement read operations or write operations based on a CXL memory device by accessing the memory space of the CXL memory device in the memory pool.

[0151] The technical solution provided by the embodiments of the present application connects multiple computing devices to multiple CXL memory devices via CXL cables, wherein each computing device is connected to multiple different CXL memory devices, allowing each computing device to access one or more CXL memory devices connected to it via the CXL cables. Furthermore, each CXL memory device is connected to multiple different computing devices, wherein any two computing devices are connected to a common CXL memory device, so that each computing device has at least one memory space with which data can be shared between the other computing devices. On this basis, each computing device can not only access the CXL memory devices connected to it via the CXL cables, but can also access the CXL memory devices connected to other computing devices via other computing devices that are connected to the common CXL memory device, thereby achieving memory sharing among multiple computing devices in a memory pool. Furthermore, through network communication between the first computing device and the second computing device, the process of the second computing device accessing the first CXL memory device via the first computing device can be completed quickly and efficiently. In this way, there is no need to rely on CXL switches to form a memory pool, which can effectively reduce the latency of memory access, ensuring not only the performance of the memory pool but also the access performance of the computing devices.

[0152] above Figure 8 The memory access process is described by taking the computing device and CXL memory device as the execution subjects. Figure 9 Describe the memory access process in detail. Figure 9 A flowchart of a memory access method provided in an embodiment of the present application is provided. Taking the interaction process between a management device, a first computing device, and a second computing device as an example, the method includes the following steps S901-S910:

[0153] S901: The second computing device sends a memory allocation request to the management device.

[0154] The memory allocation request is used to request the management device to allocate memory resources in the memory pool to the second computing device. In some possible implementations, the memory allocation request may carry the memory requirements of the second computing device, such as memory type, memory size, etc.

[0155] S902: The management device receives a memory allocation request.

[0156] S903: The management device obtains the memory requirement of the second computing device in response to the memory allocation request of the second computing device.

[0157] In some possible implementations, the management device responds to the memory allocation request of the second computing device and obtains the memory requirement of the second computing device from the memory allocation request.

[0158] S904: The management device determines whether the memory of the multiple CXL memory devices connected to the second computing device meets the memory requirements of the second computing device. If the memory of the multiple CXL memory devices connected to the second computing device meets the memory requirements of the second computing device, the management device executes S905 to S906. If the memory of the multiple CXL memory devices connected to the second computing device does not meet the memory requirements of the second computing device, the management device executes S907.

[0159] In some possible implementations, using the memory type indicated by the memory requirement as the target type and the memory size as the target capacity as an example, the process for determining whether the memory of multiple CXL memory devices connected to the second computing device meets the memory requirement of the second computing device may include: the management device determining whether the sum of the remaining available capacity of the target type of memory in the multiple CXL memory devices connected to the second computing device is greater than or equal to the target capacity. This provides a method for determining whether the memory requirement of the second computing device is met based on memory type and memory size. This ensures that memory that meets the memory requirement is allocated to the second computing device, thereby ensuring accurate memory allocation.

[0160] If the sum of the remaining available capacities of the target type of memory in the plurality of CXL memory devices connected to the second computing device is greater than or equal to the target capacity, then it is determined that the memory of the plurality of CXL memory devices connected to the second computing device meets the memory requirement of the second computing device. If the sum of the remaining available capacities of the target type of memory in the plurality of CXL memory devices connected to the second computing device is less than the target capacity, then it is determined that the memory of the plurality of CXL memory devices connected to the second computing device does not meet the memory requirement of the second computing device.

[0161] The management device may maintain information related to the memory resources of multiple CXL memory devices, such as memory type, memory size, or memory address. In some possible implementations, the management device may use the maintained information related to the memory resources of the multiple CXL memory devices to perform the process of determining in S904 whether the memory resources of the multiple CXL memory devices connected to the second computing device meet the memory requirements of the second computing device.

[0162] S905 : The management device allocates a first memory matching the memory requirement to the second computing device from a plurality of CXL memory devices connected to the second computing device.

[0163] Matching the memory requirement means having the same memory type and size as those indicated by the memory requirement. The first memory may be memory resources provided by one or more CXL memory devices among a plurality of CXL memory devices connected to the second computing device.

[0164] In some possible implementations, after the management device determines a first memory device that matches the memory requirement among multiple CXL memory devices, it may send the memory address of the first memory device to the second computing device, so that the second computing device can subsequently access the memory space of the first memory device based on the memory address. The memory address may be a memory address segment.

[0165] S906: The second computing device accesses the memory space of the first memory through the CXL cable.

[0166] In some possible implementations, the process in S906 whereby the second computing device accesses the memory space of the first memory through the CXL cable may include the following steps 1 to 3:

[0167] Step 1: The second computing device sends a memory access request to the CXL memory device where the first memory is located.

[0168] The second computing device may send a memory access request to the CXL memory device where the first memory is located based on the memory address of the first memory.

[0169] Step 2: The CXL memory device where the first memory is located receives a memory access request sent by the second computing device.

[0170] Step 3: The CXL memory device where the first memory is located performs the memory access operation indicated by the memory access request based on the memory access request.

[0171] In some possible implementations, the CXL memory device where the first memory resides performs a memory access operation, such as a read operation or a write operation, of the second computing device in the memory space. For related details, see the above S703 and will not be repeated here.

[0172] The above embodiments shown in S905 to S906 provide a detailed description of the situation where the memory of the plurality of CXL memory devices connected to the second computing device meets the memory requirement of the second computing device.

[0173] S907: The management device determines whether the memory requirements of the multiple CXL memory devices connected to the first computing device meet the memory requirements of the second computing device. If the memory requirements of the multiple CXL memory devices connected to the first computing device meet the memory requirements of the second computing device, the management device executes S908 to S909. If the memory requirements of the multiple CXL memory devices connected to the first computing device do not meet the memory requirements of the second computing device, the management device executes S910.

[0174] The first computing device may be any computing device among the multiple computing devices except the second computing device.

[0175] S908: The management device allocates a second memory matching the memory requirement to the second computing device from the multiple CXL memory devices connected to the first computing device.

[0176] The second memory may be a memory resource provided by one or more CXL memory devices among a plurality of CXL memory devices connected to the first computing device.

[0177] In some possible implementations, taking the second memory as the memory of the first CXL memory device as an example, after the management device determines the memory of the first CXL memory device that matches the memory requirement among multiple CXL memory devices, it can send the device information of the first computing device and the memory address of the first CXL memory device to the second computing device, so that the second computing device can subsequently access the memory space of the first CXL memory device through the first computing device.

[0178] In this way, by sending the device information of the first computing device and the memory address of the first CXL memory device to the second computing device, the second computing device can subsequently implement network communication with the first computing device based on the device information of the first computing device and the memory address of the first CXL memory device, thereby ensuring smooth memory access.

[0179] S909: The second computing device accesses the memory space of the second memory through the first computing device.

[0180] In some possible implementations, taking the second memory as the memory of the first CXL memory device as an example, the process in S909 in which the second computing device accesses the memory space of the second memory through the first computing device may include the following steps 1 to 4:

[0181] Step 1: The second computing device sends a communication request to the first computing device based on the device information of the first computing device.

[0182] The communication request is used to request access to the memory space of the first CXL memory device. In some possible implementations, the communication request may include the memory address of the second memory, such as the memory address of the first CXL memory device. Furthermore, the communication request may also include the type of the requested operation, such as information indicating whether it is a read operation or a write operation.

[0183] Step 2: The first computing device receives a communication request from the second computing device, and sends a memory access request to the first CXL memory device based on the communication request.

[0184] The first computing device may send a memory access request to the first CXL memory device based on the memory address of the first CXL memory device and the type of requested operation carried in the communication request. The memory access request may carry the memory address of the first CXL memory device and the type of requested operation.

[0185] Step 3: The first CXL memory device receives a memory access request sent by the first computing device.

[0186] Step 4: Based on the memory access request, the first CXL memory device performs the memory access operation indicated by the memory access request.

[0187] In some possible implementations, the first CXL memory device performs a read operation or a write operation in the memory space. For related details, refer to the above S803 and will not be repeated here.

[0188] The above embodiments shown in S907 to S909 provide detailed descriptions of the situation where the memory of the multiple CXL memory devices connected to the second computing device does not meet the memory requirement of the second computing device.

[0189] S910: The management device returns a message indicating that the memory request has failed to the second computing device.

[0190] In the above embodiment, the management device preferentially allocates memory to one or more CXL memory devices directly connected to the second computing device, and secondarily allocates memory to the CXL memory device connected to the first computing device.

[0191] Furthermore, in other embodiments, if the memory of multiple CXL memory devices connected to the second computing device can meet the memory needs of the second computing device, but some of the memory is occupied by other computing devices, the management device can coordinate the interruption of the other computing devices and control the third computing device that occupies the memory to release the memory, thereby ensuring that memory is supplied to the current computing device first.

[0192] The technical solution provided by the embodiment of the present application is that multiple computing devices are connected to multiple CXL memory devices through CXL cables, wherein each computing device is respectively connected to multiple different CXL memory devices, so that each computing device can access one or more CXL memory devices connected to it through the CXL cable. Moreover, each CXL memory device is respectively connected to multiple different computing devices, wherein any two computing devices are commonly connected to a CXL memory device, so that each computing device and other computing devices have at least one memory space for sharing data. On this basis, each computing device can not only access the CXL memory device connected to it through the CXL cable, but also access the CXL memory device connected to other computing devices through other computing devices commonly connected to a CXL memory device, thereby realizing memory sharing between multiple computing devices in the memory pool. Among them, by deploying a management device, the management device is used to manage the memory of multiple CXL memory devices in the memory pool. If the memory requirements of multiple CXL memory devices connected to a second computing device are insufficient, but the memory requirements of multiple CXL memory devices connected to a first computing device are sufficient, the memory of the first CXL memory device that meets the requirements can be allocated to the second computing device. Subsequently, network communication between the first and second computing devices allows the second computing device to quickly and efficiently access the first CXL memory device through the first computing device. This eliminates the need to rely on CXL switches to form a memory pool, effectively reducing memory access latency and ensuring both the performance of the memory pool and the access performance of the computing devices.

[0193] It should be noted that by applying the memory pool provided in the embodiments of this application, each computing device can access the memory space of any CXL memory device in the memory pool. For example, accessing the memory space of a directly connected CXL memory device requires a latency of less than 200ns. Even if accessing the memory space through a computing device, the latency is limited to a single computing device jump, keeping the latency stable to less than 400ns. This reduces memory access latency and ensures stable memory pool performance. Compared to related techniques that use CXL switches to access memory space, this approach incurs a greater latency, especially when accessing memory space across multiple stages of CXL switches, which can significantly impact memory pool performance.

[0194] The above mainly introduces the scheme of the embodiment of the present application from the perspective of method. It is understandable that the computing device (such as server) in the embodiment of the present application includes a hardware structure and / or software module corresponding to the execution of each function in order to realize the above functions. Those skilled in the art should easily appreciate that, in conjunction with the units and algorithm steps of each example described in the embodiment disclosed herein, the embodiment of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in a way that hardware or computer software drives hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the embodiment of the present application.

[0195] Figure 10 This is a schematic diagram of the structure of a memory access device provided in an embodiment of the present application. The memory access device is applied to a first computing device in a computing system. The computing system includes a memory pool and multiple computing devices. The memory pool includes multiple computing interconnect protocol CXL memory devices. Each CXL memory device includes multiple CXL ports. Each computing device includes multiple CXL ports. The multiple CXL ports on each CXL memory device are respectively connected to different computing devices. The multiple CXL ports on each computing device are respectively connected to different CXL memory devices. Any two computing devices among the multiple computing devices are connected through at least one CXL memory device. Figure 10 , the memory access device includes a sending module 1001.

[0196] in,

[0197] A sending module 1001 is configured to send a memory access request to a first CXL memory device in response to a communication request sent by a second computing device, wherein the communication request is used to request access to a memory space of the first CXL memory device, and the memory access request is used to request access to a memory space of the first CXL memory device;

[0198] The first computing device is a computing device connected to a CXL port of the first CXL memory device; and the second computing device is a computing device connected to the first computing device via the second CXL memory device.

[0199] The technical solution provided by the embodiments of the present application connects multiple computing devices to multiple CXL memory devices via CXL cables, wherein each computing device is connected to multiple different CXL memory devices, allowing each computing device to access one or more CXL memory devices connected to it via the CXL cables. Furthermore, each CXL memory device is connected to multiple different computing devices, wherein any two computing devices are connected to a common CXL memory device, so that each computing device has at least one memory space with which data can be shared between the other computing devices. On this basis, each computing device can not only access the CXL memory devices connected to it via the CXL cables, but can also access the CXL memory devices connected to other computing devices via other computing devices that are connected to the common CXL memory device, thereby achieving memory sharing among multiple computing devices in a memory pool. Furthermore, through network communication between the first computing device and the second computing device, the process of the second computing device accessing the first CXL memory device via the first computing device can be completed quickly and efficiently. In this way, there is no need to rely on CXL switches to form a memory pool, which can effectively reduce the latency of memory access, ensuring not only the performance of the memory pool but also the access performance of the computing devices.

[0200] In some possible implementations, the memory access request is a data read request, and the data read request is used to request to perform a read operation on a memory space of the first CXL memory device;

[0201] The device also includes a writing module for:

[0202] The read first data is written to the second CXL memory device.

[0203] In some possible implementations, the memory access request is a data write request, and the data write request is used to request to perform a write operation in a memory space of the first CXL memory device;

[0204] The device also includes:

[0205] a reading module, configured to read second data from a second CXL memory device;

[0206] A generating module is used to generate the memory access request based on the read second data.

[0207] Figure 11This is a structural diagram of a memory access device provided in an embodiment of the present application. The memory access device is applied to a management device, which is used to manage memory in a memory pool in a computing system. The computing system includes a memory pool and multiple computing devices. The memory pool includes multiple CXL memory devices. Each CXL memory device includes multiple CXL ports. Each computing device includes multiple CXL ports. The multiple CXL ports on each CXL memory device are respectively connected to different computing devices. The multiple CXL ports on each computing device are respectively connected to different CXL memory devices. Any two computing devices in the multiple computing devices are connected through at least one CXL memory device. Figure 11 The memory access device includes an acquisition module 1101 and an allocation module 1102.

[0208] An acquisition module 1101 is configured to acquire a memory requirement of a second computing device in response to a memory allocation request of the second computing device;

[0209] an allocation module 1102 for allocating memory of a first CXL memory device that meets the memory requirement from among the multiple CXL memory devices connected to the first computing device to the second computing device, if the memory of the multiple CXL memory devices connected to the second computing device does not meet the memory requirement of the second computing device, but the memory of the multiple CXL memory devices connected to the first computing device meets the memory requirement of the second computing device;

[0210] The first computing device is a computing device connected to a CXL port of the first CXL memory device; and the second computing device is a computing device connected to the first computing device via the second CXL memory device.

[0211] The technical solution provided by the embodiment of the present application is that multiple computing devices are connected to multiple CXL memory devices through CXL cables, wherein each computing device is respectively connected to multiple different CXL memory devices, so that each computing device can access one or more CXL memory devices connected to it through the CXL cable. Moreover, each CXL memory device is respectively connected to multiple different computing devices, wherein any two computing devices are commonly connected to a CXL memory device, so that each computing device and other computing devices have at least one memory space for sharing data. On this basis, each computing device can not only access the CXL memory device connected to it through the CXL cable, but also access the CXL memory device connected to other computing devices through other computing devices commonly connected to a CXL memory device, thereby realizing memory sharing between multiple computing devices in the memory pool. Among them, by deploying a management device, the management device is used to manage the memory of multiple CXL memory devices in the memory pool. If the memory requirements of multiple CXL memory devices connected to a second computing device are insufficient, but the memory requirements of multiple CXL memory devices connected to a first computing device are sufficient, the memory of a first CXL memory device that meets the requirements can be allocated to the second computing device. This allows the second computing device to quickly and efficiently access the first CXL memory device through the first computing device via network communication between the first and second computing devices. This eliminates the need to rely on CXL switches to form a memory pool, effectively reducing memory access latency and ensuring both the performance of the memory pool and the access performance of the computing devices.

[0212] In some possible implementations, the memory requirement indicates that the memory type is a target type and the memory size is a target capacity;

[0213] The device also includes a determination module, configured to:

[0214] If the sum of the remaining available capacities of the target type of memory in the plurality of CXL memory devices connected to the second computing device is greater than or equal to the target capacity, determining that the memory of the plurality of CXL memory devices connected to the second computing device meets the memory requirement of the second computing device;

[0215] If the sum of the remaining available capacities of the target type of memory in the plurality of CXL memory devices connected to the second computing device is less than the target capacity, it is determined that the memory of the plurality of CXL memory devices connected to the second computing device does not meet the memory requirement of the second computing device.

[0216] In some possible implementations, the allocation module 1102 is specifically configured to:

[0217] The device information of the first computing device and the memory address of the first CXL memory device are sent to the second computing device, so that the second computing device can send a communication request to the first computing device, where the communication request is used to request access to the memory space of the first CXL memory device.

[0218] The present application also provides a CXL memory device, comprising a CXL controller and a memory medium coupled to each other. The memory medium is configured to store computer program instructions, and the CXL controller is configured to invoke the computer program instructions in the memory medium to execute the contents executed by the CXL memory device in the memory access method described in the above embodiment.

[0219] An embodiment of the present application further provides an electronic device comprising a processor and a memory, the processor and the memory being coupled. The memory is configured to store computer program instructions, and the processor is configured to invoke the computer program instructions in the memory to execute the contents executed by the computing device or management device in the memory access method described in the above embodiment. In the embodiment of the present application, the computing device or the management device may be an electronic device.

[0220] An embodiment of the present application further provides a computer-readable storage medium storing computer program instructions for causing a CXL memory device or an electronic device to execute the memory access method as shown in the above embodiment.

[0221] The embodiments of the present application further provide a computer program product including computer program instructions. When the computer program instructions are executed on a CXL memory device or a computing device, the CXL memory device or the electronic device executes the memory access method as shown in the above embodiments.

[0222] The CXL memory device, electronic device (such as a computing device or management device), computer-readable storage medium, or computer program product provided in the embodiments of this application are all configured to execute the corresponding methods provided above. Therefore, the beneficial effects achieved by these devices can be referenced to the beneficial effects of the corresponding methods provided above and will not be further elaborated here.

[0223] Through the description of the above implementation methods, those skilled in the art can clearly understand that for the convenience and brevity of description, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device (such as a computing device) can be divided into different functional modules to complete all or part of the functions described above. The specific working processes of the above-described systems, devices (such as computing devices) and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0224] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices (such as computing devices) and methods can be implemented in other ways. For example, the device (such as computing device) embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0225] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0226] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0227] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of the method of each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as flash memory, mobile hard disk, read-only memory, random access memory, magnetic disk or optical disk.

[0228] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A memory access method, characterized in that: A first computing device is used in a computing system, the computing system comprising a memory pool and multiple computing devices, the memory pool comprising multiple Compute Interconnect Protocol (CXL) memory devices, each CXL memory device comprising multiple CXL ports, and each computing device comprising multiple CXL ports; wherein the multiple CXL ports on each CXL memory device are directly connected to different computing devices, the multiple CXL ports on each computing device are directly connected to different CXL memory devices, and any two computing devices among the multiple computing devices are connected via at least one CXL memory device; A first number of CXL ports in each computing device is determined based on the number of the plurality of computing devices and a second number of CXL ports in each CXL memory device; wherein the first number is positively correlated with the number of the plurality of computing devices and negatively correlated with the second number; The method comprises: In response to a communication request sent by the second computing device, send a memory access request to the first CXL memory device, wherein the communication request is used to request access to a memory space of the first CXL memory device, and the memory access request is used to request access to the memory space of the first CXL memory device; The first computing device is a computing device directly connected to a CXL port of the first CXL memory device; and the second computing device is a computing device directly connected to the first computing device via a second CXL memory device.

2. The method according to claim 1, characterized in that The memory access request is a data read request, and the data read request is used to request to perform a read operation on the memory space of the first CXL memory device; After sending the memory access request to the first CXL memory device, the method further includes: The read first data is written into the second CXL memory device.

3. The method according to claim 1, characterized in that The memory access request is a data write request, and the data write request is used to request to perform a write operation in the memory space of the first CXL memory device; Before sending the memory access request to the first CXL memory device, the method further includes: reading second data from the second CXL memory device; The memory access request is generated based on the read second data.

4. A memory access method, characterized in that: Applied to a management device, the management device is used to perform memory management on a memory pool in a computing system; the computing system includes a memory pool and multiple computing devices, the memory pool includes multiple Computing Interconnect Protocol (CXL) memory devices, each CXL memory device includes multiple CXL ports, and each computing device includes multiple CXL ports; wherein the multiple CXL ports on each CXL memory device are directly connected to different computing devices, the multiple CXL ports on each computing device are directly connected to different CXL memory devices, and any two computing devices among the multiple computing devices are connected via at least one CXL memory device; A first number of CXL ports in each computing device is determined based on the number of the plurality of computing devices and a second number of CXL ports in each CXL memory device; wherein the first number is positively correlated with the number of the plurality of computing devices and negatively correlated with the second number; The method comprises: In response to a memory allocation request from a second computing device, obtaining a memory requirement of the second computing device; If the memory of the plurality of CXL memory devices connected to the second computing device does not meet the memory requirement of the second computing device, but the memory of the plurality of CXL memory devices connected to the first computing device meets the memory requirement of the second computing device, allocating the memory of the first CXL memory device that meets the memory requirement to the second computing device from among the plurality of CXL memory devices connected to the first computing device; The first computing device is a computing device directly connected to a CXL port of the first CXL memory device; and the second computing device is a computing device directly connected to the first computing device via a second CXL memory device.

5. The method according to claim 4, characterized in that The memory requirement indicates that the memory type is the target type and the memory size is the target capacity; The method further comprises: If the sum of the remaining available capacities of the target type of memory in the plurality of CXL memory devices connected to the second computing device is greater than or equal to the target capacity, determining that the memory of the plurality of CXL memory devices connected to the second computing device meets the memory requirement of the second computing device; If the sum of the remaining available capacities of the target type of memory in the plurality of CXL memory devices connected to the second computing device is less than the target capacity, it is determined that the memory of the plurality of CXL memory devices connected to the second computing device does not meet the memory requirement of the second computing device.

6. The method according to claim 4 or 5, characterized in that Allocating memory of a first CXL memory device that meets the memory requirement to the second computing device from the plurality of CXL memory devices connected to the first computing device includes: The device information of the first computing device and the memory address of the first CXL memory device are sent to the second computing device, so that the second computing device can send a communication request to the first computing device, wherein the communication request is for requesting access to the memory space of the first CXL memory device.

7. A computing system, characterized in that The computing system includes a memory pool and multiple computing devices. The memory pool includes multiple Computing Interconnect Protocol (CXL) memory devices. Each CXL memory device includes multiple CXL ports. Each computing device includes multiple CXL ports. The multiple CXL ports on each CXL memory device are directly connected to different computing devices. The multiple CXL ports on each computing device are directly connected to different CXL memory devices. Any two computing devices among the multiple computing devices are connected through at least one CXL memory device. A first number of CXL ports in each computing device is determined based on the number of the plurality of computing devices and a second number of CXL ports in each CXL memory device; wherein the first number is positively correlated with the number of the plurality of computing devices and negatively correlated with the second number; a first computing device, configured to send a memory access request to a first CXL memory device in response to a communication request sent by a second computing device, wherein the communication request is for requesting access to a memory space of the first CXL memory device, and the memory access request is for requesting access to the memory space of the first CXL memory device; the first computing device is a computing device directly connected to a CXL port of the first CXL memory device; and the second computing device is a computing device directly connected to the first computing device via the second CXL memory device; The first CXL memory device is configured to receive a memory access request sent by the first computing device, and based on the memory access request, perform a memory access operation indicated by the memory access request.

8. The system according to claim 7, characterized in that The number of the plurality of CXL memory devices is determined based on the number of the plurality of computing devices, a first number of CXL ports in each computing device, and a second number of CXL ports in each CXL memory device; wherein the number of the plurality of CXL memory devices is positively correlated with the number of the plurality of computing devices and the first number, and negatively correlated with the second number.

9. An electronic device, characterized in that: The electronic device includes a processor and a memory; the processor and the memory are coupled; The memory is used to store computer program instructions; The processor is configured to call the computer program instructions in the memory to execute the method according to any one of claims 1-3 or 4-6.

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