Control circuit for preventing jitter of multi-level logic control, PCB board and system

Abstract

The application relates to the technical field of automatic driving domain control systems, in particular to a control circuit, a PCB and a system for preventing multi-level logic control jitter. The control circuit comprises a signal input end, a signal output end and a logic control module. The logic control module is used for performing multi-level logic control on an input signal transmitted by the signal input end and outputting to the signal output end. A mirror current source is used for maintaining a voltage signal of a control end of the logic control module to prevent the logic control module from generating jitter when outputting a signal. A direct current bias power supply is used for providing a stabilized direct current power supply for the mirror current source and the logic control module. The application uses the mirror current source to maintain the voltage signal of the control end of the logic control module to prevent the logic control module from generating jitter when outputting a signal, has universal applicability, can improve the stability of the system, avoids the case of misoperation, and reduces the production cost of the product.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of automatic driving domain control systems, and in particular to a control circuit, a PCB board and a system for preventing multi-level logic control jitter. BACKGROUND

[0002] Signal receiving, processing and judgment output are crucial in automatic driving systems. In controller system integration, correct processing and judgment of input signals can ensure that the vehicle's logic execution is accurate, thereby ensuring driving safety and performance. Therefore, in automatic driving technology, the accuracy and reliability of signal processing play a key role in the stability and performance of the system.

[0003] In the prior art, in order to prevent circuit signal jitter to ensure the reliability and stability of vehicle signals, level conversion or software control methods are usually used. Generally, level conversion: by using appropriate level conversion circuits, input signals are converted from one level to another, which can help reduce signal jitter. Common level conversion circuits include comparators, flip-flops, etc. Software control: by using software algorithms in the control system to process and control signals to ensure signal stability and accuracy, signals can be filtered, calibrated and processed to reduce the effects of jitter and noise.

[0004] Although the above-mentioned level conversion and software control methods can achieve signal stability control to some extent, in multi-level signal transmission circuits, level conversion and software control methods are not sufficient to meet the control requirements of multi-level signal jitter. On the one hand, simple level conversion is greatly affected by temperature and voltage changes, which may result in poor stability; on the other hand, software control occupies resources and is inefficient, resulting in insufficient signal control stability.

[0005] In the prior art, there is a lack of a technical solution that can stably prevent multi-level control signal jitter. SUMMARY

[0006] The present application provides a control circuit, a PCB board and a system for preventing multi-level logic control jitter to solve the technical problem of insufficient stability of existing technology in controlling multi-level signals in the background art.

[0007] In a first aspect, the present application provides a control circuit for preventing multi-level logic control jitter, comprising:

[0008] a signal input end;

[0009] a signal output end;

[0010] a logic control module for performing multi-level logic control on the input signal transmitted by the signal input end and outputting to the signal output end;

[0011] a mirror current source for maintaining the voltage signal of the control end of the logic control module to prevent the logic control module from generating jitter when outputting the signal;

[0012] a DC bias power supply for providing a stabilized DC power supply to the mirror current source and the logic control module.

[0013] In some preferred embodiments, the mirror current source comprises a first transistor, a second transistor, a first resistor and a second resistor for adjusting the current flowing through the mirror current source, the emitter of the first transistor is connected to the output end of the DC bias power supply, the collector is connected to the first control end of the logic control module through the second resistor, and the base is connected to the emitter of the second transistor; the base of the second transistor is connected to the collector of the first transistor, and the collector is connected to the second control end of the logic control module; the first resistor is connected in parallel between the emitter and the base of the first transistor.

[0014] In some preferred embodiments, the first transistor and the second transistor are both PNP type transistors.

[0015] In some preferred embodiments, the logic control module comprises an input control module and an output control module, the input control module comprises at least a first MOS transistor and a second MOS transistor, the gate of the first MOS transistor is connected to the signal input end, the drain is connected to the collector of the first transistor through the second resistor, and the source is grounded; the gate of the second MOS transistor is connected to the drain of the first MOS transistor, the drain is connected to the collector of the second transistor, and the source is grounded; the output control module comprises at least a third transistor and a fourth transistor, the base of the third transistor is connected to the drain of the second MOS transistor, the collector is connected to the base of the fourth transistor, and the emitter is grounded; the emitter of the fourth transistor is connected to the output end of the DC bias power supply, and the collector is connected to the signal output end.

[0016] In some preferred embodiments, the first MOS transistor and the second MOS transistor are N-channel MOS transistors, the third transistor is a PNP type transistor, and the fourth transistor is an NPN type transistor.

[0017] In some preferred embodiments, the circuit further comprises an anti-interference module, the anti-interference module at least comprising a third resistor, a fourth resistor and a first capacitor, the third resistor being connected between the signal input end and the gate of the first MOS tube; one end of the fourth resistor being connected between the third resistor and the gate of the first MOS tube, and the other end being grounded; one end of the first capacitor being connected between the third resistor and the gate of the first MOS tube, and the other end being grounded.

[0018] In some preferred embodiments, the anti-interference module further comprises an ESD static tube, the negative electrode of the ESD static tube being connected between the third resistor and the gate of the first MOS tube, and the positive electrode being grounded.

[0019] In some preferred embodiments, the logic control module further comprises a delay control module, the delay control module at least comprising a second capacitor, one end of the second capacitor being connected between the drain of the second MOS tube and the base of the third triode, and the other end being grounded.

[0020] In a second aspect, the present application provides a PCB board comprising the control circuit for preventing multi-level logic control jitter as described in the first aspect.

[0021] In a third aspect, the present application provides an automatic driving domain control system, comprising at least the control circuit for preventing multi-level logic control jitter as described in the first aspect, or the PCB board as described in the second aspect.

[0022] The present application has the following beneficial effects:

[0023] The present application uses a mirror current source to maintain the voltage signal of the control end of the logic control module, so as to prevent the logic control module from generating jitter when outputting a signal, has universal applicability, can improve the stability of the system, avoids the case of misoperation, and reduces the production cost of the product. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 The present application provides a control circuit for preventing multi-level logic control jitter.

[0025] Figure 2 The present application provides a control circuit for preventing multi-level logic control jitter.

[0026] Figure 3 The present application provides a control circuit for preventing multi-level logic control jitter.

[0027] In some preferred embodiments, the circuit further comprises an anti-interference module, the anti-interference module at least comprising a third resistor, a fourth resistor and a first capacitor, the third resistor being connected between the signal input end and the gate of the first MOS tube; one end of the fourth resistor being connected between the third resistor and the gate of the first MOS tube, and the other end being grounded; one end of the first capacitor being connected between the third resistor and the gate of the first MOS tube, and the other end being grounded.

[0028] 20 - logic control module, T1 - first MOS transistor, T2 - second MOS transistor, Q3 - third transistor, Q4 - fourth transistor;

[0029] 30 - signal output terminal;

[0030] 40 - mirror current source, Q1 - first transistor, Q2 - second transistor, R1 - first resistor, R2 - second resistor, C2 - second capacitor;

[0031] 50 - DC bias power supply;

[0032] 60 - anti-interference module, R3 - third resistor, R4 - fourth resistor, C1 - first capacitor, Z1 - ESD static tube;

[0033] 100 - PCB board, 200 - control circuit for preventing multi-level logic control jitter. DETAILED DESCRIPTION

[0034] The preferred embodiments of the present application will be described in detail with reference to the drawings, so that the advantages and features of the present application can be more easily understood by those skilled in the art, and the scope of protection of the present application can be more clearly defined.

[0035] Please refer to the drawings, wherein the same component symbols represent the same components, and the principles of the present application are exemplified in an appropriate operating environment. The following description is based on the exemplified embodiments of the present application, which should not be regarded as limiting other embodiments of the present application not described in detail herein.

[0036] The term "module" used herein can be a software or hardware object executed on the operating system. Different components, modules, engines and services described herein can be implemented as implemented objects on the operating system. The apparatus and method described herein can be implemented in software, of course, but also in hardware, all within the scope of protection of the present application.

[0037] In this paper, the phrase "embodiment" means that the specific features, structures or characteristics described in conjunction with the embodiment can be included in at least one embodiment of the present application. The phrase appears at various places in the specification does not necessarily refer to the same embodiment, nor is it independent or alternative to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0038] In the description of the present application, it is necessary to point out that, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "linking" should be understood in a broad sense, for example, can be fixed connection, can also be detachable connection, or integrally connected; can be mechanical connection, or electrical connection or can communicate with each other; can be directly connected, or indirectly connected through intermediate medium, can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0039] Embodiment one

[0040] Please refer to Figure 1 , Figure 1 The structure of the control circuit for preventing the jitter of multi-level logic control provided by the embodiment of the present application is shown. The circuit includes a signal input end 10, a logic control module 20, a signal output end 30, a mirror current source 40 and a DC bias power supply 50.

[0041] In the embodiment, the signal input end 10 is connected with the input end of the logic control module 20. The output end of the logic control module 20 is connected with the signal output end 30, and the control end is connected with the output end of the mirror current source 40. The input end of the mirror current source 40 is connected with the output end of the DC bias power supply 50. The output end of the DC bias power supply 50 also provides a stabilized DC power supply for the logic control module 20.

[0042] Among them, the logic control module 20 is mainly used for multi-level logic control of the input signal transmitted by the signal input end 10, so as to output to the signal output end 30. The mirror current source 40 is mainly used for maintaining the voltage signal of the control end of the logic control module 20, so as to prevent the logic control module 20 from generating jitter when outputting the signal. The DC bias power supply 50 is mainly used for providing a stabilized DC power supply for the mirror current source 40 and the logic control module 20.

[0043] Through the above module connection, the working principle of the embodiment of the present application can be:

[0044] When the input signal of the signal input end 10 is valid, the logic control module 20 is excited to start the work of transmitting the signal. Under the action of the DC bias power supply 50, the mirror current source 40 is also excited. Then, the mirror current source 40 maintains the voltage signal of the control end of the logic control module 20, so as to prevent the logic control module 20 from generating jitter when outputting the signal. Finally, the signal is output to the signal output end 30 through multi-level control.

[0045] Embodiment two

[0046] On the basis of the above embodiment, the difference of the present embodiment is:

[0047] Please refer to Figure 2 , Figure 2 The circuit diagram of the control circuit for preventing multi-level logic control jitter is shown.

[0048] In the embodiment, the mirror current source 40 comprises a first transistor Q1, a second transistor Q2, a first resistor R1 and a second resistor R2. The emitter of the first transistor Q1 is connected with the output end of the DC bias power supply 50, the collector is connected with the first control end of the logic control module 20 through the second resistor R2, and the base is connected with the emitter of the second transistor Q2. The base of the second transistor Q2 is connected on the collector of the first transistor Q1, and the collector is connected with the second control end of the logic control module 20. The first resistor R1 is connected in parallel between the emitter and the base of the first transistor Q1. Among them, the first resistor R1 mainly plays a role of load resistor in the mirror current source 40. The second resistor R2 is mainly used for adjusting the current size flowing through the mirror current source 40, that is, the current size flowing through the mirror current source 40 can be adjusted by adjusting the resistance value of the second resistor R2.

[0049] In the embodiment, the first transistor Q1 and the second transistor Q2 are both PNP type transistors.

[0050] In the embodiment, the logic control module 20 comprises an input control module and an output control module. The input control module at least comprises a first MOS tube T1 and a second MOS tube T2, and the output control module at least comprises a third transistor Q3 and a fourth transistor Q4.

[0051] Among them, the gate of the first MOS tube T1 is connected with the signal input end 10, the drain is connected with the collector of the first transistor Q1 through the second resistor R2, and the source is grounded. The gate of the second MOS tube T2 is connected with the drain of the first MOS tube T1, the drain is connected with the collector of the second transistor Q2, and the source is grounded. The output control module at least comprises a third transistor Q3 and a fourth transistor Q4, the base of the third transistor Q3 is connected with the drain of the second MOS tube T2, the collector is connected with the base of the fourth transistor Q4, and the emitter is grounded. The emitter of the fourth transistor Q4 is connected with the output end of the DC bias power supply 50, and the collector is connected with the signal output end 30. The first MOS tube T1, the second MOS tube T2, the third transistor Q3 and the fourth transistor Q4 cooperate to perform the action of multi-level signal processing, so as to gradually improve the signal quality and accuracy.

[0052] In the embodiment, the first MOS tube T1 and the second MOS tube T2 are N-channel MOS tubes, the third transistor Q3 is a PNP type transistor, and the fourth transistor Q4 is an NPN type transistor.

[0053] In the embodiment, the circuit further comprises an anti-interference module 60, which at least comprises a third resistor R3, a fourth resistor, a first capacitor C1 and an ESD static tube Z1. The third resistor R3 is connected between the signal input end 10 and the gate of the first MOS tube T1. One end of the fourth resistor is connected between the third resistor R3 and the gate of the first MOS tube T1, and the other end is grounded. One end of the first capacitor C1 is connected between the third resistor R3 and the gate of the first MOS tube T1, and the other end is grounded. The negative electrode of the ESD static tube Z1 is connected between the third resistor R3 and the gate of the first MOS tube T1, and the positive electrode is grounded. Through the cooperation of the third resistor R3, the fourth resistor and the first capacitor C1, when the input signal exists glitches, transient fluctuations, or damped oscillations and other situations that do not meet the starting characteristics, the circuit can filter out to ensure that the latter stage does not trigger the corresponding action, avoiding frequent false actions. The ESD static tube Z1 can avoid the influence of static electricity on the circuit.

[0054] In the embodiment, the circuit can introduce the function of signal delay under the condition of meeting the anti-jitter function. Signal delay refers to artificially adding delay in the process of signal transmission or processing. In the automatic driving domain controller system integration, the receiving, processing and judgment of the signal are extremely important links, which are related to the correctness of the logic execution, and the function of signal delay can improve the correctness of the logic execution.

[0055] The logic control module 20 further comprises a delay control module, which at least comprises a second capacitor C2, one end of which is connected between the drain of the second MOS tube T2 and the base of the third transistor Q3, and the other end is grounded. The second capacitor C2 is mainly used to act as a threshold, and the length of the capacitor charging time can be adjusted by changing the capacitance value of the second capacitor C2, that is, the time for the voltage of the base of the third transistor Q3 to reach the conduction threshold is adjusted, thereby realizing the function of signal delay.

[0056] Through the above structural connection, the working principle of the embodiment of the present application is as follows:

[0057] When the input signal of the signal input end 10 is valid, that is, the input is high, the first MOS tube T1 is turned on through the voltage division effect of the ESD static tube Z1, the third resistor R3, the fourth resistor and the first capacitor C1, and at the same time, the second MOS tube T2 is turned off when the gate voltage is pulled down by the conduction of the first MOS tube T1. Under the action of the direct current bias power supply 50, the mirror current source 40 is excited, and after the delay of the second capacitor C2, the voltage signal of the base of the third transistor Q3 is maintained to prevent the logic control module 20 from producing jitter when outputting the signal, and the effect of delay is achieved. Finally, the signal is output to the signal output end 30 through the fourth transistor Q4.

[0058] It is worth mentioning that the input signal and the output signal maintain the same phase, and are applied to convert the vehicle interface level to the system digital I / O port level.

[0059] Embodiment three

[0060] As shown in Figure 3 The application provides a PCB 100 including the control circuit 200 for preventing jitter of multi-level logic control as described in embodiment one or embodiment two.

[0061] Embodiment four

[0062] The application provides an automatic driving domain control system including the control circuit for preventing jitter of multi-level logic control as described in the first embodiment or the second embodiment, or the PCB 100 as described in the third embodiment.

[0063] The application utilizes the topology of the mirror current source, uses passive semiconductor elements to achieve the purpose of delay and jitter prevention, and the delay and jitter prevention parameters can be adjusted as needed. The application is stable and reliable in the automatic driving domain controller, has universal applicability, can improve the system stability, and reduces the product cost.

[0064] The embodiments of the application are described in detail above in combination with the drawings, but the application is not limited to the above-described embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the purpose of the application.

Claims

1. A control circuit for preventing dithering of a multi-level logic control, comprising: The circuit comprises: a signal input end; a signal output end; a logic control module for performing multi-level logic control on an input signal transmitted by the signal input end and outputting to the signal output end; a mirror current source for maintaining a voltage signal at a control end of the logic control module to prevent the logic control module from generating jitter when outputting a signal; a DC bias power supply for providing a stabilized DC power supply to the mirror current source and the logic control module; wherein the mirror current source comprises a first transistor Q1, a second transistor Q2, a first resistor R1, and a second resistor R2 for adjusting the current flowing through the mirror current source, the emitter of the first transistor Q1 is connected to the output end of the DC bias power supply, the collector is connected to the first control end of the logic control module through the second resistor R2, and the base is connected to the emitter of the second transistor Q2; the base of the second transistor Q2 is connected to the collector of the first transistor Q1, and the collector is connected to the second control end of the logic control module; the first resistor R1 is connected in parallel between the emitter and the base of the first transistor Q1; the logic control module comprises an input control module and an output control module, the input control module comprises at least a first MOS transistor T1 and a second MOS transistor T2, the gate of the first MOS transistor T1 is connected to the signal input end, the drain is connected to the collector of the first transistor Q1 through the second resistor R2, and the source is grounded; the gate of the second MOS transistor T2 is connected to the drain of the first MOS transistor T1, the drain is connected to the collector of the second transistor Q2, and the source is grounded; the output control module comprises at least a third transistor Q3 and a fourth transistor Q4, the base of the third transistor Q3 is connected to the drain of the second MOS transistor T2, the collector is connected to the base of the fourth transistor Q4, and the emitter is grounded; the emitter of the fourth transistor Q4 is connected to the output end of the DC bias power supply, and the collector is connected to the signal output end.

2. The control circuit to prevent chattering of a multi-level logic control of claim 1, wherein, The first transistor Q1 and the second transistor Q2 are both PNP type transistors.

3. The control circuit to prevent chattering of a multi-level logic control of claim 1, wherein, The first MOS transistor T1 and the second MOS transistor T2 are N-channel MOS transistors, the third transistor Q3 is a PNP type transistor, and the fourth transistor Q4 is an NPN type transistor.

4. The control circuit to prevent chattering of multi-level logic control of claim 1, wherein, The circuit further comprises an anti-interference module, which comprises at least a third resistor R3, a fourth resistor, and a first capacitor C1, the third resistor R3 is connected between the signal input end and the gate of the first MOS transistor T1; one end of the fourth resistor is connected between the third resistor R3 and the gate of the first MOS transistor T1, and the other end is grounded; one end of the first capacitor C1 is connected between the third resistor R3 and the gate of the first MOS transistor T1, and the other end is grounded.

5. The control circuit to prevent dithering of multi-level logic control of claim 4, wherein, The anti-interference module further comprises an ESD static tube Z1, the negative electrode of the ESD static tube Z1 is connected between the third resistor R3 and the gate of the first MOS transistor T1, and the positive electrode is grounded.

6. The control circuit to prevent chattering of multi-level logic control of claim 1, wherein, The logic control module further comprises a delay control module, which at least comprises a second capacitor C2, one end of which is connected between the drain of the second MOS transistor T2 and the base of the third triode Q3, and the other end is grounded.

7. A PCB board characterized by, The control circuit for preventing multi-level logic control jitter comprises the control circuit according to any one of claims 1-6.

8. An automated driving domain control system, characterized by, The PCB board at least comprises the control circuit for preventing multi-level logic control jitter according to any one of claims 1-6, or the PCB board according to claim 7.

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