Execution method and device for non-blocking macro instruction multi-stage pipeline processor for distributed cluster system

Abstract

The present invention provides an execution method and device for a non-blocking macro instruction multi-stage pipeline processor for a distributed cluster system, the method comprising: detecting a message cache interface and a signaling cache interface to determine whether there is a new message or signaling input; in response to a new message or signaling input, detecting whether the task identifier and the target port number in the message or signaling meet the requirements, if they meet, entering the next stage of processing, if they do not meet, discarding; sending the target port number and the start command to the processing unit for instruction fetching, decoding, data fetching, execution and write-back processing; outputting the processed message or signaling. The present invention decouples computing instructions and communication instructions, utilizes a message cache interface and a signaling cache interface to decouple the reception and processing of computing instructions and communication instructions, completes parallel processing of instructions based on a control logic unit and a multi-stage pipeline processing unit, can improve the communication efficiency of the network system, and improve the efficiency of the distributed cluster system in processing parallel tasks.

Description

Technical Field

[0001] The present invention relates to the technical field of macroinstruction processors, and in particular to an execution method and device of a non-blocking macroinstruction multi-stage pipeline processor for a distributed cluster system. Background Art

[0002] The communication and computing mode of the current distributed deep learning platform is relatively simple, and the communication instructions and computing instructions cannot be effectively combined, resulting in interactive delays in communication and computing. The communication instructions here refer to various instructions involving the transmission of data between various nodes in the distributed system, such as synchronization signaling, production and consumption communication types, parameter synchronization, and the sending and receiving of gradient update messages. The computing instructions refer to instructions that include the execution of specific mathematical operations and model training steps, such as forward propagation, backpropagation and other computing tasks. The communication instructions and computing instructions here cannot be effectively combined, which means that the communication instructions and computing instructions are highly coupled, which means that the parallelism and efficiency of computing and communication operations will be affected, resulting in interactive delays in communication and computing. In addition, the current distributed cluster system often encounters blocking situations. If a node cannot process new requests due to blocking, the node resources may be wasted. Summary of the invention

[0003] In view of this, the present invention provides an execution method and device for a non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system to solve at least one of the above-mentioned problems.

[0004] In order to achieve the above object, the present invention adopts the following scheme:

[0005] According to a first aspect of the present invention, there is provided an execution method for a non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system, the method comprising: based on hardware logic detecting a message cache interface and a signaling cache interface to determine whether there is a new message or signaling input; in response to a new message or signaling input, detecting whether a task identifier and a target port number in the message or signaling data packet meet the current processing requirements, if so, directly reading the message or signaling data packet from the message cache interface or the signaling cache interface into a register and entering the next stage of processing, if not, discarding it; sending the target port number and a start command to a multi-stage pipeline processing unit for instruction fetching, decoding, data fetching, execution and write-back processing; and encapsulating and outputting the processed message or signaling using an independent message or signaling logic interface.

[0006] As an embodiment of the present invention, the above method further includes: if it is detected that the newly input message is a trigger message, locating the corresponding subroutine area for processing according to the message content and a pre-configured offset.

[0007] As an embodiment of the present invention, the above method also includes: when the message cache interface and the signaling cache interface are empty, arbitration is performed between the macro instruction programs corresponding to the available port numbers, and after a port number is determined, the determined port number and the start command are sent to the multi-stage pipeline processing unit.

[0008] As an embodiment of the present invention, the above-mentioned multi-stage pipeline processing unit includes an instruction fetch module, a decoding module, a data fetch module, an execution module and a write-back module. The sending of the target port number and the start command to the multi-stage pipeline processing unit for instruction fetch, decoding, data fetch, execution and write-back processing includes: sending the target port number and the start command to the instruction fetch module, and the instruction fetch module queries the corresponding instruction address register according to the target port number to obtain the instruction, and sends the instruction to the decoding module; after receiving the instruction, the decoding module performs preliminary decoding to obtain the instruction code, and outputs the instruction code to the data fetch module. If the decoding module encounters a pipeline pause state, it enters a delayed processing state and outputs the decoding result in the next cycle; the data fetch module parses the operation code required by the two-level logic of the execution module and the write-back module according to the instruction code and transmits it backward; the execution module completes the execution of the instruction based on the operation code; the write-back module completes the write operation, stack operation and control flow operation based on the execution result of the execution module and the operation code.

[0009] As an embodiment of the present invention, the method further includes: when the instruction fetch module detects an instruction memory access conflict, the execution of the current level function is stopped, and the execution of the current level function is resumed after the conflict is resolved.

[0010] As an embodiment of the present invention, when the instruction fetch module detects an instruction memory access conflict, the method further includes: temporarily stacking the instruction with the memory access conflict until the conflict is resolved, and then restoring the instruction with the memory access conflict from the stack and continuing to execute it.

[0011] As an embodiment of the present invention, the above method further includes: dynamically allocating resources of the non-blocking macroinstruction multi-stage pipeline processor according to the current execution status and resource occupancy status of the message or signaling.

[0012] As an embodiment of the present invention, the above-mentioned data fetch module is also used to receive the pipeline delay, pipeline discard and atomic operation end signal generated by the write back module; when the atomic operation end signal is received, the data fetch module discards the current operation and returns the control right to the non-blocking macroinstruction multi-stage pipeline processor; when the pipeline discard signal is received, the data fetch module discards the current operation and continues to execute subsequent instructions; the instruction fetch module and the decoding module are also used to receive the atomic operation end signal generated by the write back module, and discard the current operation based on the atomic operation end signal, and then return the control right to the non-blocking macroinstruction multi-stage pipeline processor.

[0013] As an embodiment of the present invention, when the write-back module generates an atomic operation end signal, the non-blocking macro-instruction multi-stage pipeline processor temporarily stores the current state, then receives and parses new messages or signaling inputs, and the multi-stage pipeline processing unit performs a new round of pipeline operations based on the results of the analysis.

[0014] According to a second aspect of the present invention, a non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system is provided, and the non-blocking macro-instruction multi-stage pipeline processor comprises: a control logic unit, which is used to detect the message cache interface and the signaling cache interface based on hardware logic to determine whether there is a new message or signaling input; in response to the new message or signaling input, detect whether the task identifier and the target port number in the message or signaling data packet meet the current processing requirements, if they do, directly read the message or signaling data packet from the message cache interface or the signaling cache interface into a register and send the target port number and the start command to the multi-stage pipeline processing unit, if they do not meet, discard it; the multi-stage pipeline processing unit is used to perform instruction fetch, decoding, data fetch, execution and write back processing based on the target port number and the start command; an output unit is used to encapsulate and output the processed message or signaling using an independent message or signaling logic interface.

[0015] As an embodiment of the present invention, the control logic unit is further configured to: if it is detected that the newly input message is a trigger message, locate the corresponding subroutine area for processing according to the message content and a pre-configured offset.

[0016] As an embodiment of the present invention, the above-mentioned control logic unit is also used for: when the message cache interface and the signaling cache interface are empty, arbitrating between the macro instruction programs corresponding to the available port numbers, and after determining a port number, sending the determined port number and the start command to the multi-stage pipeline processing unit.

[0017] As an embodiment of the present invention, the above-mentioned multi-stage pipeline processing unit includes an instruction fetch module, a decoding module, a data fetch module, an execution module and a write-back module. The instruction fetch module is used to query the corresponding instruction address register according to the target port number to obtain the instruction, and send the instruction to the decoding module; the decoding module is used to perform preliminary decoding after receiving the instruction to obtain the instruction code, and output the instruction code to the data fetch module. If the decoding module encounters a pipeline pause state, it enters a delayed processing (Delay) state and outputs the decoding result in the next cycle; the data fetch module is used to parse the operation code required by the two-level logic of the execution module and the write-back module according to the instruction code and transmit it backward; the execution module is used to complete the execution of the instruction based on the operation code; the write-back module is used to complete the write operation, stack operation and control flow operation based on the execution result of the execution module and the operation code.

[0018] As an embodiment of the present invention, the instruction fetch module is further configured to stop the execution of the current level function when an instruction memory access conflict is detected, and resume the execution of the current level function after the conflict is resolved.

[0019] As an embodiment of the present invention, when the instruction fetch module detects an instruction memory access conflict, the device also includes a stack push processing unit: used to temporarily push the instruction with the memory access conflict into the stack until the conflict is resolved and then restore the instruction with the memory access conflict from the stack and continue execution.

[0020] As an embodiment of the present invention, the device further comprises a resource scheduling unit: configured to dynamically allocate resources of the non-blocking macro-instruction multi-stage pipeline processor according to the current execution status and resource occupancy state of the message or signaling.

[0021] As an embodiment of the present invention, the above-mentioned data fetch module is also used to receive the pipeline delay, pipeline discard and atomic operation end signal generated by the write back module; when the atomic operation end signal is received, the data fetch module discards the current operation and returns the control right to the non-blocking macroinstruction multi-stage pipeline processor; when the pipeline discard signal is received, the data fetch module discards the current operation and continues to execute subsequent instructions; the instruction fetch module and the decoding module are also used to receive the atomic operation end signal generated by the write back module, and discard the current operation based on the atomic operation end signal, and then return the control right to the non-blocking macroinstruction multi-stage pipeline processor.

[0022] As an embodiment of the present invention, when the write-back module generates an atomic operation end signal, the non-blocking macro-instruction multi-stage pipeline processor temporarily stores the current state, then receives and parses new messages or signaling inputs, and the multi-stage pipeline processing unit performs a new round of pipeline operations based on the results of the analysis.

[0023] According to a third aspect of the present invention, there is provided an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above method when executing the computer program.

[0024] According to a fourth aspect of the present invention, there is provided a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of the above method when executed by a processor.

[0025] It can be seen from the above technical scheme that the execution method and device of the non-blocking macro-instruction multi-stage pipeline processor for distributed cluster systems provided by the present invention decouples the computing instructions and communication instructions, transmits the computing instructions and communication instructions respectively through the data channel and the signaling channel, and uses the message cache interface and the signaling cache interface to decouple the received computing instructions and communication instructions, completes the parallel processing of instructions based on the control logic unit and the multi-stage pipeline processing unit, and is applied to the distributed cluster system to improve the communication efficiency of the network system. In addition, the present application can realize the resource contention and data dependency between multiple instructions through an effective resource scheduling and conflict detection mechanism, so as not to cause blocking, and after the atomic operation end signal, the current state can be temporarily stored, and then a new message or signaling input is received and parsed, and a new round of pipeline operation is performed by the multi-stage pipeline processing unit based on the parsed result, which also enables the non-blocking macro-instruction processor to effectively process parallel tasks, thereby improving the execution efficiency and response speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0027] Figure 1 It is a flowchart of an execution method of a non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system provided by an embodiment of the present application;

[0028] Figure 2 It is a schematic diagram of the execution flow of the multi-stage pipeline processing unit provided in the embodiment of the present application;

[0029] Figure 3 It is a flowchart of an execution method of a non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system provided by another embodiment of the present application;

[0030] Figure 4It is a structural schematic diagram of a non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system provided by an embodiment of the present application;

[0031] Figure 5 It is a structural schematic diagram of a multi-stage water flow processing unit provided in an embodiment of the present application;

[0032] Figure 6 It is a structural schematic diagram of a non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system provided by another embodiment of the present application;

[0033] Figure 7 It is a schematic block diagram of the system structure of the electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] To make the purpose, technical solution and advantages of the embodiments of the present invention more clear, the embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Here, the exemplary embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention.

[0035] The following is a brief description of the technical terms involved in this application:

[0036] The term "distributed cluster" refers to a computer system architecture that connects multiple independent computers (nodes) through a network to jointly perform tasks or applications. Distributed clusters not only improve computing efficiency and system reliability by distributing computing tasks to multiple computing nodes, but also provide excellent scalability and flexibility, becoming an important technical foundation for handling modern large-scale computing problems.

[0037] Term "Macro-Instruction Processor": An advanced processor design that is capable of executing complex instructions consisting of multiple microinstructions or sequences of operations, these complex instructions are called macro-instructions.

[0038] like Figure 1 The figure is a flow chart of an execution method of a non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system provided by an embodiment of the present application. The method comprises the following steps:

[0039] Step S101: Detect the message buffer interface and the signaling buffer interface based on hardware logic to determine whether there is a new message or signaling input.

[0040] The message buffer (Message FIFO) interface is specifically used to buffer messages received from other nodes of the cluster system or external sources. These messages may include data updates, processing requests, or other forms of information exchange.

[0041] The command FIFO interface is used to receive and cache control signals, which are used to manage and coordinate tasks and resources in the cluster, such as commands to start or stop tasks, resource allocation instructions, etc.

[0042] Both the message buffer interface and the signaling buffer interface adopt a first-in-first-out queue management mechanism to ensure that data is processed in the order in which it arrives. In this embodiment, the messages in the message buffer interface include computing instructions, while the signals in the signaling buffer interface include communication instructions.

[0043] Both messages and signaling exist in the form of data packets, which include data payload and header. The data payload is the actual user data or calculation data, which is the basis for the processor to perform computing tasks, while the header contains metadata used for routing decisions, such as the destination address, source address, etc., to ensure that the data packet can be correctly sent to the target processor. Each core of the non-blocking macro-instruction multi-stage pipeline processor includes a router, a data packet manager, and local storage. The router is responsible for determining the forwarding path of the data packet to ensure that the data packet reaches the target location along the optimal path; the data packet manager handles the queue and priority of the data packet, and manages the reception and transmission of the data packet; the local storage provides temporary or persistent storage space for the data required for calculation. This design allows each processor core to independently handle the reception, calculation, and forwarding of data packets.

[0044] In this embodiment, the non-blocking macroinstruction processor can periodically check the message cache and signaling cache interface to determine whether there is new input waiting to be processed. This detection mechanism enables the processor to respond to external events and internal instructions in a timely manner.

[0045] As part of "non-blocking", the macroinstruction processor can dynamically adjust its internal configuration according to the current workload and system status, such as adjusting resource allocation, or changing the priority of instruction execution to optimize processing performance. In addition, the present application detects the message cache interface and the signaling cache interface through hardware logic. The hardware logic allows the processor to independently detect the message and signaling interface while processing the core computing tasks, which means that data processing and signal detection can occur at the same time, and one party will not wait or be blocked due to the processing of the other party. Moreover, the messages and signals of the present application are transmitted through independent data channels. The non-blocking macroinstruction processor of the present application can efficiently process external communication tasks without interrupting the main computing tasks, which is especially important in multi-tasking and high-concurrency distributed cluster environments, and fully reflects the non-blocking design concept.

[0046] Step S102: In response to a new message or signaling input, check whether the task identifier and target port number in the message or signaling data packet meet the current processing requirements. If so, read the message or signaling data packet directly from the message cache interface or the signaling cache interface into the register and enter step S103; if not, discard it.

[0047] In this embodiment, each message or signaling data packet contains a task identifier (TASK_ID) that uniquely identifies the task or job associated with the data packet, which allows the processor to determine whether the data packet belongs to a task queue that is currently being processed or to be processed. The data packet also specifies a target port number (Channel), which indicates the processing unit of a specific program to which the data packet should be routed. In a distributed cluster system, different processing units can listen to different port numbers to process specific types of tasks.

[0048] Assume that the present application has a macro instruction executor in a distributed cluster system, which needs to process 8 programs in the active state, each of which is assigned a unique target port number ranging from 0 to 7. When the macro instruction executor is started, it will initialize its internal resources and configuration, including allocating necessary processing resources for each target port number (0-7). Each program in the active state is assigned a unique target port number, which is used to identify and route its data packets and instructions during the execution of the program.

[0049] The macro executor continuously checks the input queue to identify new messages or signaling packets. Each packet contains a destination port number, indicating the program it is associated with. Based on the destination port number in the packet, the macro executor routes the packet to the corresponding processing queue, which ensures that the packet of each program can be correctly identified and processed. The macro executor can process packets from all active programs at the same time. Since each program has an independent processing queue and resource allocation, these programs can be executed in parallel without interfering with each other. When a program completes its task, its status will be updated to inactive, and the macro executor can reclaim the resources used by the program for use by other tasks.

[0050] Preferably, the execution method of the present application also includes a function similar to an interrupt handler, that is, when a newly input message is detected as a trigger message (Vector message), the corresponding subroutine area is located for processing according to the message content and the pre-configured offset, and the subroutine area corresponding to each vector does not require a callback (Call) or return (Return) instruction. After execution, it can directly transfer to the next task or return to the state before the interruption. This function similar to an interrupt handler improves the ability and efficiency of the distributed cluster system to handle asynchronous events.

[0051] Further preferably, the execution method of the present application also includes an arbitration process, that is, when the message cache interface and the signaling cache interface are empty, arbitration is performed between the macro instruction programs corresponding to the available port numbers, and after a port number is determined, the determined port number and the start command are sent to the multi-stage pipeline processing unit.

[0052] When the message cache interface and signaling cache interface in the distributed cluster system are both empty, it means that there are no external messages or signals to be processed. In this case, the system needs to effectively utilize its computing resources to ensure that the system continues to operate efficiently. By arbitrating between the macroinstruction programs corresponding to the available port numbers, the system can select the next task to be executed. The purpose of this process is to maintain efficient utilization of processing units and optimize the overall allocation of computing resources.

[0053] Since each macro program is associated with a specific port number that identifies the program's communication and data flow path, the arbitration process determines which port number the program will be executed. After determining the port number to be executed, the system generates a start command that contains all the information required to execute the selected macro program, such as the starting address, execution parameters, etc. The start command and the determined port number are sent to the multi-stage pipeline processing unit to start the execution process of the macro program. In this way, the system dynamically adjusts its task execution queue to ensure that computing resources are effectively utilized even when external input is lacking. Therefore, this process helps to optimize the overall efficiency and responsiveness of the system, maximizing resource utilization and system throughput through the reasonable arrangement and execution of internal tasks.

[0054] Step S103: Send the target port number and the start command to the multi-stage pipeline processing unit for instruction fetching, decoding, data fetching, execution and write-back processing.

[0055] In this embodiment, the target port number and the startup command are taken as input, and the execution of instructions can be efficiently realized through a series of processing of a multi-stage pipeline processing unit. Especially in high-performance computing or application scenarios that require fast response, the pipeline technology significantly improves the processor's throughput and execution efficiency by processing different stages of multiple instructions in parallel.

[0056] Preferably, the pipeline processing unit of this embodiment includes an instruction fetch module, a decoding module, a data fetch module, an execution module and a write-back module. Figure 2 As shown, this step may further include the following sub-steps:

[0057] Step S1031: Send the target port number and the start command to the instruction fetch module, and the instruction fetch module queries the corresponding instruction address register according to the target port number to obtain the instruction, and sends the instruction to the decoding module.

[0058] Taking the above-mentioned need to process 8 programs in active state as an example, there can be 8 instruction address registers (Instruction address Reg) and 8 stack pointer registers (Stack Pointer Reg) in the instruction fetch module. If the message received in step S102 is a Reset message, the instruction address register and stack pointer register corresponding to the message will be set to the initial value, which enables the system to ensure execution from a known and clean state.

[0059] The instruction address register is used to store the memory address of the next instruction to be executed, and the stack pointer register is used to manage the state of the call stack or execution stack. After receiving the target port number and the start command, the instruction fetch module queries the corresponding instruction address register according to the target port number, fetches the instruction from the address stored in this instruction address register and passes it to the subsequent module for execution. After executing an instruction class, the instruction fetch module refreshes the corresponding instruction address register to the latest value, and then returns control to the non-blocking macro instruction processor of the distributed cluster system.

[0060] Preferably, the instruction fetch module in this embodiment also supports exception handling and interrupt handling, that is, when the instruction fetch module detects an instruction memory access conflict, the execution of the current level function is stopped, and the execution of the current level function is resumed after the conflict is resolved.

[0061] Instruction memory access conflict refers to the memory access conflict problem encountered during the execution of instructions. This conflict mainly occurs when the processor attempts to access multiple locations in the memory at the same time, and there is data dependency or resource contention between these access operations, resulting in the inability to satisfy all memory access requests at the same time. For example, in this implementation, when the fetch module has a read Ram operation and the write back module has a write Ram operation, the instruction fetch module will stop the execution of the current level function and resume the execution of the current level function after the conflict is resolved. By introducing the interrupt function, the non-blocking macro-instruction multi-stage pipeline processor can effectively manage and reduce the impact of instruction memory access conflicts, improving execution efficiency and processor performance.

[0062] Preferably, when the instruction fetch module detects an instruction memory access conflict, the method of the present application also includes: temporarily pushing the instruction with the memory access conflict into the stack until the conflict is resolved, and then restoring the instruction with the memory access conflict from the stack and continuing to execute it. This method can effectively avoid long-term blocking caused by memory access conflicts.

[0063] Preferably, the method of the present application further includes: dynamically allocating resources of the non-blocking macroinstruction multi-stage pipeline processor according to the current execution status of the message or signaling and the resource occupancy status, such as using priority queuing, time slice rotation or other fair scheduling algorithms to ensure that each instruction has equal and effective access to the required resources. In addition, a feedback system can be introduced to adjust the resource allocation strategy according to the real-time feedback of instruction execution to improve resource utilization and execution efficiency.

[0064] Step S1032: After receiving the instruction, the decoding module performs preliminary decoding to obtain the instruction code, and outputs the instruction code to the data acquisition module. If the decoding module encounters a pipeline pause state, it enters a delayed processing state and outputs the decoding result in the next cycle.

[0065] The design of the decoding module of the present application allows it to dynamically adapt to the current execution environment during processing and run in two states: Normal and Delay. This design enhances the processor's ability to cope with different execution challenges, especially when facing pipeline stalls.

[0066] In the Normal state, the decoding module receives instructions from the instruction fetch module. These instructions have been taken out of the memory and are ready for decoding. The decoding process includes parsing the instruction code of the instruction, determining the type of instruction (for example, whether it is an arithmetic operation, a logical operation, or a data transfer operation, etc.), and identifying the operands.

[0067] The Delay state is designed to handle pipeline stalls, which may be caused by a variety of reasons, such as data dependencies, resource contention, or the inability to process new instructions because the previous instructions have not yet completed execution. When the decode module encounters such a situation, it will pause the current decoding operation and enter the Delay state. In this state, the decoding and delivery of instructions are postponed until it is safe to continue execution. This design allows the pipeline to flexibly handle various delays in the execution process while maintaining data integrity and execution correctness.

[0068] Therefore, the decoding module of the present application dynamically switches its operating state according to the current state of the pipeline. This state switching mechanism improves the adaptability of the processor to execution barriers and helps reduce performance losses caused by pauses.

[0069] Step S1033: the data acquisition module parses the instruction code to obtain the operation code required by the two-level logic of the execution module and the write-back module and transmits it backward.

[0070] The data acquisition module transmits the parsed operation code and necessary operation information to the execution module and the write-back module to guide them to complete the specific logic and write-back operations. In this level of logic, the data acquisition module will also perform read RAM or read reg operations according to the instruction code.

[0071] Preferably, the data acquisition module is also used to receive pipeline delay (pipeline_delay), pipeline discard (pipeline_discard) and atomic operation end signal generated by the write-back module;

[0072] When receiving the atomic operation end signal, the data fetching module discards the current operation and returns the control to the non-blocking macro instruction multi-stage pipeline processor. Here, the atomic operation refers to an operation that cannot be interrupted by other threads during execution. In a multi-threaded environment, the atomic operation can ensure the consistency and integrity of the data without locking resources.

[0073] When receiving the pipeline discard signal, the data fetch module discards the current operation and continues to execute subsequent instructions;

[0074] Further preferably, the instruction fetch module and the decoding module can also receive the atomic operation end signal generated by the write-back module, and discard the current operation based on the atomic operation end signal, and then return the control to the non-blocking macro-instruction multi-stage pipeline processor.

[0075] This complex signal processing and state management mechanism reflects the high complexity and flexibility of the non-blocking macro-instruction multi-stage pipeline processor in instruction execution, exception management and task scheduling. Through this fine control, the non-blocking macro-instruction multi-stage pipeline processor can effectively deal with various situations encountered during execution, maintain high-efficiency operation, and ensure the correctness of execution and the stability of the system.

[0076] Further preferably, when the write-back module generates an atomic operation end signal, the non-blocking macro instruction multi-stage pipeline processor can temporarily store the current state, then receive and parse new messages or signaling inputs, and perform a new round of pipeline operations based on the parsed results by the multi-stage pipeline processing unit. In this way, the non-blocking macro instruction processor can effectively process parallel tasks, improve execution efficiency and response speed. It can immediately turn to process new inputs after completing the key steps of a task, thereby achieving efficient multi-tasking capabilities, which is the specific implementation of its non-blocking feature.

[0077] Step S1034: the execution module completes the execution of the instruction based on the operation code.

[0078] The execution module is responsible for the execution stage in the multi-stage pipeline processor architecture. In this stage, the processor performs specific logical or arithmetic operations on the instructions parsed and prepared in the previous stage. The work of the execution module is not limited to performing simple arithmetic operations, but also involves complex data processing and logical judgment: for example, the execution module needs to process data from RAM (Ram Data) and data from registers (Register Data), which includes reading data from the specified memory address and obtaining data from the register file; it is also necessary to perform addition or subtraction operations according to the requirements of the instructions. These operations may involve processing integer or floating-point data, and it is necessary to correctly handle the carry or borrow generated in the operation; when the updated data needs to be written back to RAM, the execution module performs a specific sequence of operations: first read the original 64-bit data in the target memory address to ensure that only the target data segment is modified without affecting other data; integrate the new data to be written (from the register or the calculation result) into the original data read, replacing the original corresponding segment or value; write the replaced complete 64-bit data back to the same address of RAM. In addition, the carry flag generated by addition and subtraction operations can also be used as a conditional judgment to control the execution of conditional jump instructions. For example, in some conditional branch instructions, the jump is only executed when the carry flag is set (or not set).

[0079] The design of the execution module in this embodiment reflects the high complexity and flexibility of the non-blocking macro-instruction multi-stage pipeline processor in the execution stage. It can handle various data operations, support complex program logic, and respond to conditional changes during instruction execution.

[0080] Step S1035: the write-back module completes the write operation, stack operation and control flow operation based on the execution result of the execution module and the operation code.

[0081] The write-back module is the last stage in the multi-stage pipeline processor architecture. The main responsibility of this stage is to complete the final steps of instruction execution, write the execution results back to the target location, and process the control flow operations in the instruction.

[0082] Among them, the write operation includes writing RAM and writing Reg: writing RAM is to write the execution result or processed data to the specified location in the memory, which can be the result of arithmetic operation, the output of data processing operation, or data generated by other instructions; writing Reg is to update a specific register in the register file, and the execution result is directly written to one or more target registers for use by subsequent instructions.

[0083] Stack operations include PUSH and POP: PUSH pushes data (such as function call parameters, local variables, or return addresses) into the call stack; POP removes data from the top of the call stack and may load it into registers or memory.

[0084] Control flow operations include CALL, RETURN, and jump operations: CALL performs a function call operation, including saving the return address (i.e., the instruction address after the CALL instruction) to the call stack and jumping to the starting address of the function for execution. RETURN is a return from the function to the call point, which usually involves popping the return address from the call stack and setting the program counter (PC) to that address to resume the execution flow before the call. The jump operation changes the execution flow of the program according to instructions or execution conditions. The jump may be unconditional or based on specific conditions (such as the result of a comparison operation). When a jump needs to be executed, the write-back module generates a jump operation signal and sends this signal back to the instruction fetch module, indicating that the current execution path needs to be changed. This requires the instruction fetch module to update the instruction address register based on the received signal to point to the new instruction address.

[0085] The design and functionality of the write-back module reflects the complexity of the processor in completing instruction execution, managing control flow, and maintaining program state consistency. By performing these operations accurately, the write-back module ensures the correct implementation of program logic and supports the efficient operation of pipelined processors.

[0086] Preferably, the above modules work in coordination in the same clock cycle to complete data flow, control and transmission, because the modules operate in parallel in the same clock cycle, that is, the data executed by the modules in the same clock cycle has no data correlation, and the execution of each module can be controlled by its control instruction. In this way, the system can process more instructions and data in each clock cycle, significantly improving the processing speed and throughput. This design makes full use of hardware resources and improves the overall efficiency of the system. Since the data executed by the modules have no data correlation in the same clock cycle, this design effectively avoids data conflicts and dependencies, and reduces the delay and complexity caused by the need to process data dependencies additionally. Each module can process its data independently without waiting for the results of other modules. Finally, the system is designed to be modular and each module can work in parallel in the same clock cycle, making the system easier to expand and maintain. When adding new functions or improving performance, it can be achieved by adding new modules or optimizing existing modules without reconstructing the entire system.

[0087] Step S104: Encapsulate and output the processed message or signaling using an independent message or signaling logic interface.

[0088] It can be seen from the above technical scheme that the execution method of the non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system provided by the present invention decouples computing instructions and communication instructions, transmits computing instructions and communication instructions through data channels and signaling channels respectively, and uses message cache interfaces and signaling cache interfaces to receive computing instructions and communication instructions respectively, completes parallel processing of instructions based on control logic units and multi-stage pipeline processing units, and is applied to distributed cluster systems to improve the communication efficiency of network systems.

[0089] like Figure 3 A flowchart of another method for executing a non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system provided in an embodiment of the present application, the method comprising the following steps:

[0090] Step S301: receiving a task source code, and determining a data loop body that can be vectorized from the source code.

[0091] The non-blocking macro-instruction multi-stage pipeline processor first receives the execution source code for deep learning or other computationally intensive tasks. Through specific analysis tools or compiler technology, it can identify the data loop body that can be vectorized from the execution source code. This step is completed at the software level with the aim of optimizing the execution efficiency of the code.

[0092] Step S302: vectorize the instructions of the data loop body to generate communication instructions and calculation instructions.

[0093] Once it is determined which loop bodies can be vectorized, the non-blocking macroinstruction multi-stage pipeline processor will vectorize the instructions of these loop bodies and generate corresponding communication instructions and storage instructions. These instructions are designed to be efficiently executed on the non-blocking macroinstruction multi-stage pipeline processor.

[0094] Step S303: encapsulate the communication instructions and the computing instructions into separate data packets, each of which includes a data payload and a header.

[0095] Communication instructions and computational instructions are encapsulated into a single data packet, each containing a data payload and a header. These packets are identified and routed within the core grid. Each non-blocking macro-instruction multi-stage pipeline processor computes the data packet. The core includes a router, a packet manager, and storage, supporting on-chip and off-chip synchronization and coordination.

[0096] Step S304: Detect the message buffer interface and the signaling buffer interface based on the hardware logic to determine whether there is a new message data packet or signaling data packet input.

[0097] Step S305: In response to a new message or signaling input, check whether the task identifier and target port number in the message or signaling data packet meet the current processing requirements. If so, read the message or signaling data packet directly from the message cache interface or the signaling cache interface into the register and enter step S306. If not, discard it.

[0098] Step S306: Send the target port number and the start command to the multi-stage pipeline processing unit for instruction fetching, decoding, data fetching, execution and write-back processing.

[0099] Step S307: Encapsulate and output the processed message or signaling using an independent message or signaling logic interface.

[0100] It can be seen from the above technical scheme that the execution method of the non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system provided by the present invention decouples computing instructions and communication instructions, transmits computing instructions and communication instructions through data channels and signaling channels respectively, and uses message cache interfaces and signaling cache interfaces to receive computing instructions and communication instructions respectively, completes parallel processing of instructions based on control logic units and multi-stage pipeline processing units, thereby decoupling the operation and execution of computing instructions and communication instructions, and can be applied to distributed cluster systems to improve the communication efficiency of network systems.

[0101] like Figure 4 The structure diagram of a non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system provided by an embodiment of the present application is shown, which includes: a control logic unit 410, a multi-stage pipeline processing unit 420 and an output unit 430, which are connected in sequence, wherein:

[0102] The control logic unit 410 is used to detect the message cache interface and the signaling cache interface based on hardware logic to determine whether there is a new message or signaling input; in response to the new message or signaling input, detect whether the task identifier and the target port number in the message or signaling data packet meet the current processing requirements. If they do, read the message or signaling data packet directly from the message cache interface or the signaling cache interface into the register and send the target port number and the start command to the multi-stage pipeline processing unit 420; if they do not meet, discard them.

[0103] The multi-stage pipeline processing unit 420 is used to perform instruction fetching, decoding, data fetching, execution and write-back processing based on the target port number and the start command.

[0104] The output unit 430 is used to encapsulate and output the processed message or signaling using an independent message or signaling logic interface.

[0105] Preferably, the control logic unit 410 is further configured to: if it is detected that the newly input message is a trigger message, locate the corresponding subroutine area for processing according to the message content and a pre-configured offset.

[0106] Preferably, the control logic unit 410 is also used for: when the message cache interface and the signaling cache interface are empty, arbitrating between the macro instruction programs corresponding to the available port numbers, and after determining a port number, sending the determined port number and the start command to the multi-stage pipeline processing unit.

[0107] Preferably, Figure 5 As shown, the multi-stage pipeline processing unit 420 includes an instruction fetch module 421, a decoding module 422, a data fetch module 423, an execution module 424 and a write-back module 425, wherein the instruction fetch module 421 is used to query the corresponding instruction address register according to the target port number to obtain the instruction, and send the instruction to the decoding module 422; the decoding module 422 is used to perform preliminary decoding after receiving the instruction to obtain the instruction code, and output the instruction code to the data fetch module 423. If the decoding module 422 encounters a pipeline pause state, it enters a delayed processing state and outputs the decoding result in the next cycle; the data fetch module 423 is used to parse the operation code required by the two-level logic of the execution module and the write-back module according to the instruction code and transmit it backward; the execution module 424 is used to complete the execution of the instruction based on the operation code; the write-back module 425 is used to complete the write operation, stack operation and control flow operation based on the execution result of the execution module and the operation code.

[0108] Preferably, the instruction fetch module 421 is further configured to stop the execution of the current level function when an instruction memory access conflict is detected, and resume the execution of the current level function after the conflict is resolved.

[0109] Preferably, when the instruction fetch module detects an instruction memory access conflict, the device further comprises a stack push processing unit: configured to temporarily stack the instruction with the memory access conflict until the conflict is resolved and then restore the instruction with the memory access conflict from the stack and continue to execute it.

[0110] Preferably, the device further comprises a resource scheduling unit: configured to dynamically allocate resources of the non-blocking macro-instruction multi-stage pipeline processor according to the current execution status and resource occupancy status of the message or signaling.

[0111] Preferably, the above-mentioned data fetch module 423 is also used to receive the pipeline delay, pipeline discard and atomic operation end signal generated by the write back module 425; when the atomic operation end signal is received, the data fetch module 423 discards the current operation and returns the control right to the non-blocking macroinstruction multi-stage pipeline processor; when the pipeline discard signal is received, the data fetch module 423 discards the current operation and continues to execute subsequent instructions; the instruction fetch module 421 and the decoding module 422 are also used to receive the atomic operation end signal generated by the write back module 425, and discard the current operation based on the atomic operation end signal, and then return the control right to the non-blocking macroinstruction multi-stage pipeline processor.

[0112] Preferably, when the write-back module generates an atomic operation end signal, the non-blocking macroinstruction multi-stage pipeline processor temporarily stores the current state, then receives and parses new messages or signaling inputs, and based on the results of the parsing, the multi-stage pipeline processing unit performs a new round of pipeline operations.

[0113] Further, the structure of the above-mentioned non-blocking macro-instruction multi-stage pipeline processor for distributed cluster system can also be seen in Figure 6 , wherein each module of the multi-stage pipeline processing unit 420 also involves the input and output of relevant data segments, signaling segments, and virtual conversion segments when executing their respective functions, that is, the non-blocking macroinstruction processor of the present application has an instruction cache, a data cache, a virtual-to-real conversion cache, and a storage system, which can provide the multi-stage pipeline processing unit 420 with the relevant data segments, signaling segments, and virtual conversion segments required for processing.

[0114] It can be seen from the above technical scheme that the execution device of the non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system provided by the present invention decouples computing instructions and communication instructions, transmits computing instructions and communication instructions through data channels and signaling channels respectively, and uses message cache interfaces and signaling cache interfaces to receive computing instructions and communication instructions respectively, completes parallel processing of instructions based on control logic units and multi-stage pipeline processing units, and is applied to distributed cluster systems to improve the communication efficiency of network systems.

[0115] An embodiment of the present invention further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the above method is implemented when the processor executes the program.

[0116] An embodiment of the present invention further provides a computer-readable storage medium, which stores a computer program for executing the above method.

[0117] like Figure 7As shown, the electronic device 600 may further include: a communication module 110, an input unit 120, an audio processor 130, a display 160, and a power supply 170. It is worth noting that the electronic device 600 does not necessarily have to include Figure 7 In addition, the electronic device 600 may also include Figure 7 For components not shown, reference may be made to the prior art.

[0118] like Figure 7 As shown, the central processor 100 is sometimes also referred to as a controller or an operation control, and may include a microprocessor or other processor devices and / or logic devices. The central processor 100 receives inputs and controls the operations of various components of the electronic device 600.

[0119] The memory 140 may be, for example, one or more of a cache, a flash memory, a hard drive, a removable medium, a volatile memory, a non-volatile memory or other suitable devices. The above-mentioned information related to the failure may be stored, and a program for executing the relevant information may also be stored. The CPU 100 may execute the program stored in the memory 140 to implement information storage or processing.

[0120] The input unit 120 provides input to the CPU 100. The input unit 120 is, for example, a key or a touch input device. The power supply 170 is used to provide power to the electronic device 600. The display 160 is used to display display objects such as images and text. The display may be, for example, an LCD display, but is not limited thereto.

[0121] The memory 140 may be a solid-state memory, such as a read-only memory (ROM), a random access memory (RAM), a SIM card, etc. It may also be a memory that saves information even when the power is off, can be selectively erased, and is provided with more data, examples of which are sometimes referred to as EPROMs, etc. The memory 140 may also be some other type of device. The memory 140 includes a buffer memory 141 (sometimes referred to as a buffer). The memory 140 may include an application / function storage unit 142, which is used to store application programs and function programs or processes for executing the operation of the electronic device 600 through the central processor 100.

[0122] The memory 140 may also include a data storage unit 143 for storing data, such as contacts, digital data, pictures, sounds, and / or any other data used by the electronic device. The driver storage unit 144 of the memory 140 may include various drivers for communication functions of the electronic device and / or for executing other functions of the electronic device (such as messaging applications, address book applications, etc.).

[0123] The communication module 110 is a transmitter / receiver 110 that transmits and receives signals via an antenna 111. The communication module (transmitter / receiver) 110 is coupled to the central processor 100 to provide input signals and receive output signals, which may be the same as the case of a conventional mobile communication terminal.

[0124] Based on different communication technologies, multiple communication modules 110 may be provided in the same electronic device, such as a cellular network module, a Bluetooth module and / or a wireless LAN module. The communication module (transmitter / receiver) 110 is also coupled to a speaker 131 and a microphone 132 via an audio processor 130 to provide an audio output via the speaker 131 and receive an audio input from the microphone 132, thereby realizing a common telecommunication function. The audio processor 130 may include any suitable buffer, decoder, amplifier, etc. In addition, the audio processor 130 is also coupled to the central processor 100, so that the sound can be recorded on the local machine through the microphone 132, and the sound stored on the local machine can be played through the speaker 131.

[0125] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0126] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0127] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0128] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0129] The present invention uses specific embodiments to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for executing a non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system, characterized in that: The method comprises: Detect the message buffer interface and signaling buffer interface based on hardware logic to determine whether there is a new message or signaling input; In response to a new message or signaling input, detecting whether the task identifier and the target port number in the message or signaling data packet meet the current processing requirements, if so, directly reading the message or signaling data packet from the message buffer interface or the signaling buffer interface into the register and entering the next stage of processing, if not, discarding it; Sending the target port number and the start command to the multi-stage pipeline processing unit for instruction fetching, decoding, data fetching, execution and write-back processing; Encapsulate and output processed messages or signals using independent message or signaling logic interfaces; When the message buffer interface and the signaling buffer interface are empty, arbitration is performed between the macroinstruction programs corresponding to the available port numbers, and after a port number is determined, the determined port number and a start command are sent to the multi-stage pipeline processing unit.

2. The execution method of the non-blocking macro instruction multi-stage pipeline processor for a distributed cluster system according to claim 1, characterized in that: The method further includes: if it is detected that the newly input message is a trigger message, locating the corresponding subroutine area for processing according to the message content and a pre-configured offset.

3. The execution method of the non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system according to claim 1, characterized in that: The multi-stage pipeline processing unit includes an instruction fetch module, a decoding module, a data fetch module, an execution module and a write-back module, and the sending of the target port number and the start command to the multi-stage pipeline processing unit for instruction fetch, decoding, data fetch, execution and write-back processing includes: The target port number and the start command are sent to the instruction fetch module, and the instruction fetch module queries the corresponding instruction address register according to the target port number to obtain the instruction, and sends the instruction to the decoding module; After receiving the instruction, the decoding module performs preliminary decoding to obtain the instruction code, and outputs the instruction code to the data acquisition module. If the decoding module encounters a pipeline pause state, it enters a delay processing state and outputs the decoding result in the next cycle; The data acquisition module parses the instruction code to obtain the operation code required by the two-level logic of the execution module and the write-back module and transmits it backward; The execution module completes the execution of the instruction based on the operation code; The write-back module completes a write operation, a stack operation, and a control flow operation based on the execution result of the execution module and the operation code.

4. The execution method of the non-blocking macro instruction multi-stage pipeline processor for a distributed cluster system as claimed in claim 3, characterized in that: The method further comprises: When the instruction fetch module detects an instruction memory access conflict, the execution of the current level function is stopped, and the execution of the current level function is resumed after the conflict is resolved.

5. The execution method of the non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system as claimed in claim 4, characterized in that: When the instruction fetch module detects an instruction memory access conflict, the method further includes: temporarily stacking the instruction with the memory access conflict until the conflict is resolved, and then restoring the instruction with the memory access conflict from the stack and continuing to execute it.

6. The execution method of the non-blocking macro instruction multi-stage pipeline processor for a distributed cluster system according to claim 1, characterized in that: The method further comprises: The resources of the non-blocking macro-instruction multi-stage pipeline processor are dynamically allocated according to the current execution status and resource occupancy status of the message or signaling.

7. The execution method of the non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system as claimed in claim 3, characterized in that: The data acquisition module is also used to receive pipeline delay, pipeline abandonment and atomic operation end signals generated by the write-back module; When receiving the atomic operation end signal, the data acquisition module abandons the current operation and returns the control right to the non-blocking macro instruction multi-stage pipeline processor; When receiving a pipeline discard signal, the data acquisition module discards the current operation and continues to execute subsequent instructions; The instruction fetch module and the decoding module are also used to receive the atomic operation end signal generated by the write-back module, and discard the current operation based on the atomic operation end signal, and then return the control right to the non-blocking macro-instruction multi-stage pipeline processor.

8. The execution method of the non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system as claimed in claim 7, characterized in that: When the write-back module generates an atomic operation end signal, the non-blocking macroinstruction multi-stage pipeline processor temporarily stores the current state, then receives and parses new messages or signaling inputs, and based on the parsed results, the multi-stage pipeline processing unit performs a new round of pipeline operations.

9. A non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system, characterized in that: The non-blocking macroinstruction multi-stage pipeline processor comprises: A control logic unit is used to detect the message cache interface and the signaling cache interface based on hardware logic to determine whether there is a new message or signaling input; in response to the new message or signaling input, detect whether the task identifier and the target port number in the message or signaling data packet meet the current processing requirements, if they meet, directly read the message or signaling data packet from the message cache interface or the signaling cache interface into a register and send the target port number and the start command to the multi-stage pipeline processing unit, if they do not meet, discard it; A multi-stage pipeline processing unit, used for performing instruction fetching, decoding, data fetching, execution and write-back processing based on the target port number and the start command; An output unit, used to encapsulate and output the processed message or signaling using an independent message or signaling logic interface; The control logic unit is also used for: when the message buffer interface and the signaling buffer interface are empty, arbitrating between the macro instruction programs corresponding to the available port numbers, and after determining a port number, sending the determined port number and the start command to the multi-stage pipeline processing unit.

10. The non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system as claimed in claim 9, characterized in that: The control logic unit is also used for: if it is detected that the newly input message is a trigger message, locating the corresponding subroutine area for processing according to the message content and the pre-configured offset.

11. The non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system according to claim 9, characterized in that: The multi-stage pipeline processing unit includes an instruction fetch module, a decoding module, a data fetch module, an execution module and a write-back module. The instruction fetch module is used to query the corresponding instruction address register according to the target port number to obtain the instruction, and send the instruction to the decoding module; The decoding module is used to perform preliminary decoding to obtain the instruction code after receiving the instruction, and output the instruction code to the data acquisition module. If the decoding module encounters a pipeline pause state, it enters a delay processing state and outputs the decoding result in the next cycle; The data acquisition module is used to parse the operation code required by the two-level logic of the execution module and the write-back module according to the instruction code and transmit it backward; The execution module is used to complete the execution of the instruction based on the operation code; The write-back module is used to complete the write operation, stack operation and control flow operation based on the execution result of the execution module and the operation code.

12. The non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system according to claim 11, characterized in that: The instruction fetch module is also used to stop the execution of the current level function when an instruction memory access conflict is detected, and resume the execution of the current level function after the conflict is resolved.

13. The non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system as claimed in claim 12, characterized in that: When the instruction fetch module detects an instruction memory access conflict, the processor further comprises a stack push processing unit for temporarily stacking the instruction with the memory access conflict until the conflict is resolved and then recovering the instruction with the memory access conflict from the stack and continuing to execute it.

14. The non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system according to claim 9, characterized in that: The processor also includes a resource scheduling unit: used for dynamically allocating resources of the non-blocking macro-instruction multi-stage pipeline processor according to the current execution status and resource occupancy status of the message or signaling.

15. The non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system according to claim 11, characterized in that: The data acquisition module is also used to receive pipeline delay, pipeline abandonment and atomic operation end signals generated by the write-back module; When receiving the atomic operation end signal, the data acquisition module abandons the current operation and returns the control right to the non-blocking macro instruction multi-stage pipeline processor; When receiving a pipeline discard signal, the data acquisition module discards the current operation and continues to execute subsequent instructions; The instruction fetch module and the decoding module are also used to receive the atomic operation end signal generated by the write-back module, and discard the current operation based on the atomic operation end signal, and then return the control right to the non-blocking macro-instruction multi-stage pipeline processor.

16. The non-blocking macro-instruction multi-stage pipeline processor for a distributed cluster system as claimed in claim 15, characterized in that: When the write-back module generates an atomic operation end signal, the non-blocking macroinstruction multi-stage pipeline processor temporarily stores the current state, then receives and parses new messages or signaling inputs, and based on the parsed results, the multi-stage pipeline processing unit performs a new round of pipeline operations.

17. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 8 are implemented.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

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