A Processor Privilege Integrity Verification Method Based on Symbolic Execution

Abstract

The present invention discloses a method for verifying the privilege integrity of a processor based on symbolic execution. First, the Verilog code of the processor RTL design is converted into functionally equivalent C++ code, and assertions related to privilege integrity are inserted into the converted C++ code. Then, a symbolic execution engine is used to search for symbolic paths to identify vulnerabilities that may lead to assertion violations. Finally, a minimum verification platform including a CPU module and a cache module is constructed to generate a proof of concept for simulating and verifying the vulnerabilities discovered in the search phase. The present invention can effectively identify and verify the privilege transition integrity problems in the processor design.

Description

Technical Field

[0001] The present invention belongs to the field of computer technology, and particularly relates to a method for verifying the processor privilege integrity based on symbolic execution. Background Art

[0002] Formal verification methods verify hardware designs through strict mathematical approaches, providing a higher level of assurance for hardware security compared to traditional testing methods. These methods can systematically explore all possible states during the operation of hardware designs, thereby further identifying design flaws that may lead to vulnerabilities. Although formal methods provide a very thorough verification coverage for hardware designs, they also have limitations. These techniques require a large amount of specialized knowledge to accurately formulate verification conditions and may consume a large amount of resources, making it difficult for them to be applied to large and complex designs.

[0003] Symbolic execution technology stands out in the application of the huge state space of processor hardware designs by exploring multiple processor execution paths simultaneously to identify potential vulnerabilities. This method provides a balance between the depth of formal verification and the practicality of traditional testing, making it particularly suitable for the verification of hardware systems. The existing symbolic execution application scenarios often lack effective automation mechanisms, requiring a large amount of manual intervention to set test parameters and parse verification results. At the same time, there is also a lack of an integrated verification platform specifically for hardware designs, which not only increases the complexity of the verification process but also limits its feasibility in a wider range of application scenarios. In addition, existing automated verification methods attempt to improve the efficiency and coverage of the verification process by automatically generating test cases, executing tests, analyzing results, and identifying vulnerabilities. However, these methods generally lack sufficient flexibility to adapt to the verification requirements of hardware designs, especially lacking relevant work on processor privilege integrity, and are insufficient in generating actionable proof-of-concepts to demonstrate the actual impact of identified vulnerabilities. In addition, they generally do not support the seamless integration of different verification technologies (such as symbolic execution formal methods and simulation verification). All of the above problems reduce the effectiveness of these methods in providing comprehensive hardware security protection. Summary of the Invention

[0004] To overcome the deficiencies of the prior art, the present invention provides a method for verifying the privilege integrity of a processor based on symbolic execution. First, the Verilog code of the processor RTL design is converted into functionally equivalent C++ code, and assertions related to privilege integrity are inserted into the converted C++ code. Then, a symbolic execution engine is used to search for symbolic paths to identify vulnerabilities that may cause assertion violations. Finally, a minimum verification platform including a CPU module and a cache module is constructed to generate a proof of concept for simulating and verifying the vulnerabilities discovered in the search phase. The present invention can effectively identify and verify the privilege transition integrity problems in the processor design.

[0005] The technical solution adopted by the present invention to solve its technical problems is as follows:

[0006] Step 1: Code conversion;

[0007] The open-source tool Verilator is used to convert the Verilog code into functionally equivalent C++ code;

[0008] A C++ wrapper file is written to instantiate the top-level module of the hardware design;

[0009] By using the klee_make_symbolic() function of KLEE, the relevant input signals are symbolized;

[0010] Assertions related to privilege escalation are inserted into the wrapper file, and the assertions define the security vulnerability conditions that need to be detected during the symbolic execution process;

[0011] Step 2: Optimize the search path;

[0012] Utilize the advanced functions of the KLEE engine to optimize the search path by alternately using the depth-first search DFS and breadth-first search BFS strategies;

[0013] Step 3: Symbolic execution analysis;

[0014] The C++ code with assertions is compiled into the intermediate code representation LLVM IR of LLVM;

[0015] Analyze the LLVM IR code through a symbolic execution engine to explore all possible execution paths and identify the states that violate the assertions, that is, potential privilege escalation vulnerabilities;

[0016] During the symbolic execution process, when encountering a branch instruction, all possible paths will be explored, and a constraint solver will be used to determine the satisfiability of these paths;

[0017] In a hardware environment, the execution of processor instructions is simulated as corresponding symbolic expressions. When a branch instruction is encountered, the search process can independently explore and analyze different paths; path conditions are collected from these execution paths, and a constraint solver is used to determine the satisfiability of these path conditions; if a path condition cannot be satisfied, then that path is considered infeasible and the search is terminated; similarly, when an error is detected along a path, the search of that path is suspended and input values that satisfy the path condition are automatically generated.

[0018] Step 4: Test case analysis;

[0019] When performing symbolic execution analysis using KLEE, set the search mode of the KLEE engine to require returning all counterexamples for each assertion violation state, rather than stopping the search when the first assertion violation state is encountered.

[0020] Use the KLEE toolchain to analyze the generated counterexamples, which contain the specific data that triggers the assertion violation state; through this process, identify the specific inputs and conditions that lead to privilege escalation vulnerabilities, and generate corresponding test cases for each identified assertion violation state.

[0021] Step 5: Minimal system simulation and PoC generation;

[0022] Construct a minimal system simulation platform that only includes a processor module and a cache management unit capable of running instructions that trigger the vulnerability, and disable other memory-related modules to improve simulation efficiency and reduce interference.

[0023] By writing an assembly program and executing it on the simulation platform, it is automatically converted into an initialization file that can be used for minimal system verification, replay the vulnerability scenario in the test case, and generate a PoC.

[0024] Preferably, the test case contains detailed triggering conditions and can reproduce the violation state in a simulation or actual hardware environment, thereby verifying the existence of the vulnerability.

[0025] The beneficial effects of the present invention are as follows:

[0026] The present invention can effectively identify and verify privilege transition integrity issues in processor designs. Using the method of the present invention, privilege integrity can be systematically verified during the design phase, thereby preventing privilege escalation attacks and enhancing the security of the processor. The present invention focuses on solving specific challenges faced by processor security and introduces a semi - automated processor security verification method that uses heuristic - guided path exploration to optimize the search process of symbolic execution. This novel method achieves more focused and efficient checks for potential security vulnerabilities, especially privilege elevation vulnerabilities, filling the gap in the limited exploration of such issues in existing inventions. More importantly, by integrating proof - of - concept (PoC) generation into the verification method, the key links in the verification process are successfully connected, transitioning from merely identifying vulnerabilities to generating actionable exploitation scenarios. This ability is crucial for comprehensive security analysis, as it not only allows for the verification of vulnerabilities but also provides guidance on potential mitigation strategies. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the instantiated encapsulation file code of the present invention;

[0028] Figure 2 It is a flowchart of the symbolic execution engine running on the LLVM architecture of the present invention;

[0029] Figure 3 It is a vulnerability search scheme diagram of the present invention;

[0030] Figure 4 It is a schematic diagram of the test case of the present invention;

[0031] Figure 5 It is a proof - of - concept scheme diagram of the vulnerability of the present invention;

[0032] Figure 6 It is a schematic diagram of the assembly code of the test program of the present invention;

[0033] Figure 7 It is a proof - of - concept simulation waveform diagram of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] The present invention will be further described below with reference to the drawings and embodiments.

[0035] The present invention proposes a method for formally verifying the privilege integrity in processor design by using the KLEE symbolic execution engine. First, the Verilog code of the processor RTL design is converted into functionally equivalent C++ code, and assertions related to privilege integrity are inserted into the converted C++ code. Then, the symbolic execution engine is used to search for symbolic paths to identify vulnerabilities that may cause assertion violations. In addition, a minimal verification platform including a CPU module and a cache module is constructed to generate a proof of concept for simulating and validating the vulnerabilities discovered in the search phase. This method involves the following main entities: Verilog-to-C++ code conversion, search path optimization, symbolic execution analysis, test case analysis, minimal system simulation platform, and proof of concept generation.

[0036] The main steps of this method are as follows:

[0037] Step 1: Code conversion

[0038] In the present invention, an open-source tool Verilator is first adopted, which can convert Verilog code into functionally equivalent C++ code. The use of Verilator is not limited to code conversion, and it also supports being used in combination with a test platform, where the test platform is used to simulate input signals (in this case, the input signals are symbolized), and perform assertion-based verification. To implement this process, a C++ wrapper file is written to instantiate the top-level module of the hardware design. By using the klee_make_symbolic() function of KLEE, the relevant input signals can be symbolized, which is crucial for subsequent symbolic execution analysis. In addition, in the wrapper file, assertions related to privilege escalation are also inserted, and the assertions define the security vulnerability conditions that need to be detected during the symbolic execution process. For example, only when the processor is in privileged mode can it read or write the content in special registers.

[0039] The advantage of using Verilator is that it can not only perform efficient code conversion, but also conduct in-depth testing and analysis through the test platform and assertion verification. After converting the Verilog code into C++ code, the powerful functions and flexibility of the C++ language can be utilized to provide a richer and more controllable test environment for the symbolic execution engine. In addition, by introducing symbolic input and security assertions at the code conversion stage, it can also ensure to a certain extent that the symbolic execution analysis comprehensively explores all potential security vulnerabilities of the hardware design.

[0040] Step 2: Optimize the search path

[0041] Both the Verilator and LLVM architectures optimize the design code during the compilation process. However, to further improve the efficiency of vulnerability search, the concept of heuristic path exploration needs to be introduced based on the KLEE native search engine. In the core stage of symbolic execution analysis, by leveraging the advanced features of the KLEE engine and interleaving the use of depth-first search (DFS) and breadth-first search (BFS) strategies, the search paths are optimized. This approach enables a detailed exploration of specific paths while maintaining a broad coverage of the overall state space, effectively balancing the depth and breadth of the analysis.

[0042] Step 3: Symbolic Execution Analysis

[0043] Compile the C++ code with assertions into the intermediate code representation of LLVM (LLVM IR) to prepare for the analysis by the symbolic execution engine. Analyze the LLVM IR code through the symbolic execution engine to explore all possible execution paths and identify the states that violate the assertions, i.e., potential privilege escalation vulnerabilities. During the symbolic execution, when a branch instruction is encountered, all possible paths are explored, and a constraint solver is used to determine the satisfiability of these paths. Traditional simulation testing requires multiple runs to ensure comprehensive coverage and a high error detection rate. In contrast, a single execution of symbolic simulation can achieve the same goal by using symbolic values as inputs. The application of this method in hardware design is similar to its application in the software field. The specific operation in the hardware environment is to simulate the execution of processor instructions as corresponding symbolic expressions. When a branch instruction is encountered, the search process can independently explore and analyze different paths. Path conditions are collected from these execution paths, and a constraint solver is used to determine the satisfiability of these path conditions. If the path conditions cannot be satisfied, then the path is considered infeasible and the search is terminated. Similarly, when an error is detected along a path, the search for that path is suspended, and input values that satisfy the path conditions are automatically generated.

[0044] This feature of symbolic execution makes the exploration of potential security vulnerabilities, especially privilege escalation vulnerabilities, more efficient and focused. By simulating the execution of processor instructions, specific conditions and code segments that may lead to violation states can be precisely identified. Additionally, by leveraging path conditions and constraint solvers, all possible execution paths in the processor design can be systematically analyzed, thereby significantly improving the coverage and accuracy of vulnerability detection.

[0045] Step 4: Test Case Analysis

[0046] When performing symbolic execution analysis using KLEE, set the search method of the KLEE engine to require returning all counterexamples for each assertion violation state, rather than stopping the search when the first assertion violation state is encountered. This method allows in-depth analysis and understanding of every scenario that may lead to security vulnerabilities, ensuring that no potential error states are missed.

[0047] Use the KLEE toolchain to analyze the generated counterexamples, which contain the specific data that triggers the assertion violation state. Through this process, the specific inputs and conditions that trigger privilege escalation vulnerabilities can be accurately identified, and corresponding test cases are generated for each identified assertion violation state. These test cases contain detailed triggering conditions and can reproduce the violation state in a simulated or actual hardware environment, thereby verifying the existence of the vulnerability. In addition, by analyzing all counterexamples, the security of the system can be more comprehensively evaluated, and all potential vulnerability points and risk paths can be identified.

[0048] The generated test cases are not only crucial for developers and security analysts to understand and fix vulnerabilities, but also provide a solid foundation for subsequent minimal system simulation and proof-of-concept (PoC) generation. Through these refined steps and specific test cases, problems can be more accurately located, the causes of vulnerabilities can be analyzed, and potential security impacts can be evaluated.

[0049] Step 5: Minimal System Simulation and PoC Generation

[0050] Build a minimal system simulation platform that includes only the processor module and cache management unit capable of running the instructions that trigger the vulnerability, and disable other memory-related modules such as the MMU to improve simulation efficiency and reduce interference. By writing an assembly program and executing it on the simulation platform, it is automatically converted into an initialization file that can be used for minimal system verification, replay the vulnerability scenario in the test case, and generate a PoC. The present invention efficiently identifies privilege escalation vulnerabilities in processor designs in a semi-automated manner and generates corresponding proofs of concept, greatly improving the efficiency and accuracy of hardware security analysis. Through the integrated verification work method, from code conversion to vulnerability detection and then to PoC generation, a closed-loop verification process is formed, providing a new solution for the privilege integrity security verification of processor hardware designs.

[0051] Example:

[0052] The hardware environment for implementation is: an Intel i7-13650HX CPU, @2.6G (14-core processor) computer, 32GB of memory, and the software environment in operation is: Windows 11 64-bit operating system. The virtual machine operating system is Ubuntu18.04, and the method proposed by the present invention is implemented by using the GNU toolchain to build a cross-compilation environment and the ModelSim S-64 10.5 simulation software.

[0053] The specific implementation of the present invention is as follows:

[0054] 1. Construct a wrapper file that can instantiate the processor source code: Figure 1 The schematic code of the wrapper file is shown. During the process of converting the Verilog code of the RISC-V processor into C++ code, key signals should be symbolized, while non-critical signals can be ignored. For example, signals from the debug interface do not need to be symbolized. By appropriately refining the input signals, the computational cost can be reduced and the efficiency of symbolic exploration can be improved. In practice, the function klee_make_symbolic(&a, sizeof(a), a) can be used to symbolize a processor signal. The eval() function in the top-level module should be properly initialized to accurately simulate the real execution process of the processor. Usually, a complete call to eval() represents one clock transition.

[0055] Throughout the implementation process, the wrapper file also acts as a testbench. Symbolic values are assigned to the ports of the processor, and relevant assertions are added in this file. Finally, Verilator is executed with the wrapper file to generate the converted C++ code, and the C++ code of the RTL design is compiled using Clang into LLVM IR code that can be recognized by the symbolic execution engine.

[0056] 2. In the present invention, the features of the advanced symbolic execution engine KLEE are fully utilized, such as Figure 2 shown. This engine is built on top of the LLVM compiler architecture. To optimize the search path, the interleaved search heuristic in KLEE is adopted. Specifically, the user can achieve a balance between depth-first search and breadth-first search in a cyclic rotation manner. Such a strategy can not only deeply explore specific execution paths but also widely cover the entire state space, ensuring that no potential violation states are missed. Through this heuristic path exploration, the efficiency and comprehensiveness in the symbolic execution process are significantly improved. Especially when dealing with complex processor designs, this method can effectively balance the depth and breadth of exploration and optimize the use of computational resources.

[0057] 3. Figure 3 The schematic diagram of the vulnerability search process is shown. After a series of code translation processes, the KLEE engine accepts the generated intermediate representation code as input and symbolically explores the processor core to collect the constraint conditions in the path. When an assertion is violated, that is, when a possible security vulnerability is detected, the constraint solver will generate a counterexample, which contains specific input values. These input values are the specific instructions that trigger the possible security vulnerability in the scenario of hardware security verification.

[0058] 4. Regarding the test case analysis process, taking the open-source processor Or1200 as an example, the detailed implementation manner and specific operation process of the present invention are given. The KLEE symbolic execution engine explores the state space of the design through assertions and symbolic inputs. A total of 54,075 test cases are generated, among which 3,455 test cases may lead to violations of assertion properties. Through analysis using the ktest toolchain, it is found that the highest six bits of the data in all test cases that violate the assertion are 101101, and the opcode matches the l.mfspr (move data from a special-purpose register) instruction in the Or1200 specification. The format of the l.mfspr instruction is l.mfspr rD,rA,K, where the result of the logical OR operation between the value of register rA and the immediate number K is used as the address to access a specific special register (for example, the access to SR is 0x0011), and then the content in this special register is loaded into register rD. During the process of generating test cases, specific data that can trigger the assertion violation state needs to be particularly concerned about. Figure 4 Shows the schematic code of a test case, where the data that triggers the assertion violation state is "b7 def0 03" in big-endian order, and the opcode is 101101, which can be determined to be the l.mfspr instruction. However, the value of the immediate number "f0 03" will result in an unreachable address being generated in the Or1200 when performing a logical OR operation with any value. In this case, the data in many test cases may be meaningless.

[0059] To improve the relevance of protection against privilege escalation attacks, it is necessary to further study the specification file of the processor Or1200. Summarize the key special-purpose register information that may leak sensitive data when executing the l.mfspr instruction, and generate test assembly programs for these registers. The privilege integrity of these special-purpose registers is verified through simulation.

[0060] 5. The proof-of-concept scheme for the vulnerability of the present invention is as Figure 5 shown. To further improve the automation level, four parts, namely compilation, linking, obtaining the binary executable file, and format conversion, are refined, and they are integrated by writing a link description script and a format conversion program. The data in the assertion violation state obtained in the previous step is converted into a file that can be used to initialize the minimum system.

[0061] First, it is necessary to create an assembly program that reflects the assertion violation state and prepare a test environment for the minimum verification system. Figure 6 Shows the schematic code of the test program. By precisely writing assembly instructions and configuring the test platform, specific assertion violation scenarios, such as improper access to privilege registers, can be simulated.

[0062] In the minimum system simulation, the execution code is configured by initializing the data file, and the system configuration is modified to ensure that the CPU can directly read instructions from the cache module. The created verification environment only contains the CPU and the QMEM cache module, and the unnecessary external ports are turned off. After the configuration is completed, the source code, initialization data, and testbench files are compiled and simulated in ModelSim to observe the changes in the key signals related to privilege conversion. The waveform picture segment is as Figure 7 shown. In the simulation waveform, the changes in the key nodes can be directly observed.

[0063] Combining the test instructions and the waveform diagram, it can be found that when the process is in user mode (0x8000), the value of the special-purpose register chip select signal spr_cs is still not zero, which indicates that the l.mfspr instruction can be wrongly executed in user mode to read the value in the special-purpose register EPCR0 (address 0x0020). This situation may lead to the leakage of sensitive data in the special-purpose register. In this way, users can not only intuitively detect the violation of the assertion status in the simulation waveform, but also verify the potential risk of sensitive data leakage. The results prove that the inventive method provides a perfect idea for identifying and solving possible processor privilege integrity security problems in the design stage, improving the overall security of the processor design.

Claims

1. A method for verifying the privilege integrity of a processor based on symbolic execution, characterized in that It includes the following steps: Step 1: Code conversion; Using the open-source tool Verilator, convert Verilog code into functionally equivalent C++ code; Write a C++ encapsulation file for instantiating the top-level module of the hardware design; By using the klee_make_symbolic() function of KLEE, symbolize the relevant input signals; Insert assertions related to privilege escalation in the encapsulation file, and the assertions define the security vulnerability conditions to be detected during symbolic execution; Step 2: Optimize the search path; Utilize the advanced features of the KLEE engine to optimize the search path by alternately using the depth-first search (DFS) and breadth-first search (BFS) strategies; Step 3: Symbolic execution analysis; Compile the C++ code with assertions into the intermediate code representation LLVM IR of LLVM; Analyze the LLVM IR code through the symbolic execution engine to explore all possible execution paths and identify the states that violate the assertions, i.e., potential privilege escalation vulnerabilities; During symbolic execution, when encountering a branch instruction, explore all possible paths and use a constraint solver to determine the satisfiability of these paths; In a hardware environment, simulate the execution of processor instructions as corresponding symbolic expressions. When encountering a branch instruction, the search process can independently explore and analyze different paths; Collect path conditions from these execution paths and use a constraint solver to determine the satisfaction of these path conditions; If the path condition cannot be satisfied, then this path is considered infeasible and the search is terminated; similarly, when an error is detected along a path, the search of this path is suspended and input values that satisfy the path condition are automatically generated; Step 4: Test case analysis; When performing symbolic execution analysis using KLEE, set the search mode of the KLEE engine to require the return of all counterexamples for each state that violates the assertion, rather than stopping the search when the first state that violates the assertion is encountered; Utilize the KLEE toolchain to analyze the generated counterexamples, which contain the specific data that triggers the state that violates the assertion; through this process, identify the specific inputs and conditions that trigger the privilege escalation vulnerability and generate corresponding test cases for each identified state that violates the assertion; Step 5: Minimal system simulation and PoC generation; Build a minimal system simulation platform that only includes a processor module and a cache management unit capable of running instructions that trigger the vulnerability, and disable other memory-related modules to improve simulation efficiency and reduce interference; By writing an assembly program and executing it on the simulation platform, it is automatically converted into an initialization file that can be used for minimal system verification, replay the vulnerability scenario in the test case, and generate a PoC.

2. The processor privilege integrity verification method based on symbolic execution according to claim 1, wherein The test case contains detailed triggering conditions and can reproduce the violation state in a simulated or actual hardware environment, thereby verifying the existence of the vulnerability.

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