A hardware security vulnerability knowledge graph assisted verilog security code generation method and device

Abstract

The application discloses a kind of hardware security vulnerability knowledge graph assisted Verilog security code generation method and device, the method is first according to the natural language description of hardware code generation task input by user, hardware code generation task is decomposed into several subtasks, signal, state conversion and circuit code example are extracted.Second, hardware security vulnerability data is acquired, and hardware vulnerability security knowledge graph is constructed from top to bottom.Then according to the natural language description of subtask, signal, state conversion and circuit code example generates Verilog code.Last, based on hardware vulnerability security knowledge graph, Verilog code is detected and repaired security vulnerability, and generates security Verilog code.The application improves the efficiency and security of hardware code generation, with flexibility and scalability, and reduces implementation complexity.

Description

Technical Field

[0001] This invention belongs to the fields of hardware security technology and code generation technology, specifically relating to a Verilog secure code generation method and apparatus assisted by a hardware security vulnerability knowledge graph. Background Technology

[0002] Designing modern integrated circuits requires designers to write code using hardware description languages ​​such as Verilog to specify the hardware architecture and model the behavior of digital systems. Due to the increasing complexity of VLSI (Very Large Scale Integration) designs, writing Verilog code has become time-consuming and error-prone, forcing designers to iterate multiple times to debug syntax, functional correctness, and security. Therefore, reducing design costs and the effort required for designers to complete hardware specifications has become a pressing need. Large Language Models (LLMs) have shown remarkable capabilities in understanding and generating natural language, enabling large-scale processing and bringing numerous potential applications and benefits across various fields. In the field of code generation, LLMs can assist developers by suggesting code snippets, providing solutions to fix errors, and generating explained code. Currently, hardware generation using large language models can be categorized into methods based on fine-tuning optimization and methods based on machine learning.

[0003] Fine-tuning optimization methods have several drawbacks: they carry the risk of overfitting, especially with small datasets; they require significant computational resources; they may introduce data bias, affecting the model's generalization ability; they carry the risk of catastrophic forgetting, causing the model to forget pre-trained knowledge; hyperparameter tuning is complex, increasing training difficulty; and they are highly domain-dependent, potentially performing poorly when the pre-training task differs significantly from the target task.

[0004] Machine learning-based methods focus on the syntactic and functional correctness of generated code, but lack mechanisms to correct errors, making it difficult to guarantee the overall correctness of the generated code in terms of syntax, functionality, and security. Summary of the Invention

[0005] To address the aforementioned issues, this invention proposes a Verilog secure code generation method and apparatus assisted by a hardware security vulnerability knowledge graph, aiming to solve the problems of insufficient comprehensiveness and security guarantees in existing hardware code generation methods. This method utilizes a multi-agent system and a large language model, combined with a hardware security vulnerability knowledge graph and a dedicated vulnerability detection and repair mechanism, to achieve automated generation, detection, and repair of Verilog code. This solution not only improves the efficiency and quality of hardware code generation but also solves the problems of lack of error correction, strong dependence on data and domain, and high training complexity in existing technologies.

[0006] The technical solution adopted by the present invention to solve the above-mentioned technical problems is as follows:

[0007] A method for generating secure Verilog code with the assistance of a hardware security vulnerability knowledge graph includes the following steps:

[0008] S1. Generate a natural language description of the hardware code generation task based on the hardware code input by the user, and decompose the hardware code generation task into several sub-tasks.

[0009] S2, Example of extracting signals, state transitions and circuit code from the hardware generation subtask natural language description.

[0010] S3. Obtain hardware security vulnerability data and build a hardware vulnerability security knowledge graph from top to bottom.

[0011] S4. Generate Verilog code based on the natural language description of the subtask, subtask signals, subtask state transitions, and subtask circuit code examples.

[0012] S5. Based on a hardware vulnerability security knowledge graph, perform security vulnerability detection and fix on Verilog code to generate secure Verilog code.

[0013] Furthermore, step S1 specifically involves the large language model understanding the natural language description of the hardware code generation task input by the user, planning the complex hardware generation task according to functional modules, and decomposing the hardware generation task into several hardware generation sub-tasks.

[0014] Further, step S2 specifically involves the large language model extracting signal, state transition, and circuit code example information of the hardware subtask based on the natural language description of the hardware-generated subtask.

[0015] Further, step S3 specifically extracts semi-structured and unstructured hardware vulnerability knowledge data from hardware security vulnerability documents. The acquired data is then processed to remove HTML tags, special characters, stop words, etc., while retaining the text content. The text is segmented and stemmed to convert it into a unified format and combine the results to obtain a dataset. A hardware vulnerability security knowledge graph is constructed from top to bottom, determining the top-level ontology in the hardware security vulnerability domain, including multiple entities, and designing attributes to represent the relationships between these entities and the attributes required for each entity. Entities, relationships, and attributes are clearly defined, establishing an ontology layer schema. A large language model is used to extract entities, relationships, and attributes from the data. Entity, relationship, and attribute data from the hardware security vulnerability data are obtained, added to the data layer, and a knowledge graph is generated. Entities, relationships, and attributes are stored in the graph database as triples.

[0016] Further, step S4 specifically involves the large language model generating Verilog code based on the natural language description of the subtask and the extracted circuit signals, state transitions, and circuit code example information. Based on the generated Verilog code, the large language model calls the syntax and functional checking tool, iverilog, to compile and start Verilog simulation. If the Verilog code contains syntax errors or is inconsistent with the subtask's functional description, the tool will report the line numbers where these errors occurred and the simulation results, providing compilation messages, the number of mismatches between operations and output signals, and the time point of the first mismatch as feedback to the calling tool. The large language model corrects the syntax and functional errors based on the syntax and functional error information returned by the called tool. These steps are repeated until the generated Verilog code is free of syntax errors and consistent with the subtask description, or until the set number of iterations is reached. Finally, the subtask-generated Verilog code is integrated to obtain syntactically and functionally correct Verilog code.

[0017] Further, step S5 specifically involves using the CWEAT code detection method to detect syntactically and functionally correct Verilog code, obtaining information on the type and location of hardware security vulnerabilities in the Verilog code. The large language model then calls a graph retrieval tool based on the feedback information from the CWEAT. The large language model then repairs the vulnerabilities based on the feedback information obtained from the hardware security vulnerability knowledge graph by the graph retrieval tool. The above steps are repeated until the generated code passes the CWEAT method detection or reaches the set number of iterations, thus generating secure, syntactically correct, and functionally correct Verilog code.

[0018] Further, in step S5, the graph retrieval tool is a Cypher language generated by the large language model to retrieve all nodes within a 2-hop of a specific hardware vulnerability security code type. The Cypher language is used to retrieve the hardware security vulnerability knowledge graph and returns information on all subgraph nodes within a 2-hop of the corresponding hardware vulnerability security code type entity. The subgraph node information includes a natural language description of the hardware security vulnerability, normative guidance for correction, and vulnerability bug fix code examples.

[0019] Further, in step S5, the CWEAT method uses a heuristic detection algorithm to traverse the rules based on hardware security vulnerabilities and construct a Verilog abstract syntax tree, then uses keywords to traverse the abstract syntax tree. Keyword matching rules include matching rules and exclusion rules. Security-related features in the Verilog code are located through keyword matching. If a code snippet's keyword does not match a security keyword, the code snippet is marked as insecure; otherwise, it is marked as secure.

[0020] Further, in step S5, the method for constructing the Verilog abstract syntax tree involves traversing the Verilog source code and interpreting the compilation instructions. This is accomplished using the lexical analyzer flex, which identifies supported keywords and literals and records the current code position through global variables to annotate the source location of each abstract syntax tree node. The parser generator bison is also used to generate an abstract syntax tree, where each node is annotated with its source location in the code. This supports different types of Verilog syntax and structures, such as modules, functions, tasks, parameters, arrays, operators, and logic blocks.

[0021] Secondly, the present invention also provides a Verilog secure code generation device assisted by a hardware security vulnerability knowledge graph, wherein the device comprises:

[0022] The task planning module is used to generate tasks from the hardware code input by the user and break them down into several sub-tasks.

[0023] The circuit signal information extraction module is used to extract signal, state transition, and circuit example information of subtasks through a large language model.

[0024] The knowledge graph construction module builds a hardware security vulnerability knowledge graph based on hardware security vulnerability data.

[0025] The Verilog code generation module generates Verilog code based on the natural language description of the subtasks and the extracted circuit signals, state transitions, and circuit code examples from the subtasks, using a large language model.

[0026] The detection and repair module is used to detect and repair hardware security vulnerabilities in the generated Verilog code, and generate secure Verilog code.

[0027] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0028] This invention improves the efficiency and security of hardware code generation by working together with modules such as task planning, signal extraction, code generation, and security detection. It also has flexibility and scalability, making it easy to update and add features later.

[0029] This invention integrates a hardware security vulnerability knowledge graph and an iterative optimization mechanism, enabling the code to reach high standards during generation, detection, and repair. It overcomes the shortcomings of current methods, improves the accuracy of code generation, and reduces implementation complexity, providing a reliable solution for hardware designers. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the overall process of the present invention;

[0031] Figure 2 This is a schematic diagram of the task planning intelligent agent module of the present invention;

[0032] Figure 3 This is a schematic diagram of the circuit signal, conversion, and case extraction intelligent agent module of the present invention;

[0033] Figure 4 A schematic diagram of the process for constructing an intelligent agent module for the hardware security vulnerability knowledge graph of this invention;

[0034] Figure 5 This is a schematic diagram of the code generation intelligent agent module of the present invention;

[0035] Figure 6 This is a schematic diagram of the hardware security detection and repair intelligent agent module of the present invention. Detailed Implementation

[0036] To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0037] This example provides a Verilog secure code generation method and apparatus assisted by a hardware security vulnerability knowledge graph. Based on this embodiment, the large language model can more accurately understand and generate functionally correct and secure hardware code that meets requirements. In specific applications, this example first uses the large language model to decompose the hardware generation task into hardware security generation sub-tasks; based on the hardware security generation sub-tasks, circuit signals, state transitions, and circuit examples are extracted. Then, a hardware security vulnerability knowledge graph is constructed based on hardware security vulnerability data. Based on the sub-task descriptions and circuit generation dependency information, these are input into the large language model. The large language model not only generates code but also automatically identifies and fixes grammatical and functional errors and security vulnerabilities using feedback from syntax and functional checking tools, the hardware security vulnerability knowledge graph, and CWEAT. Finally, syntactically and functionally correct and secure Verilog code is obtained after multiple iterations. Large language models perform excellently in the field of natural language processing, and this advantage is effectively translated and applied to hardware code generation in this example. This automation capability significantly reduces the need for manual intervention, reduces errors caused by human negligence, and thus improves the efficiency, accuracy, and security of code generation.

[0038] Example: A Verilog secure code generation method assisted by a hardware security vulnerability knowledge graph, comprising:

[0039] Step 1: Obtain user input and generate a natural language description of the hardware task. Combined with... Figure 2As shown, this example first obtains the user input hardware natural language description. The hardware generates a natural language description to implement the following Moore state machine, whose inputs are a 3-bit user_input, a clock signal clk, and a reset signal rst_n, and whose output is a 3-bit out. When the reset signal is low, the state is initialized to 2'h0; at the rising edge of the clock, according to the value of user_input, at the rising edge of the clock (posedge clk), when the value of user_input is 3'h0 to 3'h5, the state is set according to a predetermined mapping rule: 3'h0 corresponds to state = 2'h0, 3'h1 corresponds to state = 2'h1, 3'h2 corresponds to state = 2'h2, 3'h3 corresponds to state = 2'h3, 3'h4 corresponds to state = 2'h2, and 3'h5 corresponds to state = 2'h1. The 3-bit out signal is then output by concatenating the constant 1 and the state. This state machine supports six different user_input values, and defaults to outputting 2'h0 when user_input exceeds these ranges. Complex hardware tasks are decomposed into hardware generation subtasks. These hardware generation subtasks include...

[0040] 1. Define the module's input and output ports: The module should have inputs: a 3-bit 'user_input', a clock signal 'clk', a reset signal 'rst_n', and an output: a 3-bit 'out'.

[0041] 2. Define and initialize the status register: The status should be a 2-bit register, initialized to 2'h0 when the reset signal 'rst_n' is low.

[0042] 3. State transition logic: Defined to transition the state based on the value of 'user_input' on the rising edge of the clock.

[0043] 4. Output logic: Concatenate the constant value '1' with the current 'state' to generate a 3-bit output 'out'.

[0044] 5. Handle out-of-range 'user_input' values. If 'user_input' exceeds the defined range of 6 values, the 'out' signal should output 2'h0 by default.

[0045] Step Two, Combining Figure 3 As shown, a subtask description is generated based on hardware, extracting circuit signals, state transitions, and sample circuit code information. Subtask description: Defined to perform state transitions based on the value of 'user_input' on the rising edge of the clock.

[0046] - clk: Clock signal, triggers state machine update (rising edge triggered) (type: signal)

[0047] - rst_n: Reset signal. A low level activates the reset, initializing the state register to 2'h0 (type: signal).

[0048] - user_input: A 3-bit input signal that determines the state transitions of the state machine (type: signal).

[0049] - State () -- user_input=3'h0--> State0 (Type: State Transition)

[0050] - State () -- user_input=3'h1--> State1 (Type: State Transition)

[0051] - State () -- user_input=3'h2--> State2 (Type: State Transition)

[0052] - State () -- user_input=3'h3--> State3 (Type: State Transition)

[0053] - State () -- user_input=3'h4 --> State2 (Type: State Transition)

[0054] - State () -- user_input=3'h5--> State1 (Type: State Transition)

[0055] - When the value of user_input is 3'h0 to 3'h5, 3'h0 corresponds to state = 2'h0, 3'h1 corresponds to state = 2'h1, 3'h2 corresponds to state = 2'h2, 3'h3 corresponds to state = 2'h3, 3'h4 corresponds to state = 2'h2, and 3'h5 corresponds to state = 2'h1. (Type: Signal Example)

[0056] Step 3, Combining Figure 4As shown, data is obtained from the MITRE_CWE hardware security vulnerability document (an open-source vulnerability classification document that helps developers and security experts identify security vulnerabilities in software and hardware). The semi-structured and unstructured data are cleaned, standardized, and labeled to obtain a dataset. A hardware vulnerability security knowledge graph is constructed from top to bottom, determining the top-level ontology in the hardware security vulnerability domain, including multiple entities, and designing attributes to represent the relationships between these entities and the attributes required for each entity. Entities, relationships, and attributes are clearly defined, establishing an ontology layer schema. A large language model is used to extract entities, relationships, and attributes from the data. Entity, relationship, and attribute data from the hardware security vulnerability data are obtained and added to the data layer to generate the knowledge graph. Entities, relationships, and attributes are stored in a graph database as triples; for example:

[0057] Cleaning, standardization, and labeling of semi-structured and unstructured data:

[0058] Data cleaning:

[0059] Text cleaning: Remove HTML tags, special characters, stop words, etc. from text while retaining the text content.

[0060] Data format conversion: Converting unstructured data into structured data, such as converting text data into CSV format suitable for large language models.

[0061] Data standardization:

[0062] Text standardization: This involves processing the text through word segmentation, stemming, and part-of-speech tagging to convert it into a uniform format.

[0063] The ontology layer pattern is shown in Table 1:

[0064] Table 1

[0065]

[0066] Step 4: Combining Figure 5 As shown, Verilog code is generated based on the subtask description, circuit signals, state transitions, and example circuit code information:

[0067] module fsm_1(out, user_input, clk, rst_n);

[0068] input [2:0] user_input;

[0069] input clk, rst_n;

[0070] output reg [2:0] out;

[0071] reg [1:0] state;

[0072] always @ (posedge clk or negedge rst_n)

[0073] begin

[0074] if (!rst_n)

[0075] state = 3'h0;

[0076] else

[0077] case (user_input)

[0078] 3'h0: state = 2'h0;

[0079] 3'h1: state = 2'h1;

[0080] 3'h2: state = 2'h2;

[0081] 3'h3: state = 2'h3;

[0082] 3'h4: state = 2'h2;

[0083] 3'h5: state = 2'h1;

[0084] endcase

[0085] end

[0086] assign out = {1'h1, state};

[0087] endmodule

[0088] The function syntax checking tool iverb returns the following results:

[0089] [Function Check Failed]

[0090] ==Report start==

[0091] VCD info: dumpfile wave.vcd

[0092] Output was opened.

[0093] VCD warning: $dumpvars: Package

[0094] ($unit) is not dumpable with VCD.

[0095] . / Verilog_tool_tmp / / test.sv:21:

[0096] $finish called at 996 (1ps)

[0097] Hint: Output 'state' has 1 mismatches.

[0098] First mismatch occurred at time 5.

[0099] Hint: Total mismatched samples is

[0100] 1 out of 199 samples

[0101] The large language model generates code based on the results returned by the iverlog tool:

[0102] module fsm_1(out, user_input, clk, rst_n);

[0103] input [2:0] user_input;

[0104] input clk, rst_n;

[0105] output reg [2:0] out;

[0106] reg [1:0] state;

[0107] always @ (posedge clk or negedge rst_n)

[0108] begin

[0109] if (!rst_n)

[0110] state = 2'h0;

[0111] else

[0112] case (user_input)

[0113] 3'h0: state = 2'h0;

[0114] 3'h1: state = 2'h1;

[0115] 3'h2: state = 2'h2;

[0116] 3'h3: state = 2'h3;

[0117] 3'h4: state = 2'h2;

[0118] 3'h5: state = 2'h1;

[0119] endcase

[0120] end

[0121] always @(*)

[0122] out = {1'h1, state};

[0123] endmodule

[0124] The large language model calls the iverilog tool again, returning [Compiled Success] and [Function CheckSuccess] messages, completing the generation of syntactically and functionally correct Verilog code.

[0125] Step 5, Combining Figure 6 As shown, CWEAT method detection was performed on Verilog code with correct syntax and functionality, and the following code was found to contain the CWE1245 vulnerability:

[0126] case (user_input)

[0127] 3'h0: state = 2'h0;

[0128] 3'h1: state = 2'h1;

[0129] 3'h2: state = 2'h2;

[0130] 3'h3: state = 2'h3;

[0131] 3'h4: state = 2'h2;

[0132] 3'h5: state = 2'h1;

[0133] endcase

[0134] Based on the feedback information, the large language model calls the graph retrieval tool to match CWE1245 entity nodes and returns subgraph information:

[0135] / / BUG: Incorrect Finite State Machines (FSMs) in the hardware logic

[0136] / / Fix: The case statement did not include a default value to handle scenarios where the user provided 3'h6' and 3'h7 inputs. These inputs pushed the system into an undefined state and could potentially cause a crash (denial of service) or any other unexpected results. Adding a default statement to handle undefined inputs can alleviate this problem.

[0137] The large language model fixed the CWE1234 vulnerability based on feedback from the graph retrieval tool:

[0138] case (user_input)

[0139] 3'h0: state = 2'h0;

[0140] 3'h1: state = 2'h1;

[0141] 3'h2: state = 2'h2;

[0142] 3'h3: state = 2'h3;

[0143] 3'h4: state = 2'h2;

[0144] 3'h5: state = 2'h1;

[0145] default: state = 2'h0;

[0146] endcase

[0147] After the large model is repaired, the CWEAT method is called again to check the code. The feedback is [no Vulnerability], and safe Verilog code is output:

[0148] module fsm_1(out, user_input, clk, rst_n);

[0149] input [2:0] user_input;

[0150] input clk, rst_n;

[0151] output reg [2:0] out;

[0152] reg [1:0] state;

[0153] always @ (posedge clk or negedge rst_n)

[0154] begin

[0155] if (!rst_n)

[0156] state = 2'h0; / / 2-bit reset value

[0157] else

[0158] case (user_input)

[0159] 3'h0: state = 2'h0;

[0160] 3'h1: state = 2'h1;

[0161] 3'h2: state = 2'h2;

[0162] 3'h3: state = 2'h3;

[0163] 3'h4: state = 2'h2;

[0164] 3'h5: state = 2'h1;

[0165] default: state = 2'h0;

[0166] endcase

[0167] end

[0168] always @(*)

[0169] out = {1'h1, state};

[0170] endmodule

[0171] In this embodiment, the generation of hardware code is achieved through multi-step task decomposition and security vulnerability detection, ensuring that the generated Verilog code is functionally correct and meets security requirements. First, the user-input natural language description of the hardware task is obtained, and based on this description, the hardware task is decomposed into multiple sub-tasks, such as defining module inputs and outputs, initializing status registers, and designing state transition logic. Next, by extracting circuit signals and state transition information, corresponding Verilog code is generated, and its correctness is verified using a functional syntax checking tool. Based on the code verified by the functional syntax checking tool, a potential hardware security vulnerability (CWE-1245 vulnerability) is discovered using the CWEAT method. By calling a graph search tool to match corresponding vulnerability remediation suggestions, the defects in the code are further fixed, ensuring code security. Finally, the code after vulnerability remediation is tested using the CWEAT method, confirmed to be vulnerability-free, and secure Verilog code is output.

[0172] Furthermore, to enhance the large language model's generation capabilities, this embodiment decomposes the hardware task into multiple sub-tasks and provides three key pieces of information: hardware task description, sub-task description, and security vulnerability information. This information helps the large language model more accurately understand user needs and generate secure code that meets those needs. This approach not only improves the accuracy of code generation but also enhances the security of the generated code, reduces subsequent debugging and vulnerability patching work, and thus effectively improves development efficiency.

[0173] Compared with existing technologies, this embodiment overcomes the shortcomings of current hardware code generation methods, including the risk of overfitting during fine-tuning and the lack of effective error correction mechanisms in machine learning methods. Through the collaborative work of multiple agents and the powerful generation and repair capabilities of a large language model, this invention achieves efficient and automated hardware code generation and vulnerability repair. This method significantly improves the efficiency and security of code generation while reducing the complexity of implementation, providing hardware designers with an efficient and reliable solution.

[0174] Table 2

[0175]

[0176] The design representative provides the hardware name to be generated, along with a corresponding natural language description and a reference design Verilog handwritten by a human designer. By comparing with this reference design, the design quality of the automatically generated Verilog can be quantitatively evaluated. A quantitative evaluation of the syntactic and functional correctness of the large language model using a hardware security vulnerability knowledge graph-assisted Verilog secure code generation method is summarized. The correctness part counts the number of correct functions and syntaxes in the generated Verilog designs across five trials. The security part counts the number of generated RTLs that successfully pass the test benchmark, provided that the RTL has correct functionality and syntax. According to Table 2, the state-of-the-art large language model B performs best in terms of functional syntax, achieving a 92% accuracy rate and a 64% security rate. In contrast, the performance of large language model A alone drops to 72% accuracy and 42% functional correctness. After combining with a hardware security vulnerability knowledge graph-assisted Verilog secure code generation method, the performance of large language model A recovers to 88% and 64%, approaching the performance of large language model B. This clearly verifies the effectiveness of a Verilog secure code generation method assisted by a hardware security vulnerability knowledge graph. Overall, the performance ranking is: Large Language Model B + [method assisted by a hardware security vulnerability knowledge graph] > Large Language Model B > Large Language Model A + [method assisted by a hardware security vulnerability knowledge graph] > Large Language Model A > [method assisted by a hardware security vulnerability knowledge graph]

[0177] Based on the above embodiments, the present invention also provides a Verilog secure code generation device assisted by a hardware security vulnerability knowledge graph, such as... Figure 1 As shown, the device includes: a task planning module, a circuit signal information extraction module, a knowledge graph construction module, a Verilog code generation module, and a detection and repair module. This device, through the collaborative work of multiple intelligent agent modules, forms a closed-loop system, aiming to automatically generate highly secure Verilog code.

[0178] In one implementation, the task planning module includes:

[0179] Natural language descriptions of hardware modules used to receive user input, and decompose complex hardware tasks into specific hardware generation subtasks.

[0180] In one implementation, the circuit signal information extraction module includes:

[0181] Used to extract the required circuit signals and state transition information based on the hardware generation subtask description generated by the task planning agent module.

[0182] In one implementation, the knowledge graph construction module includes:

[0183] Hardware security vulnerability data is acquired, preprocessed including text cleaning, word segmentation, and stemming, and then converted into a unified format to construct a hardware security vulnerability knowledge graph. This graph includes a top-level ontology design, clearly defining entities, relationships, and attributes, which are stored as triples in a graph database.

[0184] In one implementation, the Verilog code generation module includes:

[0185] Based on the subtasks of the task planning agent module and the signal dependency information of the circuit signal extraction module, Verilog code is generated using a large language model and verified using syntax and functionality checking tools (such as Iverilog). If errors are found in the generated code, the tool will report the error location and simulation results. The generated error feedback will be used by the large language model to repair the generated code, ensuring that the generated code is syntactically correct and functionally complete.

[0186] In one implementation, the detection and repair module includes:

[0187] The CWEAT method is used to perform security vulnerability detection on the generated Verilog code. If vulnerabilities are found, the system will use a graph retrieval tool to query the knowledge graph to obtain relevant vulnerability descriptions and fix code information, assisting the large language model in fixing the vulnerabilities, and finally generating secure and functional Verilog code.

[0188] The working principle of each module in the Verilog secure code generation device assisted by the hardware security vulnerability knowledge graph in this embodiment is the same as that of each step in the above method embodiment, and will not be repeated here.

[0189] The present invention has been described by way of example in conjunction with the accompanying drawings. Obviously, the specific implementation of the present invention is not limited to the above-described manner. Any non-substantial improvement made by adopting the inventive concept and technical solution of the present invention, or the direct application of the inventive concept and technical solution of the present invention to other occasions without modification, shall be within the protection scope of the present invention.

Claims

1. A method for generating Verilog secure code assisted by a hardware security vulnerability knowledge graph, characterized in that, Includes the following steps: S1. Based on the hardware code input by the user, generate a natural language description of the task and decompose the hardware code generation task into several sub-tasks. S2, Example of extracting signals, state transitions and circuit code from the natural language description of a subtask; S3. Obtain hardware security vulnerability data and build a hardware vulnerability security knowledge graph from top to bottom; S4. Generate Verilog code based on the natural language description, signals, state transitions, and circuit code examples of the subtasks. The specific implementation process is as follows: Based on the natural language description of the subtask and the extracted circuit signals, state transitions, and circuit code example information, the large language model generates Verilog code. Based on the generated Verilog code, the large language model calls the syntax checking and functional checking tool iverilog to compile and start Verilog simulation. If there are syntax errors in the Verilog code or if it is inconsistent with the functional description of the subtask, the tool will report the number of lines where these errors occurred and the simulation results, and provide the number of mismatches between the compilation message and the output signal, as well as the time point of the first mismatch, as feedback for calling the tool. The large language model corrects syntax and functional errors based on the syntax and functional error information returned by the invoked tools. Repeat the above process until the generated Verilog code is free of syntax errors and consistent with the subtask description, or until the set number of iterations is reached; integrate the subtasks to generate Verilog code, and obtain Verilog code with correct syntax and functionality. S5. Based on the hardware vulnerability security knowledge graph, perform security vulnerability detection and fix security vulnerabilities in Verilog code to generate secure Verilog code. The specific implementation process is as follows: the Verilog code with correct syntax and function is detected by the code detection method to obtain the hardware security vulnerability type and vulnerability location information of the Verilog code. The large language model calls the graph retrieval tool according to the feedback information of the code detection method. The large language model fixes the vulnerability according to the feedback information obtained from the hardware security vulnerability knowledge graph by the graph retrieval tool. The above process is repeated until the generated code passes the code detection method or reaches the set number of iterations, generating secure, syntactically correct and functionally correct Verilog code. The graph retrieval tool is a Cypher language generated by a large language model to retrieve all nodes within 2 hops of a hardware vulnerability security code type node. It uses the Cypher language to retrieve the hardware security vulnerability knowledge graph and returns all subgraph node information within 2 hops of the corresponding hardware vulnerability security code type entity. The subgraph node information includes natural language descriptions of hardware security vulnerabilities, normative guidance for correction, and vulnerability error repair code examples. The code detection method employs a heuristic detection algorithm to traverse the Verilog abstract syntax tree based on the rules for hardware security vulnerabilities, and uses keywords to traverse the abstract syntax tree. The keyword matching rules include matching rules and exclusion rules. Security-related features in Verilog code are located through keyword matching. If the keyword of a code segment does not match the security keyword, the code segment is marked as unsafe; otherwise, the code segment is marked as safe. The specific implementation of constructing the Verilog abstract syntax tree is as follows: traversing the Verilog source code and interpreting and processing compilation instructions; using the lexical analyzer flex to identify supported keywords and literals; and recording the current code position through global variables to mark the source position of each abstract syntax tree node. The parser generator bison is used to accomplish this. Bison generates an abstract syntax tree, and each node of the abstract syntax tree is marked with the source location in the code. It supports different types of Verilog syntax and structure.

2. The Verilog secure code generation method assisted by hardware security vulnerability knowledge graph according to claim 1, characterized in that, The specific implementation process of step S1 is as follows: understand the natural language description of the hardware code generation task input by the user through a large language model, plan the hardware code generation task according to the functional modules, and decompose the hardware generation task into several hardware generation sub-tasks.

3. The Verilog secure code generation method assisted by hardware security vulnerability knowledge graph according to claim 2, characterized in that, The specific implementation process of step S2 is as follows: Based on the natural language description of the subtask, the large language model extracts the signal, state transition and circuit code examples of the subtask.

4. The Verilog secure code generation method assisted by hardware security vulnerability knowledge graph according to claim 3, characterized in that, The specific implementation process of step S3 is as follows: This process involves extracting semi-structured and unstructured hardware vulnerability knowledge data from hardware security vulnerability documents. The data is then processed by removing HTML tags, special characters, and stop words while retaining the text content. The text is segmented and stemmed to convert it into a unified format, and then combined to obtain a dataset. A top-down hardware vulnerability security knowledge graph is constructed, defining a top-level ontology in the hardware security vulnerability domain, including multiple entities and designing attributes to represent relationships between entities. Entities, relationships, and attributes are clearly defined, establishing an ontology layer schema. Finally, a large language model is used to extract entities, relationships, and attributes from the data. The entity, relation, and attribute data from hardware security vulnerability data are obtained, added to the data layer, and a knowledge graph is generated. The entities, relations, and attributes are stored in the graph database in the form of triples.

5. A Verilog secure code generation device assisted by a hardware security vulnerability knowledge graph, used to implement the code generation method according to any one of claims 1 to 4, characterized in that, Includes the following modules: The task planning module is used to generate tasks from the hardware code input by the user and decompose them into several sub-tasks; The circuit signal information extraction module is used to extract signal, state transition, and circuit example information of subtasks through a large language model; The knowledge graph construction module builds a hardware security vulnerability knowledge graph based on hardware security vulnerability data. The Verilog code generation module generates Verilog code based on the natural language description of the subtask and the extracted circuit signals, state transitions, and circuit code examples of the subtask, using a large language model. The detection and repair module is used to detect and repair hardware security vulnerabilities in the generated Verilog code, and generate secure Verilog code.

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