Frame-aware cache replacement strategy for multimedia compression

Abstract

Various embodiments include methods and apparatus for implementing a criteria-aware cache replacement policy by a computing device. Embodiments may include: updating a stale counter; writing a value of a local counter to a system cache in association with a location in the system cache for data, wherein the value of the local counter includes the value of the stale counter when the associated data was written to the system cache (i.e., at the time); and determining whether the associated data is stale using the value of the local counter for the associated data.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. non-provisional application No. 17 / 646,690, filed on December 31, 2021; the entire contents of which are incorporated herein by reference. Background Art

[0003] The system cache of the computing device may store data according to one or more replacement policies, such as not recently used (nMRU) and capacity-based first-in, first-out (FIFO). The nMRU and FIFO policies are not optimal for all use cases, such as for multimedia frame-based clients, where temporal locality is within frame time boundaries and capacity allocation may vary based on compression ratios. Summary of the invention

[0004] Various aspects of the present disclosure provide methods, including methods and apparatus for implementing such methods of implementing a criteria-aware cache replacement policy by a computing device, which may include updating a stale counter; writing a value of a local counter to a system cache in association with a location in the system cache for associated data, wherein the value of the local counter includes the value of the stale counter when the associated data is written to the system cache; and determining whether the associated data is stale using the value of the local counter for the associated data.

[0005] In some aspects, updating the stale counter may include receiving a signal from a client of the computing device configured to indicate whether to update the stale counter, determining whether to update the stale counter based on the signal, and updating the stale counter in response to determining to update the stale counter.

[0006] In some aspects, the signal is a register write command, receiving the signal from a client of the computing device may include reading a value from the register set by the client, and determining whether to update the stale counter based on the signal may include determining whether to update the stale counter based on the value from the register.

[0007] Some aspects may include setting, by a client of the computing device, a value at a register according to time-based criteria.

[0008] Some aspects may include setting, by a client of the computing device, a value at a register according to event-based criteria.

[0009] Some aspects may include receiving a memory write command, wherein writing the value of the local counter to the system cache in association with a location in the system cache for associated data may occur before updating the stale counter, and wherein the associated data is data of the write memory command.

[0010] In some aspects, determining whether the associated data is out-of-date using the value of a local counter for the associated data may include calculating a replacement value using the value of the out-of-date counter and the value of the local counter, and determining whether the replacement value exceeds an out-of-date threshold, wherein the associated data is determined to be out-of-date in response to determining that the replacement value exceeds the out-of-date threshold.

[0011] Some aspects may include receiving a memory access command and writing data of the memory access command to a system cache at a location where a replacement value exceeds a stale threshold, wherein the data of the memory access command written to the system cache is the associated data.

[0012] Some aspects may include receiving a memory write command, invalidating data at a location where a replacement value exceeds an obsolete threshold, and writing data of the memory write command to a system cache at the location with the invalid data, wherein the data of the memory write command written to the system cache is the associated data.

[0013] Some aspects may include receiving a memory write access command and, in response to determining that no replacement value exceeds a stale threshold, writing data of the memory write access command to a location of a system cache that complies with another cache replacement policy.

[0014] Other aspects include a computing device including a memory control device configured to perform the operations of any of the methods outlined above. Other aspects include a non-transitory processor-readable storage medium having processor-executable software instructions stored thereon, the instructions configured to cause a processor to perform the operations of any of the methods outlined above. Other aspects include a computing device having means for implementing the functionality of any of the methods outlined above. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated herein and constitute a part of this specification, illustrate example embodiments of the various embodiments and, together with the general description given above and the detailed description given below, serve to explain features of the claims.

[0016] Figure 1 is a component block diagram illustrating an example computing device suitable for implementing various embodiments.

[0017] Figure 2 is a component block diagram illustrating an example system-on-chip suitable for implementing various embodiments.

[0018] Figure 3A and Figure 3B is a process component signaling diagram illustrating an example of a criteria-aware cache replacement policy according to one embodiment.

[0019] Figure 4is a memory flow diagram illustrating an example of a criteria-aware cache replacement policy according to one embodiment.

[0020] Figure 5 is a memory flow diagram illustrating an example of a criteria-aware cache replacement policy that replaces data based on the value of a local counter according to one embodiment.

[0021] Figure 6 is a process flow diagram illustrating a method for implementing a criteria-aware cache replacement policy for local counters according to one embodiment.

[0022] Figure 7 is a process flow diagram illustrating a method for implementing a criteria-aware cache replacement policy that replaces data based on the value of a local counter, according to one embodiment.

[0023] Figure 8 is a process flow diagram illustrating a method for implementing a criteria-aware cache replacement policy that replaces data based on the value of a local counter, according to one embodiment.

[0024] Fig. 9 is a process flow diagram illustrating a method for implementing a criteria-aware cache replacement policy that replaces data based on invalidating the data based on the value of a local counter, according to one embodiment.

[0025] Fig.10 is a process flow diagram illustrating a method for implementing a criteria-aware cache replacement policy that replaces data based on invalidating the data based on the value of a local counter, according to one embodiment.

[0026] Fig.11 is a process flow diagram illustrating a method for implementing a criteria-aware cache replacement policy for local counters according to one embodiment.

[0027] Fig.12 is a process flow diagram illustrating a method for implementing a criteria-aware cache replacement policy that replaces data based on the value of a local counter, according to one embodiment.

[0028] Fig.13 is a process flow diagram illustrating a method for implementing a criteria-aware cache replacement policy that replaces data based on the value of a local counter, according to one embodiment.

[0029] Fig.14 is a component block diagram illustrating an example mobile computing device suitable for implementing various embodiments.

[0030] Fig.15 is a component block diagram illustrating an example mobile computing device suitable for implementing various embodiments.

[0031] Fig.16 is a component block diagram illustrating an example server suitable for implementing various embodiments. DETAILED DESCRIPTION

[0032] Various embodiments will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. References to specific examples and implementations are for illustrative purposes and are not intended to limit the scope of the claims.

[0033] Various embodiments include methods and computing devices that implement such methods for implementing a criterion-aware cache replacement strategy. Embodiments may include associating data written to a system cache with a local counter. The value of the local counter may include the value of an outdated counter at the time when the associated data is written to the system cache (i.e., when the associated data is written to the system cache). A replacement value for the data in the system cache may be calculated using the local value of the associated data and compared to an outdated threshold. The value of the local counter for the associated data may be used to determine whether the associated data is outdated. In response to the replacement value exceeding and / or equaling the outdated threshold, the data in the system cache associated with the local counter used to calculate the replacement value may be replaced.

[0034] The term "computing device" is used herein to refer to fixed computing devices, including personal computers, desktop computers, stand-alone computers, workstations, supercomputers, mainframe computers, embedded computers (such as in vehicles and other larger systems), computerized vehicles (e.g., partially or fully autonomous ground, air, and / or water vehicles, such as passenger vehicles, commercial vehicles, recreational vehicles, military vehicles, drones, etc.), servers, multimedia computers, and game consoles. The terms "computing device" and "mobile computing device" are used interchangeably herein to refer to any or all of the following: cellular phones, smart phones, personal or mobile multimedia players, personal data assistants (PDAs), laptop computers, tablet computers, convertible laptop / tablet computers (2-in-1 computers), smartbooks, ultrabooks, netbooks, palmtop computers, wireless email receivers, Internet-enabled multimedia cellular phones, mobile game consoles, wireless game controllers, and similar personal electronic devices that include memory and a programmable processor.

[0035] For ease of explanation and clarity, although various embodiments are described in terms of code (e.g., processor executable instructions), similarly applicable are any data, such as code, program data, or other information stored in memory. The terms "code," "data," and "information" are used interchangeably herein and are not intended to limit the scope of the claims and specification to the types of code, data, or information used as examples in describing various embodiments.

[0036] Typically, a system cache of a computing device controls the memory space in which data is cached using one or more data replacement policies, such as Not Recently Used (nMRU) and First In First Out (FIFO). The nMRU and FIFO policies are not optimal for various use cases, including, for example, multimedia frame-based clients, where temporal locality is within frame time boundaries and capacity allocation may vary based on compression ratios. The NMRU replacement policy is insufficient when cache lines accessed from multimedia clients have different access frequencies and are only valid for specific time frames. FIFO replacement behavior is not guaranteed in the case of adaptive partitioning, where the size of a cache partition may vary over time as the sub-cache is filled with compressed frames.

[0037] Various embodiments address and solve limitations in conventional cache replacement strategies. A client process such as a processor or a software program (e.g., an operating system and / or an application) executed by the processor may signal (e.g., via communication, register writes, direct interrupts, etc.) the need to update the stale counter of data in the system cache. For ease of illustration, some examples may be described herein in terms of register writes; however, such examples are not intended to limit the scope of the claims or the specification to register writes. Those skilled in the art will appreciate that other types or methods of signaling the processor may provide the same or similar functionality. Register writes may be issued based on criteria such as time (i.e., time-based criteria), events (i.e., event-based criteria), and / or other metrics. For example, register writes may be issued at the beginning and / or end of a compressed multimedia data frame based on frame time boundaries, color fields within a compressed multimedia data frame, etc. A processor or system cache may associate the value of a stale counter as a local counter with data in the system cache. For example, during insertion or use of data at a system cache line, a processor or system cache may associate the value of a stale counter with a tag of a system cache line. When the associated data is written to the system cache (i.e., at that time), the processor or the system cache may associate a local counter including the value of the stale counter with the data. Because the local counter is associated with the data in the system cache when the associated data is written to the system cache, the stale counter can indicate stale data by distinguishing the data in the system cache, and thus can be used by the processor or to help identify candidate replacement memory locations for new write commands.

[0038] The stale threshold may be used by the processor or the system cache to determine whether data in the system cache is stale and can be replaced the next time data is written to the system cache. The stale threshold may be preconfigured based on a criteria-aware cache replacement policy. A replacement value for data in the system cache (which may be calculated using a stale counter and a value of a local counter associated with the data) may be compared to the stale threshold to determine whether the associated data is stale and can be replaced the next time data is written to the system cache.

[0039] Various embodiments provide a cache replacement policy method by which obsolete data within a cache can be tracked so that the next time data is written to a system cache, the obsolete data has a higher chance of being replaced than non-obsolete data. Identifying obsolete data using the method of various embodiments can achieve deterministic cache usage and thus improve the operation of a computing device by improving last-level cache usage and reducing traffic in a double data rate (DDR) synchronous dynamic random access memory (SDRAM).

[0040] Figure 1 A system including a computing device 100 suitable for use with various embodiments is illustrated. The computing device 100 may include a system on a chip (SoC) 102 having a central processing unit 104, a memory 106, a communication interface 108, a memory interface 110, a peripheral device interface 120, and a processing device 124. The computing device 100 may also include a communication component 112 (such as a wired or wireless modem), the memory 114, an antenna 116 for establishing a wireless communication link, and / or peripheral devices 122. The processor 124 may include any of a variety of processing devices (e.g., multiple processor cores).

[0041] The term "system on chip" or "SoC" is used herein to refer to a group of interconnected electronic circuits, typically but not exclusively including a processing device, a memory, and a communication interface. The processing device may include a variety of different types of processors and / or processor cores, such as a central processing unit (CPU) 104, and / or a processor 124, including a general-purpose processor, a central processing unit (CPU) 104, a digital signal processor (DSP), a graphics processing unit (GPU), an accelerated processing unit (APU), a security processing unit (SPU), an intellectual property unit (IPU), a subsystem processor of a specific component of a computing device (such as an image processor of a camera subsystem or a display processor of a display), an auxiliary processor, a peripheral device processor, a single-core processor, a multi-core processor, a controller, and / or a microcontroller. The processing device may further implement other hardware and hardware combinations, such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), other programmable logic devices, discrete gate logic, transistor logic, performance monitoring hardware, watchdog hardware, and / or a time reference. The integrated circuit may be configured so that the components of the integrated circuit reside on a single piece of semiconductor material (such as silicon).

[0042] SoC 102 may include one or more CPUs 104 and processors 124. Computing device 100 may include more than one SoC 102, thereby increasing the number of CPUs 104, processors 124, and processor cores. Computing device 100 may also include CPUs 104 and processors 124 that are not associated with SoC 102. Individual CPUs 104 and processors 124 may be multi-core processors. CPUs 104 and processors 124 may each be configured for a specific purpose that may be the same or different from other CPUs 104 and processors 124 of computing device 100. One or more of the CPUs 104, processors 124, and processor cores of the same or different configurations may be grouped together. A group of CPUs 104, processors 124, or processor cores may be referred to as a multi-processor cluster.

[0043] The memory 106 of the SoC 102 may be a volatile or non-volatile memory configured to store data and processor executable code for access by the CPU 104, the processor 124, or other components of the SoC 102. The computing device 100 and / or the SoC 102 may include one or more memories 106 configured for various purposes. One or more memories 106 may include volatile memory, such as random access memory (RAM), including DDR memory implemented as main memory or cache memory. These memories 106 may be configured to temporarily hold a limited amount of data received from a data sensor or subsystem, data and / or processor executable code instructions requested from a non-volatile memory that are loaded from the non-volatile memory to the memory 106 in anticipation of future access based on a variety of factors, and / or intermediate processing data and / or processor executable code instructions generated by the CPU 104 and / or the processor 124 and temporarily stored for quick access without being stored in a non-volatile memory. Memory 106 may be configured to at least temporarily store data and processor-executable code loaded into memory 106 from another memory device (such as another memory 106 or memory 114) for access by one or more of CPU 104, processor 124, or other components of SoC 102. In some embodiments, any number and combination of memories 106 may include one-time programmable or read-only memory.

[0044] The memory interface 110 and the memory 114 may work together to allow the computing device 100 to store data and processor executable code on volatile and / or non-volatile storage media and retrieve data and processor executable code from the volatile and / or non-volatile storage media. The memory 114 may be configured like an embodiment of the memory 106 (such as a main memory), where the memory 114 may store data or processor executable code for access by one or more of the CPU 104, the processor 124, or other components of the SoC 102. In some embodiments, the non-volatile memory 114 may retain information after the computing device 100 has been powered off. When power is restored and the computing device 100 restarts, the information stored on the memory 114 is available to the computing device 100. In some embodiments, the volatile memory 114 may not retain information after the computing device 100 has been powered off. The memory interface 110 may control access to the memory 114 and allow the CPU 104 , processor 124 , or other components of the SoC 102 to read data from and write data to the memory 114 .

[0045] Some or all of the components of computing device 100 and / or SoC 102 may be arranged and / or combined differently while still supporting the functionality of various embodiments. Computing device 100 may not be limited to one of each component, and multiple instances of each component may be included in various configurations of computing device 100.

[0046] Figure 2 An example SoC suitable for implementing various embodiments is illustrated. Figure 1 and Figure 2 , SoC200 (e.g., Figure 1 SoC 102 in the example may include various combinations of components, including any number and combination of processors 202 (e.g., Figure 1 CPU 104, processor 124), L3 cache 216 (e.g., Figure 1 106 in memory), system cache 218 (e.g., Figure 1 106) and / or system memory 224 (e.g., Figure 1 Memory 106 in).

[0047] The processor 202 may include any number and combination of processor cores 204a, 204b, 204c, 206a, 206b, 206c. For example, the multi-core processor 202 may have multiple homogeneous or heterogeneous processor cores 204a, 204b, 204c, 206a, 206b, 206c. A homogeneous multi-core processor may include multiple homogeneous processor cores. The processor cores 204a, 204b, 204c, 206a, 206b, 206c may be homogeneous because the processor cores 204a, 204b, 204c, 206a, 206b, 206c of the multi-core processor 202 may be configured for the same purpose and have the same or similar performance characteristics. For example, the multi-core processor 202 may be a general-purpose processor, and the processor cores 204a, 204b, 204c, 206a, 206b, 206c may be homogeneous general-purpose processor cores. As another example, the multi-core processor 202 may be a graphics processing unit or a digital signal processor, and the processor cores 204a, 204b, 204c, 206a, 206b, 206c may be homogeneous graphics processor cores or digital signal processor cores, respectively.

[0048] A heterogeneous multi-core processor may include multiple heterogeneous processor cores. The processor cores 204a, 204b, 204c, 206a, 206b, 206c may be heterogeneous in that the processor cores 204a, 204b, 204c, 206a, 206b, 206c of the multi-core processor 202 may be configured for different purposes and / or have different performance characteristics. The heterogeneity of such heterogeneous processor cores may include different instruction set architectures, pipelines, operating frequencies, etc. Examples of such heterogeneous processor cores may include the so-called "big.LITTLE" architecture, in which a slower, low-power processor core may be coupled with a more powerful and power-hungry processor core.

[0049] The processor cores 204a, 204b, 204c, 206a, 206b, 206c may be grouped together as processor core clusters 212, 214. Generally, the processor core clusters 212, 214 may include homogeneous processor cores within each processor core cluster 212, 214. The processor core clusters 212, 214 may be homogeneous or heterogeneous with other processor core clusters 212, 214. For example, the processor core clusters 212, 214 may be homogeneous, having the same processor core as each other. As another example, the processor core clusters 212, 214 may be heterogeneous, having different processor cores from each other. For ease of description, the terms "processor", "processor core" and "processor core cluster" may be used interchangeably herein.

[0050] The processor 202 may also include any number and combination of L2 caches 208a, 208b, 208c, 210a, 210b, 210c (e.g., Figure 1 106 in memory 106). For example, each processor core cluster 212, 214 and / or each processor core 204a, 204b, 204c, 206a, 206b, 206c may have a dedicated L2 cache 208a, 208b, 208c, 210a, 210b, 210c. Each L2 cache 208a, 208b, 208c, 210a, 210b, 210c may be designated for read and / or write access by a designated processor core cluster 212, 214 and / or processor core 204a, 204b, 204c, 206a, 206b, 206c. The L2 caches 208a, 208b, 208c, 210a, 210b, 210c may store data and / or instructions and make the stored data and / or instructions available to a designated processor core cluster 212, 214 and / or processor core 204a, 204b, 204c, 206a, 206b, 206c. The L2 caches 208a, 208b, 208c, 210a, 210b, 210c may include a processor core cluster 212, 214 and / or processor core 204a, 204b, 204c, 206a, 206b, 206c. Figure 1 The memory 106 is described as a volatile memory.

[0051] The L3 cache 216, system cache 218, and system memory 224 may be shared by the processor core clusters 212, 214 and / or the processor cores 204a, 204b, 204c, 206a, 206b, 206c and configured for read and / or write access by these processor core clusters and / or processor cores. The L3 cache 216, system cache 218, and system memory 224 may store data and / or instructions and make the stored data and / or instructions available to the processor core clusters 212, 214 and / or the processor cores 204a, 204b, 204c, 206a, 206b, 206c. The L3 cache 216, system cache 218, and system memory 224 may be used as a buffer for data and / or instructions input to and / or output from the processor 202. The L3 cache 216, system cache 218, and system memory 224 may include as described herein with reference to Figure 1 The memory 106 is described as a volatile memory.

[0052] The processor 202 may include a memory controller 220 configured to manage memory access to the L2 caches 208a, 208b, 208c, 210a, 210b, 210c, the L3 cache 216, and / or the system cache 218. The memory controller may receive memory access commands from the processor cores 204a, 204b, 204c, 206a, 206b, 206c and allow and implement and / or deny memory access to the caches 208a, 208b, 208c, 210a, 210b, 210c, 216, 218. The memory controller 220 may be configured to implement cache maintenance, cache coherence, and / or cache replacement policies. The memory controller 220 may be configured to implement virtual cache address translation.

[0053] The processor 202 may include any number and combination of registers 222 that may be configured to temporarily store small amounts of data. The registers 222 may be implemented in hardware and / or as memory locations in the caches 208a, 208b, 208c, 210a, 210b, 210c, 216, 218. Any number of registers may be configured, individually and / or in combination, to store data for a specific purpose associated with the registers 222. For example, a register may store data configured to indicate to the processor 202 information about a specific purpose associated with the registers 222. As another example, an array of registers 222 may store a data vector for which any number and combination of bits may indicate to the processor 202 information about a specific purpose associated with the array of registers 222.

[0054] Some or all of the components of SoC 200 and / or processor 202 may be arranged and / or combined differently while still supporting the functionality of the various embodiments. For example, memory controller 220 may be a component of SoC 200 that is separate from processor 202 .

[0055] Figure 3A and Figure 3B Example components and signaling for a criteria-aware cache replacement policy according to various embodiments are illustrated. Figure 1 3, a processor (eg, Figure 1 The CPU 104 and the processor 124 in Figure 2 The processor 202, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214 in the system may implement a client 300 that may issue memory access commands to the system cache 218. For example, the processor may be the client 300. For another example, the processor may execute a process of a software program (such as an operating system and / or an application) that may be the client 300.

[0056] exist Figure 3AIn the example shown, the client 300 may issue a memory access command 302 (such as a write memory command) to the system cache that may be received by the memory controller 220. The client 300 may also implement a register write 304 to one or more registers 222, which may set an outdated counter update value in the register 222. The register 222 may be associated with an outdated counter update feature for a criteria-aware cache replacement policy. The value stored in the register 222 may be configured to indicate to the memory controller 220 whether to update an outdated counter (not shown) configured for use by the criteria-aware cache replacement policy. For example, the register write 304 may set the outdated counter update value to a "1" value configured to indicate to the memory controller 220 to update the outdated counter. The client 300 may implement the register write 304 based on a criterion of the criteria-aware cache replacement policy. In various embodiments, the criterion may be a time-based criterion, an event-based criterion, or other type of criterion. As an example of a time-based criterion, the client 300 may implement the register write 304 based on a time period, a number of processor clock cycles, a number of instructions executed, and the like. As an example of event-based criteria, the client 300 may implement register write 304 based on completion, suspension and / or termination of a task, process and / or application, start, restart and / or loading of a task, process and / or application, interrupt signal, error and / or fault signal, etc. As an example of other criteria, the client 300 may implement register write 304 based on a processor (e.g., Figure 1 The CPU 104 and the processor 124 in Figure 2 processor 202 in the processor 202), memory (e.g., Figure 1 The memory 106, 114 in Figure 2 caches 208a, 208b, 208c, 210a, 210b, 210c, 216, 218 in, peripheral devices (e.g., Figure 1 Register write 304 may be implemented based on a specific state or state change of a peripheral device 122 in the client 300, a communication component (e.g., communication component 112), etc. For another example, client 300 may implement register write 304 based on the beginning and / or end of a portion of data (such as a compressed multimedia data frame based on a frame time boundary, a color field within a compressed multimedia data frame, etc.).

[0057] In response to receiving the write memory command 302, the memory controller 220 may read 306 the register 222 to determine whether to update the stale counter. The memory controller 220 may retrieve the value of the register 222 and determine whether the value from the register indicates to the memory controller 220 to update the stale counter.

[0058] In response to determining that the value of register 222 indicates to memory controller 220 to update the obsolete counter, memory controller 220 may update obsolete counter 308. The obsolete counter may include a value stored in a memory (e.g., Figure 1 Memory 106, memory 114, Figure 2 L2 cache 208a, 208b, 208c, 210a, 210b, 210c, L3 cache 216, Figure 2 3 , register 222), which is accessible for read and write by the memory controller 220. The memory controller 220 may update the stale counter by any mathematical operation, algorithmic operation, heuristic operation, etc., such as by incrementing and / or decrementing the stale counter. In response to determining that the value of register 222 indicates to the memory controller 220 that the stale counter is not to be updated, the memory controller 220 may forgo updating the stale counter 308.

[0059] The memory controller 220 may read 310 local counters for data at locations in the system cache 218. The values ​​of the local counters may include values ​​of stale counters stored in association with associated data written to the system cache 218 in response to a previous write memory command. In one example, the memory controller 220 may read one or more local counter values ​​stored with a cache tag for a memory location targeted by a write memory command. In another example, the memory controller 220 may read one or more local counter values ​​for locations within a block, partition, entirety, and / or any other portion of the system cache 218.

[0060] The memory controller 220 may use the retrieved value of the local counter to help determine which portions of the system cache 218 to replace according to a criteria-aware cache replacement policy when implementing a write memory command. In operation 312, the memory controller 220 may calculate a replacement value and compare it to a staleness threshold. For example, the memory controller 220 may use an arithmetic operation to generate a replacement value using the value of the local counter and the staleness counter value. For example, the memory controller 220 may subtract the value of the local counter from the value of the staleness counter to determine the replacement value. The memory controller 220 may compare the replacement value to the staleness threshold to determine whether to replace data associated with the local counter value. The staleness threshold may be a preconfigured value. For example, the staleness threshold may be preconfigured based on a criteria-aware cache replacement policy. As another example, the staleness threshold may be preconfigured based on the size, state, usage, availability, etc. of the system cache 218. As another example, the staleness threshold may be preconfigured based on a processor and / or computing device (e.g., Figure 1The threshold value may be pre-configured based on the status, usage, power availability, etc. of the computing device 100 in the client 300. As another example, the expiration threshold value may be pre-configured based on the tasks, processes, and / or applications executed as the client 300 and / or by the client.

[0061] The comparison of the replacement value to the stale threshold may indicate to the memory controller 220 whether the criteria-aware cache replacement policy should replace the data associated with the local counter value. For example, in response to the replacement value being greater than or equal to the stale threshold, the memory controller 220 may implement the criteria-aware cache replacement policy to replace the data associated with the local counter value with the data of the write memory command. The memory controller 220 may replace the data associated with the local counter value by writing 314 the data of the write memory command to a location in the system cache 218 where the data associated with the local counter is stored. Otherwise, the memory controller 220 may write 314 the data of the write memory command to another location in the system cache 218. The memory controller 220 may also write 316 the value of the stale counter to the system cache 218 as a local counter in association with the data of the write memory command written to the system cache 218. For example, the memory controller 220 may write 316 the value of the stale counter to a tag location in the system cache 218 associated with the data of the write memory command written to the system cache 218.

[0062] exist Figure 3B In the illustrated example, the client 300 may issue a memory access command 302, such as a read memory command, to the system cache that may be received by the memory controller 220. The client 300 may also implement a register write 304 to one or more registers 222 that may set an update value for a stale counter in the register 222. In response to receiving the read memory command 302, the memory controller 220 may read 306 the register 222 to determine whether to update the stale counter. In response to determining that the value of the register 222 indicates to the memory controller 220 to update the stale counter, the memory controller 220 may update the stale counter 308. The memory controller 220 may read data associated with the local counter value by reading 315 the data at a location in the system cache 218 that stores the data associated with the local counter and targeted by the read memory command. The memory controller 220 may also write 317 the value of the stale counter to the system cache 218 as a local counter associated with the data at the location in the system cache 218 targeted by the read memory command. For example, the memory controller 220 may write 317 the value of the stale counter to a tag location in the system cache 218 that is associated with the data at the location in the system cache 218 targeted by the read memory command.

[0063] Figure 3A The order of signals 302, 304, 308, 310, 312, 314, 316 in and Figure 3B The order of signals 302, 304, 308, 315, 317 in FIG. 3 is only an example, and the order of signals 302, 304, 308, 310, 312, 314, 315, 316, 317 may be performed in a different order. For example, the order of signals 302 and 304, signals 314 and 316, and / or signals 315 and 317 may be reversed. For another example, signals 302 and 304, signals 314 and 316, and / or signals 315 and 317 may be transmitted concurrently.

[0064] Figure 4 An example of a memory flow for implementing a criterion-aware cache replacement policy according to one embodiment is illustrated. Figures 1 to 4 , memory controller (e.g., Figure 2 3) can be in the system cache 400 (eg, Figure 2 3) and implements the write memory commands 410a, 410b, 410c in the system cache 218 and FIG. 3, and implements the stale counter updates 412a, 412b of the stale counter 402. The write memory commands 410a, 410b, 410c may be executed by a computing device (e.g., Figure 1 Issued by a client (e.g., client 300) of the computing device 100 in FIG.

[0065] The write memory command 410a may be received by the memory controller and prompt the memory controller to write data to the system cache 400. The stale counter 402 at the time of implementing the write memory command 410a may be "1". The data of the write memory command 410a may be written to the system cache 400 along with a stale counter value of "1" which is a local counter associated with a location 404 in the system cache where the data is written.

[0066] Another write memory command 410b may be received by the memory controller and may prompt the memory controller to write data to the system cache 400 and may be responsive to the memory controller reading data from a register (eg, Figure 23 ). The register value may be set by a register write (e.g., register write 304 in FIG. 3 ) implemented by the client in conjunction with write memory command 410b. Stale counter 402 may be “2” when write memory command 410c is implemented. The data of write memory command 410b may be written to system cache 400 along with the stale counter value “2” which is a local counter associated with location 406 in the system cache where the data is written. In this example, location 406 may be an open location before the data of write memory command 410b and the local counter are written to location 406. Write memory command 410b may prompt a criterion-aware cache replacement policy to check the system cache 400 for data to be replaced, but replacement may not be implemented in the system cache 400. For data that does not meet the criteria of the criterion-aware cache replacement policy, replacement may not occur. For example, the criteria-aware cache replacement policy can determine whether the difference between the local counter of the location 404 where the data has been written in the system cache 400 ("1" in this example) and the stale counter 402 ("2" in this example) at the time of the write memory command 410b is less than the stale threshold.

[0067] Another write memory command 410c may be received by the memory controller and may prompt the memory controller to write data to the system cache 400, and may update 412b the stale counter in response to the register value read by the memory controller. The register value may be set by a register write (e.g., register write 304 in FIG. 3) implemented by the client in conjunction with the write memory command 410c. The stale counter 402 when the write memory command 410c is implemented may be "3". The data of the write memory command 410c may be written to the system cache 400 together with the stale counter value "3" as a local counter associated with the location 404 in the system cache where the data is written. In this example, before the data of the write memory command 410c and the local counter are written to the location 404, the location 404 may be an occupied location. The write memory command 410b may prompt the criterion-aware cache replacement policy to check the system cache 400 for data to be replaced. In this example, replacement may be implemented for some locations 404 but not other locations 406 in the system cache 400. For data that does not meet the criteria of the criteria-aware cache replacement policy, replacement may not occur. For example, the criteria-aware cache replacement policy may determine whether the difference between the local counter (in this example, "2") of the location 406 in the system cache 400 where the data has been written and the stale counter 402 (in this example, "3") at the time of writing the memory command 410c may be less than the stale threshold. For data that meets the criteria of the criteria-aware cache replacement policy, replacement may occur. For example, the criteria-aware cache replacement policy may determine whether the difference between the local counter (in this example, "1") of the location 404 in the system cache 400 where the data has been written and the stale counter 402 (in this example, "3") at the time of writing the memory command 410c may be greater than or equal to the stale threshold. The memory controller may replace the data and the local counter of the location 404 with the data and the value of the stale counter of the write memory command 410c.

[0068] Figure 5 An example of a memory flow for implementing a criterion-aware cache replacement policy according to one embodiment is illustrated. Figures 1 to 5 , memory controller (e.g., Figure 2 3) can be in a system cache (e.g., Figure 2 and the system cache 218 in FIG. 3 , Figure 4 The write memory command (write N) and the read memory command (read N) can be implemented in the system cache 400 in the computing device (e.g., Figure 1 A processor (e.g., Figure 1The CPU 104 and the processor 124 in Figure 2 202, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214, client 300 in FIG. 3) (e.g., Figure 5 issued by processor 1 and processor 2 in the process.

[0069] At the time of the write 0 write memory command from processor 1, the stale counter may have a value of “0.” The write 0 data may be written to the system cache along with the stale counter value of “0” as a local counter associated with the write 0 data.

[0070] The write 0 may be followed by a read 0 read memory command from processor 2. The memory controller may read out the data in the system cache targeted by the read 0. For example, the memory controller may read out the data at the location in the system cache associated with the local counter value "0".

[0071] The Read 0 may be followed by a Write 1 write memory command from processor 1. The stale counter may have been updated and may have a value of "1" at the time of the Write 1. The Write 1 may prompt the criteria-aware cache replacement policy to check for stale data by comparing a local counter associated with the data in the system cache to a stale threshold. For example, the memory controller may read the local counter from the system cache, calculate the difference between the value of the stale counter and the value of the local counter, and compare the difference to the stale threshold. In response to the difference being less than the stale threshold, the criteria-aware cache replacement policy may determine not to replace the data associated with the local counter in the system cache, as in the Write 1 example. In this example, the data of the Write 1 may be written to an open location in the system cache along with a stale counter value of "2" as the local counter associated with the data of the Write 1.

[0072] Write 1 may be followed by a second (i.e., Write 2) write memory command from processor 1. The stale counter may have been updated and may have a value of "2" at the time of Write 2. Write 2 may prompt the criteria-aware cache replacement policy to check for stale data by comparing a local counter associated with the data in the system cache to a stale threshold. For example, the memory controller may read the local counter from the system cache, calculate a difference between the value of the stale counter and the value of the local counter, and compare the difference to the stale threshold. In response to the difference being less than the stale threshold, the criteria-aware cache replacement policy may determine not to replace the data associated with the local counter in the system cache. In response to the difference being greater than or equal to the stale threshold, the criteria-aware cache replacement policy may determine to replace the data associated with the local counter in the system cache. In this example, the data associated with the local counter having a value of "0" may be determined to be stale because the difference between the stale counter and the local counter may be greater than or equal to the stale threshold. Therefore, the criteria-aware cache replacement policy may determine to replace the data associated with the local counter having a value of "0". The data associated with the local counter having a value of "1" may be determined to be not stale because the difference between the stale counter and the local counter is less than the stale threshold. Therefore, the criteria-aware cache replacement policy may determine not to replace the data associated with the local counter having a value of "2". The data written 2 may be written to an open location in the system cache along with the stale counter value "2" as the local counter associated with the data written 2, as well as the location occupied by the data associated with the local counter value "0".

[0073] Write 2 may be followed by a Read 1 read memory command from processor 2. The memory controller may read out the data in the system cache targeted by Read 1. For example, the memory controller may read out the data at the location in the system cache associated with the local counter value "1".

[0074] Read 1 may be followed by a Write 3 write memory command from processor 1. The stale counter may have been updated and may have a value of "3" at the time of Write 3. Write 3 may prompt the criteria-aware cache replacement policy to check for stale data by comparing a local counter associated with the data in the system cache to a stale threshold. For example, the memory controller may read the local counter from the system cache, calculate the difference between the value of the stale counter and the value of the local counter, and compare the difference to the stale threshold. In response to the difference being less than the stale threshold, the criteria-aware cache replacement policy may determine not to replace the data associated with the local counter in the system cache. In response to the difference being greater than or equal to the stale threshold, the criteria-aware cache replacement policy may determine to replace the data associated with the local counter in the system cache. In this example, the data associated with the local counter having a value of "0" or "1" may be determined to be stale because the difference between the stale counter and the local counter may be greater than or equal to the stale threshold. Therefore, the criteria-aware cache replacement policy may determine to replace the data associated with the local counter having a value of "0" or "1". Data associated with a local counter having a value of "2" may be determined to be not obsolete because the difference between the obsolete counter and the local counter may be less than an obsolete threshold. Therefore, the criteria-aware cache replacement policy may determine not to replace data associated with a local counter having a value of "2". However, the criteria-aware cache replacement policy may not control all replacements of data in the system cache. For example, a mechanism for writing data to the system cache may be defined in a manner that may not be fully aligned with the criteria-aware cache replacement policy in some cases. Data written to 3 may be written to the location occupied by data associated with a local counter value of "0" or "1" in the system cache together with an obsolete counter value of "3" as a local counter associated with data written to 2. However, the mechanism for writing data to the system cache may write data in a manner determined by the number of rows in the set. Therefore, a situation may arise in which data that is not obsolete under the criteria-aware cache replacement policy (such as data associated with a local counter value of "2") may be replaced by writing to 3.

[0075] Write 3 may be followed by a Read 2 read memory command from processor 2. The memory controller may read out the data targeted by Read 2 in the system cache. For example, the memory controller may read out the data at a location in the system cache associated with the local counter value "2." Although the data targeted by Read 2 may be partially replaced by the data written to the system cache by Write 3, the criteria-aware cache replacement policy achieves a higher hit rate (or lower miss rate) for the data in the system cache compared to other cache replacement policies (e.g., not recently used (nMRU) and capacity-based first-in, first-out (FIFO)).

[0076] Figure 6 A method 600 for implementing a criterion-aware cache replacement policy according to some embodiments is illustrated. Figures 1 to 6 , the method 600 may be performed on a computing device (e.g., Figure 1 in a computing device 100), in hardware, in a processor (e.g., Figure 1 The CPU 104 and the processor 124 in Figure 2 3 ), or in software executed in a processor 202, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214, client 300 in FIG. 3 , or in a processor configured in software and including, for example, various memories / caches (e.g., Figure 1 Memory 106, memory 114, Figure 2 L2 cache 208a, 208b, 208c, 210a, 210b, 210c, L3 cache 216, Figure 2 and the system cache 218 and register 222 in FIG. 3 , Figure 4 system cache 400 in FIG. 400 ) and various memory / cache controllers (e.g., Figure 2 3 ) is implemented in a combination of dedicated hardware of other individual components of the memory controller 220 in FIG. 3 . To cover alternative configurations implemented in various embodiments, the hardware implementing method 600 is referred to herein as a “client” and a “memory control device”.

[0077] In block 602, the client may send a request to a system cache (e.g., Figure 2 and the system cache 218 in FIG. 3 , Figure 4 In block 604, the client may signal the processor (e.g., Figure 1 The CPU 104 and the processor 124 in Figure 2 3) to update the stale counter of data in the system cache. Signaling the processor may be accomplished using various types of signal communications, including, for example, registers (e.g., Figure 23 ), a direct interrupt to the processor, etc. The register may be associated with a stale counter update feature of a criterion-aware cache replacement policy. Writing to the register may set a value of a register configured to indicate to a memory control device whether to update the stale counter. In some embodiments, the client that sends the write memory command in block 602 and signals the processor in block 604 to update the stale counter of data in the system cache may be a processor (e.g., Figure 1 The CPU 104 and the processor 124 in Figure 2 3 ), and / or software programs (e.g., the client 300 in FIG. 3 ), such as an operating system and / or an application.

[0078] In block 606, the memory control device may receive a write memory command. The memory control device may be configured to manage, control, and / or implement memory access, cache maintenance, cache coherence, and / or cache replacement policies of a system cache. In block 608, the memory control device may implement a criteria-aware cache replacement policy for writing the data of the write memory command into the system cache. The memory control device that receives the write memory command in block 606 and implements the criteria-aware cache replacement policy in block 608 may be a processor (e.g., Figure 1 CPU 104, processor 124, Figure 2 3 ) and / or a memory controller (e.g., Figure 2 and memory controller 220 in FIG. 3 ).

[0079] Figure 7 A method 700 for implementing a criteria-aware cache replacement policy that replaces data based on the value of a local counter is illustrated in accordance with some embodiments. Figures 1 to 7 , method 700 may be performed on a computing device (e.g., Figure 1 in a computing device 100), in hardware, in a processor (e.g., Figure 1 The CPU 104 and the processor 124 in Figure 23 ), or in software executed in a processor 202, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214, client 300 in FIG. 3 , or in a processor configured in software and including, for example, various memories / caches (e.g., Figure 1 Memory 106, memory 114, Figure 2 L2 cache 208a, 208b, 208c, 210a, 210b, 210c, L3 cache 216, Figure 2 and the system cache 218 and register 222 in FIG. 3 , Figure 4 system cache 400 in FIG. 400 ) and various memory / cache controllers (e.g., Figure 2 3 ). To cover alternative configurations implemented in various embodiments, the hardware implementing method 700 is referred to herein as a "memory control device." Blocks 702-714 of method 700 elaborate on the details of the memory control device that may be used in reference to FIG. Figure 6 The operations performed in block 608 of method 600 are described.

[0080] In block 702, a memory control device may receive a request for updating a system cache (eg, Figure 2 and the system cache 218 of FIG. 3 , and Figure 4 For example, the memory control device may read a register (e.g., Figure 2 3 ), receiving a direct interrupt, etc., to update the stale counter of the data in the system cache. The register may be associated with a stale counter update feature of the criterion-aware cache replacement policy and may have a value configured to indicate to the memory control device whether to update the stale counter. The value of the register may be set, for example, by writing to the register to update the stale counter of the data in the system cache, as described for method 600 ( Figure 6 ) as described in block 604 of ). The memory control device may read the value of the register to update the obsolete counter. In some embodiments, the memory control device that receives the signal for updating the obsolete counter of the data in the system cache in block 702 may be a processor (e.g., Figure 1 The CPU 104 and the processor 124 in Figure 2 3 ) and / or a memory controller (e.g., Figure 2and memory controller 220 in FIG. 3 ).

[0081] In optional determination block 704, the memory control device may interpret the register value read in block 702 to determine whether the register value indicates that the memory control device should update the obsolete counter. The value stored in the register may be configured to indicate to the memory control device whether to update the obsolete counter. For example, the register value may be set to a "1" value to indicate to the memory control device that the obsolete counter should be updated, and the register value may be set to a "0" value to indicate to the memory control device that the obsolete counter should not be updated, or vice versa. In some embodiments, the memory control device may read the value of the register to update the obsolete counter. In some embodiments, the memory control device that determines in optional determination block 704 whether the register value indicates to the memory control device to update the obsolete counter may be a processor and / or a memory controller.

[0082] After receiving a signal to update the stale counter of the data in the system cache in block 702; or in response to determining that the register value indicates to the memory control device to update the stale counter (i.e., optional determination block 704 = "Yes"), the memory control device may update the stale counter in block 706. In some embodiments, updating the stale counter in block 706 may be performed when the data is written to the system cache (i.e., at that time). The stale counter may include a register value stored in a memory (e.g., Figure 1 Memory 106, memory 114, Figure 2 L2 cache 208a, 208b, 208c, 210a, 210b, 210c, L3 cache 216, Figure 2 and the system cache 218 and register 222 in FIG. 3 , Figure 4 400 in the system cache 400, which can be read and written by the memory control device. Updating the obsolete counter can be achieved by any mathematical operation, algorithmic operation, heuristic operation, etc. (such as by incrementing and / or decrementing the obsolete counter). In some embodiments, the memory control device that updates the obsolete counter in block 706 can be a processor and / or a memory controller.

[0083] In response to determining that the register value indicates to the memory control device that the stale counter is not to be updated (i.e., optional determination block 704 = "No"); or after updating the stale counter in block 706, the memory control device may calculate a replacement value for the data associated with the local counter in block 708. In some embodiments, the memory control device that calculates the replacement value for the data associated with the local counter in block 708 may be a processor and / or a memory controller. The local counter may include the value of the stale counter stored in association with data written to the system cache in response to a previous write memory command. In one example, the memory control device may read the stale counter associated with the data in the reference cache. Figure 6 The memory control device may store one or more local counter values ​​stored with the cache tag of the memory location targeted by the write memory command received in block 606 of the described method 600. In another example, the memory control device may read one or more local counter values ​​of locations within a block, partition, entirety, and / or any other portion of the system cache.

[0084] The stale threshold may be a preconfigured value. For example, the stale threshold may be preconfigured based on a criteria-aware cache replacement policy. For another example, the stale threshold may be preconfigured based on the size, state, usage, availability, etc. of the system cache. For another example, the stale threshold may be preconfigured based on the processor (e.g., Figure 1 The CPU 104 and the processor 124 in Figure 2 3 ) and / or a computing device (e.g., Figure 1 The threshold value may be pre-configured based on the status, usage, power availability, etc. of the computing device 100 in the system. As another example, the expiration threshold value may be pre-configured based on a task, process, and / or application.

[0085] The memory control device may calculate a replacement value having an outdated threshold. For example, the memory control device may use an arithmetic operation to generate the replacement value using the value of the local counter and the outdated counter value. For example, the memory control device may subtract the value of the local counter from the value of the outdated counter to determine the replacement value.

[0086] In determination block 709, the memory control device may determine whether the replacement values ​​for all data at locations within the block, partition, entirety, and / or any other portion of the system cache are the same. In determination block 709, the memory control device may compare the replacement values ​​calculated in block 708 to one another. For example, the memory control device may determine whether the replacement values ​​are equal to one another based on the comparison. In some embodiments, the memory control device that determines in determination block 709 whether the replacement values ​​for all data at locations within the block, partition, entirety, and / or any other portion of the system cache are the same may be a processor and / or a memory controller.

[0087] In response to determining that the replacement values ​​for all data at locations within a block, partition, entirety, and / or any other portion of the system cache are the same (i.e., determination block 709 = "Yes"), the memory control device may select a cache replacement policy other than the criteria-aware cache replacement policy in block 711. For example, the memory control device may select a cache replacement policy other than nMRU, FIFO, random, etc. In some embodiments, the memory control device that selects a cache replacement policy other than the criteria-aware cache replacement policy in block 711 may be a processor and / or a memory controller.

[0088] After selecting a cache replacement policy other than the criterion-aware cache replacement policy in block 711, the memory control device may Figure 6 A write memory command is received in block 606 of the depicted method 600. The memory control device that receives the write memory command in block 606 may be a processor and / or a memory controller.

[0089] In response to determining that the replacement values ​​for all data at locations within a block, partition, entirety, and / or any other portion of the system cache are not identical (i.e., determination block 709 = "No"), the memory control device may determine in determination block 710 whether the replacement value exceeds or is equal to a stale threshold. The memory control device may compare the replacement value calculated in block 708 to the stale threshold to determine whether to replace the data associated with the local counter value. For example, the memory control device may determine, based on the comparison, whether the replacement value exceeds, is equal to, or exceeds or is equal to the stale threshold. In some embodiments, the memory control device that determines in determination block 710 whether the replacement value exceeds or is equal to the stale threshold may be a processor and / or a memory controller.

[0090] In response to determining that the replacement value exceeds or equals the obsolete threshold (ie, determination block 710 = "Yes"), the memory control device may, in method 700 ( Figure 7 ) in block 712 of method 600 ( Figure 6) and the value of the stale counter are written to the memory at a location where the replacement value exceeds or equals the stale threshold. The comparison result of the replacement value and the stale threshold in the determination block 710 may indicate to the memory control device whether the criteria-aware cache replacement policy should replace the data associated with the local counter value used to calculate the replacement value in block 708. For example, in response to the replacement value exceeding or equaling the stale threshold, the memory control device may implement the criteria-aware cache replacement policy to replace the data associated with the local counter value with the data of the write memory command. The memory control device may replace the data associated with the local counter value by writing the data of the write memory command to a location in the system cache where the data associated with the local counter is stored. The memory control device may also write the value of the stale counter to the system cache as a local counter in association with the data of the write memory command written to the system cache. For example, the memory control device may write the value of the stale counter to a tag location in the system cache associated with the data of the write memory command written to the system cache. In some embodiments, the memory control device that writes the data of the write memory command and the value of the obsolete counter to the memory in block 712 at a location where the replacement value exceeds or equals the obsolete threshold may be a processor and / or a memory controller.

[0091] In response to determining that the replacement value does not exceed or equal the obsolete threshold (ie, determination block 710 = "No"), the memory control device may, at block 714, terminate the method 600 ( Figure 6 ) is written to a location in the memory that complies with the criteria. The criteria for determining where to write the data of the write memory command and the value of the obsolete counter to the system cache may be any known criteria, such as a cache placement policy, a cache replacement policy, a cache coherence policy, etc. The memory control device may also write the value of the obsolete counter as a local counter to the system cache in association with the data of the write memory command written to the system cache. For example, the memory control device may write the value of the obsolete counter to a tag location in the system cache that is associated with the data of the write memory command written to the system cache. In some embodiments, the memory control device that writes the data of the write memory command and the value of the obsolete counter to the location in the memory that complies with the criteria in block 714 may be a processor and / or a memory controller.

[0092] After writing the data of the write memory command and the value of the obsolete counter to the location of the memory where the replacement value exceeds or equals the obsolete threshold in block 712; or after writing the data of the write memory command and the value of the obsolete counter to the location of the memory that meets the criteria in block 714, the memory control device may Figure 6 A write memory command is received in block 606 of the depicted method 600. The memory control device that receives the write memory command in block 606 may be a processor and / or a memory controller.

[0093] Figure 8 A method 800 for implementing a criteria-aware cache replacement policy that replaces data based on the value of a local counter is illustrated in accordance with some embodiments. Figures 1 to 8 , the method 800 may be performed on a computing device (e.g., Figure 1 in a computing device 100), in hardware, in a processor (e.g., Figure 1 The CPU 104 and the processor 124 in Figure 2 3 ), or in software executed in a processor 202, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214, client 300 in FIG. 3 , or in a processor configured in software and including, for example, various memories / caches (e.g., Figure 1 Memory 106, memory 114, Figure 2 L2 cache 208a, 208b, 208c, 210a, 210b, 210c, L3 cache 216, Figure 2 and the system cache 218 and register 222 in FIG. 3 , Figure 4 system cache 400 in FIG. 400 ) and various memory / cache controllers (e.g., Figure 2 3 ). To cover alternative configurations implemented in various embodiments, the hardware implementing method 800 is referred to herein as a "memory control device." Blocks 802-814 of method 800 elaborate on the memory control device that may be used in reference to FIG. Figure 6 The operations performed in block 608 of method 600 are described.

[0094] In block 802, the memory control device may calculate a replacement value for data associated with a local counter. In some embodiments, the memory control device that calculates the replacement value for data associated with the local counter in block 802 may be a processor (e.g., Figure 1 The CPU 104 and the processor 124 in Figure 2 3 ) and / or a memory controller (e.g., Figure 23 and memory controller 220). The local counter may include a counter associated with a write to the system cache in response to a previous write memory command (e.g., Figure 2 and the system cache 218 in FIG. 3 , Figure 4 The expiration counter may include a value of an expired counter stored in association with data stored in a memory (e.g., a system cache 400 in FIG. 4 ). Figure 1 Memory 106, memory 114, Figure 2 L2 cache 208a, 208b, 208c, 210a, 210b, 210c, L3 cache 216, Figure 2 and the system cache 218 and register 222 in FIG. 3 , Figure 4 The value in the system cache 400 in the memory controller can be read and written by the memory controller. In one example, the memory controller can read and write the value in the system cache 400 in the memory controller. Figure 6 The memory control device may store one or more local counter values ​​stored with the cache tag of the memory location targeted by the write memory command received in block 606 of the described method 600. In another example, the memory control device may read one or more local counter values ​​of locations within a block, partition, entirety, and / or any other portion of the system cache.

[0095] The stale threshold may be a preconfigured value. For example, the stale threshold may be preconfigured based on a criteria-aware cache replacement policy. For another example, the stale threshold may be preconfigured based on the size, state, usage, availability, etc. of the system cache. For another example, the stale threshold may be preconfigured based on the processor (e.g., Figure 1 The CPU 104 and the processor 124 in Figure 2 3 ) and / or a computing device (e.g., Figure 1 The threshold value may be pre-configured based on the status, usage, power availability, etc. of the computing device 100 in the system. As another example, the expiration threshold value may be pre-configured based on a task, process, and / or application.

[0096] The memory control device may calculate a replacement value having an outdated threshold. For example, the memory control device may use an arithmetic operation to generate the replacement value using the value of the local counter and the outdated counter value. For example, the memory control device may subtract the value of the local counter from the value of the outdated counter to determine the replacement value.

[0097] In determination block 803, the memory control device may determine whether the replacement values ​​of all data at locations within a block, partition, entirety, and / or any other portion of the system cache are the same. In this determination, the memory control device may compare the replacement values ​​calculated in block 802 to each other. For example, the memory control device may determine whether the replacement values ​​are equal to each other based on the comparison. In some embodiments, the memory control device that determines in determination block 803 whether the replacement values ​​of all data at locations within a block, partition, entirety, and / or any other portion of the system cache are the same may be a processor and / or a memory controller.

[0098] In response to determining that the replacement values ​​for all data at locations within a block, partition, entirety, and / or any other portion of the system cache are the same (i.e., determination block 803 = "Yes"), the memory control device may select a cache replacement policy other than the criteria-aware cache replacement policy in block 805. For example, the memory control device may select an nMRU or FIFO cache replacement policy. In some embodiments, the memory control device that selects a cache replacement policy other than the criteria-aware cache replacement policy in block 805 may be a processor and / or a memory controller.

[0099] After selecting a cache replacement policy other than the criterion-aware cache replacement policy in block 805, the memory control device may Figure 6 A write memory command is received in block 606 of the depicted method 600. The memory control device that receives the write memory command in block 606 may be a processor and / or a memory controller.

[0100] In response to determining that the replacement values ​​for all data at locations within a block, partition, entirety, and / or any other portion of the system cache are not identical (i.e., determination block 709 = "No"), the memory control device may determine in determination block 804 whether the replacement value exceeds or is equal to a stale threshold. The memory control device may compare the replacement value calculated in block 802 to the stale threshold to determine whether to replace the data associated with the local counter value. For example, the memory control device may determine, based on the comparison, whether the replacement value exceeds, is equal to, or exceeds or is equal to the stale threshold. In some embodiments, the memory control device that determines in determination block 804 whether the replacement value exceeds or is equal to the stale threshold may be a processor and / or a memory controller.

[0101] In response to determining that the replacement value exceeds or equals the obsolete threshold (ie, determination block 804 = "Yes"), the memory control device may, in block 806, perform the following steps in method 600 ( Figure 6) and the value of the stale counter are written to the memory at a location where the replacement value exceeds or equals the stale threshold. The comparison result of the replacement value and the stale threshold in the determination block 804 may indicate to the memory control device whether the criteria-aware cache replacement policy should replace the data associated with the local counter value used to calculate the replacement value in block 802. For example, in response to the replacement value exceeding or equaling the stale threshold, the memory control device may implement the criteria-aware cache replacement policy to replace the data associated with the local counter value with the data of the write memory command. The memory control device may replace the data associated with the local counter value by writing the data of the write memory command to a location in the system cache where the data associated with the local counter is stored. The memory control device may also write the value of the stale counter to the system cache as a local counter in association with the data of the write memory command written to the system cache. For example, the memory control device may write the value of the stale counter to a tag location in the system cache associated with the data of the write memory command written to the system cache. In some embodiments, the memory control device that writes the data of the write memory command and the value of the obsolete counter to the memory in block 806 where the replacement value exceeds or equals the obsolete threshold may be a processor and / or a memory controller.

[0102] In response to determining that the replacement value does not exceed or equal the obsolete threshold (ie, determination block 804 = "No"), the memory control device may, at block 808, terminate the method 600 ( Figure 6 ) is written to a location in the memory that complies with the criteria. The criteria for determining where to write the data of the write memory command and the value of the obsolete counter to the system cache may be any known criteria, such as a cache placement policy, a cache replacement policy, a cache coherence policy, etc. The memory control device may also write the value of the obsolete counter as a local counter to the system cache in association with the data of the write memory command written to the system cache. For example, the memory control device may write the value of the obsolete counter to a tag location in the system cache that is associated with the data of the write memory command written to the system cache. In some embodiments, the memory control device that writes the data of the write memory command and the value of the obsolete counter to the location in the memory that complies with the criteria in block 808 may be a processor and / or a memory controller.

[0103] After or as part of writing the data of the write memory command and the value of the stale counter to the memory at a location where the replacement value exceeds or equals the stale threshold in block 806, or writing the data of the write memory command and the value of the stale counter to the memory at a location that meets the criteria in block 808, the memory control device may receive a signal for updating the stale counter of the data in the system cache. For example, the memory control device may read a register (e.g., Figure 2 3 ), receiving a direct interrupt, etc., to update the stale counter of the data in the system cache. The register may be associated with the stale counter update feature of the criterion-aware cache replacement policy and may have a value configured to indicate to the memory control device whether to update the stale counter. The value of the register may be set, for example, by writing to the register to update the stale counter of the data in the system cache, as shown in FIG. Figure 6 As described with respect to block 604 of method 600. The memory control device may read the value of the register to update the stale counter. In some embodiments, the memory control device that receives the signal for updating the stale counter of the data in the system cache in block 810 may be a processor and / or a memory controller.

[0104] In optional determination block 812, the memory control device may determine whether the register value indicates to the memory control device to update the obsolete counter. The value stored in the register may be configured to indicate to the memory control device whether to update the obsolete counter. For example, the register value may be to set the obsolete counter update value to a "1" value configured to indicate to the memory control device to update the obsolete counter, and to be configured to indicate to the memory control device not to update the obsolete counter "0" value, or vice versa. The memory control device may interpret the register value read in block 810 to determine whether the register value indicates to update the obsolete counter. In some embodiments, the memory control device may read the value of the register to update the obsolete counter. In some embodiments, the memory control device that determines in optional determination block 812 whether the register value indicates to the memory control device to update the obsolete counter may be a processor and / or a memory controller.

[0105] After receiving a signal to update the stale counter of the data in the system cache in block 810; or in response to determining that the register value indicates to the memory control device to update the stale counter (i.e., optional determination block 812 = "Yes"), the memory control device may update the stale counter in block 814. In some embodiments, updating the stale counter in block 814 may be performed when the data is written to the system cache (i.e., at approximately the same time) (e.g., in blocks 806 or 808). Updating the stale counter may be accomplished by any mathematical operation, algorithmic operation, heuristic operation, etc. (such as by incrementing and / or decrementing the stale counter). In some embodiments, the memory control device that updates the stale counter in block 814 may be a processor and / or a memory controller.

[0106] After updating the obsolete counter in block 814; or in response to determining that the register value indicates to the memory control device that the obsolete counter is not updated (ie, optional determination block 812 = "No"), the memory control device may, as shown in reference Figure 6 A write memory command is received in block 606 of the depicted method 600. The memory control device that receives the write memory command in block 606 may be a processor and / or a memory controller.

[0107] Fig. 9 A method 900 for implementing a criteria-aware cache replacement policy based on replacing data based on invalidating the data based on the value of a local counter is illustrated in accordance with some embodiments. Figures 1 to 9 , method 900 may be performed on a computing device (e.g., Figure 1 in a computing device 100), in hardware, in a processor (e.g., Figure 1 The CPU 104 and the processor 124 in Figure 2 3 ), or in software executed in a processor 202, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214, client 300 in FIG. 3 , or in a processor configured in software and including, for example, various memories / caches (e.g., Figure 1 Memory 106, memory 114, Figure 2 L2 cache 208a, 208b, 208c, 210a, 210b, 210c, L3 cache 216, Figure 2 and the system cache 218 and register 222 in FIG. 3 , Figure 4 system cache 400 in FIG. 400 ) and various memory / cache controllers (e.g., Figure 23 ) are implemented in combination with dedicated hardware of other separate components of the memory controller 220 in FIG. 3 . To cover alternative configurations implemented in various embodiments, the hardware implementing method 900 is referred to herein as a “memory control device”. Blocks 702-711, 714, 902, 904 of method 900 describe Figure 6 The operations performed as part of the operations in block 608 of the method 600 described above. Blocks 702-711, 714 may be similar to those of reference Figure 7 The method 700 described herein is implemented by way of similarly numbered blocks.

[0108] In response to determining that the replacement value exceeds or equals the stale threshold (i.e., determination block 710 = "Yes"), the memory control device may invalidate the data at the location where the replacement value exceeds or equals the stale threshold in block 902. The result of comparing the replacement value to the stale threshold in determination block 710 may indicate to the memory control device whether the criteria-aware cache replacement policy should replace the data associated with the local counter value used to calculate the replacement value in block 708. For example, in response to the replacement value exceeding or equaling the stale threshold, the memory control device may implement the criteria-aware cache replacement policy to replace the data associated with the local counter value with the data of the write memory command. The memory control device may invalidate the data using known ways of invalidating data in memory. For example, the memory control device may write to a local counter value associated with a system cache (e.g., Figure 2 and the system cache 218 in FIG. 3 , Figure 4 The memory controller may be configured to determine the value of a valid / invalid bit associated with a location in the system cache 400 (in block 708) that is associated with a local counter value used to calculate a replacement value in block 708. The value of the valid / invalid bit may be configured to indicate to the memory controller whether the data at the location in the system cache is valid / invalid. In some embodiments, the memory controller that invalidates the data at the location where the replacement value exceeds or equals the stale threshold in block 902 may be a processor (e.g., Figure 1 The CPU 104 and the processor 124 in Figure 2 3 ) and / or a memory controller (e.g., Figure 2 and memory controller 220 in FIG. 3 ).

[0109] In block 904, the memory control device may Figure 6) and the value of the stale counter are written to the location of the memory where the data is invalid. The memory control device may read the valid / invalid bits of the locations in the system cache to determine which locations have valid / invalid data. The memory control device may replace the data associated with the local counter value by writing the data of the write memory command to the location in the system cache where the data associated with the valid / invalid bit is stored. The memory control device may also write the value of the stale counter as a local counter to the system cache in association with the data of the write memory command written to the system cache. For example, the memory control device may write the value of the stale counter to a tag location in the system cache associated with the data of the write memory command written to the system cache. In some embodiments, the memory control device that writes the data of the write memory command and the value of the stale counter to the location of the memory where the data is invalid in block 904 may be a processor and / or a memory controller.

[0110] After writing the data of the write memory command and the value of the obsolete counter to the location of the memory where the data is invalid in block 904; or after writing the data of the write memory command and the value of the obsolete counter to the location of the memory that meets the criteria in block 714, the memory control device may Figure 6 A write memory command is received in block 606 of the depicted method 600. The memory control device that receives the write memory command in block 606 may be a processor and / or a memory controller.

[0111] Fig.10 A method 1000 for implementing a criteria-aware cache replacement policy based on replacing data based on invalidating the data based on the value of a local counter is illustrated in accordance with some embodiments. Figures 1 to 10 , the method 1000 may be performed on a computing device (e.g., Figure 1 in a computing device 100), in hardware, in a processor (e.g., Figure 1 The CPU 104 and the processor 124 in Figure 2 3 ), or in software executed in a processor 202, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214, client 300 in FIG. 3 , or in a processor configured in software and including, for example, various memories / caches (e.g., Figure 1 Memory 106, memory 114, Figure 2 L2 cache 208a, 208b, 208c, 210a, 210b, 210c, L3 cache 216, Figure 2 and the system cache 218 and register 222 in FIG. 3 , Figure 4 system cache 400 in FIG. 400 ) and various memory / cache controllers (e.g., Figure 2 3 ). To cover alternative configurations implemented in various embodiments, the hardware implementing method 1000 is referred to herein as a "memory control device". Blocks 802-805, 808-814, 1002, 1004 of method 1000 may be described as references. Figure 6 The operations performed as part of block 608 of method 600 are described in detail. Blocks 802-805, 808-814 may be similar to those described herein with reference to Figure 8 The method 900 described herein is implemented by way of similarly numbered blocks.

[0112] In response to determining that the replacement value exceeds or equals the stale threshold (i.e., determination block 804 = "Yes"), the memory control device may invalidate the data at the location where the replacement value exceeds or equals the stale threshold in block 1002. The result of comparing the replacement value to the stale threshold in determination block 804 may indicate to the memory control device whether the criteria-aware cache replacement policy should replace the data associated with the local counter value used to calculate the replacement value in block 802. For example, in response to the replacement value exceeding or equaling the stale threshold, the memory control device may implement the criteria-aware cache replacement policy to replace the data associated with the local counter value with the data of the write memory command. The memory control device may invalidate the data using known ways of invalidating data in memory. For example, the memory control device may write to a local counter value associated with a system cache (e.g., Figure 2 and the system cache 218 in FIG. 3 , Figure 4 The memory controller may be configured to determine the value of a valid / invalid bit associated with a location in the system cache 400 in block 802 that is associated with a local counter value used to calculate a replacement value in block 802. The value of the valid / invalid bit may be configured to indicate to the memory controller whether the data at the location in the system cache is valid / invalid. In some embodiments, the memory controller that invalidates the data at the location where the replacement value exceeds or equals the stale threshold in block 1002 may be a processor (e.g., Figure 1 The CPU 104 and the processor 124 in Figure 2 3 ) and / or a memory controller (e.g., Figure 2 and memory controller 220 in FIG. 3 ).

[0113] In block 1004, the memory control device may Figure 6) and the value of the stale counter are written to the memory at locations where the data is invalid. The memory control device may read the valid / invalid bits of the locations in the system cache to determine which locations have valid / invalid data. The memory control device may replace the data associated with the local counter value by writing the data of the write memory command to the locations in the system cache where the data associated with the valid / invalid bits are stored. The memory control device may also write the value of the stale counter to the system cache as a local counter in association with the data of the write memory command written to the system cache. In some embodiments, when the data is written to the system cache (i.e., at approximately the same time), updating the stale counter by writing the value of the stale counter to the system cache as a local counter in association with the data of the write memory command in block 1004 may be performed. For example, the memory control device may write the value of the stale counter to a tag location in the system cache associated with the data of the write memory command written to the system cache. In some embodiments, the memory control device that writes the data of the write memory command and the value of the stale counter to the locations where the data is invalid in block 1004 may be a processor and / or a memory controller.

[0114] Fig.11 A method 1100 for implementing a criterion-aware cache replacement policy according to some embodiments is illustrated. Figures 1 to 11 , the method 1100 may be performed on a computing device (e.g., Figure 1 in a computing device 100), in hardware, in a processor (e.g., Figure 1 The CPU 104 and the processor 124 in Figure 2 3 ), or in software executed in a processor 202, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214, client 300 in FIG. 3 , or in a processor configured in software and including, for example, various memories / caches (e.g., Figure 1 Memory 106, memory 114, Figure 2 L2 cache 208a, 208b, 208c, 210a, 210b, 210c, L3 cache 216, Figure 2 and the system cache 218 and register 222 in FIG. 3 , Figure 4 system cache 400 in FIG. 400 ) and various memory / cache controllers (e.g., Figure 23 ) in combination with dedicated hardware of other individual components of the memory controller 220 in FIG. 3 . To cover alternative configurations implemented in various embodiments, the hardware implementing method 1100 is referred to herein as a “client” and a “memory control device”.

[0115] In block 1102, the client may send a request to a system cache (e.g., Figure 2 and the system cache 218 in FIG. 3 , Figure 4 A read memory command targeting the system cache 400 in FIG.

[0116] In block 1104, the client may send a signal to a processor (e.g., Figure 1 The CPU 104 and the processor 124 in Figure 2 3 ), indicating that the processor should update the stale counter of the data in the system cache. The client can use various types of signal communication to signal the processor, including, for example, registers (e.g., Figure 2 3 ), a direct interrupt to the processor, etc. The register may be associated with a stale counter update feature of a criterion-aware cache replacement policy. Writing to the register may set a value of a register configured to indicate to a memory control device whether a stale counter should be updated. In some embodiments, the client that sends the read memory command in block 1102 and signals the processor in block 1104 to update the stale counter of data in the system cache may be a processor (e.g., Figure 1 The CPU 104 and the processor 124 in Figure 2 3 ), and / or software programs (e.g., the client 300 in FIG. 3 ), such as an operating system and / or an application.

[0117] The memory control device may receive a read memory command in block 1106. The memory control device may be configured to manage, control and / or implement memory access, cache maintenance, cache coherency and / or cache replacement policies of a system cache.

[0118] In block 1108, the memory control device may implement a criteria-aware cache replacement policy for writing the data of the read memory command into the system cache. The memory control device that receives the read memory command in block 1106 and implements the criteria-aware cache replacement policy in block 1108 may be a processor (e.g., Figure 1 The CPU 104 and the processor 124 in Figure 2 3 ) and / or a memory controller (e.g., Figure 2 and memory controller 220 in FIG. 3 ).

[0119] Fig.12 A method 1200 for implementing a criteria-aware cache replacement policy based on replacing data based on invalidating the data based on the value of a local counter is illustrated in accordance with some embodiments. Figures 1 to 12 , the method 1200 may be performed on a computing device (e.g., Figure 1 in a computing device 100), in hardware, in a processor (e.g., Figure 1 The CPU 104 and the processor 124 in Figure 2 3 ), or in software executed in a processor 202, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214, client 300 in FIG. 3 , or in a processor configured in software and including, for example, various memories / caches (e.g., Figure 1 Memory 106, memory 114, Figure 2 L2 cache 208a, 208b, 208c, 210a, 210b, 210c, L3 cache 216, Figure 2 and the system cache 218 and register 222 in FIG. 3 , Figure 4 system cache 400 in FIG. 400 ) and various memory / cache controllers (e.g., Figure 2 3 ). To cover alternative configurations implemented in various embodiments, the hardware implementing method 1200 is referred to herein as a "memory control device". Blocks 702-706 of method 1200, 1202, describe a memory control device that can be used as a reference. Fig.11 The operations performed as part of the operations in block 1108 of the method 1100 described herein. Blocks 702-706 may be similar to those described herein with reference to Figure 7 The method 700 described herein is implemented by way of similarly numbered blocks.

[0120] In response to determining that the register value indicates that the memory control device should not update the obsolete counter (ie, optional determination block 704 = "No"); or after updating the obsolete counter in block 706, the memory control device may, in method 1100 ( Fig.11 ) and writes the value of the obsolete counter to the memory. The memory control device may read the system cache (e.g., Figure 2 and the system cache 218 in FIG. 3 , Figure 4 The memory control device may further write the value of the stale counter as a local counter to the system cache in association with the data targeted by the read memory command in the system cache. For example, the memory control device may write the value of the stale counter to a tag location in the system cache associated with the data targeted by the read memory command in the system cache. In some embodiments, the memory control device that reads the data from the memory at the location targeted by the read memory command and writes the value of the stale counter to the memory in block 1202 may be a processor (e.g., Figure 1 The CPU 104 and the processor 124 in Figure 2 3 ) and / or a memory controller (e.g., Figure 2 and memory controller 220 in FIG. 3 ).

[0121] After reading data from the memory at the location targeted by the read memory command and writing the value of the obsolete counter to the memory in block 1202, the memory control device may Figure 6 A write memory command is received in block 606 of the depicted method 600. The memory control device that receives the write memory command in block 606 may be a processor and / or a memory controller.

[0122] Fig.13 A method 1300 for implementing a criteria-aware cache replacement policy based on replacing data based on invalidating the data based on the value of a local counter is illustrated in accordance with some embodiments. Figures 1 to 13 , the method 1300 may be performed on a computing device (e.g., Figure 1 in a computing device 100), in hardware, in a processor (e.g., Figure 1 The CPU 104 and the processor 124 in Figure 23 ), or in software executed in a processor 202, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214, client 300 in FIG. 3 , or in a processor configured in software and including, for example, various memories / caches (e.g., Figure 1 Memory 106, memory 114, Figure 2 L2 cache 208a, 208b, 208c, 210a, 210b, 210c, L3 cache 216, Figure 2 and the system cache 218 and register 222 in FIG. 3 , Figure 4 system cache 400 in FIG. 400 ) and various memory / cache controllers (e.g., Figure 2 3 ). To cover alternative configurations implemented in various embodiments, the hardware implementing method 1300 is referred to herein as a "memory control device". Blocks 810-814, 1202 of method 1200 describe a memory control device that can be used as a reference. Fig.11 The operations performed as part of the operations in block 1108 of the method 1100 described herein. Blocks 810-814 may be similar to those described herein with reference to Figure 8 The method 800 described herein is implemented by way of similarly numbered blocks.

[0123] In block 1302, a memory control device may, in method 1100 ( Fig.11 ) and writes the obsolete counter value to the memory. The memory control device may read the system cache (e.g., Figure 2 and the system cache 218 in FIG. 3 , Figure 4 The memory control device may further write the value of the stale counter as a local counter to the system cache in association with the data targeted by the read memory command in the system cache. For example, the memory control device may write the value of the stale counter to a tag location in the system cache associated with the data targeted by the read memory command in the system cache. In some embodiments, the memory control device that reads the data from the memory at the location targeted by the read memory command and writes the value of the stale counter to the memory in block 1302 may be a processor (e.g., Figure 1 The CPU 104 and the processor 124 in Figure 23 ) and / or a memory controller (e.g., Figure 2 and memory controller 220 in FIG. 3 ).

[0124] According to various embodiments (including but not limited to the above reference Figures 1 to 13 The system of the embodiments described herein can be implemented in a variety of computing systems including mobile computing devices. An example of a mobile computing device suitable for use with various embodiments is Fig.14 1400. The mobile computing device 1400 may include a processor 1402 coupled to a touch screen controller 1404 and an internal memory 1406. The processor 1402 may be one or more multi-core integrated circuits designated for general or specific processing tasks. The internal memory 1406 may be volatile or non-volatile memory, and may also be secure and / or encrypted memory, or unsecure and / or unencrypted memory, or any combination thereof. Examples of available memory types include, but are not limited to, DDR, low power DDR (LPDDR), graphic DDR (GDDR), WIDEIO, RAM, static RAM (SRAM), dynamic RAM (DRAM), parameter RAM (P-RAM), resistive RAM (R-RAM), magnetoresistive RAM (M-RAM), spin transfer torque RAM (STT-RAM), and embedded DRAM. The touch screen controller 1404 and the processor 1402 may also be coupled to a touch screen panel 1412, such as a resistive sensing touch screen, a capacitive sensing touch screen, an infrared sensing touch screen, etc. In addition, the display of the mobile computing device 1400 does not need to have touch screen capabilities.

[0125] The mobile computing device 1400 may have one or more radio signal transceivers 1408 (e.g., Peanut, Bluetooth, ZigBee, Wi-Fi, RF radios) coupled to each other and / or to the processor 1402 and an antenna 1410 for sending and receiving communications. The transceiver 1408 and antenna 1410 may be used with the circuits mentioned above to implement various wireless transmission protocol stacks and interfaces. The mobile computing device 1400 may include a cellular network wireless modem chip 1416 that enables communication via a cellular network and is coupled to the processor.

[0126] The mobile computing device 1400 may include a peripheral device connection interface 1418 coupled to the processor 1402. The peripheral device connection interface 1418 may be configured solely to accept one type of connection, or may be configured to accept various types of physical and communication connections that are shared or proprietary, such as Universal Serial Bus (USB), FireWire, Thunderbolt, or PCIe. The peripheral device connection interface 1418 may also be coupled to a similarly configured peripheral device connection port (not shown).

[0127] The mobile computing device 1400 may also include a speaker 1414 for providing audio output. The mobile computing device 1400 may also include a housing 1420 for housing all or some of the components described herein, the housing being constructed of plastic, metal, or a combination of materials. The mobile computing device 1400 may include a power source 1422, such as a disposable or rechargeable battery, coupled to the processor 1402. The rechargeable battery may also be coupled to a peripheral device connection port to receive a charging current from a source external to the mobile computing device 1400. The mobile computing device 1400 may also include a physical button 1424 for receiving user input. The mobile computing device 1400 may also include a power button 1426 for turning the mobile computing device 1400 on and off.

[0128] According to various embodiments (including but not limited to the above reference Figures 1 to 12 The system of the embodiment described in the present invention can be implemented in a variety of computing systems including a laptop computer 1500, an example of which is shown in FIG. Fig.15 1500. Many laptop computers include a touchpad touch surface 1517 that serves as a pointing device for the computer and can therefore receive drag, scroll, and tap gestures similar to those implemented on computing devices equipped with a touch screen display and as described above. Laptop computer 1500 will typically include a processor 1502 coupled to volatile memory 1512 and a disk drive 1513 of a large capacity non-volatile memory such as flash memory. In addition, computer 1500 may have one or more antennas 1508 for sending and receiving electromagnetic radiation, connectable to a wireless data link, and / or a cellular telephone transceiver 1516 coupled to processor 1502. Computer 1500 may also include a floppy disk drive 1514 and a compact disk (CD) drive 1515 coupled to processor 1502. In a notebook configuration, the computer housing includes a touchpad 1517, a keyboard 1518, and a display 1519, all coupled to processor 1502. Other configurations of computing devices may include a computer mouse or trackball coupled to a processor (eg, via USB input) as is well known, which may also be used in conjunction with various embodiments.

[0129] According to various embodiments (including but not limited to the above reference Figures 1 to 12 The system of the described embodiments) may also be implemented in a fixed computing system, such as any of a variety of commercially available servers. Fig.16 An example server 1600 is illustrated in FIG. Such a server 1600 typically includes one or more multi-core processor assemblies 1601 coupled to a volatile memory 1602 and a large capacity non-volatile memory (such as a disk drive 1604). Fig.16 As shown, a multi-core processor assembly 1601 can be added to a server 1600 by inserting it into a chassis for the assembly. The server 1600 may also include a floppy disk drive, a compact disk (CD), or a digital versatile disk (DVD) disk drive 1606 coupled to the processor 1601. The server 1600 may also include a network access port 1603 coupled to the multi-core processor assembly 1601 for establishing a network interface connection with a network 1605, such as a local area network coupled to other broadcast system computers and servers, the Internet, a public switched telephone network, and / or a cellular data network (e.g., CDMA, TDMA, GSM, PCS, 3G, 4G, LTE, 5G, or any other type of cellular data network).

[0130] Each specific implementation example is described in the following paragraphs. Although some of the specific implementation examples in the following specific implementation examples are described in terms of example systems, devices, or methods, other example implementations may include: an example system or device implemented as a method for performing the operations of an example system or device discussed in the following paragraphs, an example system, device, or method implemented by a computing device including a processing device configured with processing device executable instructions to perform the operations of an example system, device, or method discussed in the following paragraphs; a computing device including a memory control device configured to perform the operations of an example system, device, or method; an example system, device, or method implemented by a computing device discussed in the following paragraphs, the computing device including a component for performing the functions of an example system, device, or method; and an example system, device, or method implemented as a non-transitory processor-readable storage medium having processor executable instructions stored thereon, which are configured to cause a processor of the computing device to perform the operations of the example system, device, or method discussed in the following paragraphs.

[0131] Embodiment 1. A method for implementing a criteria-aware cache replacement policy by a computing device, comprising: updating an outdated counter; writing a value of a local counter to a system cache in association with a location in the system cache for associated data, wherein the value of the local counter includes the value of the outdated counter when the associated data is written to the system cache; and determining whether the associated data is outdated using the value of the local counter of the associated data.

[0132] Embodiment 2. A method according to embodiment 1, wherein updating the expiration counter comprises receiving a signal configured to indicate whether to update the expiration counter from a client of the computing device; determining whether to update the expiration counter based on the signal; and updating the expiration counter in response to determining to update the expiration counter.

[0133] Embodiment 3. A method according to any one of embodiments 1 or 2, wherein the signal is a register write command, and wherein receiving the signal from the client of the computing device includes reading a value from a register set by the client, and determining whether to update the expiration counter based on the signal includes determining whether to update the expiration counter based on the value from the register.

[0134] Embodiment 4. The method of embodiment 3 further comprises setting, by the client of the computing device, the value at the register according to time-based criteria.

[0135] Embodiment 5. The method of embodiment 3 further comprises setting, by the client of the computing device, the value at the register according to event-based criteria.

[0136] Embodiment 6. The method according to any one of embodiments 1 to 5 further includes receiving a memory write command, wherein writing the value of the local counter to the system cache in association with the location in the system cache for the associated data may occur before updating the obsolete counter, wherein the associated data is data of the write memory command.

[0137] Embodiment 7. A method according to any one of embodiments 1 to 6, wherein determining whether the associated data is outdated using the value of the local counter of the associated data includes calculating a replacement value using the value of the outdated counter and the value of the local counter, and determining whether the replacement value exceeds an outdated threshold, wherein the associated data is determined to be outdated in response to determining that the replacement value exceeds the outdated threshold.

[0138] Embodiment 8. The method according to embodiment 7 further includes receiving a memory access command, and writing data of the memory access command to the system cache at a location where the replacement value exceeds the obsolete threshold, wherein the data of the memory access command written to the system cache is the associated data.

[0139] Embodiment 9. The method according to embodiment 7 further includes receiving a memory write command, invalidating data at a location where the replacement value exceeds the obsolete threshold, and writing the data of the memory write command to the location of the system cache having the invalid data, wherein the data of the memory write command written to the system cache is the associated data.

[0140] Embodiment 10. The method according to any one of embodiments 1 to 9 further includes receiving a memory write access command, and in response to determining that no replacement value exceeds the obsolete threshold, writing the data of the memory write access command to a location of the system cache that complies with another cache replacement policy.

[0141] Computer program code or "program code" for execution on a programmable processor to perform the operations of the various embodiments may be written in a high-level programming language (such as C, C++, C#, Smalltalk, Java, JavaScript, Visual Basic), a structured query language (e.g., Transact-SQL), Perl, or in a variety of other programming languages. Program code or program stored on a computer-readable storage medium as used in this application may refer to machine language code (such as object code) in a format that can be understood by a processor.

[0142] The foregoing method descriptions and process flow charts are provided only as illustrative examples and are not intended to require or imply that the operations of the various embodiments must be performed in the order presented. As will be appreciated by those skilled in the art, the order of operations in the foregoing embodiments may be performed in any order. Words such as "thereafter", "then", "next", etc. are not intended to limit the order of operations; these words are only used to guide the reader to read the description of the method. In addition, any reference to a claim element in singular form (e.g., a reference using the article "one", "an", or "said") should not be interpreted as limiting the element to a singular.

[0143] The various illustrative logical blocks, modules, circuits, and algorithmic operations described in conjunction with the various embodiments may be implemented as electronic hardware, computer software, or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and operations have been generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system. Although a technician may implement the described functionality in different ways for each specific application, such implementation decisions should not be interpreted as causing a departure from the scope of the claims.

[0144] The hardware for implementing the various exemplary logics, logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or executed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, a discrete hardware component, or any combination thereof designed to perform the functions described herein. Although a general purpose processor may be a microprocessor, in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. Alternatively, some operations or methods may be performed by circuits specific to a given function.

[0145] In one or more embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, each function may be stored as one or more instructions or codes on a non-transient computer-readable medium or a non-transient processor-readable medium. The operation of the method or algorithm disclosed herein may be implemented in a processor-executable software module, which may reside on a non-transient computer-readable or processor-readable storage medium. A non-transient computer-readable or processor-readable storage medium may be any storage medium accessible by a computer or processor. By way of example and not limitation, such non-transient computer-readable or processor-readable media may include RAM, ROM, EEPROM, flash memory, CD-ROM or other optical disk storage, disk storage or other magnetic storage devices, or any other medium that may be used to store desired program codes in the form of instructions or data structures and may be accessed by a computer. Disks and optical disks as used herein include compact discs (CDs), laser discs, optical disks, digital versatile discs (DVDs), floppy disks, and blue discs, wherein disks generally magnetically replicate data, and optical disks optically replicate data with lasers. The above combination is also included in the scope of non-transient computer-readable and processor-readable media. Additionally, the operations of a method or algorithm may reside as one or any combination or set of codes and / or instructions on a non-transitory processor-readable medium and / or computer-readable medium, which may be incorporated into a computer program product.

[0146] The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the claims. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and implementations without departing from the scope of the claims. Thus, the present disclosure is not intended to be limited to the embodiments and implementations described herein, but should be granted the broadest scope consistent with the appended claims and the principles and novel features disclosed herein.

Claims

1. A method for implementing a criterion-aware cache replacement policy by a computing device, comprising: Update the expiration counter; writing a value of a local counter to a system cache in association with a location in the system cache for associated data, wherein the value of the local counter includes a value of the stale counter when the associated data was written to the system cache; calculating a replacement value using the value of the stale counter and the value of the local counter of the associated data; determining whether all replacement values ​​of a plurality of associated data in a portion of the system cache are equal to one another; as well as In response to determining that not all of the replacement values ​​for the plurality of associated data in the portion of the system cache are equal to one another, determining whether the replacement value exceeds a staleness threshold is determined, wherein the associated data is determined to be stale in response to determining that the replacement value exceeds the staleness threshold.

2. The method of claim 1 , wherein updating the stale counter comprises: receiving a signal from a client of the computing device, the signal configured to indicate whether to update the stale counter; determining whether to update the expiration counter based on the signal; as well as The expiration counter is updated in response to determining to update the expiration counter.

3. The method of claim 2, wherein the signal is a register write command, and wherein: Receiving the signal from the client of the computing device comprises reading a value from a register set by the client; as well as Determining whether to update the expiration counter based on the signal includes determining whether to update the expiration counter based on the value from the register. 4 . The method of claim 3 , further comprising setting, by the client of the computing device, the value at the register according to a time-based criterion. 5 . The method of claim 3 , further comprising setting, by the client of the computing device, the value at the register according to event-based criteria.

6. The method of claim 1 further comprising receiving a memory write command, wherein writing the value of the local counter to the system cache in association with the location in the system cache for the associated data occurs before updating the stale counter, wherein the associated data is data of the write memory command.

7. The method according to claim 1, further comprising: receiving a memory access command; as well as Writing data of the memory access command to the system cache at a location where the replacement value exceeds the stale threshold, wherein the data of the memory access command written to the system cache is the associated data.

8. The method according to claim 1, further comprising: receiving a memory write command; invalidating data at locations where the replacement value exceeds the obsolete threshold; as well as Writing data of the memory write command to the system cache at a location having the invalid data, wherein the data of the memory write command written to the system cache is the associated data.

9. The method according to claim 1, further comprising: receiving a memory write access command; as well as Data of the memory write access command is written to the system cache at a location that complies with another cache replacement policy in response to determining that no replacement value exceeds the staleness threshold.

10. The method of claim 1, wherein calculating the replacement value using the value of the stale counter and the value of the local counter of the associated data comprises calculating a difference between the value of the stale counter and the value of the local counter.

11. A computing device comprising: A memory control device, the memory control device being configured to: Update the expiration counter; writing a value of a local counter to a system cache in association with a location in the system cache for associated data, wherein the value of the local counter includes a value of the stale counter when the associated data was written to the system cache; calculating a replacement value using the value of the stale counter and the value of the local counter of the associated data; determining whether all replacement values ​​of a plurality of associated data in a portion of the system cache are equal to one another; as well as In response to determining that not all of the replacement values ​​for the plurality of associated data in the portion of the system cache are equal to one another, determining whether the replacement value exceeds a staleness threshold is determined, wherein the associated data is determined to be stale in response to determining that the replacement value exceeds the staleness threshold.

12. The computing device of claim 11 , wherein the memory control device is further configured to update the obsolete counter by: receiving a signal from a client of the computing device, the signal configured to indicate whether to update the stale counter; determining whether to update the expiration counter based on the signal; as well as The expiration counter is updated in response to determining to update the expiration counter.

13. The computing device of claim 12, wherein: The signal is a register write command; and The memory control device is further configured to: receiving the signal from the client of the computing device by reading a value from a register set by the client; as well as Determining whether to update the expiration counter based on the signal is performed by determining whether to update the expiration counter based on the value from the register.

14. The computing device of claim 13, further comprising a client configured to set the value at the register according to a time-based criterion.

15. The computing device of claim 13, further comprising a client configured to set the value at the register according to event-based criteria.

16. The computing device of claim 11, wherein the memory control device is further configured to: receiving a memory write command; and Prior to updating the stale counter, the value of the local counter is written to the system cache in association with the location in the system cache for the associated data, wherein the associated data is data for the write memory command.

17. The computing device of claim 11, wherein the memory control device is further configured to: receiving a memory access command; and Writing data of the memory access command to the system cache at a location where the replacement value exceeds the stale threshold, wherein the data of the memory access command written to the system cache is the associated data.

18. The computing device of claim 11, wherein the memory control device is further configured to: receiving a memory write command; invalidating data at locations where the replacement value exceeds the staleness threshold; and Data of the memory write command is written to the system cache at a location having the invalid data, wherein the data of the memory write command written to the system cache is the associated data.

19. The computing device of claim 11, wherein the memory control device is further configured to: receiving a memory write access command; and Responsive to determining that no replacement value exceeds the staleness threshold, writing data of the memory write access command to a location of the system cache that complies with a cache replacement policy different than a criteria-aware cache replacement policy.

20. The computing device of claim 11, wherein the memory control device is further configured to calculate the replacement value as a difference between the value of the stale counter and the value of the local counter.

21. A computing device comprising: A component for updating the expiration counter; means for writing a value of a local counter to a system cache in association with a location in the system cache for associated data, wherein the value of the local counter comprises a value of the stale counter when the associated data is written to the system cache; means for calculating a replacement value using the value of the stale counter and the value of the local counter of the associated data; means for determining whether all replacement values ​​of a plurality of associated data in a portion of the system cache are equal to one another; and means for determining whether the replacement values ​​exceed a staleness threshold in response to determining that not all of the replacement values ​​for the plurality of associated data in the portion of the system cache are equal to one another, wherein the associated data is determined to be stale in response to determining that the replacement values ​​exceed the staleness threshold.

22. The computing device of claim 21, wherein the means for updating the stale counter comprises: means for receiving a signal from a client of the computing device, the signal configured to indicate whether to update the stale counter; means for determining whether to update the expiration counter based on the signal; and Means for updating the expiration counter in response to determining to update the expiration counter.

23. The computing device of claim 22, wherein the signal is a register write command, and wherein: means for receiving the signal from the client of the computing device comprises means for reading a value from a register set by the client; and The means for determining whether to update the staleness counter based on the signal comprises means for determining whether to update the staleness counter based on the value from the register.

24. The computing device of claim 23, further comprising a component for setting the value at the register by the client of the computing device according to time-based criteria or setting the value at the register by the client of the computing device according to event-based criteria.

25. The computing device of claim 21, further comprising means for receiving a memory write command, wherein the means for writing the value of the local counter to the system cache in association with the location in the system cache for the associated data is implemented before updating the stale counter, wherein the associated data is data of the write memory command.

26. The computing device of claim 21, further comprising: means for receiving a memory access command; and Means for writing data of the memory access command to the system cache at a location where the replacement value exceeds the stale threshold, wherein the data of the memory access command written to the system cache is the associated data.

27. The computing device of claim 21, further comprising: A means for receiving a memory write command; means for invalidating data at locations where the replacement value exceeds the staleness threshold; and means for writing data of the memory write command to the system cache at a location having invalid data, wherein the data of the memory write command written to the system cache is the associated data.

28. The computing device of claim 21, further comprising: means for receiving a memory write access command; and Means for writing data of the memory write access command to a location of the system cache that complies with a cache replacement policy different than a criteria-aware cache replacement policy in response to determining that no replacement value exceeds the staleness threshold.

29. The computing device of claim 21, wherein the means for calculating the replacement value using the value of the stale counter and the value of the local counter of the associated data comprises means for calculating a difference between the value of the stale counter and the value of the local counter.

30. A non-transitory processor-readable medium having stored thereon processor-executable instructions configured to cause a processing device to perform operations comprising: Update the expiration counter; writing a value of a local counter to a system cache in association with a location in the system cache for associated data, wherein the value of the local counter includes a value of the stale counter when the associated data was written to the system cache; calculating a replacement value using the value of the stale counter and the value of the local counter of the associated data; determining whether all replacement values ​​of a plurality of associated data in a portion of the system cache are equal to one another; as well as In response to determining that not all of the replacement values ​​for the plurality of associated data in the portion of the system cache are equal to one another, determining whether the replacement value exceeds a staleness threshold is determined, wherein the associated data is determined to be stale in response to determining that the replacement value exceeds the staleness threshold.

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