Instruction Marking Circuit and Processor

Abstract

An embodiment of the present application discloses an instruction marking circuit and a processor. The instruction marking circuit includes: a first instruction detection module, configured to perform instruction detection on an instruction to be processed to obtain a first detection result; the first detection result includes: a first conditional branch instruction in the instruction to be processed whose jump range is within a first range, and a non-jump instruction to be executed when the first conditional branch instruction does not jump; a first instruction marking module, configured to set instruction marks for the first conditional branch instruction and the non-jump instruction in the instruction to be processed according to the first detection result to obtain a target marked instruction; the target marked instruction is used to instruct the instruction execution circuit to execute a jump instruction including the instruction mark when it is determined that the first conditional branch instruction jumps.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of circuit technologies, and in particular, to an instruction marking circuit and a processor. Background Art

[0002] When a processor processes instructions, it usually adopts a pipeline method for instruction processing. When a part of the instructions start to be executed, the predicted subsequent instructions to be executed have been fetched from the instruction register and enter the pipeline. However, when the predicted jump result of a conditional branch instruction is incorrect, the instructions to be executed that enter the pipeline will not be executed. At this time, the processor needs to flush the pipeline and fetch the correct instructions to be executed again; in this way, the processing performance of the processor will decrease. Summary of the Invention

[0003] An embodiment of this application provides an instruction marking circuit, which can reduce the probability of the processor flushing the pipeline again, thereby improving the processing efficiency of the processor.

[0004] The technical solution of this application is implemented as follows:

[0005] An embodiment of this application provides an instruction marking circuit, including:

[0006] A first instruction detection module, configured to perform instruction detection on an instruction to be processed to obtain a first detection result; the first detection result includes: a first conditional branch instruction in the to-be-processed instruction whose jump range is within a first range, and a non-jump instruction to be executed when the first conditional branch instruction does not jump;

[0007] A first instruction marking module, configured to set instruction marks for the first conditional branch instruction and the non-jump instruction in the to-be-processed instruction according to the first detection result to obtain a target marked instruction; the target marked instruction is used to instruct the instruction execution circuit to execute the non-jump instruction including the instruction mark when it is determined that the first conditional branch instruction included jumps.

[0008] An embodiment of this application provides a processor, including:

[0009] The above instruction marking circuit is configured to set instruction marks for the first conditional branch instruction and the non-jump instruction in the to-be-processed instruction to obtain a target marked instruction;

[0010] An instruction execution circuit, configured to execute the target marked instruction according to the jump situation of the first conditional branch instruction and the instruction mark of the target marked instruction.

[0011] An instruction marking circuit and a processor provided by an embodiment of the present application. Since the instruction marking circuit can detect a first conditional branch instruction being processed and executed, by setting an instruction mark for a non-jump instruction to distinguish between a jump instruction and a non-jump instruction; in this way, regardless of whether the first conditional branch instruction jumps subsequently, the correct instruction can be executed according to the instruction mark; thereby reducing the probability of pipeline flushing and improving the processing efficiency of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings herein are incorporated into the specification and form a part of this specification. These drawings illustrate embodiments consistent with the present application and, together with the specification, are used to explain the technical solutions of the present application.

[0013] Figure 1 It is a schematic structural diagram of an optional instruction marking circuit provided by an embodiment of the present application;

[0014] Figure 2 It is a schematic structural diagram of an optional instruction marking circuit provided by an embodiment of the present application;

[0015] Figure 3 It is a schematic structural diagram of an optional instruction marking circuit provided by an embodiment of the present application;

[0016] Figure 4 It is a schematic diagram of an optional first marking instruction for three consecutive clock cycles provided by an embodiment of the present application;

[0017] Figure 5 It is a schematic structural diagram of an optional instruction marking circuit provided by an embodiment of the present application;

[0018] Figure 6 It is a schematic structural diagram of an optional instruction marking circuit provided by an embodiment of the present application;

[0019] Figure 7 It is a schematic structural diagram of an optional instruction marking circuit provided by an embodiment of the present application;

[0020] Figure 8 It is a schematic structural diagram of an optional instruction marking circuit provided by an embodiment of the present application;

[0021] Figure 9 It is a schematic structural diagram of an optional instruction marking circuit provided by an embodiment of the present application;

[0022] Figure 10 It is a schematic structural diagram of an optional instruction marking circuit provided by an embodiment of the present application;

[0023] Figure 11 It is a schematic structural diagram of an optional processor provided by an embodiment of the present application;

[0024] Figure 12 It is a schematic diagram of a process of an optional instruction marking method provided by an embodiment of the present application. Specific implementation manners

[0025] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be construed as limitations on the present application. All other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present application.

[0026] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0027] In the following description, the terms "first / second / third" are merely used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0029] When a processor processes instructions in a pipeline manner, it generally includes instruction fetching, instruction decoding, instruction execution, instruction memory access, and instruction write-back. In this way, while the processor is executing an instruction, a part of the subsequent instructions to be executed has already been fetched from the memory, and a part of them has already started to be decoded. Since the instructions to be executed after a conditional branch instruction will be different depending on whether the conditional branch instruction jumps or not, when the processor needs to process a conditional branch instruction, it usually needs to first predict whether the conditional branch instruction jumps; according to the prediction result, the instructions matching the prediction result are fetched from the memory as the instructions to be executed. In this way, in the case where the prediction result of the conditional branch instruction is incorrect, the instructions to be executed fetched from the memory include instructions that do not need to be executed. The processor needs to flush the pipeline and re-fetch the correct instructions to be executed from the memory, thereby affecting the processing efficiency of the processor and resulting in performance degradation.

[0030] Based on this, an instruction marking circuit is provided in an embodiment of the present application, which can mark the instructions to be executed after a conditional branch instruction, enabling the processor to execute the instructions with a mark matching the jump direction of the conditional branch instruction, reducing the probability of the processor flushing the pipeline, and thus improving the processing efficiency of the processor. The instruction marking circuit provided in the embodiment of the present application can be set in any electronic device including a processor, such as a server, a laptop computer, a tablet computer, a desktop computer, a smart TV, a mobile device (such as a mobile phone, a portable video player, a personal digital assistant, a dedicated messaging device, a portable gaming device), etc., which require the processor to execute instructions.

[0031] Figure 1 Fig. shows a structure of an optional instruction marking circuit, as Figure 1 shown. The circuit includes: a first instruction detection module 10, configured to perform instruction detection on the instruction to be processed to obtain a first detection result; the first detection result includes: a first conditional branch instruction in the instruction to be processed whose jump range is within a first range, and a non-jump instruction to be executed when the first conditional branch instruction does not jump; a first instruction marking module 20, configured to set instruction marks for the first conditional branch instruction and the non-jump instruction in the instruction to be processed according to the first detection result to obtain a target marked instruction; the target marked instruction is used to instruct the instruction execution circuit to execute the jump instruction including the mark when it is determined that the first conditional branch instruction jumps.

[0032] In the embodiment of the present application, the instruction to be processed includes a first conditional branch instruction, a jump instruction to be executed when the first conditional branch instruction jumps, and a non-jump instruction to be executed when it does not jump. Here, the first instruction detection module 10 can read the instruction to be processed from the instruction memory in real time, or read the instruction to be processed every reading time interval, or read the instruction to be processed in batches according to the read data volume, or read the instruction to be processed in batches according to the number of read instructions; the reading time interval, the read data volume, and the number of read instructions can be set as needed, and the embodiment of the present application does not limit them.

[0033] In the embodiment of the present application, after obtaining the instruction to be processed, the first instruction detection module 10 can perform instruction detection on the instruction to be processed to obtain instruction information; determine the first detection result according to the instruction information. The instruction information includes: whether the instruction to be processed is a conditional branch instruction, the jump range, etc.; thus, the first instruction detection module 10 can determine its jump direction and the target instruction to jump according to the jump range of the conditional branch instruction. When the jump direction is forward, that is, the target instruction is after the conditional branch instruction and the jump range is within the first range, the conditional branch instruction can be determined as the first conditional branch instruction.

[0034] In some embodiments, the instructions to be processed include multiple beats, and the number of instructions to be processed per beat is the same. The first range may represent the current beat range, may also represent the range of two consecutive beats, or may also represent a preset number of instructions, etc. This can be set according to actual needs, and the embodiments of the present application do not limit this.

[0035] Exemplarily, the first range is 10; if the second instruction to be processed is a conditional branch instruction and the jump range is 5, then the second instruction to be processed is the first conditional branch instruction. If the second instruction to be processed is a conditional branch instruction and the jump range is 12, then the second instruction to be processed is not the first conditional branch instruction.

[0036] In the embodiments of the present application, the instruction code of the instructions to be processed generally includes: a main opcode, a function code, a source operand register 1, a source operand register 2, and a jump range. Among them, the function code is used to represent the type of the instruction code, and the conditional branch instruction is one of the types. The number of bits of the function code can be 3 bits, that is, the funct3 field, and the number of bits of the function code can also be 7 bits, that is, the funct7 field, etc. This can be set according to needs, and the embodiments of the present application do not limit this. The comparison result of the values of the source operand register 1 and the source operand register 2 determines whether the conditional branch instruction jumps.

[0037] In the embodiments of the present application, the first instruction detection module 10 can detect the main opcode, function code, and jump range of the instructions to be processed, and determine the first conditional branch instruction from the instructions to be processed. The first instruction detection module 10 can determine it as the first conditional branch instruction when the main opcode and the function code represent that the instruction to be processed is a conditional branch instruction and the jump range is within the first range.

[0038] In the embodiments of the present application, when the first instruction detection module 10 determines that the instruction to be processed is the first conditional branch instruction according to the jump range, it also determines the first instruction of the jump instruction and the non-jump instruction. Among them, the non-jump instruction is the instruction within the jump range of the first conditional branch instruction, and the non-jump instruction includes: the next instruction after the first conditional branch instruction to the instruction before the jump instruction; the first instruction of the jump instruction is the target instruction indicated by the jump range in the instruction code.

[0039] In the embodiments of the present application, the first instruction marking module 20 can set an instruction mark for the instructions to be processed that need to be marked; among them, the instructions to be processed that need to be marked include the first conditional branch instruction and the non-jump instruction. The instruction mark of the first conditional branch instruction is a branch mark, and the instruction mark of the non-jump instruction is a non-jump mark.

[0040] Exemplarily, the fifth instruction to be processed in the current shot is the first conditional branch instruction, the jump range is 2, the non-jump instruction is the sixth instruction to be processed, and the first jump instruction is the seventh instruction to be processed. The fifth instruction to be processed in the current shot is the first conditional branch instruction, the jump range is 3, the non-jump instruction is the sixth to seventh instructions to be processed, and the first jump instruction is the eighth instruction to be processed.

[0041] In an embodiment of the present application, the instruction tags of the first conditional branch instruction and the non-jump instruction may be the same or different; in this regard, they may be set as needed, and the embodiment of the present application does not impose any limitation.

[0042] In some embodiments, each pending instruction is provided with a tag code having a number of tag bits. Here, the number of tag bits can be set according to actual needs, and the embodiments of the present application are not limited thereto. In some embodiments, different tag codes can represent different tags; for example, the number of tag bits is 2, tag code 00 is a branch tag, and tag code 11 is a no-jump tag. In some embodiments, the number of tag bits is 1; each instruction type of each pending instruction can have its own tag code, 0 means that the instruction tag is not set, and 1 means that the instruction tag is set. Exemplarily, the tag code of the branch tag of 5 pending instructions is 00010, indicating that the 4th pending instruction is set with an instruction tag.

[0043] In some embodiments, the instruction code may further include a marking code, and the first instruction marking module 20 may mark a no-jump instruction by setting the marking code; illustratively, the marking code may be 1 bit, where 1 represents a no-jump mark.

[0044] It should be noted that the instruction flag can be set according to actual needs and is not limited in the embodiments of the present application.

[0045] In the embodiment of the present application, after the instruction to be processed is marked by the instruction marking circuit, when entering the instruction execution circuit, the instruction execution circuit can execute the instruction after the first conditional branch instruction according to the mark. When the first conditional branch instruction determines that a jump occurs, an instruction without an instruction mark is executed, that is, a jump instruction; when the first conditional branch instruction determines that no jump occurs, an instruction with an instruction mark is executed, that is, a non-jump instruction.

[0046] It can be understood that the instruction marking circuit can detect the first conditional branch instruction to be processed and executed, and distinguish jump instructions from non-jump instructions by setting an instruction mark for non-jump instructions; in this way, regardless of whether the first conditional branch instruction jumps subsequently, the correct instruction can be executed according to the instruction mark; thereby reducing the probability of pipeline re-flush and improving the processing efficiency of the processor.

[0047] In some embodiments of the present application, the instruction to be processed includes multiple beats; the number of instructions within the first range is less than or equal to the total number of instructions in the current beat; based on Figure 1 , Figure 2 shows the structure of an instruction marking circuit. As shown in Figure 2 , the instruction marking circuit further includes: a marking record module 30, configured to determine the number of non-jump instructions of the first conditional branch instruction in the next beat according to the number of non-jump instructions and the jump range of the last instruction group, and use it as the remaining unmarked number in the current beat; one instruction group corresponds to one first conditional branch instruction; and, send the remaining unmarked number of the previous beat to the first instruction marking module; the first instruction marking module 20 is further configured to set instruction marks for the earliest remaining number of instructions in the instruction to be processed in the current beat, and the remaining number is the remaining unmarked number of the previous beat; and, set instruction marks for the first conditional branch instruction and the corresponding non-jump instructions in the instruction to be processed in the current beat, to obtain the first marked instruction in the current beat; use the first marked instruction in the current beat as the target marked instruction in the current beat.

[0048] In the embodiments of the present application, each beat corresponds to one clock cycle. The first instruction detection module 10 and the first instruction marking module 20 can process one beat of instructions to be processed in each clock cycle. In this way, the first conditional branch instruction and the corresponding non-jump instructions can be instructions in the same beat or instructions in different beats.

[0049] In the embodiments of the present application, the number of instructions within the first range is less than or equal to the total number of instructions in the current beat, indicating that when the first conditional branch instruction determines a jump, the target instruction may be in the instructions to be processed in the current beat and the next beat.

[0050] Exemplarily, the first instruction detection module 10 reads 10 instructions to be processed in one beat, the first range is 10, and the 5th instruction in the instructions to be processed in the current beat is the first conditional branch instruction; if its jump range is 4, it means that when it jumps, it will jump to the 9th instruction in the current beat; if its jump range is 8, it means that when it jumps, it will jump to the 3rd instruction in the next beat.

[0051] In the embodiments of the present application, the instructions to be processed in each beat can be grouped according to the first conditional branch instruction to obtain at least one instruction group; one instruction group corresponds to one first conditional branch instruction.

[0052] Exemplarily, there are 10 instructions to be processed in the current beat; among them, the 1st instruction is the first conditional branch instruction, and the 2nd - 3rd instructions are the non-jump instructions of the 1st instruction; the 6th instruction is the first conditional branch instruction, and the 7th - 9th instructions are the non-jump instructions of the 6th instruction; thus, the 1st - 3rd instructions form one instruction group; the 6th - 8th instructions form one instruction group.

[0053] In an embodiment of the present application, if the non-jump instruction of the first conditional branch instruction in the to-be-processed instruction to be taken also includes the to-be-processed instruction of the next beat, the first conditional branch instruction generally belongs to the last instruction group of the current beat. The first instruction detection module 10 may determine the number of non-jump instructions of the first conditional branch instruction according to the jump range of the first conditional branch instruction in the last instruction group; use the difference between the number of non-jump instructions of the first conditional branch instruction and the number of non-jump instructions of the first conditional branch instruction in the current beat as the non-jump instruction of the first conditional branch instruction in the next beat, obtain the remaining unmarked quantity of the current beat, and send the remaining unmarked quantity of the current beat to the mark recording module 30.

[0054] While receiving the remaining unmarked quantity of the current beat, the mark recording module 30 may send the remaining unmarked quantity of the previous beat to the first instruction marking module 20. The first instruction marking module 20 may set instruction marks for the first conditional branch instruction and the non-jump instructions of the current beat according to the first detection result of the current beat; and set instruction marks for the first remaining quantity of instructions that are the earliest in the to-be-processed instructions of the current beat, obtain the first marked instruction of the current beat, and use the first marked instruction as the target marked instruction.

[0055] Exemplarily, there are 10 to-be-processed instructions in each beat of to-be-processed instructions. The first instruction detection module 10 detects that the 5th instruction in the to-be-processed instructions of the 1st beat is the first conditional branch instruction, and the jump range is 8; the non-jump instructions of the first conditional branch instruction include: the 6th - 10th instructions of the 1st beat and the 1st - 3rd instructions of the 2nd beat. The first instruction marking module 20 will set instruction marks for the 5th - 10th instructions in the to-be-processed instructions of the 1st beat. The mark recording module 30 obtains the remaining unmarked quantity 3 of the 1st beat from the first instruction detection module 10 and saves it. Then, the first instruction detection module 10 receives the to-be-processed instructions of the 2nd beat and determines that the 8th instruction in the to-be-processed instructions of the 2nd beat is the first conditional branch instruction, and the jump range is 3. The non-jump instructions of the first conditional branch instruction include: the 9th - 10th instructions of the 2nd beat and the 1st instruction of the 3rd beat. At this time, the remaining unmarked quantity of the 2nd beat is 1. The mark recording module 30 obtains the remaining unmarked quantity 1 of the 2nd beat from the first instruction detection module 10 and saves it, and sends the remaining unmarked quantity 3 of the 1st beat to the first instruction marking module 20. In this way, in addition to setting instruction marks for the 8th - 10th instructions of the 2nd beat, the first instruction marking module 20 will also set instruction marks for the 1st - 3rd instructions of the 2nd beat, and obtain the first marked instruction of the 2nd beat.

[0056] It can be understood that the remaining unmarked quantity of the current beat is recorded by the marking record module 30, and when the remaining unmarked quantity of the next beat arrives, the remaining unmarked quantity of the current beat is informed to the first instruction marking module 20; in this way, the first instruction marking module 20 can continue to complete the setting of the non-jump instruction mark for the first conditional branch mark of the current beat in the instructions to be processed in the next beat, which can improve the accuracy of the instruction mark in the target mark instruction, thereby improving the processing performance of the processor.

[0057] Based on Figure 2 , Figure 3 shows the structure of an instruction marking circuit, as Figure 3 shown, the instruction marking circuit further includes: a second instruction detection module 40, configured to perform pointer jump detection on the instructions to be processed in the current beat to determine the pointer jump instructions in the current beat; the first instruction marking module 20 is further configured to set instruction marks for the first remaining number of instructions in the instructions to be processed in the current beat and the instructions in other instruction groups except the last instruction group, to obtain the first marking instructions in the current beat; update the remaining unmarked quantity in the current beat to 0; the remaining unmarked quantity represents the number of non-jump instructions of the last first conditional branch instruction in the next beat.

[0058] In the embodiments of the present application, the second instruction detection module 40 can detect pointer jump instructions according to the instruction codes of the instructions to be processed in the current beat; the pointer jump instructions indicate that the pointer of the instruction does not point to the next instruction of the instruction, and the pointer jump instructions may include: conditional branch instructions and unconditional jump instructions. In the case where the non-jump instruction is a pointer jump instruction, the non-jump instruction may not be executed normally; thus, the non-jump instruction cannot be used as an instruction to be executed; thus, the first instruction marking module 20 can determine the mark validity of the instruction group to be invalid in the case where any non-jump instruction in the instruction group is a pointer jump instruction, and determine the mark validity of the instruction group to be valid in the case where all non-jump instructions in the instruction group are not pointer jump instructions.

[0059] In the embodiments of the present application, in the case where the remaining unmarked quantity in the current beat is greater than 0, the non-jump instructions of the last first conditional branch instruction in the current beat further include the instructions to be processed in the next beat; at this time, if any non-jump instruction in the last instruction group in the current beat is a pointer jump instruction, it indicates that the mark validity of the last instruction group in the current beat and the first instruction group in the next beat is invalid. The first instruction marking module 20 may further not set instruction marks for the last instruction group in the current beat and update the remaining unmarked quantity in the current beat to 0; since the first instruction group in the next beat is the non-jump instruction of the last first conditional branch instruction in the current beat, in the case where the remaining unmarked quantity in the current beat is updated to 0, the first instruction group in the next beat will not be marked.

[0060] Exemplarily, Figure 4 the first marking instruction for three consecutive beats is shown, such as Figure 4 shown. Each beat instruction includes 4 instructions. The first instruction in the first beat is the first conditional branch instruction Sfb, the second instruction is the non-jump instruction sfb_shadow of the first instruction, the third instruction is the first conditional branch instruction Sfb, and the non-jump instruction sfb_shadow of the third instruction is the fourth instruction of the first beat and the fifth to sixth instructions of the second beat. At this time, it can be determined that the remaining unmarked quantity of the current beat is 2. For the instructions of the first beat, the first to second instructions form an instruction group, and the third to fourth instructions form an instruction group; the second instruction marking module 50 can set instruction marks for the first to second instructions; and, in the case where the fourth instruction is a pointer jump instruction, the second instruction marking module 50 can not set instruction marks for the third to fourth instructions and update the remaining unmarked quantity of the current beat to 0; thus, when the second instruction marking module 50 processes the instructions of the second beat, it will not set instruction marks for the fifth to sixth instructions either.

[0061] It can be understood that since the second instruction detection module 40 can detect pointer jump instructions, the first instruction marking module 20 can not set instruction marks for the last instruction group of the current beat and the first instruction group of the next beat when the non-jump instruction of the last first conditional branch instruction of the current beat includes the instruction to be processed in the next beat and the non-jump instruction in the last instruction group of the current beat includes a pointer jump instruction. In this way, the accuracy of the instruction marks in the target marking instruction can be improved.

[0062] Based on Figure 3 , Figure 5 a structure of an instruction marking circuit is shown, such as Figure 5 shown. The instruction marking circuit further includes: a second instruction marking module 50, configured to detect the marking validity of each instruction group of the current beat according to the pointer jump instruction and the non-jump instruction of the current beat; a marking deletion module 60, configured to determine the invalid marking group in the first marking instruction of the current beat according to the marking validity of each instruction group of the current beat; delete the instruction marks of the invalid marking group to obtain the second marking instruction of the current beat; and use the second marking instruction of the current beat as the target marking instruction.

[0063] In the embodiment of the present application, when any non-jump instruction in the instruction group is a pointer jump instruction, the second instruction marking module 50 may determine the marking validity of the instruction group as invalid. When all non-jump instructions in the instruction group are not pointer jump instructions, the marking validity of the instruction group is determined to be valid. After determining the marking validity of each instruction group in the current cycle, the second instruction marking module 50 may send the marking validity to the marking deletion module 60. The marking deletion module 60 may determine the instruction group with invalid marking validity as an invalid marking group according to the instruction marking validity in the current cycle; delete the instruction markings of the invalid marking group, and determine the obtained second marking instruction in the current cycle as the target marking instruction.

[0064] Exemplarily, there are 10 first marking instructions in the current cycle; among them, the 2nd to 6th instructions are an instruction group, the 2nd instruction is the first conditional branch instruction, and the 3rd to 6th instructions are non-jump instructions of the 2nd instruction. The second marking detection module 40 determines that the 5th instruction is a pointer operation instruction, and the second instruction marking module 50 may determine that the instruction group to which the 2nd to 6th instructions belong is an invalid marking group, and delete the instruction markings of the 2nd to 6th instructions.

[0065] It can be understood that since the second instruction marking module 50 can detect the marking validity of the first marking instruction in the current cycle, the marking deletion module 60 can delete the invalid instruction markings in the first marking instruction in the current cycle to obtain the second marking instruction in the current cycle; thus, the accuracy of the instruction markings of the second marking instruction in the current cycle can be improved.

[0066] Based on Figure 5 , Figure 6 shows the structure of an instruction marking circuit, as Figure 6 shown, the instruction marking circuit includes a first-stage circuit 01 and a second-stage circuit 02; the first-stage circuit 01 includes: a first instruction detection module 10, a first instruction marking module 20, a marking recording module 30, a second instruction detection module 40, and a second instruction marking module 50; the second-stage circuit 02 includes a marking deletion module 60; the second instruction marking module 50 is further configured to generate a first indication signal in the current cycle according to the marking validity of each instruction in the current cycle; generate a feedforward signal in the current cycle according to the marking validity of each instruction in the first instruction group in the current cycle; the marking validity of each instruction is the same as the marking validity of the instruction group to which the instruction belongs; and generate a second indication signal in the current cycle according to the remaining unmarked quantity in the current cycle; the marking deletion module 60 is further configured to determine an invalid marking group in the current cycle according to the first indication signal in the current cycle, the feedforward signal in the next cycle, and the second indication signal in the current cycle.

[0067] In the embodiment of the present application, the instruction marking circuit includes two levels and can process two consecutive beats of instructions to be processed. Exemplarily, within one clock cycle, the instructions to be processed in the first beat are subjected to first-level processing in the first-level circuit; when the next clock cycle arrives, the instructions to be processed in the first beat are processed in the first-level circuit and then enter the second-level circuit for second-level processing; meanwhile, the instructions to be processed in the second beat enter the first-level circuit for first-level processing.

[0068] In the embodiment of the present application, the first indication signal is used to represent the marking validity of each instruction in the current beat; the second indication signal is used to represent the remaining unmarked quantity in the current beat. The second instruction marking module 50 can send the first indication signal and the second indication signal of the current beat to the marking deletion module 60 in the next-level circuit when the clock cycle corresponding to the current beat ends and the clock cycle corresponding to the next beat arrives. The feed-forward signal of the current beat is used to indicate the marking validity of each instruction in the last instruction group of the current beat and can be transmitted to the marking deletion module 60 in real time without waiting for the clock cycle.

[0069] It should be noted that when the current remaining unmarked quantity is greater than 0, it indicates that each instruction in the last instruction group of the current beat is not a pointer jump instruction and the marking validity is valid; at this time, whether the last instruction group of the current beat is an invalid marking group needs to be determined in combination with the marking validity of the first instruction group of the next beat.

[0070] In the embodiment of the present application, the marking deletion module 60 can determine the actual validity of each instruction according to the first indication signal of the current beat when the second indication signal of the current beat indicates that the current remaining unmarked quantity is equal to 0; or, when the second indication signal of the current beat indicates that the current remaining unmarked quantity is greater than 0, determine the actual validity of each instruction together according to the first indication signal and the feed-forward signal of the current beat; when the actual validity of the instruction represents that the marking validity is invalid, determine that the instruction group to which the instruction belongs is an invalid marking group.

[0071] Exemplarily, Figure 4In the second beat instruction, the 5th - 6th are an instruction group, and the 7th - 8th instructions are another instruction group. Among them, the 7th is the first conditional branch instruction Sfb, the 8th instruction and the 9th - 10th instructions in the third beat are the non - jump instructions sfb_shadow of the 7th instruction, and the 8th instruction is not a pointer jump instruction; the instruction validity of the last instruction group in the second beat is valid; at this time, the current remaining unmarked quantity is 2; the second instruction marking module 50 needs to combine whether the 9th - 10th instructions in the third beat are pointer jump instructions to determine the actual validity of the instruction marks of the 7th - 8th instructions in the second beat; if any one of the 9th - 10th instructions in the third beat is a pointer jump instruction, it is determined that the actual validity of the instruction marks of the 7th - 8th instructions in the second beat is invalid; if there is no pointer jump instruction among the 9th - 10th instructions in the third beat, the actual validity of the instruction marks of the 7th - 8th instructions in the second beat is valid.

[0072] It can be understood that since the instruction marking circuit includes two - stage circuits, and the marking deletion module 60 is arranged in the next - stage circuit of the second instruction marking module 50, the marking deletion module 60 can obtain the first indication signal of the current beat, the second indication signal of the current beat, and the feed - forward signal of the next beat when processing the first marking instruction of the current beat; in this way, the marking deletion module 60 can flexibly determine the invalid marking group and improve the accuracy of the invalid marking group.

[0073] In some embodiments of the present application, the second instruction marking module 50 is further configured to determine that the first indication signal of the instruction is the first signal when the marking validity of the instruction is valid; determine that the first indication signal of the instruction is the second signal when the marking validity of the instruction is invalid; the first signal and the second signal are inverse signals; when the marking validity of the first instruction group is valid, determine that the feed - forward signal of each instruction in the first instruction group is the first signal, and the feed - forward signals of other instructions are the second signal; or, when the marking validity of the first instruction group is invalid, determine that the feed - forward signal of each instruction is the second signal; when the remaining unmarked quantity of the current beat is equal to 0, determine that the second indication signal of each instruction of the current beat is the first signal; or, when the remaining unmarked quantity of the current beat is greater than 0, determine that the second indication signal of each instruction of the last instruction group of the current beat is the second signal, and the second indication signals of other instructions except the last instruction group of the current beat are the first signal.

[0074] In the embodiments of the present application, when the marking validity of the instruction is valid, the first indication signal and the feed - forward signal of the instruction are both the first signal; when the marking validity of the instruction is invalid, the first indication signal and the feed - forward signal of the instruction are the second signal.

[0075] In the embodiments of the present application, when the remaining unmarked quantity of the current beat is equal to 0, the marking validity of each instruction group of the current beat is the actual validity of the instruction marks of each instruction group, and the actual validity can be confirmed at the current beat, without using the marking validity of the first instruction group of the next beat to determine the actual validity of the instruction marks of the last instruction group of the current beat; that is to say, the marking validity of each instruction of the current beat is determined, and at this time, the second indication signal of each instruction is the first signal. When the remaining unmarked quantity of the current beat is greater than 0, the marking validity of the last instruction group of the current beat is valid, but when the marking validity of the first instruction group of the next beat is invalid, the actual validity of the instruction marks of the last instruction group of the current beat is invalid; when the marking validity of the first instruction group of the next beat is also valid, the actual validity of the instruction marks of the last instruction group of the current beat can remain valid; that is to say, when the remaining unmarked quantity of the current beat is greater than 0, the marking validity of the last instruction group of the current beat is uncertain, and the second indication signal of each instruction in the last instruction group is the second signal.

[0076] In some embodiments, the first signal is a low-level signal and the second signal is a high-level signal; in some embodiments, the first signal is a high-level signal and the second signal is a low-level signal. In this regard, it can be set as needed, and the embodiments of the present application do not make limitations.

[0077] It can be understood that among the first indication signal and the feedforward signal, the corresponding signals of valid and invalid are inverse signals; among the second indication signals, the signals corresponding to the determination and uncertainty of validity are also inverse signals; thus, it is convenient for the marking deletion module 60 to identify the first indication signal, the feedforward signal, and the second indication signal, perform logical processing on the first indication signal, the feedforward signal, and the second indication signal, and improve the efficiency of the marking deletion module 60 to determine the invalid mark group.

[0078] In some embodiments of the present application, the first signal is a low-level signal; the second signal is a high-level signal; the marking deletion module 60 is further configured to, when the remaining unmarked quantity of the current beat is equal to 0, perform an AND operation on the first indication signal of the current beat and the inverse signal of the second indication signal of the current beat to obtain the valid indication signal of the current beat; determine the instruction group to which the instruction corresponding to the low-level signal in the valid indication signal belongs as the invalid mark group of the current beat.

[0079] In an embodiment of the present application, when the remaining unmarked quantity of the current beat is equal to 0, the marking validity of the instructions of the current beat is determined, and it is not necessary to judge in combination with the marking validity of the first group of instructions of the next beat. Therefore, the second indication signal of each instruction is at a low level. Performing an AND operation on the first indication signal of the current beat and the inverted signal of the second indication signal of the current beat still results in the first indication signal of the current beat. The marking deletion module 60 may determine the instruction group to which the instruction corresponding to the low-level signal in the first indication signal of the current beat belongs as the invalid marking group.

[0080] Exemplarily, Figure 4 The instruction marks of the first beat in [the example] are 1100, indicating that the instruction group composed of the 3rd - 4th instructions is the invalid marking group, so the setting instruction marks of the 3rd - 4th instructions are not set. Since the 3rd - 4th instructions themselves have no instruction marks, the result of deleting the instruction marks of the 3rd - 4th instructions is still that the 3rd - 4th instructions have no marks. Thus, the execution mark of the target marked instruction is still 1100.

[0081] It can be understood that when the remaining unmarked quantity of the current beat is 0, the marking deletion module 60 can perform a logical operation on the first indication signal of the current beat and the second indication signal of the current beat, and the obtained valid indication signal is the indication signal of the current beat; enabling the marking deletion module 60 to quickly implement the function of directly using the marking validity of the instruction mark of each instruction of the current beat as the actual validity when the remaining unmarked quantity of the current beat is 0, and improving the efficiency of determining the invalid marking group.

[0082] In some embodiments of the present application, the first signal is at a low level; the second signal is at a high level; the marking deletion module 60 is further configured to perform an OR operation on the first indication signal of the current beat and the feedforward signal of the next beat to obtain the OR processing signal of the current beat; perform an AND operation on the inverted signal of the OR processing signal of the current beat and the inverted signal of the second indication signal of the current beat to obtain the valid indication signal of the current beat; and determine the instruction group to which the instruction corresponding to the low-level signal in the valid indication signal belongs as the invalid marking group of the current beat.

[0083] In an embodiment of the present application, when the remaining unmarked quantity of the current beat is greater than 0, the marking validity of the last instruction group in the instructions of the current beat is uncertain and needs to be judged in combination with the marking validity of the first group of instructions of the next beat; while the marking validity of other instruction groups is determined. Therefore, the second indication signal of each instruction in the last instruction group of the current beat is at a high level, and the second indication signal of each instruction in other instruction groups is at a low level.

[0084] Exemplarily, Figure 4Among them, the instruction marker of the second beat is marked as 0011. In the 7th - 8th items, the 8th item is not a pointer jump instruction, that is, the marker validity of the 7th - 8th items of the second beat is valid. At this time, the first indication signal of the second beat is 0000. Since the remaining unmarked quantity of the second beat is 2, that is, the actual validity of the instruction markers of the 7th - 8th items still needs to be determined in combination with the marker validity of the 9th - 10th items of the third beat. Therefore, the second indication signal of the second beat is 0011. When the 9th - 10th items of the third beat include pointer jump instructions, the feed - forward signal of the third beat is 1100; thus, the marker deletion module 60 can obtain or process the signal as 1100, perform an AND operation on the inverse signal of the OR processing and the inverse signal of the second indication signal, and obtain a valid indication signal of 0000; that is to say, it is necessary to delete the instruction markers of the 5th - 8th items. Therefore, there are no instruction markers in the target marker instructions of the second beat.

[0085] It can be understood that when the remaining marked quantity of the current beat is greater than 0, the marker deletion module 60 can perform logical operations through the first indication signal, the feed - forward signal, and the second indication signal of the current beat to obtain a valid indication signal; enabling the marker deletion module 60 to quickly determine the invalid marker group when the remaining marked quantity of the current beat is greater than 0.

[0086] In some embodiments of the present application, multiple beats include empty beats; the number of instructions to be processed in the empty beat is 0; when the current beat is an empty beat, the instruction to be processed in the current beat is still the instruction to be processed in the previous beat. Based on Figure 6 , Figure 7 shows the structure of an instruction marker circuit, as Figure 7 shown, the second - stage circuit 02 further includes: a pause indication module 70, configured to feed - forward a pause working signal to the second instruction marker module; the pause working signal is used to indicate that the second instruction marker module pauses working for one beat.

[0087] In the embodiments of the present application, when the number of to-be-processed instructions in the current cycle obtained in the first-level circuit 01 is 0, it indicates that the current cycle is an idle cycle. Since the first-level circuit 01 updates data in each cycle, the idle cycle will cause the data in each module in the first-level circuit 01 to be updated to incorrect data. When the first-level circuit 01 processes an idle cycle, the current cycle of the pause indication module 70 is the previous cycle of the first-level circuit 01; the pause indication module 70 can feed forward a pause working signal to the second instruction marking module 50 when the current cycle is an idle cycle, so that the second instruction marking module 50 pauses working for one cycle when processing the idle cycle, and resumes working when the next cycle of the first-level circuit 01 is not idle cycle data. In this way, the probability of the marking deletion module 60 processing errors caused by the first indication signal, the feed-forward signal, and the second indication signal sent by the second instruction marking module 50 according to incorrect data can be reduced, thereby improving the accuracy of the instruction marking in the target marking instruction.

[0088] In some embodiments of the present application, the pause indication module 70 is further configured to obtain the remaining unmarked quantity of the previous cycle from the marking record module; when the current cycle is an idle cycle, send the remaining marked data of the previous cycle to the second instruction marking module; the second instruction marking module 50 is further configured to set instruction marks for the earliest remaining quantity of instructions in the to-be-processed instructions of the next cycle; and use the obtained third marking instruction of the current cycle as the marking completion instruction.

[0089] In the embodiments of the present application, when there is a remaining unmarked quantity in the previous cycle of the second-level circuit 02 and marking needs to be performed in the current cycle, if the current cycle is an idle cycle, the remaining unmarked quantity of the previous cycle recorded by the marking record module 30 is still transmitted to the first marking module 20. In this way, the first marking module 20 cannot utilize the remaining unmarked quantity of the previous cycle. Moreover, the remaining unmarked quantity of the previous cycle in the marking record module 30 will also change due to the idle cycle, resulting in errors. Therefore, when the next cycle arrives in the first-level circuit 01, the remaining unmarked quantity of the current cycle needs to be transmitted to the pause indication module 70 in the second-level circuit 02. In this way, when the current cycle of the first-level circuit 01 is an idle cycle, the second instruction marking module 50 can receive a pause working signal from the pause indication module 70, and the remaining unmarked quantity of the previous cycle is carried therein; thus, when the first-level circuit 01 processes the to-be-processed instructions of the next cycle, the second instruction marking module 50 can use the received remaining unmarked quantity to perform marking on the to-be-processed instructions of the next cycle, so that the marking that the first instruction marking module 20 fails to complete is completed by the second instruction marking module 50, and a third marking instruction is obtained. The second instruction marking module 50 uses the third marking instruction of the current cycle as the marking completion instruction of the current cycle, and then sends the first indication signal of the current cycle, the feed-forward signal of the current cycle, and the second indication signal of the current cycle to the marking deletion circuit 70.

[0090] It can be understood that when multiple beats include empty beats, the first instruction marking module may not be able to complete the marking in the current beat according to the remaining unmarked quantity; at this time, by feeding forward the remaining unmarked quantity of the previous beat to the second instruction marking module 50 through the pause indication module 70, the second instruction marking module 70 can continue to mark according to the remaining unmarked quantity in the next beat after the end of the empty beat, which can improve the accuracy of the instruction marking of the marking completion instruction.

[0091] Based on Figure 7 , Figure 8 shows the structure of an instruction marking circuit, as Figure 8 shown, the first-stage circuit 01 further includes: an empty beat judgment module 80, configured to judge whether the number of instructions to be processed in the current beat is 0, and obtain an empty beat judgment result; a pause indication module 70, further configured to, when the empty beat judgment result indicates that the current beat is an empty beat, send the remaining unmarked quantity of the current beat to the second marking record module.

[0092] In the embodiment of the present application, the empty beat judgment module 80 can judge whether the number of instructions to be processed in the current beat is 0, and obtain an empty beat judgment result. The empty beat judgment result includes a first result and a second result. The first result is that the number of instructions to be processed is 0, indicating that the current beat is an empty beat. The second result is that the number of instructions to be processed is greater than 0, indicating that the current beat is not an empty beat.

[0093] In the embodiment of the present application, the empty beat judgment module 80 can send the empty beat judgment result to the pause indication module 70 when the first-stage circuit 01 finishes processing. The pause indication module 70 feeds forward a pause working signal to the second marking record module 50 when determining that the empty beat judgment result is the first result.

[0094] It can be understood that since the empty beat judgment module 80 can indicate the two empty beat judgment results of the current beat to the pause indication module 70, in this way, the method for the pause indication module 70 to determine whether the current beat is an empty beat can be simplified, and the efficiency of the pause indication module 70 to determine the empty beat judgment result can be improved.

[0095] Based on Figure 8 , Figure 9 shows the structure of an instruction marking circuit, as Figure 9 shown, the first-stage circuit 01 further includes: a remaining marking judgment module 90, configured to obtain the remaining unmarked quantity of the previous beat from the marking record module 30; judge whether the remaining unmarked quantity of the previous beat is greater than 0, and obtain a remaining quantity judgment result; a pause indication module 70, further configured to, when the remaining quantity judgment result indicates that the remaining unmarked quantity of the previous beat is greater than 0 and the empty beat judgment result indicates that the number of instructions to be processed in the current beat is 0, carry the remaining unmarked quantity of the previous beat in the pause working signal.

[0096] In an embodiment of the present application, the remaining tag determination module 90 may obtain the remaining unmarked quantity of the previous beat from the tag recording module 30, determine whether the remaining unmarked quantity of the previous beat is greater than 0, and obtain a remaining quantity determination result. The remaining quantity determination result includes a third result and a fourth result. The third result is that the remaining unmarked quantity of the previous beat is 0, indicating that the current beat of the first-stage circuit 01 does not need to set instruction tags using the remaining unmarked quantity of the previous beat. The fourth result is that the remaining unmarked quantity of the previous beat is greater than 0, indicating that the current beat of the first-stage circuit 01 needs to set instruction tags using the remaining unmarked quantity of the previous beat.

[0097] In an embodiment of the present application, when the first-stage circuit 01 finishes processing, the remaining tag determination module 90 may send the remaining tag determination result to the pause indication module 70. When the pause indication module 70 determines that the empty beat determination result is the first result and its remaining tag determination result is the fourth result, it carries the remaining unmarked quantity of the previous beat in the pause work signal.

[0098] It can be understood that since the remaining tag determination module 90 can indicate two remaining tag determination results of the current beat to the pause indication module 70; in this way, the method for the pause indication module 70 to determine whether to send the remaining unmarked quantity of the previous beat to the second instruction tagging module 50 can be simplified, thereby improving the processing efficiency of the pause indication module 70.

[0099] Based on Figure 9 , Figure 10 shows the structure of an instruction tagging circuit, as Figure 10 shown, the instruction tagging circuit may further include: an instruction acquisition module 00, configured to acquire the to-be-processed instruction of the current beat from the instruction register; and when sending the to-be-processed instruction of the current beat to the first instruction tagging module, acquire the to-be-processed instruction of the next beat from the instruction register.

[0100] In an embodiment of the present application, the instruction tagging circuit includes three levels, and the instruction acquisition module 00 may be the previous level of the first-stage circuit 01. In this way, the instruction acquisition module 00 can acquire one beat of instructions from the instruction register in each clock cycle, and when the next clock cycle comes, send the acquired one beat of instructions to the first-stage circuit 01; at the same time, acquire the to-be-processed instruction of the next beat from the instruction register.

[0101] In an embodiment of the present application, the instruction acquisition module 00 may send the to-be-processed instruction of the current beat to the first-stage circuit 01 when the number of to-be-processed instructions of the current beat is equal to a preset quantity; in this way, the number of to-be-processed instructions per beat can be made the same, which is convenient for the instruction tagging circuit to set instruction tags for each beat of to-be-processed instructions.

[0102] Based on the above embodiments, an embodiment of the present application further provides a processor 0, asFigure 11 As shown in the figure, the processor 0 includes: the above-mentioned instruction marking circuit 1 and instruction execution circuit 2. Among them, the instruction marking circuit 1 is used to set instruction marks for the first conditional branch instruction and non-jump instruction in the instruction to be processed, so as to obtain a target marked instruction; the instruction execution circuit 2 is used to execute the target marked instruction according to the jump situation of the first conditional branch instruction and the instruction mark of the target marked instruction.

[0103] Based on the above-mentioned instruction marking circuit, the embodiment of the present application also provides an instruction marking method, which is applied to the instruction marking circuit, as Figure 12 shown, the method includes: S101-S102.

[0104] S101. Through the first instruction detection module, perform instruction detection on the instruction to be processed to obtain a first detection result; the first detection result includes: the first conditional branch instruction with a jump range within the first range in the instruction to be processed and the non-jump instruction that needs to be executed when the first conditional branch instruction does not jump.

[0105] S102. Through the first instruction marking module, according to the first detection result, set instruction marks for the first conditional branch instruction and non-jump instruction in the instruction to be processed to obtain a target marked instruction; the target marked instruction is used to instruct the instruction execution circuit to execute the jump instruction containing the instruction mark when it is determined that the first conditional branch instruction jumps.

[0106] In some embodiments, the instruction to be processed includes multiple beats; the number of instructions within the first range is less than or equal to the total number of instructions in the current beat; the method further includes: through the mark recording module, according to the number of non-jump instructions in the last instruction group of the current beat and the jump range of the last first conditional branch instruction in the current beat, determine the number of non-jump instructions of the first conditional branch instruction in the next beat as the remaining unmarked number in the current beat; one instruction group corresponds to one first conditional branch instruction; set instruction marks for the first remaining number of instructions in the instruction to be processed in the current beat through the first instruction marking module; the remaining number is the remaining unmarked number in the previous beat; and, set instruction marks for the first conditional branch instruction and the corresponding non-jump instruction in the instruction to be processed in the current beat to obtain the first marked instruction in the current beat; use the first marked instruction in the current beat as the target marked instruction in the current beat.

[0107] In some embodiments, the method further includes: detecting, by a second instruction detection module, pointer jump of the to-be-processed instruction of the current cycle to determine the pointer jump instruction of the current cycle; in a case where the remaining unmarked quantity of the current cycle is greater than 0, detecting the mark validity of the last instruction group of the current cycle according to the pointer jump instruction; when the mark validity of the last instruction group of the current cycle is invalid, setting instruction marks for the most forward remaining quantity of instructions in the to-be-processed instruction of the current cycle and instructions in other instruction groups except the last instruction group by the first instruction marking module to obtain the first marked instruction of the current cycle; and updating the remaining unmarked quantity of the current cycle to 0; the remaining unmarked quantity represents the number of non-jump instructions of the last first conditional branch instruction in the next cycle.

[0108] In some embodiments, the method further includes: using, by a second instruction marking module, the first marked instruction of the current cycle as the marked completed instruction of the current cycle; detecting the mark validity of each instruction group of the current cycle according to the non-jump instructions in the pointer jump instruction of the current cycle and the marked completed instruction of the current cycle; determining, by a mark deletion module, the invalid mark group in the first marked instruction of the current cycle according to the mark validity of each instruction group of the current cycle; deleting the instruction marks of the invalid mark group to obtain the second marked instruction of the current cycle; and using the second marked instruction of the current cycle as the target marked instruction.

[0109] In some embodiments, the circuit includes a first-stage circuit and a second-stage circuit; the first-stage circuit includes: the first instruction detection module, the first instruction marking module, and the second instruction marking module; the second-stage circuit includes the mark deletion module; the method further includes: generating, by the second instruction marking module, a first indication signal of the current cycle according to the mark validity of each instruction of the current cycle; generating a feedforward signal of the current cycle according to the mark validity of each instruction in the first instruction group of the current cycle; the mark validity of each instruction is the same as the mark validity of the instruction group to which the instruction belongs; and generating a second indication signal of the current cycle according to the remaining unmarked quantity of the current cycle; determining, by the mark deletion module, the invalid mark group of the current cycle according to the first indication signal of the current cycle, the feedforward signal of the next cycle, and the second indication signal of the current cycle.

[0110] In some embodiments, the method further includes: through the second instruction marking module, when the marking validity of the instruction is valid, determining that the first indication signal of the instruction is the first signal; when the marking validity of the instruction is invalid, determining that the first indication signal of the instruction is the second signal; the first signal and the second signal are inverse signals; when the marking validity of the first instruction group is valid, determining that the feedforward signal of each instruction in the first instruction group is the first signal, and the feedforward signals of other instructions are the second signals; or, when the marking validity of the first instruction group is invalid, determining that the feedforward signal of each instruction is the second signal; when the remaining unmarked quantity in the current cycle is equal to 0, determining that the second indication signal of each instruction in the current cycle is the first signal; or, when the remaining unmarked quantity in the current cycle is greater than 0, determining that the second indication signal of each instruction in the last instruction group in the current cycle is the second signal, and the second indication signals of other instructions in the current cycle except the last instruction group are the first signals.

[0111] In some embodiments, the first signal is a low-level signal; the second signal is a high-level signal; the method further includes: through the marking deletion module, when the remaining unmarked quantity in the current cycle is equal to 0, performing an AND operation on the first indication signal in the current cycle and the inverse signal of the second indication signal in the current cycle to obtain the valid indication signal in the current cycle; determining the instruction group to which the instruction corresponding to the low-level signal in the valid indication signal belongs as the invalid marking group in the current cycle.

[0112] In some embodiments, the first signal is a low-level signal; the second signal is a high-level signal; the method further includes: through the marking deletion module, performing an OR operation on the first indication signal in the current cycle and the feedforward signal in the next cycle to obtain the OR processing signal in the current cycle; performing an AND operation on the inverse signal of the OR processing signal in the current cycle and the inverse signal of the second indication signal in the current cycle to obtain the valid indication signal in the current cycle; determining the instruction group to which the instruction corresponding to the low-level signal in the valid indication signal belongs as the invalid marking group in the current cycle.

[0113] In some embodiments, the multiple cycles include idle cycles; the number of instructions to be processed in the idle cycle is 0; when the current cycle is the idle cycle, the instructions to be processed in the current cycle are still the instructions to be processed in the previous cycle; the second-level circuit further includes: a pause indication module; the method further includes: through the pause indication module, feeding forward a pause working signal to the second instruction marking module; the pause working signal is used to instruct the second instruction marking module to pause working for one cycle.

[0114] In some embodiments, the method further includes: obtaining, by the pause indication module, the remaining unmarked quantity of the previous beat from the marking record module; when the current beat is an empty beat, carrying the remaining unmarked quantity of the previous beat in the pause working signal; setting, by the second instruction marking module, the instruction marks of the earliest remaining quantity of instructions in the to-be-processed instructions of the next beat as the third marking instructions for indicating completion in the current beat; and using the obtained third marking instructions of the current beat as the marking completion instructions.

[0115] In some embodiments, the first-level circuit further includes an empty beat determination module, and the method further includes: determining, by the empty beat determination module, whether the quantity of the to-be-processed instructions in the current beat is 0 to obtain an empty beat determination result; and feeding forward, by the pause indication module, the pause working signal to the second marking record module when the empty beat determination result indicates that the current beat is an empty beat.

[0116] In some embodiments, the first-level circuit further includes a remaining marking determination module, and the method further includes: obtaining, by the remaining marking determination module, the remaining unmarked quantity of the previous beat from the marking record module; determining whether the remaining unmarked quantity of the previous beat is greater than 0 to obtain a remaining quantity determination result; and carrying, by the pause indication module, the remaining unmarked quantity of the previous beat in the pause working signal when the remaining quantity determination result indicates that the remaining unmarked quantity of the previous beat is greater than 0 and the empty beat determination result indicates that the quantity of the to-be-processed instructions in the current beat is 0.

[0117] It should be noted that for the description of the above instruction marking method, reference can be made to the description in the instruction marking circuit, which will not be elaborated here.

[0118] It should be pointed out here that: the descriptions of the above embodiments tend to emphasize the differences between the embodiments, and their similarities can be referred to each other. The description of the above processor embodiments is similar to the description of the above circuit embodiments and has similar beneficial effects to the circuit embodiments. For the technical details not disclosed in the processors of the present application, please refer to the description of the circuit embodiments of the present application for understanding.

[0119] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the magnitude of the sequence numbers of the above steps / processes does not mean the order of execution, and the order of execution of each step / process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The serial numbers of the embodiments of the present application above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0120] It should be noted that in this text, the term "comprise", "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the existence of additional identical elements in the process, method, article or device including that element.

[0121] In several embodiments provided by the present application, the circuit embodiments described above are only illustrative. For example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation. For example, multiple modules or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the couplings, direct couplings or communication connections between the components shown or discussed with each other can be indirect couplings or communication connections through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0122] The modules described above as separate components may or may not be physically separated; they may be located in one place or distributed to multiple network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0123] In addition, each functional module in the embodiments of the present application can be all integrated in a processing unit, or each unit can be separately used as a unit, or two or more units can be integrated in one unit; the above integrated unit can be implemented in the form of hardware, or in the form of a hardware plus software functional unit.

[0124] As described above, it is only the implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application.

Claims

1. An instruction marking circuit, characterized in that, Comprising: A first instruction detection module, configured to perform instruction detection on a to-be-processed instruction to obtain a first detection result; The first detection result includes: a first conditional branch instruction in the to-be-processed instruction whose jump range is within a first range, and a non-jump instruction to be executed when the first conditional branch instruction does not jump; A first instruction marking module, configured to set instruction marks for the first conditional branch instruction and the non-jump instruction in the to-be-processed instruction according to the first detection result to obtain a target marked instruction; the target marked instruction is used to instruct an instruction execution circuit to execute a jump instruction including the instruction mark when it is determined that the first conditional branch instruction jumps; 2. The circuit according to claim 1, wherein The to-be-processed instruction includes multiple beats; the number of instructions within the first range is less than or equal to the total number of instructions in the current beat; the circuit further includes: A mark recording module, configured to determine, according to the number of non-jump instructions in the last instruction group of the current beat and the jump range of the last first conditional branch instruction in the current beat, the number of non-jump instructions of the first conditional branch instruction in the next beat as the remaining unmarked quantity of the current beat; one instruction group corresponds to one first conditional branch instruction; and send the remaining unmarked quantity of the previous beat to the first instruction marking module; The first instruction marking module is configured to set the instruction marks for the first remaining quantity of the earliest instructions in the to-be-processed instruction of the current beat; the remaining quantity is the remaining unmarked quantity of the previous beat; and set the instruction marks for the first conditional branch instruction and the corresponding non-jump instruction in the to-be-processed instruction of the current beat to obtain a first marked instruction of the current beat; use the first marked instruction of the current beat as the target marked instruction of the current beat.

3. The circuit according to claim 2, wherein The circuit further includes: A second instruction detection module, configured to perform pointer jump detection on the to-be-processed instruction of the current beat to determine the pointer jump instruction of the current beat; The first instruction marking module is further configured to, when the remaining unmarked quantity of the current beat is greater than 0, detect the mark validity of the last instruction group of the current beat according to the pointer jump instruction; when the mark validity of the last instruction group of the current beat is invalid, set the instruction marks for the first remaining quantity of the earliest instructions in the to-be-processed instruction of the current beat and the instructions in other instruction groups except the last instruction group to obtain the first marked instruction of the current beat; and update the remaining unmarked quantity of the current beat to 0; the remaining unmarked quantity represents the number of non-jump instructions of the last first conditional branch instruction in the next beat.

4. The circuit according to any one of claims 2-3, characterized in that, The circuit further includes: A second instruction marking module, configured to use the first marked instruction of the current beat as the marked completed instruction of the current beat; detect the mark validity of each instruction group of the current beat according to the pointer jump instruction of the current beat and the non-jump instructions in the marked completed instruction of the current beat; A tag deletion module is configured to determine an invalid tag group in the first tag instruction of the current cycle according to the tag validity of each instruction group in the current cycle; delete the instruction tags of the invalid tag group to obtain the second tag instruction of the current cycle; and use the second tag instruction of the current cycle as the target tag instruction.

5. The circuit according to claim 4, wherein The circuit includes a first-stage circuit and a second-stage circuit; the first-stage circuit includes: the first instruction detection module, the first instruction tagging module, and the second instruction tagging module; the second-stage circuit includes the tag deletion module; The second instruction tagging module is further configured to generate a first indication signal of the current cycle according to the tag validity of each instruction in the current cycle; generate a feedforward signal of the current cycle according to the tag validity of each instruction in the first instruction group of the current cycle; the tag validity of each instruction is the same as the tag validity of the instruction group to which the instruction belongs; and generate a second indication signal of the current cycle according to the remaining un-tagged quantity in the current cycle; The tag deletion module is further configured to determine the invalid tag group of the current cycle according to the first indication signal of the current cycle, the feedforward signal of the next cycle, and the second indication signal of the current cycle.

6. The circuit according to claim 5, wherein The second instruction tagging module is further configured to determine that the first indication signal of the instruction is a first signal when the tag validity of the instruction is valid; and determine that the first indication signal of the instruction is a second signal when the tag validity of the instruction is invalid; the first signal and the second signal are inverse signals; When the tag validity of the first instruction group is valid, determine that the feedforward signal of each instruction in the first instruction group is the first signal, and the feedforward signals of other instructions are the second signal; or, when the tag validity of the first instruction group is invalid, determine that the feedforward signal of each instruction is the second signal; When the remaining un-tagged quantity in the current cycle is equal to 0, determine that the second indication signal of each instruction in the current cycle is the first signal; Or, when the remaining un-tagged quantity in the current cycle is greater than 0, determine that the second indication signal of each instruction in the last instruction group of the current cycle is the second signal, and the second indication signals of other instructions in the current cycle except the last instruction group are the first signal.

7. The circuit according to claim 6, characterized in that, The first signal is a low-level signal; the second signal is a high-level signal; The tag deletion module is further configured to, when the remaining un-tagged quantity in the current cycle is equal to 0, perform an AND operation on the first indication signal of the current cycle and the inverse signal of the second indication signal of the current cycle to obtain a valid indication signal of the current cycle; and determine the instruction group to which the instruction corresponding to the low-level signal in the valid indication signal belongs as the invalid tag group of the current cycle.

8. The circuit according to claim 6, wherein The first signal is a low-level signal; the second signal is a high-level signal; The marker deletion module is further configured to perform an OR operation on the current-shot first indication signal and the next-shot feedforward signal to obtain the current-shot OR-processed signal; perform an AND operation on the inverse signal of the current-shot OR-processed signal and the inverse signal of the current-shot second indication signal to obtain the current-shot valid indication signal; and determine the instruction group to which the instruction corresponding to the low-level signal in the valid indication signal belongs as the current-shot invalid marker group.

9. The circuit according to claim 5, wherein The multi-shot includes a null shot; the number of instructions to be processed in the null shot is 0; when the current shot is the null shot, the instruction to be processed in the current shot is still the instruction to be processed in the previous shot. The second-level circuit further includes: A pause indication module, configured to feedforward a pause working signal to the second instruction marker module. The pause working signal is used to instruct the second instruction marker module to pause working for one shot.

10. The circuit according to claim 9, wherein The pause indication module is further configured to obtain the remaining unmarked quantity of the previous shot from the marker recording module; and carry the remaining unmarked quantity of the previous shot in the pause working signal when the current shot is the null shot. The second instruction marker module is further configured to set the instruction marker of the current-shot completion marker as the third marker instruction for the earliest remaining quantity of instructions among the instructions to be processed in the next shot; and use the obtained current-shot third marker instruction as the marker completion instruction.

11. The circuit according to claim 9, wherein The first-level circuit further includes: A null shot determination module, configured to determine whether the number of instructions to be processed in the current shot is 0 to obtain a null shot determination result. The pause indication module is further configured to feedforward the pause working signal to the second marker recording module when the null shot determination result indicates that the current shot is a null shot.

12. The circuit according to claim 11, characterized in that, The first-level circuit further includes: A remaining marker determination module, configured to obtain the remaining unmarked quantity of the previous shot from the marker recording module; and determine whether the remaining unmarked quantity of the previous shot is greater than 0 to obtain a remaining quantity determination result. The pause indication module is further configured to carry the remaining unmarked quantity of the previous shot in the pause working signal when the remaining quantity determination result indicates that the remaining unmarked quantity of the previous shot is greater than 0 and the null shot determination result indicates that the number of instructions to be processed in the current shot is 0.

13. The circuit according to any one of claims 1-3 or 5-12, characterized in that The circuit further includes: An instruction acquisition module, configured to acquire the instruction to be processed in the current shot from the instruction register; and acquire the instruction to be processed in the next shot from the instruction register when sending the instruction to be processed in the current shot to the first instruction marker module.

14. A processor, characterized in that, including: The instruction marker circuit according to any one of claims 1-13, configured to set instruction markers for the first conditional branch instruction and the non-jump instruction in the instruction to be processed to obtain a target marker instruction. An instruction execution circuit, configured to execute the target marker instruction according to the jump condition of the first conditional branch instruction and the instruction marker of the target marker instruction.

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