Instruction parsing method and system across operating systems and supporting multiple programming languages

Abstract

The present invention provides an instruction parsing method and system that crosses operating systems and supports multiple programming languages, which belongs to the field of data processing technology and is used to implement instruction parsing that crosses operating systems and supports multiple programming languages ​​by means of template matching. The method includes: an electronic device obtains a program instruction set to be parsed; the electronic device determines a target operating system suitable for the program instruction set to be parsed to run, and a target programming language used by the program instruction set to be parsed from multiple operating systems and multiple programming languages ​​according to the operating system information and programming language information carried by the program instruction set to be parsed; the electronic device parses the program instruction set to be parsed according to the parsing rules of the target programming language under the target operating system operating environment.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to an instruction parsing method and system that crosses operating systems and supports multiple programming languages. Background Art

[0002] Program instruction parsing is an important field in computer science, which involves converting source code in a high-level programming language into machine code or intermediate code that a computer can understand and execute. This process is crucial to software development and computer system design because it enables computers to understand and execute programs, thereby achieving various complex calculations and tasks. Over the past few decades, computer scientists and programmers have been researching and developing various parsing techniques and tools. One of the common parsing methods is a parser based on an abstract syntax tree (AST). AST is a data structure that represents the structure of program code, which can capture the syntax and semantic information of the program code. By using AST, we can parse different programming languages ​​more flexibly because they all have similar syntax structures and semantic meanings.

[0003] However, although the AST parser provides a certain degree of flexibility, there are still some limitations. For example, it cannot complete instruction parsing when the operating systems are different or the programming languages ​​are quite different. Summary of the invention

[0004] The embodiment of the present invention provides an instruction parsing method that crosses operating systems and supports multiple programming languages, so as to implement instruction parsing that crosses operating systems and supports multiple programming languages ​​by means of template matching.

[0005] In order to achieve the above object, the present invention adopts the following technical scheme:

[0006] In a first aspect, a method for parsing instructions that crosses operating systems and supports multiple programming languages ​​is provided, and the method is applied to an electronic device, and the method comprises: the electronic device obtains a program instruction set to be parsed; the electronic device determines, from a plurality of operating systems and a plurality of programming languages, a target operating system suitable for running the program instruction set to be parsed and a target programming language adopted by the program instruction set to be parsed based on the operating system information and programming language information carried by the program instruction set to be parsed; and the electronic device parses the program instruction set to be parsed according to the parsing rules of the target programming language under the target operating system running environment.

[0007] Optionally, the electronic device can simulate the operating environments of multiple operating systems. In the target operating system operating environment, the electronic device parses the program instruction set to be parsed according to the parsing rules of the target programming language, including: the electronic device simulates the target operating system operating environment; in the target operating system operating environment, the electronic device parses the program instruction set to be parsed in an interleaved manner according to the parsing rules of the target programming language.

[0008] Optionally, the electronic device parses the program instruction set to be parsed in an interleaved manner according to the parsing rules of the target programming language, including: the electronic device interleaves each program instruction sub-block in rows and columns according to the energy level of each program instruction sub-block in the program instruction set to be parsed, to obtain each program instruction sub-block after row and column interleaving, wherein program instruction sub-blocks of the same energy level in each program instruction sub-block after row and column interleaving are adjacent in each program instruction sub-block after row and column interleaving; the electronic device jointly parses the program instruction sub-blocks of the same energy level in each program instruction sub-block after row and column interleaving according to the parsing rules of the target programming language.

[0009] Optionally, the program instruction set to be parsed includes M program instruction sub-blocks, M is an integer greater than 2, each program instruction sub-block is used to execute a corresponding complete program function, and the three energy levels of the program instruction sub-blocks are, from high to low, the first level, the second level, and the third level, and the dependency relationship between the M program instruction sub-blocks is: the program instruction sub-block of the third level depends on the program instruction sub-block of the second level, and the program instruction sub-block of the second level depends on the program instruction sub-block of the first level; the electronic device interleaves each program instruction sub-block in rows and columns according to the energy level of each program instruction sub-block in the program instruction set to be parsed to obtain each program instruction sub-block after row and column interleaving, including: the electronic device interleaves the M program instruction sub-blocks in rows and columns according to the energy levels of each of the M program instruction sub-blocks to obtain M1 first level, second level, and third level in order. The target program design language comprises a program instruction sub-block of the first level, M2 program instruction sub-blocks of the second level, and M3 program instruction sub-blocks of the third level after the row and column interleaving, wherein M1, M2 and M3 are all integers greater than or equal to 1, and M1+M2+M3=M; accordingly, the electronic device jointly parses the program instruction sub-blocks of the same energy level in each program instruction sub-block after the row and column interleaving according to the parsing rules of the target programming language, including: the electronic device jointly parses the M1 program instruction sub-blocks of the first level using the first computing power, jointly parses the M2 program instruction sub-blocks of the second level using the second computing power, and jointly parses the M3 program instruction sub-blocks of the third level using the third computing power according to the parsing rules of the target programming language, wherein the first computing power is greater than the second computing power, and the second computing power is greater than the third computing power.

[0010] Optionally, the electronic device parses the program instruction set to be parsed in an interleaved manner according to the parsing rules of the target programming language, including: the electronic device interleaves each program instruction sub-block in reverse order according to the energy level of each program instruction sub-block in the program instruction set to be parsed, to obtain each program instruction sub-block after reverse order interleaving, wherein program instruction sub-blocks of the same energy level in each program instruction sub-block after reverse order interleaving are adjacent in each program instruction sub-block after reverse order interleaving; the electronic device jointly parses the program instruction sub-blocks of the same energy level in each program instruction sub-block after reverse order interleaving according to the parsing rules of the target programming language.

[0011] Optionally, the program instruction set to be parsed includes M program instruction sub-blocks, M is an integer greater than 2, each program instruction sub-block is used to execute a corresponding complete program function, and the three energy levels of the program instruction sub-blocks are, from high to low, the first level, the second level, and the third level, and the dependency relationship between the M program instruction sub-blocks is: the program instruction sub-block of the first level depends on the program instruction sub-block of the second level, and the program instruction sub-block of the second level depends on the program instruction sub-block of the third level; the electronic device interleaves each program instruction sub-block in reverse order according to the energy level of each program instruction sub-block in the program instruction set to be parsed, and obtains each program instruction sub-block after reverse order row and column interleaving, including: the electronic device interleaves the M program instruction sub-blocks in rows and columns according to the energy levels of each of the M program instruction sub-blocks, and obtains M1 first level sub-blocks in order. For each program instruction sub-block after the reverse row-column interleaving of M1 program instruction sub-blocks, M2 program instruction sub-blocks of the second level, and M3 program instruction sub-blocks of the third level, M1, M2 and M3 are all integers greater than or equal to 1, and M1+M2+M3=M; accordingly, the electronic device jointly parses the program instruction sub-blocks of the same energy level in each program instruction sub-block after the reverse row-column interleaving according to the parsing rules of the target programming language, including: the electronic device uses the first computing power to jointly parse the M1 program instruction sub-blocks of the first level, uses the second computing power to jointly parse the M2 program instruction sub-blocks of the second level, and uses the third computing power to jointly parse the M3 program instruction sub-blocks of the third level according to the parsing rules of the target programming language, wherein the first computing power is greater than the second computing power, and the second computing power is greater than the third computing power.

[0012] Optionally, for the ith program instruction sub-block among M program instruction sub-blocks, i is an integer traversing from 1 to M, the ith program instruction sub-block contains Ni program instruction functions, each program instruction function is used to execute a sub-function in a complete program function executed by the ith program instruction sub-block; the method also includes: the electronic device interweaves the Ni program instruction functions according to the mutual dependencies between the Ni program instruction functions to obtain the interleaved Ni program instruction functions, wherein the Ni program instruction functions are configured to participate in row-column interleaving or reverse row-column interleaving according to the order of the program instruction functions in the interleaved Ni program instruction functions.

[0013] Optionally, the dependencies are configured as a first dependency set, a second dependency set, and a third dependency set, the program instruction functions in the first dependency set have dependencies, the program instruction functions in the second dependency set have dependencies, the program instruction functions in the third dependency set have dependencies, the first dependency set depends on the second dependency set, and the second dependency set depends on the third dependency set; the interleaved Ni program instruction functions are, in order: N1i program instruction functions belonging to the first dependency set, N2i program instruction functions belonging to the second dependency set, and N3i program instruction functions belonging to the third dependency set, N1i, N2i and N3i are all integers greater than or equal to 1, N1i+N2i+N3i=Ni.

[0014] Optionally, the electronic device obtains the program instruction set to be parsed, including: in response to a user operation, the electronic device obtains the program instruction set to be parsed input by the user.

[0015] In a second aspect, an instruction parsing system that is cross-operating system and supports multiple programming languages ​​is provided, and the system is applied to an electronic device, and the system is configured as follows: the electronic device obtains a program instruction set to be parsed; the electronic device determines a target operating system suitable for running the program instruction set to be parsed and a target programming language adopted by the program instruction set to be parsed from a plurality of operating systems and a plurality of programming languages ​​based on the operating system information and programming language information carried by the program instruction set to be parsed; the electronic device parses the program instruction set to be parsed according to the parsing rules of the target programming language under the target operating system running environment.

[0016] Optionally, the electronic device can simulate the operating environments of multiple operating systems. In the target operating system operating environment, the electronic device parses the program instruction set to be parsed according to the parsing rules of the target programming language, including: the electronic device simulates the target operating system operating environment; in the target operating system operating environment, the electronic device parses the program instruction set to be parsed in an interleaved manner according to the parsing rules of the target programming language.

[0017] Optionally, the electronic device parses the program instruction set to be parsed in an interleaved manner according to the parsing rules of the target programming language, including: the electronic device interleaves each program instruction sub-block in rows and columns according to the energy level of each program instruction sub-block in the program instruction set to be parsed, to obtain each program instruction sub-block after row and column interleaving, wherein program instruction sub-blocks of the same energy level in each program instruction sub-block after row and column interleaving are adjacent in each program instruction sub-block after row and column interleaving; the electronic device jointly parses the program instruction sub-blocks of the same energy level in each program instruction sub-block after row and column interleaving according to the parsing rules of the target programming language.

[0018] Optionally, the program instruction set to be parsed includes M program instruction sub-blocks, M is an integer greater than 2, each program instruction sub-block is used to execute a corresponding complete program function, and the three energy levels of the program instruction sub-blocks are, from high to low, the first level, the second level, and the third level, and the dependency relationship between the M program instruction sub-blocks is: the program instruction sub-block of the third level depends on the program instruction sub-block of the second level, and the program instruction sub-block of the second level depends on the program instruction sub-block of the first level; the electronic device interleaves each program instruction sub-block in rows and columns according to the energy level of each program instruction sub-block in the program instruction set to be parsed to obtain each program instruction sub-block after row and column interleaving, including: the electronic device interleaves the M program instruction sub-blocks in rows and columns according to the energy levels of each of the M program instruction sub-blocks to obtain M1 first level, second level, and third level in order. The target program design language comprises a program instruction sub-block of the first level, M2 program instruction sub-blocks of the second level, and M3 program instruction sub-blocks of the third level after the row and column interleaving, wherein M1, M2 and M3 are all integers greater than or equal to 1, and M1+M2+M3=M; accordingly, the electronic device jointly parses the program instruction sub-blocks of the same energy level in each program instruction sub-block after the row and column interleaving according to the parsing rules of the target programming language, including: the electronic device jointly parses the M1 program instruction sub-blocks of the first level using the first computing power, jointly parses the M2 program instruction sub-blocks of the second level using the second computing power, and jointly parses the M3 program instruction sub-blocks of the third level using the third computing power according to the parsing rules of the target programming language, wherein the first computing power is greater than the second computing power, and the second computing power is greater than the third computing power.

[0019] Optionally, the electronic device parses the program instruction set to be parsed in an interleaved manner according to the parsing rules of the target programming language, including: the electronic device interleaves each program instruction sub-block in reverse order according to the energy level of each program instruction sub-block in the program instruction set to be parsed, to obtain each program instruction sub-block after reverse order interleaving, wherein program instruction sub-blocks of the same energy level in each program instruction sub-block after reverse order interleaving are adjacent in each program instruction sub-block after reverse order interleaving; the electronic device jointly parses the program instruction sub-blocks of the same energy level in each program instruction sub-block after reverse order interleaving according to the parsing rules of the target programming language.

[0020] Optionally, the program instruction set to be parsed includes M program instruction sub-blocks, M is an integer greater than 2, each program instruction sub-block is used to execute a corresponding complete program function, and the three energy levels of the program instruction sub-blocks are, from high to low, the first level, the second level, and the third level, and the dependency relationship between the M program instruction sub-blocks is: the program instruction sub-block of the first level depends on the program instruction sub-block of the second level, and the program instruction sub-block of the second level depends on the program instruction sub-block of the third level; the electronic device interleaves each program instruction sub-block in reverse order according to the energy level of each program instruction sub-block in the program instruction set to be parsed, and obtains each program instruction sub-block after reverse order row and column interleaving, including: the electronic device interleaves the M program instruction sub-blocks in rows and columns according to the energy levels of each of the M program instruction sub-blocks, and obtains M1 first level sub-blocks in order. For each program instruction sub-block after the reverse row-column interleaving of M1 program instruction sub-blocks, M2 program instruction sub-blocks of the second level, and M3 program instruction sub-blocks of the third level, M1, M2 and M3 are all integers greater than or equal to 1, and M1+M2+M3=M; accordingly, the electronic device jointly parses the program instruction sub-blocks of the same energy level in each program instruction sub-block after the reverse row-column interleaving according to the parsing rules of the target programming language, including: the electronic device uses the first computing power to jointly parse the M1 program instruction sub-blocks of the first level, uses the second computing power to jointly parse the M2 program instruction sub-blocks of the second level, and uses the third computing power to jointly parse the M3 program instruction sub-blocks of the third level according to the parsing rules of the target programming language, wherein the first computing power is greater than the second computing power, and the second computing power is greater than the third computing power.

[0021] Optionally, for the ith program instruction sub-block among M program instruction sub-blocks, i is an integer traversing from 1 to M, the ith program instruction sub-block contains Ni program instruction functions, each program instruction function is used to execute a sub-function in a complete program function executed by the ith program instruction sub-block; the system is further configured as: the electronic device interleaves the Ni program instruction functions according to the dependencies between the Ni program instruction functions to obtain the interleaved Ni program instruction functions, wherein the Ni program instruction functions are configured to participate in row-column interleaving or reverse row-column interleaving according to the order of the program instruction functions in the interleaved Ni program instruction functions.

[0022] Optionally, the dependencies are configured as a first dependency set, a second dependency set, and a third dependency set, the program instruction functions in the first dependency set have dependencies, the program instruction functions in the second dependency set have dependencies, the program instruction functions in the third dependency set have dependencies, the first dependency set depends on the second dependency set, and the second dependency set depends on the third dependency set; the interleaved Ni program instruction functions are, in order: N1i program instruction functions belonging to the first dependency set, N2i program instruction functions belonging to the second dependency set, and N3i program instruction functions belonging to the third dependency set, N1i, N2i and N3i are all integers greater than or equal to 1, N1i+N2i+N3i=Ni.

[0023] Optionally, the electronic device obtains the program instruction set to be parsed, including: in response to a user operation, the electronic device obtains the program instruction set to be parsed input by the user.

[0024] In a third aspect, an electronic device is provided, comprising: a processor and a memory; the memory is used to store a computer program, and when the processor executes the computer program, the electronic device executes the method described in the first aspect.

[0025] In a possible design solution, the electronic device described in the third aspect may further include a transceiver. The transceiver may be a transceiver circuit or an interface circuit. The transceiver may be used for the electronic device described in the third aspect to communicate with other electronic devices.

[0026] In an embodiment of the present invention, the electronic device described in the third aspect may be a terminal, or a chip (system) or other parts or components that may be arranged in the terminal, or a system including the terminal.

[0027] In a fourth aspect, a computer-readable storage medium is provided, comprising: a computer program or instructions; when the computer program or instructions are executed on a computer, the computer is caused to execute the method described in the first aspect.

[0028] In summary, the above method and system have the following technical effects:

[0029] Since the program instruction set to be parsed can carry operating system information and programming language information, the electronic device can determine the target operating system suitable for the program instruction set to be parsed, and the target programming language used by the program instruction set to be parsed, so as to simulate the target operating system operating environment and parse the program instruction set to be parsed according to the parsing rules of the target programming language, that is, through template matching, instruction parsing across operating systems and supporting multiple programming languages ​​can be achieved, thereby improving the flexibility of instruction parsing. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A flowchart of an instruction parsing method that is cross-operating system and supports multiple programming languages ​​provided by an embodiment of the present invention;

[0031] Figure 2 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The technical solution of the present invention will be described below in conjunction with the accompanying drawings.

[0033] In the embodiment of the present invention, "indication" may include direct indication and indirect indication, and may also include explicit indication and implicit indication. The information indicated by a certain information is called information to be indicated. In the specific implementation process, there are many ways to indicate the information to be indicated, such as but not limited to, the information to be indicated can be directly indicated, such as the information to be indicated itself or the index of the information to be indicated. The information to be indicated can also be indirectly indicated by indicating other information, wherein there is an association relationship between the other information and the information to be indicated. It is also possible to indicate only a part of the information to be indicated, while the other parts of the information to be indicated are known or agreed in advance. For example, the indication of specific information can also be achieved by means of the arrangement order of each information agreed in advance (for example, specified by the protocol), thereby reducing the indication overhead to a certain extent. At the same time, the common parts of each information can also be identified and indicated uniformly to reduce the indication overhead caused by indicating the same information separately.

[0034] In addition, the specific indication method may also be various existing indication methods, such as but not limited to the above-mentioned indication methods and various combinations thereof. The specific details of the various indication methods can refer to the prior art and will not be repeated herein. As can be seen from the above, for example, when it is necessary to indicate multiple information of the same type, different indication methods may be used for different information. In the specific implementation process, the desired indication method can be selected according to specific needs. The embodiment of the present invention does not limit the selected indication method. In this way, the indication method involved in the embodiment of the present invention should be understood to cover various methods that can enable the party to be indicated to obtain the information to be indicated.

[0035] It should be understood that the information to be indicated can be sent as a whole or divided into multiple sub-information and sent separately, and the sending period and / or sending time of these sub-information can be the same or different. The specific sending method is not limited in the embodiment of the present invention. Among them, the sending period and / or sending time of these sub-information can be pre-defined, for example, pre-defined according to a protocol, or can be configured by the sending end device by sending configuration information to the receiving end device.

[0036] "Pre-definition" or "pre-configuration" can be implemented by pre-saving corresponding codes, tables or other methods that can be used to indicate relevant information in the device, and the embodiments of the present invention do not limit the specific implementation method. Among them, "saving" can mean saving in one or more memories. The one or more memories can be set separately or integrated in an encoder or decoder, a processor, or an electronic device. The one or more memories can also be partially set separately and partially integrated in a decoder, a processor, or an electronic device. The type of memory can be any form of storage medium, which is not limited by the embodiments of the present invention.

[0037] The "protocol" involved in the embodiments of the present invention may refer to a protocol family in the communication field, a standard protocol with a similar protocol family frame structure, or a related protocol used in future cross-operating systems and instruction parsing method systems that support multiple programming languages. The embodiments of the present invention do not make specific limitations on this.

[0038] In the embodiments of the present invention, descriptions such as "when...", "in the case of...", "if" and "if" all mean that the device will perform corresponding processing under certain objective circumstances, but do not limit the time, nor do they require the device to perform judgment actions when implementing, nor do they mean the existence of other limitations.

[0039] In the description of the embodiments of the present invention, unless otherwise specified, " / " indicates that the objects associated before and after are in an "or" relationship, for example, A / B can represent A or B; "and / or" in the embodiments of the present invention is only a kind of association relationship describing the associated objects, indicating that there can be three relationships, for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. In addition, in the description of the embodiments of the present invention, unless otherwise specified, "multiple" refers to two or more than two. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple. In addition, in order to facilitate the clear description of the technical solution of the embodiments of the present invention, in the embodiments of the present invention, the words "first" and "second" are used to distinguish the same or similar items with basically the same functions and effects. Those skilled in the art will appreciate that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit the difference. At the same time, in the embodiments of the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way for easy understanding.

[0040] The network architecture and business scenarios described in the embodiments of the present invention are intended to more clearly illustrate the technical solutions of the embodiments of the present invention, and do not constitute a limitation on the technical solutions provided by the embodiments of the present invention. A person of ordinary skill in the art can appreciate that with the evolution of the network architecture and the emergence of new business scenarios, the technical solutions provided by the embodiments of the present invention are equally applicable to similar technical problems.

[0041] Figure 1 The flowchart of the method provided by the embodiment of the present invention is as follows. The instruction parsing method across operating systems and supporting multiple programming languages ​​can be executed by an electronic device, which can be a terminal. The specific process is as follows:

[0042] S101, the electronic device obtains a program instruction set to be parsed.

[0043] The program instruction set to be parsed may be a set of program instructions written in a programming language, which can be executed to implement a variety of program functions. The programming language may be C, Java, Python, etc. In response to the user's operation, the electronic device obtains the program instruction set to be parsed input by the user, that is, the program instruction set to be parsed may be input by the user to the electronic device, or may be obtained in other ways, such as from other devices, without specific limitation.

[0044] The program instruction set to be parsed may carry operating system information and programming language information. The operating system information may be used to indicate the operating system on which the program instruction set is running, such as Windows, macOS, Linux, Android, iOS, or Unix. The programming language information may be used to indicate the programming language used to write the program instruction set.

[0045] S102, the electronic device determines a target operating system suitable for running the program instruction set to be parsed and a target programming language adopted by the program instruction set to be parsed from a plurality of operating systems and a plurality of programming languages ​​according to the operating system information and programming language information carried by the program instruction set to be parsed.

[0046] The electronic device is preset with templates, such as templates including simulations of various operating systems and templates of various programming languages. In this way, the electronic device can perform template matching on the operating system information and programming language information carried by the program instruction set to be parsed, and determine the target operating system suitable for the program instruction set to be parsed to run, and the target programming language used by the program instruction set to be parsed.

[0047] S103, the electronic device parses the program instruction set to be parsed according to the parsing rules of the target programming language under the target operating system running environment.

[0048] Based on preset templates, electronic devices can simulate the operating environments of multiple operating systems. In this way, the electronic device can simulate the target operating system operating environment; in the target operating system operating environment, the electronic device parses the program instruction set to be parsed in an interleaved manner according to the parsing rules of the target programming language. Among them, the parser can be an existing parser, which can include parsers corresponding to multiple different programming languages, such as parsers corresponding to C language, Java and Python, that is, whichever specific target programming language is, the electronic device triggers the use of the parser corresponding to the target programming language.

[0049] Method 1:

[0050] Drawing on the idea of ​​interleaving in the field of communications, the electronic device can interleave each program instruction sub-block in rows and columns according to the energy level of each program instruction sub-block in the program instruction set to be parsed, and obtain each program instruction sub-block after row and column interleaving. Among them, the program instruction sub-blocks of the same energy level in each program instruction sub-block after row and column interleaving are adjacent in the positions of each program instruction sub-block after row and column interleaving. For example, the program instruction set to be parsed may include M program instruction sub-blocks, M is an integer greater than 2, each program instruction sub-block is used to execute a corresponding complete program function, and the three energy levels of the program instruction sub-blocks are first level, second level, and third level from high to low (which is to refer to the three energy levels of high, medium, and low corresponding to interleaving in the field of communications). The energy level of the program instruction sub-block can be preset when writing, and the more important or critical the function of the program instruction sub-block is, the higher the energy level can be.

[0051] If the dependency relationship between the M program instruction sub-blocks can be: the third-level program instruction sub-block depends on the second-level program instruction sub-block, and the second-level program instruction sub-block depends on the first-level program instruction sub-block, then the interleaving method can adopt row-column interleaving. For example, the electronic device can interleave the M program instruction sub-blocks in rows and columns according to the energy levels of the M program instruction sub-blocks, and obtain the program instruction sub-blocks after row-column interleaving, which are M1 first-level program instruction sub-blocks, M2 second-level program instruction sub-blocks, and M3 third-level program instruction sub-blocks in order, M1, M2 and M3 are all integers greater than or equal to 1, M1+M2+M3=M, that is, by adjusting the order of the program instruction sub-blocks by row-column interleaving, the program instruction sub-blocks of the same energy level can be placed together.

[0052] The electronic device can jointly parse the program instruction sub-blocks of the same energy level in each program instruction sub-block after the rows and columns are interleaved according to the parsing rules of the target programming language. For example, the electronic device can use the first computing power to jointly parse M1 first-level program instruction sub-blocks, use the second computing power to jointly parse M2 second-level program instruction sub-blocks, and use the third computing power to jointly parse M3 third-level program instruction sub-blocks according to the parsing rules of the target programming language (i.e., using the parser corresponding to the target programming language), so as to improve the overall parsing efficiency and success rate. Among them, the first computing power is greater than the second computing power, and the second computing power is greater than the third computing power, that is, the higher the energy level of the program instruction sub-block, the more computing power can be used for parsing, the higher the parsing accuracy can be, and the parsing success rate can be sufficient to ensure that the key functions can be executed. The specific values ​​of the first computing power, the second computing power, and the third computing power can be set according to the actual situation, and there is no specific limitation.

[0053] Method 2:

[0054] The electronic device can interleave each program instruction sub-block in reverse order according to the energy level of each program instruction sub-block in the program instruction set to be parsed, and obtain each program instruction sub-block after reverse order interleaving. Among them, program instruction sub-blocks of the same energy level in each program instruction sub-block after reverse order interleaving are adjacent in each program instruction sub-block after reverse order interleaving. For example, the program instruction set to be parsed includes M program instruction sub-blocks, M is an integer greater than 2, each program instruction sub-block is used to execute a corresponding complete program function, and the three energy levels of the program instruction sub-blocks are first level, second level, and third level from high to low.

[0055] If the dependency relationship between the M program instruction sub-blocks is: the first-level program instruction sub-block depends on the second-level program instruction sub-block, and the second-level program instruction sub-block depends on the third-level program instruction sub-block, then in this case, the parent node in the dependency relationship needs to be prioritized, that is, the second-level program instruction sub-block, or the third-level program instruction sub-block, which needs to be successfully parsed, otherwise even if the first-level program instruction sub-block is successfully parsed, it may not be successfully executed because the second-level program instruction sub-block or the third-level program instruction sub-block is not successfully parsed. Therefore, in this case, the electronic device needs to use reverse row and column interleaving, that is, the interleaving result is opposite to the row and column interleaving. For example, the electronic device can interleave the M program instruction sub-blocks in rows and columns according to the energy levels of each of the M program instruction sub-blocks, and obtain the program instruction sub-blocks after the row and column interleaving of M1 first-level program instruction sub-blocks, M2 second-level program instruction sub-blocks, and M3 third-level program instruction sub-blocks in order, M1, M2 and M3 are all integers greater than or equal to 1, M1+M2+M3=M.

[0056] Accordingly, the electronic device can jointly parse the program instruction sub-blocks of the same energy level in each program instruction sub-block after the reverse row and column interleaving according to the parsing rules of the target programming language. For example, the electronic device can use the first computing power to jointly parse M1 first-level program instruction sub-blocks, use the second computing power to jointly parse M2 second-level program instruction sub-blocks, and use the third computing power to jointly parse M3 third-level program instruction sub-blocks according to the parsing rules of the target programming language, so as to improve the overall parsing efficiency and success rate. Among them, the first computing power is greater than the second computing power, and the second computing power is greater than the third computing power, so as to ensure that the dependent program instruction sub-blocks can use more computing power resources for parsing to ensure the parsing success rate.

[0057] Optionally, for the ith program instruction sub-block among the M program instruction sub-blocks, i is an integer traversing from 1 to M, and the ith program instruction sub-block contains Ni program instruction functions, each of which is used to execute a sub-function in a complete program function executed by the ith program instruction sub-block. The electronic device may also interleave the Ni program instruction functions according to the dependencies between the Ni program instruction functions to obtain the interleaved Ni program instruction functions, wherein the Ni program instruction functions are configured to participate in the above-mentioned row-column interleaving or reverse row-column interleaving according to the order of the program instruction functions in the interleaved Ni program instruction functions, thereby improving the parsing efficiency and success rate of each program instruction sub-block.

[0058] Among them, the dependencies can be configured as a first dependency set, a second dependency set and a third dependency set, the program instruction functions in the first dependency set have dependencies, the program instruction functions in the second dependency set have dependencies, the program instruction functions in the third dependency set have dependencies, the first dependency set depends on the second dependency set, and the second dependency set depends on the third dependency set; the interleaved Ni program instruction functions are, in order: N1i program instruction functions belonging to the first dependency set, N2i program instruction functions belonging to the second dependency set, and N3i program instruction functions belonging to the third dependency set, N1i, N2i and N3i are all integers greater than or equal to 1, N1i+N2i+N3i=Ni.

[0059] In summary: since the program instruction set to be parsed can carry operating system information and programming language information, the electronic device can determine the target operating system suitable for the program instruction set to be parsed, and the target programming language used by the program instruction set to be parsed, so as to simulate the target operating system running environment and parse the program instruction set to be parsed according to the parsing rules of the target programming language, that is, through template matching, instruction parsing across operating systems and supporting multiple programming languages ​​can be achieved, thereby improving the flexibility of instruction parsing.

[0060] Combination of the above Figure 2 The method provided by the embodiment of the present invention is described in detail. The following is a detailed description of an instruction parsing system that is cross-operating system and supports multiple programming languages ​​for executing the method provided by the embodiment of the present invention.

[0061] The system is applied to an electronic device, and the system is configured as follows: the electronic device obtains a program instruction set to be parsed; the electronic device determines a target operating system suitable for running the program instruction set to be parsed and a target programming language adopted by the program instruction set to be parsed from a plurality of operating systems and a plurality of programming languages ​​according to the operating system information and programming language information carried by the program instruction set to be parsed; and the electronic device parses the program instruction set to be parsed according to the parsing rules of the target programming language under the target operating system running environment.

[0062] Optionally, the electronic device can simulate the operating environments of multiple operating systems. In the target operating system operating environment, the electronic device parses the program instruction set to be parsed according to the parsing rules of the target programming language, including: the electronic device simulates the target operating system operating environment; in the target operating system operating environment, the electronic device parses the program instruction set to be parsed in an interleaved manner according to the parsing rules of the target programming language.

[0063] Optionally, the electronic device parses the program instruction set to be parsed in an interleaved manner according to the parsing rules of the target programming language, including: the electronic device interleaves each program instruction sub-block in rows and columns according to the energy level of each program instruction sub-block in the program instruction set to be parsed, to obtain each program instruction sub-block after row and column interleaving, wherein program instruction sub-blocks of the same energy level in each program instruction sub-block after row and column interleaving are adjacent in each program instruction sub-block after row and column interleaving; the electronic device jointly parses the program instruction sub-blocks of the same energy level in each program instruction sub-block after row and column interleaving according to the parsing rules of the target programming language.

[0064] Optionally, the program instruction set to be parsed includes M program instruction sub-blocks, M is an integer greater than 2, each program instruction sub-block is used to execute a corresponding complete program function, and the three energy levels of the program instruction sub-blocks are, from high to low, the first level, the second level, and the third level, and the dependency relationship between the M program instruction sub-blocks is: the program instruction sub-block of the third level depends on the program instruction sub-block of the second level, and the program instruction sub-block of the second level depends on the program instruction sub-block of the first level; the electronic device interleaves each program instruction sub-block in rows and columns according to the energy level of each program instruction sub-block in the program instruction set to be parsed to obtain each program instruction sub-block after row and column interleaving, including: the electronic device interleaves the M program instruction sub-blocks in rows and columns according to the energy levels of each of the M program instruction sub-blocks to obtain M1 first level, second level, and third level in order. The target program design language comprises a program instruction sub-block of the first level, M2 program instruction sub-blocks of the second level, and M3 program instruction sub-blocks of the third level after the row and column interleaving, wherein M1, M2 and M3 are all integers greater than or equal to 1, and M1+M2+M3=M; accordingly, the electronic device jointly parses the program instruction sub-blocks of the same energy level in each program instruction sub-block after the row and column interleaving according to the parsing rules of the target programming language, including: the electronic device jointly parses the M1 program instruction sub-blocks of the first level using the first computing power, jointly parses the M2 program instruction sub-blocks of the second level using the second computing power, and jointly parses the M3 program instruction sub-blocks of the third level using the third computing power according to the parsing rules of the target programming language, wherein the first computing power is greater than the second computing power, and the second computing power is greater than the third computing power.

[0065] Optionally, the electronic device parses the program instruction set to be parsed in an interleaved manner according to the parsing rules of the target programming language, including: the electronic device interleaves each program instruction sub-block in reverse order according to the energy level of each program instruction sub-block in the program instruction set to be parsed, to obtain each program instruction sub-block after reverse order interleaving, wherein program instruction sub-blocks of the same energy level in each program instruction sub-block after reverse order interleaving are adjacent in each program instruction sub-block after reverse order interleaving; the electronic device jointly parses the program instruction sub-blocks of the same energy level in each program instruction sub-block after reverse order interleaving according to the parsing rules of the target programming language.

[0066] Optionally, the program instruction set to be parsed includes M program instruction sub-blocks, M is an integer greater than 2, each program instruction sub-block is used to execute a corresponding complete program function, and the three energy levels of the program instruction sub-blocks are, from high to low, the first level, the second level, and the third level, and the dependency relationship between the M program instruction sub-blocks is: the program instruction sub-block of the first level depends on the program instruction sub-block of the second level, and the program instruction sub-block of the second level depends on the program instruction sub-block of the third level; the electronic device interleaves each program instruction sub-block in reverse order according to the energy level of each program instruction sub-block in the program instruction set to be parsed, and obtains each program instruction sub-block after reverse order row and column interleaving, including: the electronic device interleaves the M program instruction sub-blocks in rows and columns according to the energy levels of each of the M program instruction sub-blocks, and obtains M1 first level sub-blocks in order. For each program instruction sub-block after the reverse row-column interleaving of M1 program instruction sub-blocks, M2 program instruction sub-blocks of the second level, and M3 program instruction sub-blocks of the third level, M1, M2 and M3 are all integers greater than or equal to 1, and M1+M2+M3=M; accordingly, the electronic device jointly parses the program instruction sub-blocks of the same energy level in each program instruction sub-block after the reverse row-column interleaving according to the parsing rules of the target programming language, including: the electronic device uses the first computing power to jointly parse the M1 program instruction sub-blocks of the first level, uses the second computing power to jointly parse the M2 program instruction sub-blocks of the second level, and uses the third computing power to jointly parse the M3 program instruction sub-blocks of the third level according to the parsing rules of the target programming language, wherein the first computing power is greater than the second computing power, and the second computing power is greater than the third computing power.

[0067] Optionally, for the ith program instruction sub-block among M program instruction sub-blocks, i is an integer traversing from 1 to M, the ith program instruction sub-block contains Ni program instruction functions, each program instruction function is used to execute a sub-function in a complete program function executed by the ith program instruction sub-block; the system is further configured as: the electronic device interleaves the Ni program instruction functions according to the dependencies between the Ni program instruction functions to obtain the interleaved Ni program instruction functions, wherein the Ni program instruction functions are configured to participate in row-column interleaving or reverse row-column interleaving according to the order of the program instruction functions in the interleaved Ni program instruction functions.

[0068] Optionally, the dependencies are configured as a first dependency set, a second dependency set, and a third dependency set, the program instruction functions in the first dependency set have dependencies, the program instruction functions in the second dependency set have dependencies, the program instruction functions in the third dependency set have dependencies, the first dependency set depends on the second dependency set, and the second dependency set depends on the third dependency set; the interleaved Ni program instruction functions are, in order: N1i program instruction functions belonging to the first dependency set, N2i program instruction functions belonging to the second dependency set, and N3i program instruction functions belonging to the third dependency set, N1i, N2i and N3i are all integers greater than or equal to 1, N1i+N2i+N3i=Ni.

[0069] Optionally, the electronic device obtains the program instruction set to be parsed, including: in response to a user operation, the electronic device obtains the program instruction set to be parsed input by the user.

[0070] Figure 2 The schematic diagram of the structure of the electronic device provided by the embodiment of the present invention. For example, the electronic device may be a network device, or a chip (system) or other components or assemblies that can be set in the network device. Figure 2 As shown, the electronic device 400 may include a processor 401. Optionally, the electronic device 400 may further include a memory 402 and / or a transceiver 403. The processor 401 is coupled with the memory 402 and the transceiver 403, such as being connected via a communication bus.

[0071] Combine the following Figure 2 The components of the electronic device 400 are described in detail:

[0072] The processor 401 is the control center of the electronic device 400, and may be a processor or a general term for multiple processing elements. For example, the processor 401 is one or more central processing units (CPUs), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present invention, such as one or more microprocessors (digital signal processors, DSPs), or one or more field programmable gate arrays (field programmable gate arrays, FPGAs).

[0073] Optionally, the processor 401 can execute various functions of the electronic device 400 by running or executing the software program stored in the memory 402 and calling the data stored in the memory 402, such as executing the above Figure 1 The instruction parsing method shown is cross-operating system and supports multiple programming languages.

[0074] In a specific implementation, as an embodiment, the processor 401 may include one or more CPUs, such as Figure 2 CPU0 and CPU1 are shown in FIG.

[0075] In a specific implementation, as an embodiment, the electronic device 400 may also include multiple processors. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor here may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0076] The memory 402 is used to store the software program for executing the solution of the present invention, and the execution is controlled by the processor 401. The specific implementation method can refer to the above method embodiment, which will not be repeated here.

[0077] Optionally, the memory 402 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 402 may be integrated with the processor 401, or may exist independently and accessed through the interface circuit ( Figure 2 The processor 401 is coupled to the processor 401 (not shown), which is not specifically limited in this embodiment of the present invention.

[0078] The transceiver 403 is used for communication with other electronic devices. For example, if the electronic device 400 is a terminal, the transceiver 403 can be used to communicate with a network device, or with another terminal device. For another example, if the electronic device 400 is a network device, the transceiver 403 can be used to communicate with a terminal, or with another network device.

[0079] Optionally, the transceiver 403 may include a receiver and a transmitter ( Figure 2 The receiver is used to implement a receiving function, and the transmitter is used to implement a sending function.

[0080] Optionally, the transceiver 403 may be integrated with the processor 401, or may exist independently and communicate with the electronic device 400 through an interface circuit ( Figure 2 The processor 401 is coupled to the processor 401 (not shown), which is not specifically limited in this embodiment of the present invention.

[0081] Understandably, Figure 2 The structure of the electronic device 400 shown in the figure does not constitute a limitation on the electronic device, and the actual electronic device may include more or fewer components than those shown in the figure, or combine certain components, or arrange the components differently.

[0082] In addition, the technical effects of the electronic device 400 can refer to the technical effects of the methods described in the above method embodiments, which will not be repeated here.

[0083] It should be understood that the processor in the embodiment of the present invention may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0084] It should also be understood that the memory in the embodiments of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus RAM (DR RAM).

[0085] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0086] It should be understood that the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship, but it may also indicate an "and / or" relationship. Please refer to the context for specific understanding.

[0087] In the present invention, "at least one" means one or more, and "plurality" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0088] It should be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0089] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0090] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0091] In the several embodiments provided by the present invention, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0092] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0093] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0094] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0095] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A command parsing method that crosses operating systems and supports multiple programming languages, characterized in that: The method is applied to an electronic device, and the method comprises: The electronic device obtains a program instruction set to be parsed; The electronic device determines, from a plurality of operating systems and a plurality of programming languages, a target operating system suitable for running the program instruction set to be parsed and a target programming language adopted by the program instruction set to be parsed, according to the operating system information and programming language information carried by the program instruction set to be parsed; The electronic device parses the program instruction set to be parsed according to the parsing rules of the target programming language under the target operating system running environment; The electronic device can simulate the operating environments of the multiple operating systems, and the electronic device parses the program instruction set to be parsed according to the parsing rules of the target programming language under the target operating system operating environment, including: The electronic device simulates the target operating system operating environment; In the target operating system running environment, the electronic device parses the program instruction set to be parsed in an interleaved manner according to the parsing rules of the target programming language; The electronic device parses the program instruction set to be parsed in an interleaved manner according to the parsing rules of the target programming language, including: The electronic device interleaves the program instruction sub-blocks in rows and columns according to the energy levels of the program instruction sub-blocks in the program instruction set to be parsed, to obtain the program instruction sub-blocks after the row-column interleaving, wherein the program instruction sub-blocks of the same energy level in the program instruction sub-blocks after the row-column interleaving are located adjacently in the program instruction sub-blocks after the row-column interleaving; The electronic device jointly analyzes the program instruction sub-blocks of the same energy level in each program instruction sub-block after the row and column interleaving according to the analysis rules of the target programming language; The program instruction set to be parsed includes M program instruction sub-blocks, where M is an integer greater than 2, each program instruction sub-block is used to execute a corresponding complete program function, and the three energy levels of the program instruction sub-blocks are, from high to low, the first level, the second level, and the third level, and the dependency relationship between the M program instruction sub-blocks is: the program instruction sub-block of the third level depends on the program instruction sub-block of the second level, and the program instruction sub-block of the second level depends on the program instruction sub-block of the first level; The electronic device interleaves the program instruction sub-blocks in rows and columns according to the energy level of each program instruction sub-block in the program instruction set to be parsed, to obtain each program instruction sub-block after row and column interleaving, including: The electronic device interleaves the M program instruction sub-blocks in rows and columns according to the energy levels of the M program instruction sub-blocks, to obtain the interleaved program instruction sub-blocks, which are M1 program instruction sub-blocks of the first level, M2 program instruction sub-blocks of the second level, and M3 program instruction sub-blocks of the third level in order, wherein M1, M2, and M3 are all integers greater than or equal to 1, and M1+M2+M3=M; Accordingly, the electronic device performs joint parsing of the program instruction sub-blocks of the same energy level in each program instruction sub-block after the row and column interleaving according to the parsing rule of the target programming language, including: The electronic device uses a first computing power to jointly parse the M1 first-level program instruction sub-blocks, uses a second computing power to jointly parse the M2 second-level program instruction sub-blocks, and uses a third computing power to jointly parse the M3 third-level program instruction sub-blocks according to the parsing rule of the target programming language, wherein the first computing power is greater than the second computing power, and the second computing power is greater than the third computing power; The electronic device parses the program instruction set to be parsed in an interleaved manner according to the parsing rules of the target programming language, including: The electronic device performs reverse row-column interleaving on each program instruction sub-block according to the energy level of each program instruction sub-block in the program instruction set to be parsed, to obtain each program instruction sub-block after reverse row-column interleaving, wherein program instruction sub-blocks of the same energy level in each program instruction sub-block after reverse row-column interleaving are located adjacently in each program instruction sub-block after reverse row-column interleaving; The electronic device jointly analyzes the program instruction sub-blocks of the same energy level in each program instruction sub-block after the reverse order row and column interleaving according to the analysis rules of the target programming language; The program instruction set to be parsed includes M program instruction sub-blocks, where M is an integer greater than 2, each program instruction sub-block is used to execute a corresponding complete program function, and the three energy levels of the program instruction sub-blocks are, from high to low, the first level, the second level, and the third level, and the dependency relationship between the M program instruction sub-blocks is: the program instruction sub-block of the first level depends on the program instruction sub-block of the second level, and the program instruction sub-block of the second level depends on the program instruction sub-block of the third level; The electronic device interleaves the program instruction sub-blocks in reverse order according to the energy level of each program instruction sub-block in the program instruction set to be parsed, to obtain each program instruction sub-block after reverse order interleave, including: The electronic device interleaves the M program instruction sub-blocks in rows and columns according to the energy levels of the M program instruction sub-blocks, to obtain the interleaved program instruction sub-blocks, which are M1 program instruction sub-blocks of the first level, M2 program instruction sub-blocks of the second level, and M3 program instruction sub-blocks of the third level in order, wherein M1, M2, and M3 are all integers greater than or equal to 1, and M1+M2+M3=M; Accordingly, the electronic device performs joint parsing of the program instruction sub-blocks of the same energy level in each program instruction sub-block after the reverse row and column interleaving according to the parsing rule of the target programming language, including: The electronic device uses a first computing power to jointly parse the M1 first-level program instruction sub-blocks, uses a second computing power to jointly parse the M2 second-level program instruction sub-blocks, and uses a third computing power to jointly parse the M3 third-level program instruction sub-blocks according to the parsing rule of the target programming language, wherein the first computing power is greater than the second computing power, and the second computing power is greater than the third computing power; For the i-th program instruction sub-block in the M program instruction sub-blocks, i is an integer ranging from 1 to M, the i-th program instruction sub-block includes Ni program instruction functions, each program instruction function is used to execute a sub-function in a complete program function executed by the i-th program instruction sub-block; The method further comprises: The electronic device interleaves the Ni program instruction functions according to the dependencies between the Ni program instruction functions to obtain interleaved Ni program instruction functions, wherein the Ni program instruction functions are configured to participate in the row-column interleaving or the reverse row-column interleaving according to the order of the program instruction functions in the interleaved Ni program instruction functions; The dependencies are configured as a first dependency set, a second dependency set and a third dependency set, the program instruction functions in the first dependency set have dependencies, the program instruction functions in the second dependency set have dependencies, the program instruction functions in the third dependency set have dependencies, the first dependency set depends on the second dependency set, and the second dependency set depends on the third dependency set; the interleaved Ni program instruction functions are, in order: N1i program instruction functions belonging to the first dependency set, N2i program instruction functions belonging to the second dependency set, and N3i program instruction functions belonging to the third dependency set, N1i, N2i and N3i are all integers greater than or equal to 1, N1i+N2i+N3i=Ni.

2. The method according to claim 1, characterized in that The electronic device obtains a program instruction set to be parsed, including: In response to the user's operation, the electronic device obtains the program instruction set to be parsed input by the user.

3. An instruction parsing system that crosses operating systems and supports multiple programming languages, characterized in that: The system is applied to electronic equipment, and the system is configured as follows: The electronic device obtains a program instruction set to be parsed; The electronic device determines, from a plurality of operating systems and a plurality of programming languages, a target operating system suitable for running the program instruction set to be parsed and a target programming language adopted by the program instruction set to be parsed, according to the operating system information and programming language information carried by the program instruction set to be parsed; The electronic device parses the program instruction set to be parsed according to the parsing rules of the target programming language under the target operating system running environment; The electronic device can simulate the operating environments of the multiple operating systems, and the electronic device parses the program instruction set to be parsed according to the parsing rules of the target programming language under the target operating system operating environment, including: The electronic device simulates the target operating system operating environment; In the target operating system running environment, the electronic device parses the program instruction set to be parsed in an interleaved manner according to the parsing rules of the target programming language; The electronic device parses the program instruction set to be parsed in an interleaved manner according to the parsing rules of the target programming language, including: The electronic device interleaves the program instruction sub-blocks in rows and columns according to the energy levels of the program instruction sub-blocks in the program instruction set to be parsed, to obtain the program instruction sub-blocks after the row-column interleaving, wherein the program instruction sub-blocks of the same energy level in the program instruction sub-blocks after the row-column interleaving are located adjacently in the program instruction sub-blocks after the row-column interleaving; The electronic device jointly analyzes the program instruction sub-blocks of the same energy level in each program instruction sub-block after the row and column interleaving according to the analysis rules of the target programming language; The program instruction set to be parsed includes M program instruction sub-blocks, where M is an integer greater than 2, each program instruction sub-block is used to execute a corresponding complete program function, and the three energy levels of the program instruction sub-blocks are, from high to low, the first level, the second level, and the third level, and the dependency relationship between the M program instruction sub-blocks is: the program instruction sub-block of the third level depends on the program instruction sub-block of the second level, and the program instruction sub-block of the second level depends on the program instruction sub-block of the first level; The electronic device interleaves the program instruction sub-blocks in rows and columns according to the energy level of each program instruction sub-block in the program instruction set to be parsed, to obtain each program instruction sub-block after row and column interleaving, including: The electronic device interleaves the M program instruction sub-blocks in rows and columns according to the energy levels of the M program instruction sub-blocks, to obtain the interleaved program instruction sub-blocks, which are M1 program instruction sub-blocks of the first level, M2 program instruction sub-blocks of the second level, and M3 program instruction sub-blocks of the third level in order, wherein M1, M2, and M3 are all integers greater than or equal to 1, and M1+M2+M3=M; Accordingly, the electronic device performs joint parsing of the program instruction sub-blocks of the same energy level in each program instruction sub-block after the row and column interleaving according to the parsing rule of the target programming language, including: The electronic device uses a first computing power to jointly parse the M1 first-level program instruction sub-blocks, uses a second computing power to jointly parse the M2 second-level program instruction sub-blocks, and uses a third computing power to jointly parse the M3 third-level program instruction sub-blocks according to the parsing rule of the target programming language, wherein the first computing power is greater than the second computing power, and the second computing power is greater than the third computing power; The electronic device parses the program instruction set to be parsed in an interleaved manner according to the parsing rules of the target programming language, including: The electronic device performs reverse row-column interleaving on each program instruction sub-block according to the energy level of each program instruction sub-block in the program instruction set to be parsed, to obtain each program instruction sub-block after reverse row-column interleaving, wherein program instruction sub-blocks of the same energy level in each program instruction sub-block after reverse row-column interleaving are located adjacently in each program instruction sub-block after reverse row-column interleaving; The electronic device jointly analyzes the program instruction sub-blocks of the same energy level in each program instruction sub-block after the reverse order row and column interleaving according to the analysis rules of the target programming language; The program instruction set to be parsed includes M program instruction sub-blocks, where M is an integer greater than 2, each program instruction sub-block is used to execute a corresponding complete program function, and the three energy levels of the program instruction sub-blocks are, from high to low, the first level, the second level, and the third level, and the dependency relationship between the M program instruction sub-blocks is: the program instruction sub-block of the first level depends on the program instruction sub-block of the second level, and the program instruction sub-block of the second level depends on the program instruction sub-block of the third level; The electronic device interleaves the program instruction sub-blocks in reverse order according to the energy level of each program instruction sub-block in the program instruction set to be parsed, to obtain each program instruction sub-block after reverse order interleave, including: The electronic device interleaves the M program instruction sub-blocks in rows and columns according to the energy levels of the M program instruction sub-blocks, to obtain the interleaved program instruction sub-blocks, which are M1 program instruction sub-blocks of the first level, M2 program instruction sub-blocks of the second level, and M3 program instruction sub-blocks of the third level in order, wherein M1, M2, and M3 are all integers greater than or equal to 1, and M1+M2+M3=M; Accordingly, the electronic device performs joint parsing of the program instruction sub-blocks of the same energy level in each program instruction sub-block after the reverse row and column interleaving according to the parsing rule of the target programming language, including: The electronic device uses a first computing power to jointly parse the M1 first-level program instruction sub-blocks, uses a second computing power to jointly parse the M2 second-level program instruction sub-blocks, and uses a third computing power to jointly parse the M3 third-level program instruction sub-blocks according to the parsing rule of the target programming language, wherein the first computing power is greater than the second computing power, and the second computing power is greater than the third computing power; For the i-th program instruction sub-block in the M program instruction sub-blocks, i is an integer ranging from 1 to M, the i-th program instruction sub-block includes Ni program instruction functions, each program instruction function is used to execute a sub-function in a complete program function executed by the i-th program instruction sub-block; The electronic device interleaves the Ni program instruction functions according to the dependencies between the Ni program instruction functions to obtain interleaved Ni program instruction functions, wherein the Ni program instruction functions are configured to participate in the row-column interleaving or the reverse row-column interleaving according to the order of the program instruction functions in the interleaved Ni program instruction functions; The dependencies are configured as a first dependency set, a second dependency set and a third dependency set, the program instruction functions in the first dependency set have dependencies, the program instruction functions in the second dependency set have dependencies, the program instruction functions in the third dependency set have dependencies, the first dependency set depends on the second dependency set, and the second dependency set depends on the third dependency set; the interleaved Ni program instruction functions are, in order: N1i program instruction functions belonging to the first dependency set, N2i program instruction functions belonging to the second dependency set, and N3i program instruction functions belonging to the third dependency set, N1i, N2i and N3i are all integers greater than or equal to 1, N1i+N2i+N3i=Ni.

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