Memory board segmentation to reduce operating power

Abstract

The present application relates to memory plate segmentation to reduce operating power. Methods, systems and devices for operating ferroelectric memory cells are described. An electronic memory device may include multiple plate portions separated by multiple segmentation lines, which may be oriented in a plane parallel to the rows of a memory array or the columns of the memory array or both. The segmentation plate may be used instead of a single plate for the array. The one or more plate portions may be powered during access operations of a ferroelectric cell to form a voltage difference across the cell or to facilitate changing the charge of the cell. Each of the plate portions may include one or more memory cells. The memory cells on the plate portion may be read from or written to after the plate portion is activated by a plate driver.

Description

[0001] Information about divisional applications

[0002] This case is a divisional application. The parent case of the divisional application is an invention patent application with application date of July 19, 2018, application number 201880047227.8, and invention name “Memory board segmentation to reduce operating power”.

[0003] Cross Reference

[0004] This patent application claims priority to PCT Application No. PCT / US2018 / 042875, entitled “Memory Plate Segmentation to Reduce Operating Power,” filed by Kim et al. on July 19, 2018, which claims priority to U.S. Patent Application No. 15 / 655,675, entitled “Memory Plate Segmentation to Reduce Operating Power,” filed by Kim et al. on July 20, 2017, each of which is assigned to the present assignee, and each of which is expressly incorporated herein by reference in its entirety.

[0005] The technical field relates to memory board partitioning to reduce operating power. Background Art

[0006] The following relates generally to memory devices, and more particularly to electronic memory devices including a plurality of board portions separated by a plurality of separation lines, and methods of using the same.

[0007] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, a binary device has two states, usually represented as a logical "1" or a logical "0". In other systems, more than two states can be stored. To access the stored information, the electronic device can read or sense the stored states in the memory device. To store information, the electronic device can write or program the states in the memory device.

[0008] There are various types of memory devices, including random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, etc. Memory devices can be volatile or non-volatile. Non-volatile memory (e.g., flash memory) can store data for a long time even without external power. Volatile memory devices (e.g., DRAM) may lose their stored state over time unless they are periodically refreshed by an external power source. Binary memory devices may, for example, include charged or discharged capacitors. However, charged capacitors may become discharged over time through leakage current, causing the stored information to be lost.

[0009] If power consumption can be reduced, the advantages of non-volatile memory over volatile memory can be further increased. Operating some non-volatile memories such as FeRAM may include powering certain components to facilitate access operations. Limiting the size of such components, or limiting the frequency of powering such components can help reduce power consumption. Summary of the invention

[0010] An electronic memory device is described. In some examples, the electronic memory device may include: a plurality of board portions separated by a plurality of dividing lines, the plurality of dividing lines including a first set of dividing lines extending in a first direction; at least one memory cell disposed on each of the plurality of board portions, each of the memory cells coupled to a sensing component via one of a plurality of digit lines extending in the first direction; and a board driver component including a plurality of board drivers, each of the plurality of board drivers connected to one of the plurality of board portions by a board line.

[0011] An electronic memory device is described. In some examples, the electronic memory device may include: a plurality of board portions separated by a plurality of dividing lines, the plurality of dividing lines including a first set of dividing lines extending in a first direction and a second set of dividing lines extending in a second direction perpendicular to the first direction; at least one memory cell disposed on each of the plurality of board portions; and a board driver assembly including a plurality of board drivers, each of the plurality of board drivers connected to at least one of the plurality of board portions by a board line.

[0012] A method is described. In some examples, the method may include determining a location of a target memory cell and activating, by a plate driver, a plate portion corresponding to the location of the target memory cell, the plate portion being separated from a plurality of other plate portions by partition lines, the partition lines comprising a first set of partition lines extending in a vertical direction.

[0013] A method is described. In some examples, the method may include determining a location of a target memory cell and activating, by a plate driver, a plate portion corresponding to the location of the target memory cell, the plate portion being separated from a plurality of other plate portions by partition lines, the partition lines comprising a first set of partition lines extending in a first direction and a second set of partition lines extending in a second direction perpendicular to the first direction.

[0014] An electronic memory device is described. In some examples, the electronic memory device may include: a plurality of plate portions separated by a plurality of partition lines, the plurality of partition lines including a first set of partition lines extending in a first direction and a second set of partition lines extending in a second direction perpendicular to the first direction; a plate driver assembly including a plurality of plate drivers coupled to the plurality of plate portions; and a controller in electronic communication with the plate driver assembly. The controller may be operable to cause the device to identify a location of a target memory cell and activate one of the plurality of plate portions corresponding to the location of the target memory cell.

[0015] An apparatus is described. In some examples, the apparatus may include means for determining a location of a target memory cell and means for activating, by a plate driver, a plate portion corresponding to the location of the target memory cell, the plate portion being separated from a plurality of other plate portions by partition lines, the partition lines comprising a first set of partition lines extending in a vertical direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The disclosure herein refers to and includes the following figures:

[0017] Figure 1 illustrates an example memory array having memory plane partitioning according to various embodiments of the invention;

[0018] Figure 2 Example circuits illustrating memory cells in a device having memory plane partitioning according to various embodiments of the invention;

[0019] Figure 3 illustrating example hysteresis curves for ferroelectric memory cells used in devices with memory plane partitioning according to various embodiments of the present invention;

[0020] Figure 4illustrates an example memory array having memory plane partitioning according to various embodiments of the invention;

[0021] Figure 5 illustrates example timing diagrams for a memory array with memory plane partitioning according to various embodiments of the invention;

[0022] Figure 6 illustrates an example memory array having memory plane partitioning according to various embodiments of the invention;

[0023] Figure 7 illustrates an example memory array having memory plane partitioning according to various embodiments of the invention;

[0024] Figure 8 illustrates example circuits in a memory array having memory plane partitioning according to various embodiments of the present invention;

[0025] Fig. 9 An example memory controller is described that supports operation for a device having memory plane partitioning according to various embodiments of the present invention;

[0026] Fig.10 A system including an electronic memory device having memory plane partitioning according to various embodiments of the present invention is described;

[0027] Figures 11 to 14 A method for operating a device having memory plane partitioning according to an embodiment of the present invention is described. DETAILED DESCRIPTION

[0028] A memory array having ferroelectric cells may have a partitioned board that may allow subsections or portions of the board to be energized to access cells associated with those portions. This may allow portions of the board associated with inaccessible cells to remain isolated (i.e., not energized) and thus may reduce or minimize power consumption relative to a device having a single board.

[0029] By way of example, when a board is activated to facilitate cell access (e.g., reading from or writing to a cell), a memory device may consume a certain amount of power. The power consumption for board activation may be increased due to parasitic capacitance, such as parasitic capacitance between a digit line and a word line, parasitic capacitance between a word line and a memory cell, and parasitic capacitance between a digit line and a memory cell. Parasitic capacitance may be generated for each memory cell coupled to an activated memory board, which may cause significant power consumption when a large number of memory cells are coupled to an activated memory board.

[0030] In order to reduce the total parasitic capacitance of the electronic memory unit, and thus reduce power consumption, the electronic memory unit may include a plurality of memory board portions separated by a plurality of partition lines. At least one memory cell may be arranged on each of the plurality of memory board portions and may be coupled to the sensing component via one of the plurality of digital lines. The memory cell may be, for example, a ferroelectric memory cell. The electronic memory unit may also include a board driver assembly, the board driver assembly including a plurality of board drivers, each board driver being connected to at least one of the plurality of memory board portions via a board line.

[0031] In some examples, the plurality of dividing lines includes a first set of dividing lines parallel to the plurality of digital lines. In some other examples, the plurality of dividing lines includes a first set of dividing lines extending in a first direction and a second set of dividing lines extending in a second direction perpendicular to the first direction. As used herein, dividing lines may refer to physical breaks or discontinuities between portions of a plate; these may or may not be lines.

[0032] In some examples, each board driver can be coupled to a single memory board portion. In some other examples, each board driver can be coupled to two or more memory board portions. The board driver can activate one or more of the memory board portions so that information can be written to or read from the memory cells connected to the memory board portions.

[0033] Features of the invention introduced above are further described below in the context of a memory array. Specific examples are then described for configuration and operation of an electronic memory device having or supporting memory board segmentation to reduce operating power. These and other features of the invention are further illustrated and described with reference to device diagrams, system diagrams, and flow charts relating to memory board segmentation.

[0034] Figure 1 An example memory array 100 having memory plane partitioning according to various embodiments of the present invention is described. The memory array 100 may also be referred to as an electronic memory device. The memory array 100 includes memory cells 105 that are programmable to store different states. Each memory cell 105 may be programmable to store two states, represented as a logical 0 and a logical 1. In some cases, the memory cell 105 is configured to store more than two logical states.

[0035] The memory cell 105 may include a capacitor to store a charge representing a programmable state; for example, a charged and uncharged capacitor may represent two logic states, respectively. The memory cell 105 may include a capacitor having a ferroelectric material. Ferroelectric materials have a spontaneous electric polarization, i.e., they have a non-zero polarization in the absence of an electric field. Different charge levels of the ferroelectric capacitor may represent different logic states. Some details and advantages of the ferroelectric memory cell 105 are discussed below.

[0036] Operations such as reading and writing can be performed on the memory cell 105 by activating or selecting the appropriate access line 110 and digit line 115. The access line 110 may also be referred to as a word line 110, and the digit line 115 may also be referred to as a bit line 115. Activating or selecting a word line 110 or a digit line 115 may include applying a voltage to the corresponding line. The word line 110 and the digit line 115 are made of a conductive material. For example, the word line 110 and the digit line 115 may be made of a metal (e.g., copper, aluminum, gold, tungsten, etc.), a metal alloy, other conductive materials, or the like. According to Figure 1 In an example of a memory cell 105, each row of memory cells 105 is connected to a single word line 110, and each column of memory cells 105 is connected to a single digit line 115. By activating one word line 110 and one digit line 115 (e.g., applying a voltage to the word line 110 or the digit line 115), a single memory cell 105 can be accessed at their intersection. Accessing a memory cell 105 can include reading or writing to the memory cell 105. The intersection of a word line 110 and a digit line 115 can be referred to as the address of the memory cell. In some examples, a memory cell 105 can be coupled to other lines in addition to a word line 110 and a digit line 115. For example, a memory cell 105 can be coupled to a plate line (not shown). The use and connection of the plate line is described below.

[0037] In some architectures, the logical storage device (e.g., capacitor) of the cell can be electrically isolated from the digit line by a selection component. The word line 110 can be connected to the selection component and can control the selection component. For example, the selection component can be a transistor and the word line 110 can be connected to the gate of the transistor. Activating the word line 110 causes an electrical connection or closed circuit to be created between the capacitor of the memory cell 105 and its corresponding digit line 115. The digit line can then be accessed to read or write to the memory cell 105.

[0038] Access to the memory cells 105 may be controlled by a row decoder 120 and a column decoder 130. In some examples, the row decoder 120 receives a row address from the memory controller 140 and activates the appropriate word line 110 based on the received row address. Similarly, the column decoder 130 receives a column address from the memory controller 140 and activates the appropriate digital line 115. For example, the memory array 100 may include a plurality of word lines 110 labeled WL_1 to WL_M and a plurality of digital lines 115 labeled DL_1 to DL_N, where M and N depend on the array size. Thus, by activating a word line 110 and a digital line 115, for example, WL_2 and DL_3, the memory cells 105 at their intersections may be accessed.

[0039] For example, if Figure 4 and 6 As depicted in , the plate can be located below the array of cells 105. The plate can be segmented in a plane parallel to the word lines 110 or the digit lines 115, or both. Each cell can be coupled to a portion of the plate, and the plate or portion of the plate can be activated or powered to access the cell to which the portion is coupled. As described herein, memory plate segmentation can avoid parasitic capacitance and thus reduce power consumption.

[0040] After access, the memory cell 105 may be read or sensed by the sensing component 125 to determine the stored state of the memory cell 105. For example, after accessing the memory cell 105, the ferroelectric capacitor of the memory cell 105 may be discharged onto its corresponding digit line 115. Discharging the ferroelectric capacitor may be based on biasing or applying a voltage to the ferroelectric capacitor. The discharge may induce a change in the voltage of the digit line 115, and the sensing component 125 may compare the change in voltage with a reference voltage (not shown) to determine the stored state of the memory cell 105. For example, if the digit line 115 has a higher voltage than the reference voltage, the sensing component 125 may determine that the stored state in the memory cell 105 is a logic 1, and vice versa. The sensing component 125 may include various transistors or amplifiers to detect and amplify the difference in the signal, which may be referred to as latching. The detected logic state of the memory cell 105 may then be output as an output 135 through the column decoder 130.

[0041] The memory cells 105 may be set or written to by activating the associated word lines 110 and digit lines 115. As discussed above, activating the word lines 110 electrically connects the corresponding rows of memory cells 105 to their corresponding digit lines 115. By controlling the associated digit lines 115 when the word lines 110 are activated, the memory cells 105 may be written to, i.e., a logic value may be stored in the memory cells 105. The column decoders 130 may accept data to be written to the memory cells 105, e.g., inputs 135. The ferroelectric memory cells 105 may be written to by applying a voltage across the ferroelectric capacitors. This process is discussed in more detail below.

[0042] In some memory architectures, accessing the memory cells 105 may degrade or destroy the stored logic state, and a rewrite or refresh operation may be performed to return the memory cells 105 to the original logic state. In DRAM, for example, the capacitors may be partially or completely discharged during a sensing operation, thereby destroying the stored logic state. Thus, the logic state may be rewritten after the sensing operation. Additionally, activating a single word line 110 may cause all memory cells in a row to discharge, and therefore, some or all memory cells 105 in a row may need to be rewritten.

[0043] Some memory architectures, including DRAM, may lose their stored states over time unless periodically refreshed by an external power source. For example, a charged capacitor may become discharged over time through leakage current, causing the stored information to be lost. The refresh rate of these so-called volatile memory devices may be relatively high, e.g., tens of refresh operations per second for a DRAM array, which may result in significant power consumption. As memory arrays become larger, increased power consumption may inhibit the deployment or operation of the memory arrays (e.g., power supply, heat generation, material limitations, etc.), particularly for mobile devices that rely on limited power sources such as batteries. As discussed below, the ferroelectric memory cell 105 may have beneficial properties that may result in improved performance relative to other memory architectures.

[0044] The memory controller 140 may control the operation (e.g., reading, writing, rewriting, refreshing, etc.) of the memory cells 105 through various components such as the row decoder 120, the column decoder 130, and the sensing component 125. The memory controller 140 may generate row address signals and column address signals in order to activate the desired word lines 110 and digit lines 115. The memory controller 140 may also generate and control various voltage potentials used during the operation of the memory array 100. In general, the magnitude, shape, or duration of the applied voltages discussed herein may be adjusted or varied and may be different for various operations used to operate the memory array 100. In addition, one, multiple, or all memory cells 105 within the memory array 100 may be accessed simultaneously; for example, multiple or all cells of the memory array 100 may be accessed simultaneously during a reset operation in which all memory cells 105 or groups of memory cells 105 are set to a single logic state.

[0045] Figure 2 An example circuit 200 is described that includes a memory cell 105, which may be a component of a device having memory board partitioning, according to various embodiments of the present invention. The circuit 200 includes a memory cell 105-a, a word line 110-a, a digit line 115-a, and a sensing component 125-a, which may be respectively as described in reference to Figure 1 An example of a memory cell 105, word line 110, digit line 115, and sense component 125 is described. Memory cell 105-a may include a logic storage component, such as a capacitor 205 having a first plate, a cell plate 230, and a second plate, a cell bottom 215. The cell plate 230 and the cell bottom 215 may be capacitively coupled via a ferroelectric material placed therebetween. The orientation of the cell plate 230 and the cell bottom 215 may be flipped without changing the operation of the memory cell 105-a. Circuit 200 also includes a selection component 220 and a reference signal 225. In Figure 2 In the example of , cell plate 230 is accessible via plate line 210 and cell bottom 215 is accessible via digit line 115 - a. As described above, various states can be stored by charging or discharging capacitor 205 .

[0046] The stored state of capacitor 205 may be read or sensed by operating various elements represented in circuit 200. Capacitor 205 may be in electronic communication with digital line 115-a. For example, capacitor 205 may be isolated from digital line 115-a when selection component 220 is deactivated, and capacitor 205 may be connected to digital line 115-a when selection component 220 is activated. Activating selection component 220 may be referred to as selecting memory cell 105-a. In some cases, selection component 220 is a transistor and its operation is controlled by applying a voltage to the transistor gate, where the voltage magnitude is greater than the threshold magnitude of the transistor. Word line 110-a may activate selection component 220; for example, the voltage applied to word line 110-a is applied to the transistor gate, thereby connecting capacitor 205 to digital line 115-a. In an alternative embodiment, the positions of select component 220 and capacitor 205 may be swapped such that select component 220 is connected between plate line 210 and cell plate 230 and such that capacitor 205 is between digit line 115-a and another terminal of select component 220. In this embodiment, select component 220 may remain in electronic communication with digit line 115-a through capacitor 205. This configuration may be associated with alternative timing and biasing for read and write operations.

[0047] Due to the presence of ferroelectric material between the plates of capacitor 205, and as discussed in more detail below, capacitor 205 may not discharge after being connected to digit line 115-a. In one approach, to sense the logic state stored by ferroelectric capacitor 205, word line 110-a may be biased to select memory cell 105-a, and a voltage may be applied to plate line 210. In some cases, digit line 115-a is virtually grounded before biasing plate line 210 and word line 110-a, and is then isolated from the virtual ground (i.e., "floating"). Biasing plate line 210 may cause a voltage difference across capacitor 205 (e.g., plate line 210 voltage minus digit line 115-a voltage). The voltage difference may produce a change in the stored charge on capacitor 205, wherein the magnitude of the change in the stored charge may depend on the initial state of capacitor 205, for example, whether the initial state stores a logic 1 or a logic 0. This may induce a change in the voltage of digit line 115-a based on the charge stored on capacitor 205. Operating the memory cell 105-a by changing the voltage to the cell plate 230 may be referred to as "moving the cell plate."

[0048] The change in voltage of digit line 115-a may depend on its intrinsic capacitance. As charge flows through digit line 115-a, some finite charge may be stored in digit line 115-a and the resulting voltage depends on the intrinsic capacitance. The intrinsic capacitance may depend on the physical properties of digit line 115-a, including size. Digit line 115-a may connect many memory cells 105, so digit line 115-a may have a length that causes a non-negligible capacitance (e.g., on the order of pico-farads (pF) or femto-farads (fF)). The resulting voltage of digit line 115-a may then be compared to a reference (e.g., the voltage of reference signal 225 line) by sensing component 125-a in order to determine the stored state of memory cell 105-a.

[0049] The sensing component 125-a may include various transistors or amplifiers to detect and amplify the difference in the signal, which may be referred to as latching. The sensing component 125-a may include a sense amplifier that receives and compares the voltage of the digital line 115-a and the reference signal 225, which may be a reference voltage. The sense amplifier output may be driven to a higher (e.g., positive) or lower (e.g., negative or ground) supply voltage based on the comparison. For example, if the digital line 115-a has a higher voltage than the reference signal 225, the sense amplifier output may be driven to the positive supply voltage. In some cases, the sense amplifier may additionally drive the digital line 115-a to the supply voltage. The sensing component 125-a may then latch the output of the sense amplifier and / or the voltage of the digital line 115-a, which may be used to determine the stored state in the memory cell 105-a, e.g., a logical 1. Alternatively, if the digital line 115-a has a lower voltage than the reference signal 225, the sense amplifier output may be driven to a negative or ground voltage. Sensing component 125-a may similarly latch the sense amplifier output to determine the stored state, eg, a logical 0, in memory cell 105-a. Figure 1 , the latched logic state of memory cell 105 - a may then be output, for example, by column decoder 130 as output 135 .

[0050] To write to memory cell 105-a, a voltage may be applied across capacitor 205. Various methods may be used. In one example, select component 220 may be activated via word line 110-a so as to electrically connect capacitor 205 to digit line 115-a. A voltage may be applied across capacitor 205 by controlling the voltage of cell plate 230 (via plate line 210) and cell bottom 215 (via digit line 115-a). To write a logical 0, cell plate 230 may be taken high, i.e., a positive voltage may be applied to plate line 210, and cell bottom 215 may be taken low, e.g., virtually grounded or a negative voltage applied to digit line 115-a. The reverse process is performed to write a logical 1, where cell plate 230 is taken low and cell bottom 215 is taken high.

[0051] Figure 3 An example of nonlinear electrical properties with hysteresis curves 300-a and 300-b for a memory cell in a device with memory plate partitioning according to various embodiments of the present invention is illustrated. Hysteresis curves 300-a and 300-b illustrate example ferroelectric memory cell write and read processes, respectively. Hysteresis curve 300 depicts the variation of a voltage difference V stored in a ferroelectric capacitor (e.g., Figure 2 The charge Q on capacitor 205).

[0052] refer to Figure 3 The described nonlinear characteristics may give rise to the beneficial nonvolatile memory properties described herein. However, operating a ferroelectric cell having such properties may imply considerations involving powering the plates, parasitic capacitances, and the like. Thus, in operating a ferroelectric cell, a cell that implements such operation may be considered (an example of which is referenced in Figure 3 described) and characteristics of circuit components (e.g., segmented or unsegmented boards).

[0053] Ferroelectric materials are characterized by spontaneous electric polarization, that is, they maintain a non-zero electric polarization in the absence of an electric field. Example ferroelectric materials include barium titanate (BaTiO3), lead titanate (PbTiO3), lead zirconate titanate (PZT), and strontium bismuth tantalate (SBT). The ferroelectric capacitors described herein may include these or other ferroelectric materials. The electric polarization within the ferroelectric capacitor produces a net charge at the surface of the ferroelectric material and attracts opposite charges through the capacitor terminals. Therefore, the charge is stored at the interface between the ferroelectric material and the capacitor terminals. Because the electric polarization can be maintained for a relatively long time, or even indefinitely, in the absence of an externally applied electric field, charge leakage can be significantly reduced compared to capacitors used in DRAM arrays, for example. This can reduce the need to perform refresh operations as described above for some DRAM architectures.

[0054] The hysteresis curve 300 can be understood from the perspective of a single terminal of a capacitor. By way of example, if the ferroelectric material has a negative polarization, positive charge accumulates at the terminal. Similarly, if the ferroelectric material has a positive polarization, negative charge accumulates at the terminal. In addition, it should be understood that the voltage in the hysteresis curve 300 represents the voltage difference across the capacitor and is directional. For example, a positive voltage can be achieved by applying a positive voltage to the terminal in question (e.g., the cell plate 230) and maintaining the second terminal (e.g., the cell bottom 215) at ground (or approximately zero volts (0V)). A negative voltage can be applied by maintaining the terminal in question at ground and applying a positive voltage to the second terminal, that is, a positive voltage can be applied to negatively polarize the terminal in question. Similarly, two positive voltages, two negative voltages, or any combination of positive and negative voltages can be applied to the appropriate capacitor terminals to produce the voltage difference shown in the hysteresis curve 300.

[0055] As depicted in hysteresis curve 300-a, the ferroelectric material can maintain either positive polarization or negative polarization under zero voltage difference, resulting in two possible charged states: charge state 305 and charge state 310. Figure 3 In the example of , charge state 305 represents a logical 0 and charge state 310 represents a logical 1. In some examples, the logic values ​​of the corresponding charge states can be inverted to accommodate other schemes for operating the memory cell.

[0056] The electrical polarization of the ferroelectric material and thus the charge on the capacitor terminals can be controlled by applying a voltage, so that a logical 0 or 1 can be written to the memory cell. For example, applying a net positive voltage 315 across the capacitor causes charge accumulation until charge state 305-a is reached. After removing voltage 315, charge state 305-a follows path 320 until it reaches charge state 305 at zero voltage potential. Similarly, charge state 310 is written by applying a net negative voltage 325, which causes charge state 310-a. After removing negative voltage 325, charge state 310-a follows path 330 until it reaches charge state 310 at zero voltage. Charge states 305 and 310 may also be referred to as remanent polarization (Pr) values, i.e., the polarization (or charge) remaining after removing an external bias (e.g., voltage). The coercive voltage is the voltage when the charge (or polarization) is zero.

[0057] To read or sense the stored state of a ferroelectric capacitor, a voltage may be applied across the capacitor. In response, the stored charge Q changes, and the extent of the change depends on the initial charge state, i.e., the final stored charge (Q) depends on whether the charge state 305-b or 310-b was initially stored. For example, hysteresis curve 300-b illustrates two possible stored charge states 305-b and 310-b. As can be seen in reference Figure 2Voltage 335 is applied across the capacitor as discussed. Although depicted as a positive voltage, voltage 335 may be negative. In response to voltage 335, charge state 305-b may follow path 340. Similarly, if charge state 310-b was initially stored, it follows path 345. The final positions of charge state 305-c and charge state 310-c depend on a number of factors, including the particular sensing scheme and circuitry.

[0058] In some cases, the final charge may depend on the intrinsic capacitance of the digit line connected to the memory cell. For example, if a capacitor is electrically connected to a digit line and voltage 335 is applied, the voltage of the digit line may rise due to its intrinsic capacitance. Therefore, the voltage measured at the sensing component may not be equal to voltage 335, and may instead depend on the voltage of the digit line. Therefore, the position of the final charge states 305-c and 310-c on the hysteresis curve 300-b may depend on the capacitance of the digit line and may be determined by load line analysis, i.e., charge states 305-c and 310-c may be defined relative to the capacitance of the digit line. Therefore, the voltage of the capacitor, voltage 350 or voltage 355, may be different and may depend on the initial state of the capacitor.

[0059] By comparing the digital line voltage with a reference voltage, the initial state of the capacitor can be determined. The digital line voltage can be the difference between voltage 335 and the final voltage across the capacitor, that is, voltage 350 or voltage 355, that is, (voltage 335-voltage 350) or (voltage 335-voltage 355). The reference voltage can be generated so that its amplitude is between two possible voltages of two possible digital line voltages in order to determine the stored logic state, that is, whether the digital line voltage is higher or lower than the reference voltage. For example, the reference voltage can be the average of the two quantities (voltage 335-voltage 350) and (voltage 335-voltage 355). After comparison by the sensing component, it can be determined whether the sensed digital line voltage is higher or lower than the reference voltage, and the stored logic value (that is, logic 0 or 1) of the ferroelectric memory cell can be determined.

[0060] As discussed above, reading a memory cell that does not use a ferroelectric capacitor can degrade or destroy the stored logic state. However, a ferroelectric memory cell can maintain the initial logic state after a read operation. For example, if charge state 305-b is stored, the charge state can follow path 340 to charge state 305-c during a read operation, and after removing voltage 335, the charge state can return to initial charge state 305-b by following path 340 in the reverse direction.

[0061] Figure 4An example memory array 400 having a memory plane partition according to various embodiments of the present invention is illustrated. The memory array 400 can include a plurality of plane portions 405 separated by a plurality of partition lines 410. In some embodiments, the partition lines 410 can extend in a first direction. In some cases, the first direction can be a vertical direction. Each of the plurality of plane portions 405 can include a plurality of memory cells, which can be as described in reference Figure 1 The memory unit 105 described or as referenced Figure 2 Examples of aspects of the memory cell 105-a described herein. Each of the memory cells may be accessed by applying voltages to a word line (not shown) and a digit line 415, as shown in reference Figure 1 The word lines and digit lines 415 may be as described in reference Figure 1 The example of word line 110 and digit line 115 described above. Figure 4 4. A single line is shown coupled to each board portion 405, but those skilled in the art will appreciate that each board portion 405 may be coupled to multiple digit lines 415, and each line may therefore represent multiple digit lines. For example, in some instances each board portion 405 may have 256 digit lines 415 coupled thereto.

[0062] Each of the plurality of plate sections 405 may be activated by a plate driver assembly 420. The plate driver assembly 420 may include a plurality of plate drivers 425, wherein each plate driver 425 is configured to activate one of the plurality of plate sections 405. Each of the plate drivers 425 may be connected to the plate section 405 via a plate wire 430. The plate wire 430 may be as described with reference to Figure 2 4. The plate driver 425 may activate the plate portion 405 by applying a voltage to the corresponding plate line 430. In some cases, the plate driver component 420 may be located at a different position among possible positions relative to the sensing component 445, the column decoder 440, or both. In some embodiments, the plate driver component 420 may be located at a different position than the sensing component 445, the column decoder 440, or both. Figure 4 In some other embodiments, the plate driver assembly 420 can be located on the same side of the memory array 400 as the sense assembly 445 and / or the column decoder 440. In some other embodiments, the plate driver assembly 420 can be located on the opposite side of the memory array 400 as the sense assembly 445 and / or the column decoder 440.

[0063] The memory array 400 may include a number of additional components, including a memory controller 435, a row decoder (not shown), a column decoder 440, and a sensing component 445. The memory controller 435, the row decoder, the column decoder 440, and the sensing component 445 may be respectively as described in reference to Figure 1Examples of aspects of the memory controller 140, row decoder 120, column decoder 130, and sense component 125 are described. In some examples, the sense component 125 can include a multiplexer coupled to a plurality of sense amplifiers to select a digit line 415 from a selected plate portion 405.

[0064] When reading information from or writing information to the memory array, the memory controller 435 may identify a target memory cell from a plurality of memory cells in the memory array 400. The target memory cell may be, for example, a memory cell containing information that a user desires to read from the memory array 400 or an unused memory cell that may be used to store information that a user desires to write to the memory array 400. The memory controller 435 may identify the location of the target memory cell in the memory array 400. The memory controller 435 may then cause the plate driver assembly 420 to activate a single plate portion 405 corresponding to the location of the target memory cell. In some embodiments, the plate driver assembly 420 may activate the plate portion 405 by using one of the plurality of plate drivers 425 to apply a voltage to the plate line 430 corresponding to the location of the target memory cell. In some embodiments, the plate driver assembly 420 may not activate other plate portions 405 other than the plate portion 405 corresponding to the location of the target memory cell. That is, the plate driver assembly 420 may only activate the plate portion 405 corresponding to the location of the target memory cell, but may not activate any other plate portions. The plate driver 420 may set the other plate portions 405 to a deactivated state (which may include maintaining those plate portions 405 in the deactivated state). The memory controller 435 may cause the row decoder to activate a selection component (not shown) corresponding to the location of the target memory cell to connect the target memory cell to one of the digit lines 415. The selection component may be as described in reference Figure 2 The memory controller may then read from or write to the target memory cell via the column decoder 440 and the sense component 445, as described with reference to FIG. Figure 1 as described.

[0065] In some examples, the memory array 400 may include one or more dummy lines. For example, a plurality of word lines in the memory array 400 may include one or more dummy word lines. The dummy word line may be located at the edge of at least one of the adjacent plate portions 405. The dummy word line may be electrically isolated from the memory cells of the memory array 400. For example, each of the dummy word lines may not be connected to any of the memory cells on any of the plate portions 405. The dummy word lines may be used to solve design problems. For example, if the cell pitch of the plate is 2F, the plate line spacing may be increased from F to 3F by adding a dummy word line. In some examples, a plurality of digital lines may similarly include one or more dummy digital lines located at the edge of at least one of the adjacent plate portions 405 and electrically isolated from the memory cells of the memory array 400.

[0066] Figure 5 An example timing diagram 500 is illustrated for a memory array with memory plane partitioning according to various embodiments of the present invention. The memory array may be as described in reference Figure 4 An example of aspects of memory array 400 is described.

[0067] Timing diagram 500 includes a plate signal 505 corresponding to a first voltage at a plate line, which may be a reference Figure 4 The timing diagram further includes a word line signal 510 corresponding to a second voltage at the word line, which may be as described in reference Figure 1 The timing diagram further includes a digit line signal 515 corresponding to a third voltage at the digit line, which may be as described in reference Figure 4 4. For example, the digital line signal 515 may indicate that the Figure 6 The timing diagram also includes an input / output signal 520 corresponding to a fourth voltage at the input / output of the sensing component, which may be as shown in FIG. Figure 4 For example, the input / output signal 520 may indicate that Figure 6 The voltage shown in represents the voltage at the position of the digit line B (DB).

[0068] At time t0, the plate portion is activated by applying a voltage to the plate line. Accordingly, the plate signal 505 increases based on the voltage applied to the plate line by, for example, a plate driver. At time t1, a voltage is applied to the word line, which increases the second voltage on the word line signal 510. Applying the voltage to the word line causes the memory cell to be connected to the digit line, as shown in FIG. Figure 2As described. Digital line signal 515 increases accordingly at time t2. The sensing component then compares the third voltage of digital line signal 515 with the reference signal and determines that the third voltage corresponds to a logic "0" at time t3. The read operation is then completed. The plate is deactivated by reducing the voltage of plate signal 505 to zero at time t4, and word line signal 510 is similarly reduced to zero at time t5. Thereafter, data can be read from or written to another memory cell in the memory array.

[0069] In some examples, plate lines coupled to non-addressed lines (not shown) may not be biased when accessing selected cells. Accordingly, power consumption can be reduced compared to systems in which non-addressed lines are biased because power consumption is limited to biasing of the selected plate lines while avoiding power consumption that would otherwise be involved in biasing plate lines coupled to non-addressed lines. In some embodiments, the lack of biasing of non-addressed cells can also reduce electrical interference with non-addressed cells.

[0070] Figure 6 An example memory array 600 having a memory plane partition according to various embodiments of the invention is illustrated. The memory array 600 may include a plurality of plane portions 605 separated by a plurality of partition lines, the plurality of partition lines including a first group 610 of partition lines extending in a first direction (e.g., a vertical direction) and a second group 615 of partition lines extending in a second direction (e.g., a horizontal direction). Each of the plurality of plane portions 605 may include a plurality of memory cells, which may be as described in reference to Figure 1 The memory unit 105 described or as referenced Figure 2 An example of aspects of the memory cell 105-a described herein. The memory cell may be accessed by applying voltages to the word line and the digit line, as described with reference to Figure 1 as described.

[0071] Each of the plurality of plate sections 605 may be activated by a plate driver assembly 620. The plate driver assembly 620 may include a plurality of plate drivers 625, wherein each plate driver 625 is coupled and configured to activate one of the plurality of plate sections 605. Each of the plate drivers 625 may be connected to the plate section 605 via a plate wire 630. The plate wire 630 may be as described with reference to Figure 2 The plate driver 625 can activate the plate portion 605 by applying a voltage to the corresponding plate line 630. In some cases, the plate driver component 620 can be located at different positions among the possible positions relative to the sensing component 635. In some embodiments, the plate driver component 620 can be as Figure 6In some other embodiments, the plate driver assembly 620 can be located on the same side of the memory array 600 and the sensing assembly 635. In some other embodiments, the plate driver assembly 620 can be located on the opposite side of the memory array 600 and the sensing assembly 635.

[0072] The memory array 600 may include additional components, such as a sensing component 635 and a row decoder, a column decoder, and a memory controller, such as the row decoder 120, the column decoder 130, and the memory controller 140, respectively, as described with reference to FIG. Figure 1 Data may be written to and read from the memory array 600, as described with reference to Figure 4 However, the power consumption of memory array 600 may be reduced compared to the power consumption of memory array 400. For example, the power consumption of memory array 600 may be approximately 25% of the power consumption of memory array 400.

[0073] Figure 7 An example memory array 700 having a memory plane partition according to various embodiments of the invention is illustrated. The memory array 700 may include a plurality of plane portions 705 separated by a plurality of partition lines, the plurality of partition lines including a first group 710 of partition lines extending in a first direction (e.g., a vertical direction) and a second group 715 of partition lines extending in a second direction (e.g., a horizontal direction). Each of the plurality of plane portions 705 may include a plurality of memory cells, which may be as described in reference to Figure 1 The memory unit 105 described or as referenced Figure 2 An example of aspects of the memory cell 105-a described herein. The memory cell may be accessed by applying voltages to the word line and the digit line, as described with reference to Figure 1 as described.

[0074] Each of the plurality of panel sections 705 can be activated by a panel driver assembly 720. The panel driver assembly 720 can include a plurality of panel drivers 725, wherein each panel driver 725 is coupled and configured to activate one of the plurality of panel sections 705. Each of the panel drivers 725 can be connected to a number of panel sections 705. For example, each panel driver 725 can be coupled to a panel driver line 730. The panel driver line 730 can be coupled to a panel line 735 on the plurality of panel sections 705. The panel line 735 can be as described in reference Figure 2705. An example of an aspect of the plate line 210 described herein. By applying a voltage to the plate driver line 730, the plate driver 725 can activate each of the plate portions 705 to which it is coupled. The plate driver line 730 can be coupled to a plate driver line 730 connected to a plate portion 705 in each row 740 of the memory array 600. In some examples, the plate driver line 730 can be coupled to the plate portions 705 in at least two columns 745. For example, the plate driver line 730 can be coupled to the plate portions 705 in each column 745 such that applying a voltage to the plate driver line 730 will activate the plate portions 705 in each column 745.

[0075] The memory array 700 may include additional components, such as a sensing component, a row decoder, a column decoder, and a memory controller, which components may be examples of aspects of the sensing component 125, the row decoder 120, the column decoder 130, and the memory controller 140, respectively, as described with reference to FIG. Figure 1 Data may be written to and read from the memory array 700, as described with reference to Figure 1 and 4 as described.

[0076] In some examples, the memory array 700 may include one or more dummy lines. For example, a plurality of word lines in the memory array 700 may include one or more dummy word lines. The dummy word line may be located at the edge of at least one of the adjacent plate portions 705. The dummy word line may be electrically isolated from the memory cells of the memory array 700. For example, each of the dummy word lines may not be connected to any of the memory cells on any of the plate portions 705. The dummy word lines may be used to solve design problems. For example, if the cell spacing of the plate is 2F, the plate line spacing may be increased from F to 3F by adding dummy word lines. In some examples, a plurality of digital lines may similarly include one or more dummy digital lines located at the edge of at least one of the adjacent plate portions 705 and electrically isolated from the memory cells of the memory array 700.

[0077] Figure 8 An example circuit diagram 800 is illustrated for a memory cell in a memory array with memory plane partitioning according to various embodiments of the invention. The circuit diagram may include a memory cell 805 including a memory plane 810 and a selection component 815. The memory cell 805 may be coupled to a word line 820 and a digit line 825. The memory cell 805, the word line 820, and the digit line 825 may be as described in reference to Figure 1 105, word lines 110, and digit lines 115 are examples of aspects of the described memory cells 105. The memory board 810 may be as described in reference Figure 4Examples of aspects of the described board portion 405. The selection component 815 may be referenced Figure 2 An example of aspects of the selection component 220 is described.

[0078] When the memory board 810 is activated, parasitic capacitance may be generated. For example, a first parasitic capacitance 830 may be generated between a digital line 825 and a memory cell 805, a second parasitic capacitance 835 may be generated between a word line 820 and the memory cell 805, and a third parasitic capacitance 840 may be generated between the word line 820 and the digital line 825. When the memory board 810 is activated, a first parasitic capacitance 830, a second parasitic capacitance 835, and a third parasitic capacitance 840 may be generated for each memory cell coupled to the memory board 810. The combination of the first parasitic capacitance 830, the second parasitic capacitance 835, and the third parasitic capacitance 840 may be regarded as a parasitic load of the memory board 810. Power consumption may be reduced by reducing the number of memory cells coupled to the activated memory board, and thereby reducing the number of parasitic loads.

[0079] For example, an electronic memory device having 4,096 memory cells may have a single memory board. In this example, when the memory board is activated, the memory device may have 4,096 parasitic loads. In some other examples, the memory device may have four separate memory boards as described, for example, with reference to Figure 4 In such an example, when one of the four memory boards is activated, the memory device may have 1,024 parasitic loads, reducing power consumption due to parasitic capacitance by 75% compared to using a single board. The other three memory boards are not activated. In some other examples, the memory device may have sixteen separate memory boards, such as, for example, referring to Figure 6 In such an example, when one of the sixteen memory boards is activated, the memory device may have 256 parasitic loads, and therefore the power consumption due to parasitic capacitance will be 1 / 16 of the power consumption of a memory device with a single board. The other fifteen memory boards are not activated.

[0080] Fig. 9 A block diagram 900 of a memory controller 915 is shown to support operation of a device having memory plane partitioning according to an embodiment of the present invention. The memory controller 915 may be a reference Figure 1 or Fig.101 or both. The memory controller 915 may include a bias component 920, a timing component 925, a target memory cell locator 930, a plate driver activation component 935, a word line selector 940, a memory cell reader 945, and a memory cell writer 950. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0081] The target memory cell locator 930 may determine the location of the target memory cell. The target memory cell may be the memory cell 105 described with reference to the previous figures.

[0082] The plate driver activation component 935 may activate a plate portion corresponding to the location of the target memory cell, the plate portion being separated from a set of other plate portions by a split line, the split line comprising a first set of split lines extending in a perpendicular direction. The plate driver activation component 935 may activate the plate portion by sending an instruction to the plate driver to apply a first voltage to a plate line coupled to the plate portion. The plate driver activation component 935 may activate a plate portion corresponding to the location of the target memory cell, the plate portion being separated from a set of other plate portions by a split line, the split line comprising a first set of split lines extending in a first direction and a second set of split lines extending in a second direction perpendicular to the first direction. The plate driver activation component 935 may activate the plate portion by sending an instruction to the plate driver to apply a first voltage to a plate line coupled to the plate portion. In some examples, no voltage may be applied to a plate portion associated with a non-addressed memory cell.

[0083] The word line selector 940 may apply a first voltage to a word line coupled to a memory cell disposed on the plate portion to connect the target memory cell to a digit line extending in a first direction.

[0084] The memory cell reader 945 may determine a logic value associated with the target memory cell based on the second voltage on the digit line.

[0085] The memory cell writer 950 may apply a second voltage to the digit line to set a logic value associated with a target memory cell.

[0086] Fig.10A diagram of a system 1000 including a device 1005 with memory board partitioning according to an embodiment of the invention is shown. The device 1005 may include components for two-way voice and data communications, including components for transmitting and receiving communications, including a memory controller 1015, a memory unit 1020, a basic input / output system (BIOS) component 1025, a processor 1030, an I / O controller 1035, and peripheral components 1040. These components may communicate electronically via one or more buses (e.g., bus 1010).

[0087] The memory controller 1015 may be as described above with reference to, for example, Figure 1 Examples of components of the memory controller 140 described in or including the above references such as Figure 1 9. Memory cell 1020 may store information (ie, in the form of logic states) as described herein.

[0088] BIOS component 1025 is a software component including BIOS operating as firmware that can initialize and run various hardware components. BIOS component 1025 can also manage the data flow between the processor and various other components such as peripheral components, input / output control components, etc. BIOS component 1025 can include a program or software stored in a read-only memory (ROM), flash memory, or any other non-volatile memory.

[0089] The processor 1030 may include an intelligent hardware device (e.g., a general purpose processor, a DSP, a central processing unit (CPU), a microcontroller, an ASIC, an FPGA, a programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof). In some cases, the processor 1030 may be configured to operate the memory array using a memory controller. In other cases, the memory controller may be integrated into the processor 1030. The processor 1030 may be configured to execute computer readable instructions stored in the memory to perform various functions (e.g., functions or tasks that support memory board partitioning to reduce operating power).

[0090] I / O controller 1035 can manage input and output signals for device 1005. I / O controller 1035 can also manage peripheral devices that are not integrated into device 1005. In some cases, I / O controller 1035 can represent a physical connection or port to an external peripheral device. In some cases, I / O controller 1035 can utilize, for example, MS- MS- 1005 . In some cases, the I / O controller 1035 may be implemented as part of the processor. In some cases, a user may interact with the device 1005 via the I / O controller 1035 or via hardware components controlled by the I / O controller 1035.

[0091] Peripheral components 1040 may include any input or output device, or an interface for such a device. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot, such as a Peripheral Component Interconnect (PCI) or Accelerated Graphics Port (AGP) slot.

[0092] Input 1045 may represent a device or signal external to device 1005 that provides input to device 1005 or its components. This may include a user interface or an interface with other devices or between other devices. In some cases, input 1045 may be managed by I / O controller 1035 and may interact with device 1005 via peripheral components 1040.

[0093] Output 1050 may also represent a device or signal external to device 1005 that is configured to receive output from device 1005 or any of its components. Examples of output 1050 may include a display, an audio speaker, a printing device, another processor or printed circuit board, etc. In some cases, output 1050 may be a peripheral element that interfaces with device 1005 via peripheral components 1040. In some cases, output 1050 may be managed by I / O controller 1035.

[0094] The components of device 1005 may include circuits designed to perform their functions. This may include various circuit elements configured to perform the functions described herein, such as conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements. Device 1005 may be a computer, server, laptop, notebook, tablet, mobile phone, wearable electronic device, personal electronic device, or the like. Alternatively, device 1005 may be a portion or aspect of such a device.

[0095] Fig.11 1 is a flowchart illustrating a method 1100 for operating a device having memory board partitioning according to an embodiment of the present invention. The operations of the method 1100 may be implemented by the memory controller 140 or its components as described herein. For example, the operations of the method 1100 may be implemented by the memory controller 140 or its components as described in reference to Figure 1 and 10The memory controller 140 described herein performs. In some examples, the memory controller 140 may execute a set of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the memory controller 140 may use dedicated hardware to perform aspects of the functions described below.

[0096] In some cases, the method may also include determining the location of the target memory cell. In some cases, the method may also include activating a plate portion corresponding to the location of the target memory cell by a plate driver, the plate portion being separated from a plurality of other plate portions by a partition line, the partition line comprising a first set of partition lines extending in a vertical direction. In some cases, the method may also include activating the plate portion, including applying a first voltage to a plate line coupled to the plate portion. In some cases, the method may also include applying the first voltage to a word line coupled to a memory cell disposed on the plate portion to connect the target memory cell to a digital line extending in a vertical direction. In some cases, the method may also include determining a logic value associated with the target memory cell based on a second voltage on the digital line. In some cases, the method may also include applying a second voltage to the digital line to set a logic value associated with the target memory cell.

[0097] At block 1105, the memory controller 140 may determine the location of the target memory cell. The operations of block 1105 may be performed according to the methods described herein. In some examples, aspects of the operations of block 1105 may be described by reference to Figure 4 , 6 , 7, 9 and 10 described in the target memory cell locator execution.

[0098] At block 1110, the memory controller 140 may activate a plate portion corresponding to the location of the target memory cell, the plate portion being separated from a plurality of other plate portions by a partition line, the partition line comprising a first set of partition lines extending in a vertical direction. The memory controller 140 may activate the plate portion by sending an instruction to a plate driver to apply a voltage to the plate portion corresponding to the location of the target memory cell. The operations of block 1110 may be performed according to the methods described herein. In some examples, aspects of the operations of block 1110 may be described by referring to Figure 4 , 6 , 7, 9 and 10 described board driver activation components are executed.

[0099] Fig.12 1 is a flowchart illustrating a method 1200 for operating a device having memory board partitioning according to an embodiment of the present invention. The operations of the method 1200 may be implemented by the memory controller 140 or its components as described herein. For example, the operations of the method 1200 may be implemented by the memory controller 140 or its components as described in reference to Figure 1The memory controller 140 described herein performs. In some examples, the memory controller 140 may execute a set of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the memory controller 140 may use dedicated hardware to perform aspects of the functions described below.

[0100] In some cases, the method may also include determining a location of a target memory cell. In some cases, the method may also include activating, by a plate driver, a plate portion corresponding to the location of the target memory cell, the plate portion being separated from a plurality of other plate portions by a partition line, the partition lines comprising a first set of partition lines extending in a vertical direction. In some cases, the method may also include applying a first voltage to a word line coupled to a memory cell disposed on the plate portion to connect the target memory cell to a digit line extending in the vertical direction.

[0101] At block 1205, the memory controller 140 may determine the location of the target memory cell. The operations of block 1205 may be performed according to the methods described herein. In some examples, aspects of the operations of block 1205 may be described by referring to Figure 4 , 6 , 7, 9 and 10 described in the target memory cell locator execution.

[0102] At block 1210, the memory controller 140 may activate a plate portion corresponding to the location of the target memory cell, the plate portion being separated from a plurality of other plate portions by a partition line, the partition line comprising a first set of partition lines extending in a vertical direction. The memory controller 140 may activate the plate portion by sending an instruction to a plate driver to apply a voltage to the plate portion corresponding to the location of the target memory cell. The operations of block 1210 may be performed according to the methods described herein. In some examples, aspects of the operations of block 1210 may be described by referring to Figure 4 , 6 , 7, 9 and 10 described board driver activation components are executed.

[0103] At block 1215, the memory controller 140 may apply a first voltage to a word line coupled to a memory cell disposed on the plate portion to connect the target memory cell to a digit line extending in a vertical direction. The operations of block 1215 may be performed according to the methods described herein. In some examples, aspects of the operations of block 1215 may be described by referring to Figure 4 , 6 , 7, 9 and 10 described word line selectors are performed.

[0104] Fig.131 is a flowchart illustrating a method 1300 for operating a device having memory board partitioning according to an embodiment of the present invention. The operations of the method 1300 may be implemented by the memory controller 140 or its components as described herein. For example, the operations of the method 1300 may be implemented by the memory controller 140 or its components as described in reference to Figure 1 , 4 , 6, 7, 9 and 10. In some examples, the memory controller 140 may execute a collection of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the memory controller 140 may use dedicated hardware to perform aspects of the functions described below.

[0105] In some cases, the method may also include determining the location of the target memory cell. In some cases, the method may also include activating a plate portion corresponding to the location of the target memory cell by a plate driver, the plate portion being separated from a plurality of other plate portions by a splitting line, the splitting line comprising a first set of splitting lines extending in a first direction and a second set of splitting lines extending in a second direction perpendicular to the first direction. In some cases, the method may also include activating the plate portion, including applying a first voltage to a plate line coupled to the plate portion. In some cases, the method may also include applying the first voltage to a word line coupled to a memory cell disposed on the plate portion to connect the target memory cell to a digital line extending in the first direction. In some cases, the method may also include determining a logic value associated with the target memory cell based on a second voltage on the digital line. In some cases, the method may also include applying a second voltage to the digital line to set a logic value associated with the target memory cell.

[0106] At block 1305, the memory controller 140 may determine the location of the target memory cell. The operations of block 1305 may be performed according to the methods described herein. In some examples, aspects of the operations of block 1305 may be described by referring to Figure 4 , 6 , 7, 9 and 10 described in the target memory cell locator execution.

[0107] At block 1310, the memory controller 140 may activate a plate portion corresponding to the location of the target memory cell, the plate portion being separated from a plurality of other plate portions by partition lines, the partition lines comprising a first set of partition lines extending in a first direction and a second set of partition lines extending in a second direction perpendicular to the first direction. The memory controller 140 may activate the plate portion by sending an instruction to a plate driver to apply a voltage to the plate portion corresponding to the location of the target memory cell. The operations of block 1310 may be performed according to the methods described herein. In some examples, aspects of the operations of block 1310 may be performed as described in reference to Figure 4, 6 , 7, 9 and 10 described board driver activation components are executed.

[0108] Fig.14 1 is a flowchart illustrating a method 1400 for operating a device having memory board partitioning according to an embodiment of the present invention. The operations of the method 1400 may be implemented by the memory controller 140 or its components as described herein. For example, the operations of the method 1400 may be implemented by the memory controller 140 or its components as described herein. Figure 4 , 6 , 7, 9 and 10. In some examples, the memory controller 140 may execute a collection of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the memory controller 140 may use dedicated hardware to perform aspects of the functions described below.

[0109] In some cases, the method may also include determining a location of a target memory cell. In some cases, the method may also include activating, by a plate driver, a plate portion corresponding to the location of the target memory cell, the plate portion being separated from a plurality of other plate portions by partition lines, the partition lines comprising a first set of partition lines extending in a first direction and a second set of partition lines extending in a second direction perpendicular to the first direction. In some cases, the method may also include applying a first voltage to a word line coupled to a memory cell disposed on the plate portion to connect the target memory cell to a digit line extending in the first direction.

[0110] At block 1405, the memory controller 140 may determine the location of the target memory cell. The operations of block 1405 may be performed according to the methods described herein. In some examples, aspects of the operations of block 1405 may be described by referring to Figure 4 , 6 , 7, 9 and 10 described in the target memory cell locator execution.

[0111] At block 1410, the memory controller 140 may activate a plate portion corresponding to the location of the target memory cell, the plate portion being separated from a plurality of other plate portions by partition lines, the partition lines comprising a first set of partition lines extending in a first direction and a second set of partition lines extending in a second direction perpendicular to the first direction. The memory controller 140 may activate the plate portion by sending an instruction to a plate driver to apply a voltage to the plate portion corresponding to the location of the target memory cell. The operations of block 1410 may be performed according to the methods described herein. In some examples, aspects of the operations of block 1410 may be performed as described in reference to Figure 4 , 6 , 7, 9 and 10 described board driver activation components are executed.

[0112] At block 1415, the memory controller 140 may apply a first voltage to a word line coupled to a memory cell disposed on the plate portion to connect the target memory cell to a digit line extending in the first direction. The operations of block 1415 may be performed according to the methods described herein. In some examples, aspects of the operations of block 1415 may be described by referring to Figure 4 , 6 , 7, 9 and 10 described word line selectors are performed.

[0113] An apparatus is described. In some examples, the apparatus may support means for determining a location of a target memory cell and means for activating, by a plate driver, a plate portion corresponding to the location of the target memory cell, the plate portion being separated from a plurality of other plate portions by partition lines, the partition lines comprising a first set of partition lines extending in a vertical direction.

[0114] In some examples, the apparatus may support means for setting a plurality of other plate portions to a deactivated state. In some examples, the means for activating the plate portion may include means for applying a first voltage to a plate line coupled to the plate portion. In some examples, the apparatus may support means for applying a first voltage to a word line coupled to a memory cell disposed on the plate portion to connect the target memory cell to a digital line extending in a vertical direction. In some examples, the apparatus may support means for determining a logic value associated with the target memory cell based on a second voltage on the digital line. In some examples, the apparatus may support means for applying a second voltage to the digital line to set a logic value associated with the target memory cell.

[0115] An apparatus is described. In some examples, the apparatus may support means for determining a location of a target memory cell and activating, by a plate driver, a plate portion corresponding to the location of the target memory cell, the plate portion being separated from a plurality of other plate portions by partition lines, the partition lines comprising a first set of partition lines extending in a first direction and a second set of partition lines extending in a second direction perpendicular to the first direction.

[0116] In some examples, the apparatus may support applying a first voltage to a plate line coupled to the plate portion when the plate portion is activated. In some examples, the apparatus may support means for applying the first voltage to a word line coupled to a memory cell disposed on the plate portion to connect the target memory cell to a digit line extending in a first direction. In some examples, the apparatus may support means for determining a logic value associated with the target memory cell based on a second voltage on the digit line. In some examples, the apparatus may support means for applying the second voltage to the digit line to set the logic value associated with the target memory cell.

[0117] An apparatus is described. In some examples, the apparatus may include a plurality of plate portions separated by a plurality of dividing lines, the plurality of dividing lines including a first set of dividing lines extending in a first direction and a second set of dividing lines extending in a second direction perpendicular to the first direction, a plate driver assembly including a plurality of plate drivers coupled to the plurality of plate portions, and a controller in electronic communication with the plate driver assembly. In some examples, the controller may support means for identifying a location of a target memory cell and means for activating one of the plurality of plate portions corresponding to the location of the target memory cell.

[0118] In some examples, the controller may support means for applying a first voltage to a word line coupled to a target memory cell to connect the target memory cell to a digit line. In some examples, the controller may support means for determining a logic value associated with the target memory cell based on a second voltage on the digit line. In some examples, the controller may support means for applying a second voltage to the digit line to set a logic value associated with the target memory cell.

[0119] The description herein provides examples and does not limit the scope, applicability or examples set forth in the claims. The functions and arrangements of the elements discussed may be changed without departing from the scope of the invention. Various examples may omit, replace or add various programs or components as appropriate. Furthermore, features described with respect to some examples may be combined in other examples.

[0120] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The terms "example," "exemplary," and "embodiment" as used herein mean "serving as an example, instance, or illustration," and are not "preferred" or "superior to other examples." For the purpose of providing an understanding of the described techniques, the specific embodiments include specific details. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid confusing the concepts of the described examples.

[0121] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes the similar components. When a first reference label is used in this specification, the description applies to any of the similar components having the same first reference label regardless of the second reference label.

[0122] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may show a signal as a single signal; however, those skilled in the art will understand that the signal may represent a bus of signals, where the bus may have a variety of bit widths.

[0123] As used herein, the term "virtual ground" refers to a node of a circuit that is maintained at a voltage of approximately zero volts (0V) but is not directly connected to ground. Accordingly, the voltage of the virtual ground may temporarily fluctuate and return to approximately 0V in a stable state. Virtual ground can be implemented using various electronic circuit elements such as a voltage divider consisting of an operational amplifier and a resistor. Other embodiments are also possible. "Virtual ground" or "virtual ground" refers to a connection to approximately 0V.

[0124] The term "electronic communication" refers to a relationship between components that supports the flow of electrons between the components. This may include a direct connection between the components or may include intermediate components. Components in electronic communication may actively exchange electrons or signals (e.g., in an energized circuit) or may not actively exchange electrons or signals (e.g., in a de-energized circuit), but may be configured and operable to exchange electrons or signals after the circuit is energized. By way of example, two components that are physically connected via a switch (e.g., a transistor) are in electronic communication regardless of the state of the switch (i.e., open or closed).

[0125] The term "isolation" refers to a relationship between components in which electrons are currently unable to flow between the components; if there is an open circuit between the components, the components are isolated from each other. For example, two components physically connected by a switch can be isolated from each other when the switch is open.

[0126] As used herein, the term "short" refers to a relationship between components in which a conductive path is established between the components via activation of a single intermediate component between the two components in question. For example, a first component shorted to a second component may exchange electrons with the second component when a switch between the two components is closed. Thus, shorting may be a dynamic operation that enables charge flow between components (or lines) in electronic communication.

[0127] The devices including the memory array 100 discussed herein may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of a semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0128] The transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most of the carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), then the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0129] The various illustrative blocks, components, and modules described in conjunction with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0130] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the function may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of the present invention and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software, hardware, firmware, hard wiring, or any combination of these executed by a processor. The features of the implementation functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations. Also, as used herein, included in the claims, the "or" used in the list of items (e.g., a list of items starting with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C).

[0131] Computer-readable media include both non-transitory computer storage media and communication media including any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code means in the form of instructions or data structures and can be accessed by a general or special-purpose computer or a general or special-purpose processor.

[0132] Also, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves are used to transmit software from a website, server, or other remote source, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves are included in the definition of media. As used herein, magnetic disks and optical disks include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where magnetic disks typically reproduce data magnetically, while optical discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0133] The description herein is provided to enable one skilled in the art to make or use the invention. Various modifications of the invention will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the invention. Therefore, the invention is not limited to the examples and designs described herein, but should be in the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: a plurality of plates arranged in rows and columns, wherein at least one memory cell is disposed on each of the plurality of plates; A panel driver is coupled to a panel driver line that traverses at least a portion of a first column of panels, wherein the panel driver line is coupled to a first panel in the first column of panels and to a second panel in a second column of panels.

2. The apparatus according to claim 1, wherein: The first plate is located in a first row of plates; the second plate is located in a second row of plates; and The plate driver line is coupled to the second plate via a plate line that traverses at least a portion of the second row of plates.

3. The apparatus according to claim 1, further comprising: A third plate in a third column of plates and a third row of plates, wherein the plate driver line is coupled to the third plate through a second plate line that traverses at least a portion of the third row of plates.

4. The apparatus according to claim 1, wherein: The second plate is traversed by a second plate driver line traversing the second column of plates, wherein the second plate driver line is coupled to a third plate in the second column of plates and to a fourth plate in the first column of plates.

5. The apparatus according to claim 4, wherein: The first plate and the fourth plate are located in different rows; and The second plate and the third plate are located in different rows.

6. The apparatus of claim 1, further comprising: a plurality of word lines extending in a first direction, wherein each word line of the plurality of word lines traverses a respective row of the plate; as well as A plurality of bit lines extend along a second direction, wherein each bit line of the plurality of bit lines traverses a corresponding column of the plate.

7. The apparatus of claim 1, wherein: the plate driver line is coupled to a set of plates including the first plate and the second plate; Each plate in the set of plates is located in a different row of plates; and Each plate in the set of plates is located in a different column of plates.

8. The apparatus of claim 1, further comprising: A plurality of additional panel drivers, each of the plurality of additional panel drivers being coupled to a respective additional panel driver line, wherein the panel driver is configured to be activated when the plurality of additional panel drivers are deactivated.

9. A method comprising: identifying a target memory cell for an access operation, the target memory cell being within an array of memory cells disposed on a plurality of plates arranged in rows and columns; activating a plate driver based at least in part on identifying the target memory cell, wherein the plate driver is coupled to a plate driver line that traverses at least a portion of a first column of a plate, and wherein the plate driver line is coupled to a plate line that traverses at least a portion of a first row of a plate; as well as The target memory cell is accessed based at least in part on activating the plate driver, wherein the target memory cell is disposed on a plate located in the first row of plates and a second column of plates.

10. The method according to claim 9, further comprising: A second target memory cell is accessed based at least in part on activating the plate driver, wherein the second target memory cell is disposed on a second plate in the first column of plates and a second row of plates.

11. The method according to claim 10, further comprising: A third target memory cell is accessed based at least in part on activating the plate driver, wherein the third target memory cell is disposed on a third plate in a fourth column of plates and a third row of plates.

12. The method according to claim 9, further comprising: identifying a fourth target memory cell for a second access operation; activating a second plate driver based at least in part on identifying the fourth target memory cell, wherein the second plate driver is coupled to a second plate driver line that traverses at least a portion of the second column of the plate, and wherein the second plate driver line is coupled to a second plate line that traverses at least a portion of the first row of the plate; as well as The fourth target memory cell is accessed based at least in part on activating the second plane driver, wherein the fourth target memory cell is disposed on a second plane located in the first row of planes and the first column of planes.

13. The method according to claim 9, further comprising: A logic state of the target memory cell is determined, wherein the logic state of the target memory cell is based at least in part on a voltage of a digit line coupled to the target memory cell, and wherein the digit line traverses the first column of a plate.

14. An apparatus comprising: a plurality of plates arranged in a plurality of rows and a plurality of columns, wherein a respective group of one or more memory cells is disposed on each of the plurality of plates; A plurality of plate drivers, each of the plurality of plate drivers being coupled to at least one plate in each of the plurality of columns and at least one plate in each of the plurality of rows.

15. The apparatus of claim 14, wherein a first panel driver of the plurality of panel drivers is coupled to: a first panel located in a first column of the plurality of columns and a first row of the plurality of rows; a second plate located in a second one of the plurality of columns and a second one of the plurality of rows; a third panel located in a third column of the plurality of columns and a third row of the plurality of rows; as well as A fourth plate is located in a fourth column of the plurality of columns and a fourth row of the plurality of rows.

16. The apparatus of claim 15, wherein a second panel driver of the plurality of panel drivers is coupled to: a fifth plate located in the second one of the plurality of columns and in the first one of the plurality of rows; a sixth plate located in the third of the plurality of columns and in the second of the plurality of rows; a seventh plate located in the fourth of the plurality of columns and in the third of the plurality of rows; and An eighth plate is located in the first of the plurality of columns and in the fourth of the plurality of rows.

17. The apparatus of claim 16, wherein the first panel driver is configured to be activated when the second panel driver is deactivated.

18. The apparatus of claim 15, further comprising: a controller coupled to the plurality of panel drivers, wherein the controller is configured to cause the device to: activating the first board driver; as well as A plurality of target memory cells are accessed based at least in part on activating the first plane driver, wherein at least one target memory cell of the plurality of target memory cells is located on each of the first plane, the second plane, the third plane, and the fourth plane.

19. The apparatus of claim 18, wherein the controller is operable to cause the apparatus to: A logic state of at least one of the plurality of target memory cells is determined, wherein the logic state of the target memory cell is based at least in part on a voltage of a digit line coupled to the target memory cell, and wherein the digit line traverses a first column of a plate.

20. The apparatus of claim 14, wherein each plate in a row of plates is coupled to a different plate driver of the plurality of plate drivers.

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