Solar cell and method for manufacturing solar cell

Abstract

The present application provides a solar cell and a method for manufacturing a solar cell, the solar cell comprising: a silicon substrate having a relative front and back surface; a first front tunneling layer and a first front doping layer, which are sequentially arranged on the front surface; a second front tunneling layer and a second front doping layer, which are sequentially arranged on a local area of ​​the first front doping layer, the doping concentration and thickness of the first front doping layer are less than the second front doping layer; a first back tunneling layer and a first back doping layer, which are sequentially arranged on the back surface; a second back tunneling layer and a second back doping layer, which are sequentially arranged on a local area of ​​the first back doping layer, the doping concentration and thickness of the first back doping layer are less than the second back doping layer; a first electrode and a second electrode, the first electrode is in contact with the second front doping layer, and the second electrode is in contact with the second back doping layer. The solar cell and the method for manufacturing a solar cell of the present application can reduce metal recombination and parasitic absorption.

Description

Technical Field

[0001] The present application mainly relates to the field of photovoltaic technology, and in particular to a solar cell and a method for manufacturing a solar cell. Background Art

[0002] TOPCon solar cells have high conversion efficiency. Current TOPCon solar cells have the problem of serious metal recombination caused by direct contact between the metal electrode and the silicon substrate. Although metal recombination can be reduced by increasing the thickness of the doped polysilicon layer, increasing the thickness of the doped polysilicon layer will bring about serious parasitic absorption problems. How to simultaneously reduce metal recombination and reduce parasitic absorption is one of the important research directions. Summary of the invention

[0003] The technical problem to be solved by the present application is to provide a solar cell and a method for manufacturing the solar cell, which can reduce metal recombination and lower parasitic absorption.

[0004] To solve the above technical problems, the present application provides a solar cell, comprising: a silicon substrate having a relative front side and back side; a first front side tunneling layer and a first front side doping layer, which are sequentially arranged on the front side; a second front side tunneling layer and a second front side doping layer, which are sequentially arranged on a local area of ​​the first front side doping layer, and the doping concentration and thickness of the first front side doping layer are smaller than those of the second front side doping layer; a first back side tunneling layer and a first back side doping layer, which are sequentially arranged on the back side; a second back side tunneling layer and a second back side doping layer, which are sequentially arranged on a local area of ​​the first back side doping layer, and the doping concentration and thickness of the first back side doping layer are smaller than those of the second back side doping layer; and a first electrode and a second electrode, the first electrode being in contact with the second front side doping layer, and the second electrode being in contact with the second back side doping layer, wherein the doping types of the first front side doping layer and the second front side doping layer are opposite to the doping types of the first back side doping layer and the second back side doping layer.

[0005] In one embodiment of the present application, the first front doping layer contains carbon and / or nitrogen, and the first back doping layer contains carbon, wherein the first front doping layer is N-type doped, and the first back doping layer is P-type doped.

[0006] In one embodiment of the present application, the thickness of the second front tunneling layer is smaller than that of the first front tunneling layer, and the thickness of the second back tunneling layer is smaller than that of the first back tunneling layer.

[0007] In an embodiment of the present application, the first front doped layer, the second front doped layer, the first back doped layer and the second back doped layer include doped polysilicon.

[0008] On the other hand, the present application also proposes a method for manufacturing a solar cell, comprising: providing a silicon substrate, the silicon substrate having a relative front side and back side; forming a first front side tunneling layer and a first front side doping layer in sequence on the front side; forming a second front side tunneling layer and a second front side doping layer in sequence on a local area of ​​the first front side doping layer; forming a first back side tunneling layer and a first back side doping layer in sequence on the back side; forming a second back side tunneling layer and a second back side doping layer in sequence on a local area of ​​the first back side doping layer; and forming a first electrode and a second electrode, the first electrode being in contact with the second front side doping layer, and the second electrode being in contact with the second back side doping layer, wherein the doping types of the first front side doping layer and the second front side doping layer are opposite to the doping types of the first back side doping layer and the second back side doping layer.

[0009] In one embodiment of the present application, the method for forming the first front doped layer, the second front doped layer, the first back doped layer and the second back doped layer includes: forming a first front amorphous silicon layer and a second front amorphous silicon layer on the front side; forming a first back amorphous silicon layer and a second back amorphous silicon layer on the back side; removing a portion of the second front amorphous silicon layer and a portion of the second back amorphous silicon layer to form a patterned second front amorphous silicon layer and a patterned second back amorphous silicon layer; annealing the first front amorphous silicon layer, the patterned second front amorphous silicon layer, the first back amorphous silicon layer and the patterned second back amorphous silicon layer, wherein the annealing transforms the first front amorphous silicon layer into the first front doped layer, the patterned second front amorphous silicon layer into the second front doped layer, the first back amorphous silicon layer into the first back doped layer, and the patterned second back amorphous silicon layer into the second back doped layer.

[0010] In one embodiment of the present application, the step of removing part of the second front amorphous silicon layer and part of the second back amorphous silicon layer to form a patterned second front amorphous silicon layer and a patterned second back amorphous silicon layer includes: using a laser to form a silicon oxide layer that partially covers the second front amorphous silicon layer and the second back amorphous silicon layer; using the silicon oxide layer as a mask, etching the second front amorphous silicon layer and the second back amorphous silicon layer to form the patterned second front amorphous silicon layer and the patterned second back amorphous silicon layer.

[0011] In one embodiment of the present application, PECVD is used to form the first front amorphous silicon layer, the second front amorphous silicon layer, the first back amorphous silicon layer and the second back amorphous silicon layer.

[0012] In an embodiment of the present application, the method further includes: after the annealing treatment, removing the initial second front tunneling layer not covered by the second front doped layer and the initial second back tunneling layer not covered by the second back doped layer.

[0013] In one embodiment of the present application, in the process of forming the first front doping layer, PECVD is used to dope carbon elements and / or nitrogen elements, and in the process of forming the first back doping layer, PECVD is used to dope carbon elements, wherein the first front doping layer is N-type doped and the first back doping layer is P-type doped.

[0014] In one embodiment of the present application, the thickness of the second front tunneling layer is smaller than that of the first front tunneling layer, and the thickness of the second back tunneling layer is smaller than that of the first back tunneling layer.

[0015] Compared with the prior art, this application has the following advantages:

[0016] (1) The doping concentration and thickness of the doping layer adjacent to the silicon substrate are smaller than those of the doping layer away from the silicon substrate, which can improve the passivation effect, help reduce carrier recombination, and help reduce parasitic absorption. The higher doping concentration and greater thickness of the doping layer away from the silicon substrate help reduce contact resistance and avoid serious metal recombination caused by electrode burn-through of the doping layer.

[0017] (2) The solar cell of the present application is provided with a second front doping layer and a second back doping layer in a local area, which can reduce parasitic absorption.

[0018] (3) The present application simultaneously performs annealing treatment on the first front amorphous silicon layer, the patterned second front amorphous silicon layer, the first back amorphous silicon layer and the patterned second back amorphous silicon layer, which helps to improve production capacity. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are included to provide a further understanding of the present application. They are included and constitute a part of the present application. The accompanying drawings illustrate embodiments of the present application and together with the present specification serve to explain the principles of the present application. In the accompanying drawings:

[0020] Figure 1 is a cross-sectional schematic diagram of a solar cell in one embodiment of the present application;

[0021] Figure 2 is a schematic flow chart of a method for manufacturing a solar cell in one embodiment of the present application;

[0022] Figures 3 to 6 Schematic diagram of cross-sections of a solar cell in different steps of a process for manufacturing a solar cell in one embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of the present application. For ordinary technicians in this field, the present application can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.

[0024] As shown in this application and claims, unless the context clearly indicates an exception, the words "a", "an", "an" and / or "the" do not refer to the singular and may also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0025] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present application. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant field may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the authorization specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so that once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0026] In the description of the present application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction, and therefore cannot be understood as limiting the scope of protection of the present application; the directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0027] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0028] In addition, it should be noted that the use of words such as "first" and "second" to define components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above words have no special meaning and cannot be understood as limiting the scope of protection of this application. In addition, although the terms used in this application are selected from well-known and commonly used terms, some terms mentioned in the specification of this application may be selected by the applicant at his or her discretion, and their detailed meanings are explained in the relevant parts of the description of this article. In addition, it is required to understand this application not only by the actual terms used, but also by the meaning implied by each term.

[0029] Flowcharts are used in the present application to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed accurately in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may be added to these processes, or one or more operations may be removed from these processes.

[0030] Next, the solar cell and the method for manufacturing the solar cell of the present application are described through examples.

[0031] Figure 1 is a schematic cross-sectional view of a solar cell in one embodiment. Figure 1 As shown, the solar cell in this embodiment includes a silicon substrate 110, a first front tunneling layer 120, a first front doping layer 130, a second front tunneling layer 140, a second front doping layer 150, a first back tunneling layer 160, a first back doping layer 170, a second back tunneling layer 180, a second back doping layer 190, a first electrode 210 and a second electrode 220.

[0032] Specifically, the silicon substrate 110 has a front surface 111 and a back surface 112 which are opposite to each other in the thickness direction thereof. The front surface 111 can be a light-receiving surface or a backlight surface. When the front surface 111 is a light-receiving surface, the back surface 112 is a backlight surface. When the front surface 111 is a backlight surface, the back surface 112 is a light-receiving surface. The silicon substrate 110 is an N-type doped silicon substrate or a P-type doped silicon substrate.

[0033] The first front tunneling layer 120 is located on the front side 111 of the silicon substrate 110, and the first front doping layer 130 is located on the surface of the first front tunneling layer 120 away from the silicon substrate 110. The material of the first front tunneling layer 120 may include silicon oxide (SiO x ), for example, the first front tunneling layer 120 is a silicon dioxide (SiO2) film. The first front tunneling layer 120 has a passivation effect on the solar cell. The first front doped layer 130 is N-type doped or P-type doped. The material of the first front doped layer 130 may include doped polysilicon, for example, the first front doped layer 130 is P-type doped polysilicon or N-type doped polysilicon.

[0034] For the convenience of description, the surface of the first front doped layer 130 facing away from the silicon substrate 110 is marked as the first surface 131. The second front tunneling layer 140 is located on a local area of ​​the first surface 131. The material of the second front tunneling layer 140 may include silicon oxide, for example, the second front tunneling layer 140 is a silicon dioxide film. The thickness of the second front tunneling layer 140 is less than the thickness of the first front tunneling layer 120, and the second front tunneling layer 140 with a smaller thickness helps to reduce the impact on the series resistance of the solar cell.

[0035] The second front doped layer 150 is located on the surface of the second front tunneling layer 140 away from the silicon substrate 110. The doping type of the second front doped layer 150 is the same as the doping type of the first front doped layer 130, for example, the first front doped layer 130 and the second front doped layer 150 are both N-type doped or P-type doped. The material of the second front doped layer 150 may include doped polysilicon, for example, the second front doped layer 150 is P-type doped polysilicon or N-type doped polysilicon.

[0036] The first electrode 210 is in contact with the second front doping layer 150 , and the first electrode 210 may be formed by sintering.

[0037] The doping concentration of the first front doping layer 130 is less than the doping concentration of the second front doping layer 150, and the thickness of the first front doping layer 130 is less than the thickness of the second front doping layer 150. The low doping concentration and small thickness of the first front doping layer 130 can improve the passivation effect on the front surface 111, which helps to reduce the recombination of carriers. In addition, the small thickness of the first front doping layer 130 also helps to reduce parasitic absorption. The high doping concentration and large thickness of the second front doping layer 150 help to form a good contact between the first electrode 210 and the second front doping layer 150, thereby reducing the contact resistance between the first electrode 210 and the second front doping layer 150. The large thickness of the second front doping layer 150 can also avoid the first electrode 210 burning through the first front doping layer 130 and the second front doping layer 150 during the preparation of the first electrode 210, thereby avoiding the first electrode 210 from directly contacting the silicon substrate 110, which will lead to increased metal recombination. In addition, compared with the technical solution of providing the second front doping layer 150 on the entire first surface 131 , the solar cell of the present application is provided with the second front doping layer 150 only on a local area of ​​the first surface 131 , which can reduce parasitic absorption.

[0038] Continue to refer Figure 1 As shown, the first back tunneling layer 160 is located on the back side 112 of the silicon substrate 110, and the first back doping layer 170 is located on the surface of the first back tunneling layer 160 away from the silicon substrate 110. The material of the first back tunneling layer 160 may include silicon oxide, for example, the first back tunneling layer 160 is a silicon dioxide film. The first back tunneling layer 160 has a passivation effect on the solar cell. The material of the first back doping layer 170 may include doped polysilicon, for example, the first back doping layer 170 is P-type doped polysilicon or N-type doped polysilicon.

[0039] The doping type of the first back doped layer 170 is opposite to the doping type of the first front doped layer 130. In one embodiment, the silicon substrate 110 is N-type doped, the first front doped layer 130 is N-type doped, the first back doped layer 170 is P-type doped, the front side of the silicon substrate 110 is the light-receiving side, and the back side of the silicon substrate 110 is the backlight side.

[0040] For the convenience of description, the surface of the first back doped layer 170 facing away from the silicon substrate 110 is marked as the second surface 171. The second back tunneling layer 180 is located on a local area of ​​the second surface 171. The material of the second back tunneling layer 180 may include silicon oxide, for example, the second back tunneling layer 180 is a silicon dioxide film. The thickness of the second back tunneling layer 180 is less than the thickness of the first back tunneling layer 160. The second back tunneling layer 180 with a smaller thickness helps to reduce the influence of the second back tunneling layer 180 on the series resistance.

[0041] The second back doped layer 190 is located on the surface of the second back tunneling layer 180 away from the silicon substrate 110. The doping type of the second back doped layer 190 is the same as the doping type of the first back doped layer 170, for example, the first back doped layer 170 and the second back doped layer 190 are both P-type doped or N-type doped. The material of the second back doped layer 190 may include doped polysilicon, for example, the second back doped layer 190 is P-type doped polysilicon or N-type doped polysilicon.

[0042] The second electrode 220 contacts the second back doping layer 190 and can be formed by sintering.

[0043] The doping concentration of the first back doping layer 170 is less than the doping concentration of the second back doping layer 190, and the thickness of the first back doping layer 170 is less than the thickness of the second back doping layer 190. The low doping concentration and small thickness of the first back doping layer 170 can improve the passivation effect on the back 112, which helps to reduce the recombination of carriers. In addition, the first back doping layer 170 with a small thickness can also help reduce parasitic absorption. The high doping concentration and large thickness of the second back doping layer 190 help to form a good contact between the second electrode 220 and the second back doping layer 190, thereby reducing the contact resistance between the second electrode 220 and the second back doping layer 190. The large thickness of the second back doping layer 190 can also avoid the second electrode 220 burning through the first back doping layer 170 and the second back doping layer 190 during the preparation of the second electrode 220, thereby avoiding the second electrode 220 from directly contacting the silicon substrate 110, which will lead to increased metal recombination. In addition, compared with the technical solution of providing the second back doping layer 190 on the entire second surface 171 , the solar cell of the present application is provided with the second back doping layer 190 only on a local area of ​​the second surface 171 , which can reduce parasitic absorption.

[0044] In one embodiment, the silicon substrate 110 is N-type doped, the first front doped layer 130 is N-type doped, the first front doped layer 130 contains carbon and / or nitrogen, and the second front doped layer 150 does not contain carbon and nitrogen. Carbon and nitrogen help to assist the passivation effect of the first front doped layer 130, and can also reduce parasitic absorption in the medium and long wave bands. The second front doped layer 150 does not contain carbon and nitrogen, which can avoid the carbon and nitrogen elements causing the contact resistance between the electrode and the second front doped layer 150 to increase. The first back doped layer 170 is P-type doped, the first back doped layer 170 contains carbon, and the second back doped layer 190 does not contain carbon. Carbon can assist the passivation effect of the first back doped layer 170, and the second back doped layer 190 does not contain carbon, which can avoid the carbon element causing the contact resistance between the electrode and the second back doped layer 190 to increase.

[0045] refer to Figure 1 As shown, in one embodiment, the solar cell further includes a front passivation anti-reflection layer 230 and a back passivation anti-reflection layer 240. The front passivation anti-reflection layer 230 covers the area of ​​the first surface 131 not covered by the second front tunneling layer 140 and the surface of the second front doped layer 150 away from the silicon substrate 110, and one end of the first electrode 210 penetrates the front passivation anti-reflection layer 230 and contacts the second front doped layer 150. The back passivation anti-reflection layer 240 covers the area of ​​the second surface 171 not covered by the second back tunneling layer 180 and the surface of the second back doped layer 190 away from the silicon substrate 110, and one end of the second electrode 220 penetrates the back passivation anti-reflection layer 240 and contacts the second back doped layer 190. The front passivation anti-reflection layer 230 and the back passivation anti-reflection layer 240 have a passivation effect and can also reduce the reflection of light.

[0046] Figure 2 FIG. 1 is a schematic diagram of a method for manufacturing a solar cell in an embodiment. Figure 2 As shown, the manufacturing method in this embodiment includes the following steps:

[0047] Step S310: providing a silicon substrate, wherein the silicon substrate has a front side and a back side opposite to each other;

[0048] Step S320: sequentially forming a first front tunneling layer and a first front doping layer on the front surface;

[0049] Step S330: sequentially forming a second front tunneling layer and a second front doping layer on a local area of ​​the first front doping layer;

[0050] Step S340: sequentially forming a first back-side tunneling layer and a first back-side doping layer on the back side;

[0051] Step S350: sequentially forming a second back tunneling layer and a second back doping layer on a local area of ​​the first back doping layer;

[0052] Step S360: forming a first electrode and a second electrode, the first electrode contacts the second front doping layer, the second electrode contacts the second back doping layer, and the doping types of the first front doping layer and the second front doping layer are opposite to the doping types of the first back doping layer and the second back doping layer.

[0053] Next, steps S310 to S360 are described in detail.

[0054] refer to Figure 1 As shown, in step S310, a silicon substrate 110 is provided. The silicon substrate 110 has a front side 111 and a back side 112 opposite to each other in the thickness direction thereof. In step S320, a first front side tunneling layer 120 and a first front side doping layer 130 are sequentially formed on the front side 111. In step S340, a first back side tunneling layer 160 and a first back side doping layer 170 are sequentially formed on the back side 112.

[0055] The first front tunneling layer 120, the first front doping layer 130, the first back tunneling layer 160 and the first back doping layer 170 may be prepared by a plasma enhanced chemical vapor deposition (PECVD) process. In the process of forming the first front doping layer 130, PECVD is used to dope carbon elements and / or nitrogen elements, so that the first front doping layer 130 contains carbon elements and / or nitrogen elements. In the process of forming the first back doping layer 170, PECVD is used to dope carbon elements, so that the first back doping layer 170 contains carbon elements, wherein the first front doping layer 130 is N-type doped and the first back doping layer 170 is P-type doped. Compared with the low pressure chemical vapor deposition (LPCVD) process, PECVD can simultaneously deposit an amorphous silicon layer and dope the amorphous silicon layer, while LPCVD needs to first deposit an amorphous silicon layer and then dope the amorphous silicon layer, so PECVD has the advantage of fewer process steps. In addition, PECVD can also dope the doped layer with carbon and nitrogen.

[0056] refer to Figure 1 As shown, in step S330, a second front tunneling layer 140 and a second front doping layer 150 are sequentially formed on a local area of ​​the first front doping layer 130. In step S350, a second back tunneling layer 180 and a second back doping layer 190 are sequentially formed on a local area of ​​the first back doping layer 170.

[0057] refer to Figures 3 to 5 As shown, in one embodiment, the method of forming the first front doped layer 130, the second front doped layer 150, the first back doped layer 170 and the second back doped layer 190 includes the following steps 11 to 14:

[0058] Step 11: forming a first front amorphous silicon layer 130 - 1 and a second front amorphous silicon layer 150 - 1 on the front surface 111 .

[0059] Specifically, refer to Figure 3 As shown, a first front amorphous silicon layer 130-1 is formed on the first front tunneling layer 120, an initial second front tunneling layer 140-1 is formed on the first front amorphous silicon layer 130-1, and a second front amorphous silicon layer 150-1 is formed on the initial second front tunneling layer 140-1, wherein the first front amorphous silicon layer 130-1 and the second front amorphous silicon layer 150-1 are both doped.

[0060] PECVD can be used to form the tunneling layer and the amorphous silicon layer in step 11. Compared with the LPCVD process, thanks to the advantage of PECVD in-situ doping, the PECVD process can be used to prepare the first front amorphous silicon layer 130-1 with a low doping concentration and the second front amorphous silicon layer 150-1 with a high doping concentration in the same process chamber.

[0061] Step 12: forming a first back side amorphous silicon layer 170 - 1 and a second back side amorphous silicon layer 190 - 1 on the back side 112 .

[0062] Specifically, refer to Figure 3 As shown, a first back amorphous silicon layer 170-1 is formed on the first back tunneling layer 160, an initial second back tunneling layer 180-1 is formed on the first back amorphous silicon layer 170-1, and a second back amorphous silicon layer 190-1 is formed on the initial second back tunneling layer 180-1, wherein the first back amorphous silicon layer 170-1 and the second back amorphous silicon layer 190-1 are both doped. PECVD can be used to form the tunneling layer and the amorphous silicon layer. Compared with the LPCVD process, thanks to the advantages of PECVD in-situ doping, the PECVD process can be used to prepare the first back amorphous silicon layer 170-1 with a low doping concentration and the second back amorphous silicon layer 190-1 with a high doping concentration in the same process chamber, which saves the step of transferring the solar cell.

[0063] Step 13: removing a portion of the second front amorphous silicon layer and a portion of the second back amorphous silicon layer to form a patterned second front amorphous silicon layer 150 - 2 and a patterned second back amorphous silicon layer 190 - 2 .

[0064] Specifically, refer to Figure 3 and Figure 4As shown, the patterned second front amorphous silicon layer 150-2 and the patterned second back amorphous silicon layer 190-2 can be formed by the following method: using a laser to form a silicon oxide layer 250 that partially covers the second front amorphous silicon layer 150-1 and the second back amorphous silicon layer 190-1; using the silicon oxide layer 250 as a mask, etching away the second front amorphous silicon layer 150-1 and the second back amorphous silicon layer 190-1 that are not covered by the silicon oxide layer 250 to form the patterned second front amorphous silicon layer 150-2 and the patterned second back amorphous silicon layer 190-2. The second front amorphous silicon layer 150-1 and the second back amorphous silicon layer 190-1 that are not covered by the silicon oxide layer 250 can be removed by a wet etching process.

[0065] Step 14: performing annealing treatment on the first front amorphous silicon layer 130 - 1 , the patterned second front amorphous silicon layer 150 - 2 , the first back amorphous silicon layer 170 - 1 , and the patterned second back amorphous silicon layer 190 - 2 .

[0066] refer to Figure 4 and Figure 5 As shown, the annealing process transforms the first front amorphous silicon layer 130-1 into the first front doped layer 130, the patterned second front amorphous silicon layer 150-2 into the second front doped layer 150, the first back amorphous silicon layer 170-1 into the first back doped layer 170, and the patterned second back amorphous silicon layer 190-2 into the second back doped layer 190. In step 14, the annealing process has a crystallization effect, transforming the amorphous silicon into polycrystalline silicon.

[0067] In step 11 to step 14, a patterned second front amorphous silicon layer 150-2 is first formed, and then annealing is performed. The above step sequence has the following technical effects: since amorphous silicon has high reactivity and does not have the anisotropy of crystalline silicon, in the process of etching and removing the second front amorphous silicon layer 150-1 not covered by the silicon oxide layer 250, the thin initial second front tunneling layer 140-1 is sufficient to protect the first front amorphous silicon layer 130-1 located thereunder from being etched. Figure 1 As shown, in the subsequent process steps, part of the initial second front tunneling layer 140-1 will be retained, and the retained part becomes the second front tunneling layer 140. The thin thickness of the initial second front tunneling layer 140-1 can make the thickness of the second front tunneling layer 140 thinner, thereby reducing the influence of the second front tunneling layer 140 on the series resistance. Similarly, the step sequence of first forming the patterned second back amorphous silicon layer 190-2 and then performing the annealing treatment also has the above-mentioned technical effect.

[0068] In addition, in the above embodiment, in step 14, the first front amorphous silicon layer 130-1, the patterned second front amorphous silicon layer 150-2, the first back amorphous silicon layer 170-1 and the patterned second back amorphous silicon layer 190-2 are annealed simultaneously. Compared with annealing the above film layers separately, performing annealing simultaneously can reduce the process steps and thus improve production capacity.

[0069] refer to Figure 5 and Figure 6 As shown, in one embodiment, after the annealing treatment, the initial second front tunneling layer 140-1 not covered by the second front doping layer 150 and the initial second back tunneling layer 180-1 not covered by the second back doping layer 190 are removed, or in other words, the exposed initial second front tunneling layer 140-1 and the initial second back tunneling layer 180-1 are removed.

[0070] The portion of the initial second front tunneling layer 140-1 that is not removed becomes the second front tunneling layer 140, and the portion of the initial second back tunneling layer 180-1 that is not removed becomes the second back tunneling layer 180. In one embodiment, the thickness of the second front tunneling layer 140 is less than the thickness of the first front tunneling layer 120, and the thickness of the second back tunneling layer 180 is less than the thickness of the first back tunneling layer 160.

[0071] In one embodiment, after the annealing process, the silicon oxide layer 250 is removed.

[0072] refer to Figure 1 As shown, in step S360, a first electrode 210 and a second electrode 220 are formed. The first electrode 210 contacts the second front doped layer 150, and the second electrode 220 contacts the second back doped layer 190. The doping type of the first front doped layer 130 and the doping type of the second front doped layer 150 are opposite to the doping type of the first back doped layer 170 and the doping type of the second back doped layer 190.

[0073] In some embodiments, reference Figure 6 and Figure 1 As shown, the manufacturing method of the present application also includes forming a front passivation anti-reflection layer 230 and a back passivation anti-reflection layer 240, one end of the first electrode 210 penetrates the front passivation anti-reflection layer 230 and contacts the second front doped layer 150, and one end of the second electrode 220 penetrates the back passivation anti-reflection layer 240 and contacts the second back doped layer 190.

[0074] For other descriptions on the manufacturing method of solar cells, please refer to the previous description of solar cells, which will not be elaborated here.

[0075] In order to more clearly understand the solar cell and the method for manufacturing the solar cell of the present application, a non-limiting embodiment is given here. The process flow of this embodiment is as follows:

[0076] Polishing: The silicon substrate is polished to obtain a flat surface. The silicon substrate is N-type doped single crystal silicon.

[0077] Depositing a tunneling layer and P-type doped amorphous silicon on the back side of the silicon substrate: First, using a PECVD process to form a first tunneling layer with a thickness of 1nm to 2nm on the back side of the silicon substrate; then, depositing a first layer of P-type doped amorphous silicon on the surface of the first tunneling layer away from the silicon substrate, the process gas used to deposit the first layer of P-type doped amorphous silicon includes a boron source, and methane is introduced during the deposition of the first layer of P-type doped amorphous silicon to dope carbon into the first layer of P-type doped amorphous silicon, and the deposition temperature is 400℃ to 500℃. 50℃, the thickness of the first layer of P-type doped amorphous silicon is 10nm~20nm; then, a second layer of tunneling layer with a thickness of 0.5nm~1nm is formed on the surface of the first layer of P-type doped amorphous silicon away from the silicon substrate; then, a second layer of P-type doped amorphous silicon is deposited on the surface of the second layer of tunneling layer away from the silicon substrate, the process gas used to deposit the second layer of P-type doped amorphous silicon includes a boron source, the deposition temperature is 400℃~550℃, and the thickness of the second layer of P-type doped amorphous silicon is 200nm~400nm. The thickness of the second layer of tunneling layer is less than that of the first layer of tunneling layer, the thickness of the first layer of P-type doped amorphous silicon is less than that of the second layer of P-type doped amorphous silicon, and the doping concentration of the first layer of P-type doped amorphous silicon is less than that of the second layer of P-type doped amorphous silicon.

[0078] The first de-plating: sequentially remove the borosilicate glass (BSG) on the front side of the silicon substrate, the second layer of P-type doped amorphous silicon, the second layer of tunneling layer, the first layer of P-type doped amorphous silicon and the first layer of tunneling layer. The second layer of P-type doped amorphous silicon and the first layer of P-type doped amorphous silicon are removed using a chemical solution including an alkali and a first additive, the alkali can be one or more of potassium hydroxide (KOH), sodium hydroxide (NaOH) or tetramethylammonium hydroxide (TMAH), the first additive is used to control the etching rate, the application does not limit the type of the first additive, and it can be an additive commonly used in the art.

[0079] Front texturing: A pyramid texture surface is prepared on the front side of a silicon substrate using a chemical solution comprising an alkali and a second additive. The size of the pyramid base is 1 μm to 5 μm, and the average reflectivity of the pyramid texture surface is 10% to 15%. The alkali can be KOH and / or NaOH, and the second additive is used to regulate the etching rate. This application does not limit the type of the second additive, which can be an additive commonly used in this field.

[0080] A tunneling layer and an N-type doped amorphous silicon layer are deposited on the front side of the silicon substrate: first, a first tunneling layer with a thickness of 1 nm to 2 nm is formed on the front side of the silicon substrate using a PECVD process; then, a first N-type doped amorphous silicon layer is deposited on the surface of the first tunneling layer away from the silicon substrate, and the process gas used to deposit the first N-type doped amorphous silicon layer includes a phosphorus source. Ammonia gas is introduced during the deposition of the first N-type doped amorphous silicon layer to dope nitrogen into the first N-type doped amorphous silicon layer. The deposition temperature is 400°C. ~550℃, the thickness of the first layer of N-type doped amorphous silicon is 10nm~20nm; then, a second layer of tunneling layer with a thickness of 0.5nm~1nm is formed on the surface of the first layer of N-type doped amorphous silicon away from the silicon substrate; then, a second layer of N-type doped amorphous silicon is deposited on the surface of the second layer of tunneling layer away from the silicon substrate, the process gas used to deposit the second layer of N-type doped amorphous silicon includes a phosphorus source, the deposition temperature is 400℃~550℃, and the thickness of the second layer of N-type doped amorphous silicon is 100nm~200nm. The thickness of the second layer of tunneling layer is less than that of the first layer of tunneling layer, the thickness of the first layer of N-type doped amorphous silicon is less than that of the second layer of N-type doped amorphous silicon, and the doping concentration of the first layer of N-type doped amorphous silicon is less than that of the second layer of N-type doped amorphous silicon.

[0081] Second de-plating: sequentially remove the phosphosilicate glass (PSG), the second layer of N-type doped amorphous silicon, the second tunneling layer, the first layer of N-type doped amorphous silicon and the first layer of tunneling layer located on the back of the silicon substrate. The second layer of N-type doped amorphous silicon and the first layer of N-type doped amorphous silicon are removed using a chemical solution including an alkali and a third additive, the alkali can be one or more of potassium hydroxide (KOH), sodium hydroxide (NaOH) or tetramethylammonium hydroxide (TMAH), the third additive is used to adjust the etching rate, the application does not limit the type of the third additive, and it can be an additive commonly used in the art.

[0082] Prepare the mask: first, remove the BSG on the back side of the silicon substrate and remove the PSG on the front side of the silicon substrate; then, use a laser to oxidize a local area of ​​the second layer of P-type doped amorphous silicon to form a silicon oxide layer with a thickness of 3nm~8nm, and use a laser to oxidize a local area of ​​the second layer of N-type doped amorphous silicon to form a silicon oxide layer with a thickness of 3nm~8nm. The above silicon oxide layer is a mask for subsequent etching.

[0083] Etching the second layer of P-type doped amorphous silicon and the second layer of N-type doped amorphous silicon: using the silicon oxide layer as a mask, etching the second layer of P-type doped amorphous silicon and the second layer of N-type doped amorphous silicon, retaining the second tunneling layer located on the front side of the silicon substrate and the second tunneling layer located on the back side of the silicon substrate. A chemical solvent including an alkali and a fourth additive may be used for etching, the alkali may be KOH and / or NaOH, and the fourth additive is used to regulate the etching rate. The present application does not limit the type of the fourth additive, which may be an additive commonly used in the art.

[0084] Annealing treatment: The first layer of P-type doped amorphous silicon, the second layer of P-type doped amorphous silicon, the first layer of N-type doped amorphous silicon and the second layer of N-type doped amorphous silicon are annealed at the same time, and the annealing temperature is 850℃~950℃. After annealing, the first layer of P-type doped amorphous silicon is transformed into the first layer of P-type doped polycrystalline silicon, the second layer of P-type doped amorphous silicon is transformed into the second layer of P-type doped polycrystalline silicon, the first layer of N-type doped amorphous silicon is transformed into the first layer of N-type doped polycrystalline silicon, and the second layer of N-type doped amorphous silicon is transformed into the second layer of N-type doped polycrystalline silicon. The doping concentration of the first layer of P-type doped polycrystalline silicon is 5E+18~1E+19 cm -3 The doping concentration of the second layer of P-type doped polysilicon is 1E+19~1E+20 cm -3 , and the doping concentration of the first layer of P-type doped polysilicon is less than the doping concentration of the second layer of P-type doped polysilicon; the doping concentration of the first layer of N-type doped polysilicon is 5E+19~1E+20 cm -3 The doping concentration of the second layer of N-type doped polysilicon is 5E+20~1E+21 cm -3 , and the doping concentration of the first layer of N-type doped polysilicon is less than the doping concentration of the second layer of N-type doped polysilicon.

[0085] Cleaning: First, remove the masks on the front and back sides of the silicon substrate; then, perform cleaning; and then remove the exposed second tunneling layer.

[0086] Prepare passivation anti-reflection layer and electrodes.

[0087] For other details about the above embodiment, please refer to the above text and will not be repeated here.

[0088] Next, Comparative Example 1 and Example 1 of the present application are given.

[0089] Embodiment 1 includes the following steps 21 to 33:

[0090] Step 21: Polish the silicon substrate to obtain a flat surface, the silicon substrate being N-type doped single crystal silicon.

[0091] Step 22: First, a first tunneling layer with a thickness of 1.3 nm is formed on the back side of the silicon substrate using a PECVD process; then, a first layer of P-type doped amorphous silicon is deposited on the surface of the first tunneling layer facing away from the silicon substrate, the process gas used to deposit the first layer of P-type doped amorphous silicon includes a boron source, methane is introduced during the deposition of the first layer of P-type doped amorphous silicon, the deposition temperature is 440°C, and the thickness of the first layer of P-type doped amorphous silicon is 10 nm; then, a second tunneling layer with a thickness of 0.8 nm is formed on the surface of the first layer of P-type doped amorphous silicon facing away from the silicon substrate; then, a second layer of P-type doped amorphous silicon is deposited on the surface of the second tunneling layer facing away from the silicon substrate, the process gas used to deposit the second layer of P-type doped amorphous silicon includes a boron source, the deposition temperature is 440°C, and the thickness of the second layer of P-type doped amorphous silicon is 300 nm.

[0092] Step 23: sequentially remove the borosilicate glass, the second layer of P-type doped amorphous silicon, the second tunneling layer, the first layer of P-type doped amorphous silicon and the first tunneling layer located on the front side of the silicon substrate.

[0093] Step 24: Prepare a pyramid velvet surface on the front side of the silicon substrate, the size of the pyramid base is 4 μm, and the average reflectivity of the pyramid velvet surface is 10.2%.

[0094] Step 25: First, a first tunneling layer with a thickness of 1.3 nm is formed on the front side of the silicon substrate using a PECVD process; then, a first layer of N-type doped amorphous silicon is deposited on the surface of the first tunneling layer away from the silicon substrate, the process gas used to deposit the first layer of N-type doped amorphous silicon includes a phosphorus source, ammonia is introduced during the deposition of the first layer of N-type doped amorphous silicon, the deposition temperature is 440°C, and the thickness of the first layer of N-type doped amorphous silicon is 10 nm; then, a second tunneling layer with a thickness of 0.8 nm is formed on the surface of the first layer of N-type doped amorphous silicon away from the silicon substrate; then, a second layer of N-type doped amorphous silicon is deposited on the surface of the second tunneling layer away from the silicon substrate, the process gas used to deposit the second layer of N-type doped amorphous silicon includes a phosphorus source, the deposition temperature is 440°C, and the thickness of the second layer of N-type doped amorphous silicon is 120 nm.

[0095] Step 26: sequentially remove the phosphosilicate glass, the second layer of N-type doped amorphous silicon, the second tunneling layer, the first layer of N-type doped amorphous silicon and the first tunneling layer on the back side of the silicon substrate.

[0096] Step 27: Remove the BSG on the back side of the silicon substrate, and remove the PSG on the front side of the silicon substrate; then, use a laser to form a silicon oxide layer with a thickness of 7 nm in a local area of ​​the second layer of P-type doped amorphous silicon, and form a silicon oxide layer with a thickness of 7 nm in a local area of ​​the second layer of N-type doped amorphous silicon.

[0097] Step 28: Using the silicon oxide layer as a mask, etching the second layer of P-type doped amorphous silicon and the second layer of N-type doped amorphous silicon.

[0098] Step 29: The first layer of P-type doped amorphous silicon, the second layer of P-type doped amorphous silicon, the first layer of N-type doped amorphous silicon and the second layer of N-type doped amorphous silicon are annealed at 910°C. After annealing, the first layer of P-type doped amorphous silicon is transformed into the first layer of P-type doped polycrystalline silicon, the second layer of P-type doped amorphous silicon is transformed into the second layer of P-type doped polycrystalline silicon, the first layer of N-type doped amorphous silicon is transformed into the first layer of N-type doped polycrystalline silicon, and the second layer of N-type doped amorphous silicon is transformed into the second layer of N-type doped polycrystalline silicon. The doping concentration of the first layer of P-type doped polycrystalline silicon is 1.1E+19 cm -3 The doping concentration of the second layer of P-type doped polysilicon is 4.9E+19 cm -3 The doping concentration of the first layer of N-type doped polysilicon is 9.3E+19cm -3 The doping concentration of the second layer of N-type doped polysilicon is 5.8E+20cm -3 .

[0099] Step 30: remove the masks on the front and back sides of the silicon substrate; then, perform cleaning; and then remove the exposed second tunneling layer.

[0100] Step 31: A 10 nm thick aluminum oxide is deposited on the front side of the silicon substrate using an atomic layer deposition (ALD) process. A 80 nm thick silicon nitride is deposited on the aluminum oxide using PECVD, and the average refractive index of the silicon nitride layer is 2.08.

[0101] Step 32: Use PECVD to deposit a 75 nm thick silicon nitride layer on the back side of the silicon substrate. The average refractive index of the silicon nitride layer is 2.15.

[0102] Step 33: Prepare electrodes through printing and sintering processes.

[0103] Comparative Example 1 includes the following steps 41 to 53:

[0104] Step 41: Polish the silicon substrate to obtain a flat surface, the silicon substrate being N-type doped single crystal silicon.

[0105] Step 42: First, a tunneling layer with a thickness of 1.6 nm is formed on the back side of the silicon substrate using a PECVD process; then, a layer of P-type doped amorphous silicon is deposited on the tunneling layer, the process gas used for deposition includes a boron source, the deposition temperature is 440°C, and the thickness of the P-type doped amorphous silicon is 300 nm.

[0106] Step 43: First remove the BSG located on the front side of the silicon substrate, and then use a chemical solution to remove the P-type doped amorphous silicon that is plated around the front side of the silicon substrate.

[0107] Step 44: Prepare a pyramid velvet surface on the front side of the silicon substrate, the size of the pyramid base is 4 μm, and the average reflectivity of the pyramid velvet surface is 10.2%.

[0108] Step 45: First, a tunneling layer with a thickness of 1.6 nm is formed on the front side of the silicon substrate using a PECVD process; then, a layer of N-type doped amorphous silicon is deposited on the tunneling layer, the process gas used for deposition includes a phosphorus source, the deposition temperature is 440° C., and the thickness of the N-type doped amorphous silicon is 120 nm.

[0109] Step 46: First remove the PSG on the back of the silicon substrate, and then remove the N-type doped amorphous silicon that is plated around the back of the silicon substrate.

[0110] Step 47: Remove the PSG located on the front side of the silicon substrate, and use a laser to form a silicon oxide layer with a thickness of 7 nm in a local area of ​​the N-type doped amorphous silicon located on the front side.

[0111] Step 48: Using the silicon oxide layer in step 47 as a mask, the N-type doped amorphous silicon on the front side of the silicon substrate is etched.

[0112] Step 49: Annealing the N-type doped amorphous silicon and P-type doped amorphous silicon in the previous step to transform the N-type doped amorphous silicon into N-type doped polysilicon and transform the P-type doped amorphous silicon into P-type doped polysilicon. The doping concentration of the N-type doped polysilicon is 2.5E+20 cm -3 The doping concentration of P-type doped polysilicon is 3.3E+19 cm -3 .

[0113] Step 50: Remove the PSG and the exposed tunneling layer on the front side of the silicon substrate, remove the BSG on the back side of the silicon substrate, and perform cleaning.

[0114] Step 51: Aluminum oxide is deposited on the front surface by ALD with a thickness of 10 nm; a silicon nitride anti-reflection layer is deposited by PECVD with a thickness of 80 nm and an average refractive index of 2.08.

[0115] Step 52: A silicon nitride passivation anti-reflection layer is deposited on the back side by PECVD, with a thickness of 75 nm and an average refractive index of 2.15.

[0116] Step 53: Print metallization paste on the front and back sides and sinter.

[0117] Referring to Table 1 below, the conversion efficiency (Eta), open circuit voltage (Voc) and short circuit current (Jsc) of the solar cell manufactured in Example 1 are all greater than those of the solar cell manufactured in Comparative Example 1, which indicates that the passivation effect of Example 1 is better than that of Comparative Example 1.

[0118] Table 1 Parameters of solar cells manufactured in Example 1 and Comparative Example 1

[0119] Eta / % Voc / V <![CDATA[Jsc / mA·cm -2 ]]> FF / % Example 1 25.66 0.742 41.12 84.1 Comparative Example 1 25.47 0.738 40.99 84.2

[0120] The basic concepts have been described above. Obviously, for those skilled in the art, the above application disclosure is only an example and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and amendments to the present application. Such modifications, improvements and amendments are suggested in the present application, so such modifications, improvements and amendments still belong to the spirit and scope of the exemplary embodiments of the present application.

[0121] At the same time, the present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different positions in this specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

[0122] Similarly, it should be noted that in order to simplify the description of the disclosure of this application and thus help understand one or more application embodiments, in the above description of the embodiments of this application, multiple features are sometimes merged into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the object of this application are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

[0123] In some embodiments, numbers describing the number of components and attributes are used. It should be understood that such numbers used for the description of the embodiments are modified by the modifiers "about", "approximately" or "substantially" in some examples. Unless otherwise specified, "about", "approximately" or "substantially" indicate that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which can be changed according to the required features of individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and adopt the method of general digit retention. Although the numerical domains and parameters used to confirm the breadth of the range in some embodiments of the present application are approximate values, in specific embodiments, the setting of such numerical values ​​is as accurate as possible within the feasible range.

[0124] Although the present application has been described with reference to the current specific embodiments, ordinary technicians in this technical field should recognize that the above embodiments are only used to illustrate the present application, and various equivalent changes or substitutions may be made without departing from the spirit of the present application. Therefore, as long as the changes and modifications to the above embodiments are within the essential spirit of the present application, they will fall within the scope of the claims of the present application.

Claims

1. A solar cell, characterized in that: include: a silicon substrate having opposing front and back surfaces; A first front tunneling layer and a first front doping layer are sequentially arranged on the front surface; A second front tunneling layer and a second front doped layer are sequentially arranged on a local area of ​​the first front doped layer, the doping concentration and thickness of the first front doped layer are smaller than those of the second front doped layer, the first front doped layer and the second front doped layer are N-type, the first front doped layer contains carbon and / or nitrogen, and the second front doped layer does not contain carbon and nitrogen; A first back-side tunneling layer and a first back-side doping layer are sequentially arranged on the back side; A second back tunneling layer and a second back doping layer are sequentially arranged on a local area of ​​the first back doping layer, the doping concentration and thickness of the first back doping layer are smaller than those of the second back doping layer, the first back doping layer and the second back doping layer are P-type, the first back doping layer contains carbon, and the second back doping layer does not contain carbon; as well as A first electrode and a second electrode, the first electrode contacts the second front doped layer, and the second electrode contacts the second back doped layer, wherein the doping types of the first front doped layer and the second front doped layer are opposite to the doping types of the first back doped layer and the second back doped layer.

2. The solar cell according to claim 1, wherein: The second front tunneling layer has a thickness smaller than that of the first front tunneling layer, and the second back tunneling layer has a thickness smaller than that of the first back tunneling layer.

3. The solar cell according to claim 1, wherein: The first front doped layer, the second front doped layer, the first back doped layer, and the second back doped layer include doped polysilicon.

4. A method for manufacturing a solar cell, characterized in that: include: Providing a silicon substrate having opposite front and back surfaces; forming a first front tunneling layer and a first front doping layer in sequence on the front surface; forming a second front tunneling layer and a second front doping layer in sequence on a local area of ​​the first front doping layer, wherein the first front doping layer and the second front doping layer are N-type, the first front doping layer contains carbon and / or nitrogen, and the second front doping layer does not contain carbon and nitrogen; forming a first back-side tunneling layer and a first back-side doping layer in sequence on the back side; forming a second back tunneling layer and a second back doping layer in sequence on a local area of ​​the first back doping layer, wherein the first back doping layer and the second back doping layer are P-type, the first back doping layer contains carbon, and the second back doping layer does not contain carbon; as well as A first electrode and a second electrode are formed, wherein the first electrode contacts the second front doped layer, and the second electrode contacts the second back doped layer, wherein the doping types of the first front doped layer and the second front doped layer are opposite to the doping types of the first back doped layer and the second back doped layer.

5. The manufacturing method according to claim 4, characterized in that: The method of forming the first front doped layer, the second front doped layer, the first back doped layer and the second back doped layer comprises: forming a first front amorphous silicon layer and a second front amorphous silicon layer on the front surface; forming a first back side amorphous silicon layer and a second back side amorphous silicon layer on the back side; removing a portion of the second front amorphous silicon layer and a portion of the second back amorphous silicon layer to form a patterned second front amorphous silicon layer and a patterned second back amorphous silicon layer; The first front amorphous silicon layer, the patterned second front amorphous silicon layer, the first back amorphous silicon layer and the patterned second back amorphous silicon layer are annealed, and the annealing process transforms the first front amorphous silicon layer into the first front doped layer, the patterned second front amorphous silicon layer into the second front doped layer, the first back amorphous silicon layer into the first back doped layer, and the patterned second back amorphous silicon layer into the second back doped layer.

6. The manufacturing method according to claim 5, characterized in that: The step of removing a portion of the second front amorphous silicon layer and a portion of the second back amorphous silicon layer to form a patterned second front amorphous silicon layer and a patterned second back amorphous silicon layer comprises: Using a laser to form a silicon oxide layer partially covering the second front amorphous silicon layer and the second back amorphous silicon layer; The second front amorphous silicon layer and the second back amorphous silicon layer are etched using the silicon oxide layer as a mask to form the patterned second front amorphous silicon layer and the patterned second back amorphous silicon layer.

7. The manufacturing method according to claim 5, characterized in that: The first front side amorphous silicon layer, the second front side amorphous silicon layer, the first back side amorphous silicon layer, and the second back side amorphous silicon layer are formed using PECVD.

8. The manufacturing method according to claim 5, characterized in that Also includes: After the annealing process, the initial second front tunneling layer not covered by the second front doped layer and the initial second back tunneling layer not covered by the second back doped layer are removed.

9. The manufacturing method according to claim 4, characterized in that: In the process of forming the first front doping layer, PECVD is used to dope carbon and / or nitrogen, and in the process of forming the first back doping layer, PECVD is used to dope carbon.

10. The manufacturing method according to claim 4, characterized in that: The second front tunneling layer has a thickness smaller than that of the first front tunneling layer, and the second back tunneling layer has a thickness smaller than that of the first back tunneling layer.

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