Surge suppression circuits and network equipment

Abstract

The surge suppression circuit and network device provided by the embodiments of the present disclosure include: a first voltage signal generating module, which generates a first voltage at the control end of the input transistor according to the input voltage of the input voltage node when receiving a first control signal, so that the input transistor charges the capacitor with a first charging current, and the first charging current is less than the surge current; a second voltage signal generating module, which generates a second voltage at the control end of the input transistor when receiving the first control signal and the second control signal, so that the input transistor charges the capacitor with a second charging current, and the second charging current is greater than the first charging current; the first control signal generating module, which outputs a first control signal to the first voltage signal generating module and the second voltage signal generating module when receiving a power-on indication signal; and the second control signal generating module, which outputs a second control signal to the second voltage signal generating module when the voltage at the first end of the capacitor meets a preset threshold voltage.

Description

Technical Field

[0001] The present invention relates to the field of control technology and related technical fields, and in particular to a surge suppression circuit and a network device. Background Art

[0002] Network equipment usually includes multiple subsystem devices, each of which includes a control mainboard. Since the control mainboard consumes a lot of power, each control mainboard is equipped with an energy storage capacitor. When the control mainboard is just powered on, the capacitor is equivalent to a short circuit, which will generate a huge surge impact on the power chip of the control mainboard, causing the power chip of the control mainboard to be protected or even damaged. In order to prevent the huge surge current during the startup process of the network equipment from causing the whole machine to be powered off, when the control mainboard corresponding to each subsystem device is powered on, the startup surge current of the control mainboard of each subsystem is different, exceeding 2 to 2.5 times the normal working current of the network equipment.

[0003] In the prior art, a resistor and capacitor slow-start circuit is designed between the gate and source of the input transistor. When the network device starts, the gate voltage change curve of the transistor is adjusted by adjusting the values ​​of the resistor and capacitor, thereby increasing the time it takes for the input transistor to be fully turned on, thereby achieving surge suppression. However, the charging efficiency of the input transistor is reduced, and the capacitor and resistor in the slow-start circuit need to be adjusted based on experience, with low accuracy. Summary of the invention

[0004] The embodiments described herein provide a surge suppression circuit and a network device to solve the problems existing in the prior art.

[0005] In a first aspect, according to the present disclosure, there is provided a surge suppression circuit, comprising: an input transistor, a capacitor, a first voltage signal generating module, a second voltage signal generating module, a first control signal generating module, and a second control signal generating module, wherein the input transistor and the capacitor are connected in series between an input voltage node and a chip power supply;

[0006] The first voltage signal generating module is configured to generate a first voltage at the control terminal of the input transistor according to the input voltage of the input voltage node when receiving the first control signal output by the first control signal generating module, so that the input transistor charges the capacitor with a first charging current, and the first charging current is less than the surge current;

[0007] The second voltage signal generating module is configured to generate a second voltage at the control terminal of the input transistor when receiving the first control signal output by the first control signal generating module and the second control signal output by the second control signal generating module, so that the input transistor charges the capacitor with a second charging current, and the second charging current is greater than the first charging current;

[0008] The first control signal generating module is configured to output a first control signal to the first voltage signal generating module and the second voltage signal generating module when receiving a power-on indication signal;

[0009] The second control signal generating module is configured to output a second control signal to the second voltage signal generating module when the voltage at the first terminal of the capacitor meets a preset threshold voltage.

[0010] In some embodiments of the present disclosure, the first voltage signal generating module includes a first switch unit and a first resistor unit;

[0011] The first switch unit is configured to be turned on when receiving the first control signal;

[0012] The first resistance unit is configured to generate a first voltage at the control terminal of the input transistor according to the input voltage.

[0013] In some embodiments of the present disclosure, the first switch unit includes a first transistor, the first resistance unit includes a first resistor and a second resistor, the control end of the first transistor is electrically connected to the first control signal generating module, the first end of the first transistor is electrically connected to the first end of the second resistor, the second end of the first transistor is electrically connected to a ground node, the second end of the second resistor is electrically connected to the control end of the input transistor and the first end of the first resistor, respectively, and the second end of the first resistor is electrically connected to an input voltage node.

[0014] In some embodiments of the present disclosure, the second voltage signal generating module includes a control unit and a second switch unit;

[0015] The control unit is configured to output a target control signal to the second switch unit according to the first control signal and the second control signal;

[0016] The second switch unit is configured to be turned on when the target control signal is at a high level, so as to generate a second voltage at the control terminal of the input transistor.

[0017] In some embodiments of the present disclosure, the control unit includes an AND gate, the second switch unit includes a second transistor, the first input end of the AND gate is electrically connected to the first control signal generating module, the second input end of the AND gate is electrically connected to the second control signal generating module, the output end of the AND gate is electrically connected to the control end of the second transistor, the first end of the second transistor is electrically connected to the ground node, and the second end of the second transistor is electrically connected to the control end of the input transistor.

[0018] In some embodiments of the present disclosure, the second control signal generating module includes a second resistance unit and a trigger unit;

[0019] The second resistance unit is configured to output a third voltage to the trigger unit according to the first terminal voltage of the capacitor;

[0020] The trigger unit is configured to output a second control signal to the second voltage signal generating module when the third voltage meets a preset threshold voltage.

[0021] In some embodiments of the present disclosure, the second resistance unit includes a third resistor and a fourth resistor, the trigger unit includes a Schmitt trigger, the first end of the third resistor is electrically connected to the first end of the capacitor, the second end of the third resistor is electrically connected to the input end of the Schmitt trigger and the first end of the fourth resistor, respectively, the second end of the fourth resistor is electrically connected to the ground node, and the output end of the Schmitt trigger is electrically connected to the second control signal generating module.

[0022] In some embodiments of the present disclosure, the input transistor is a PMOS transistor, and the first transistor and the second transistor are NMOS transistors.

[0023] In some embodiments of the present disclosure, the first control signal generating module includes a single chip microcomputer.

[0024] In a second aspect, according to the content of the present disclosure, a network device is provided, comprising the surge suppression circuit described in any one of the first aspects.

[0025] The surge suppression circuit and network device provided by the embodiments of the present disclosure include a first voltage signal generating module, a second voltage signal generating module, a first control signal generating module and a second control signal generating module. In the power-on stage of the network device, the first voltage signal generating module is turned on, the second voltage signal generating module is in an off state, the control end of the input transistor receives the first voltage output by the first voltage signal generating module, and the input transistor is in an on state. Since the on-current of the input transistor is related to the gate-source voltage of the input transistor, the voltage division of the first voltage signal generating module is used to achieve that when the first voltage signal generating module outputs the first voltage, the on-current of the input transistor is less than the surge current, that is, the first charging current is less than the surge current, thereby avoiding a huge surge current causing the network device to be powered off for protection when the network device is in the power-on state. Due to the charging of the capacitor during the power-on process, the voltage at the first end of the capacitor gradually increases. When the power-on is completed, the surge current between the input transistor and the capacitor gradually disappears. At this time, the second control signal generating module outputs a second control signal to the second voltage generating module based on the relationship between the voltage at the first end of the capacitor and the preset threshold voltage. The second voltage signal generating module outputs a second voltage to the control end of the input transistor, that is, the control end of the input transistor is directly electrically connected to the ground node. Since the second voltage output by the second voltage signal generating module is less than the first voltage output by the first voltage signal generating module, the on-current (second charging current) of the input transistor increases, thereby improving the charging rate of the capacitor.

[0026] The above description is only an overview of the technical solution of the embodiment of the present application. In order to more clearly understand the technical means of the embodiment of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure, wherein:

[0028] Figure 1 is a schematic diagram of a schematic diagram of a surge suppression circuit provided by an embodiment of the present disclosure;

[0029] Figure 2 is a circuit structure schematic diagram of a structural schematic diagram of a surge suppression circuit provided by an embodiment of the present disclosure;

[0030] Figure 3 It is a structural diagram of a computer device provided in an embodiment of the present disclosure.

[0031] In the drawings, reference numerals with the same last two digits correspond to the same elements. It should be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0034] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiments" in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0035] The term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0036] Furthermore, in all embodiments of the present disclosure, terms such as “first” and “second” are used only to distinguish one component (or a part of a component) from another component (or another part of a component).

[0037] In the description of the present application, unless otherwise specified, "plurality" means more than two (including two), and similarly, "multiple groups" means more than two groups (including two).

[0038] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0039] Based on the problems existing in the prior art, the present disclosure provides a surge suppression circuit. Figure 1 is a schematic diagram of the structure of a surge suppression circuit provided by an embodiment of the present disclosure, Figure 2 is a schematic diagram of the circuit structure of the surge suppression circuit provided by the embodiment of the present disclosure, combined with Figure 1 and Figure 2 The surge suppression circuit includes: an input transistor M, a capacitor C, a first voltage signal generating module 10, a second voltage signal generating module 20, a first control signal generating module 30 and a second control signal generating module 40, wherein the input transistor M and the capacitor C are connected in series between the input voltage node Vin and the chip power supply U; the first voltage signal generating module 10 is configured to generate a first voltage at the control end of the input transistor M according to the input voltage of the input voltage node Vin when receiving the first control signal output by the first control signal generating module 30, so that the input transistor M charges the capacitor C with a first charging current, and the first charging current is less than the surge current; the second voltage signal generating module 20, It is configured to generate a second voltage at the control end of the input transistor M when receiving the first control signal output by the first control signal generating module 30 and the second control signal output by the second control signal generating module 40, so that the input transistor M charges the capacitor C with a second charging current, and the second charging current is greater than the first charging current; the first control signal generating module 30 is configured to output the first control signal to the first voltage signal generating module 10 and the second voltage signal generating module 20 when receiving the power-on indication signal; the second control signal generating module 40 is configured to output the second control signal to the second voltage signal generating module 20 when the voltage at the first end of the capacitor C meets the preset threshold voltage.

[0040] Specifically, the input transistor is a PMOS tube, the first end of the input transistor M is electrically connected to the input voltage node Vin, the second end of the input transistor M is electrically connected to the first end of the capacitor C, and the second end of the capacitor is electrically connected to the chip power supply U.

[0041] According to the characteristics of the PMOS tube, the larger the gate-source voltage of the input transistor, the larger the on-current of the input transistor, and the smaller the gate-source voltage of the input transistor, the smaller the on-current of the input transistor. Therefore, in the surge suppression circuit provided by the embodiment of the present disclosure, the surge suppression circuit includes a first voltage signal generating module 10, a second voltage signal generating module 20, a first control signal generating module 30, and a second control signal generating module 40. After receiving the power-on indication signal, the first control signal generating module 30 outputs the first control signal to the first voltage signal generating module 10 and the second voltage signal generating module 20 respectively. After receiving the first control signal output by the first control signal generating module, the first voltage signal generating module 10 is turned on. Since the second control signal generating module does not receive the enable signal, the second control signal generating module 40 is turned on. The generating module 40 does not output the second control signal, and the second voltage signal generating module 20 is in the off state, that is, the control end of the input transistor M receives the first voltage output by the first voltage signal generating module 10, and the input transistor M is in the on state. Since the on-current of the input transistor M is related to the gate-source voltage of the input transistor M, by setting the voltage division of the first voltage signal generating module, when the first voltage signal generating module 10 outputs the first voltage, the on-current of the input transistor M is less than the surge current. At this time, the on-current of the input transistor M is the first charging current, which avoids the network device from being powered on due to a huge surge current and causing the network device to be powered off for protection. As the capacitor C is charged, the voltage at the first end of the capacitor C gradually increases. When the voltage at the first end of the capacitor C meets the preset threshold voltage, the second control signal generating module 40 outputs a second control signal to the second voltage signal generating module 20. At this time, the second voltage signal generating module 20 is turned on under the action of the first control signal and the second control signal, and the control end of the input transistor M is directly electrically connected to the ground node, that is, the second voltage applied by the second voltage signal generating module 20 to the control end of the input transistor M is 0. Since the second voltage output by the second voltage signal generating module 20 is less than the first voltage output by the first voltage signal generating module, the on-current of the input transistor M increases. At this time, the on-current of the input transistor M is the second charging current, which improves the charging rate of the capacitor.

[0042] The surge suppression circuit provided by the embodiment of the present disclosure includes a first voltage signal generating module, a second voltage signal generating module, a first control signal generating module and a second control signal generating module. In the power-on stage of the network device, the first voltage signal generating module is turned on, the second voltage signal generating module is in an off state, the control end of the input transistor receives the first voltage output by the first voltage signal generating module, and the input transistor is in an on state. Since the on-current of the input transistor is related to the gate-source voltage of the input transistor, therefore, through the voltage division of the first voltage signal generating module, when the first voltage signal generating module outputs the first voltage, the on-current of the input transistor is less than the surge current, that is, the first charging current is less than the surge current, thereby avoiding the huge surge current causing the network device to be powered off for protection when the network device is in the power-on state. Due to the charging of the capacitor during the power-on process, the voltage at the first end of the capacitor gradually increases. When the power-on is completed, the surge current between the input transistor and the capacitor gradually disappears. At this time, the second control signal generating module outputs a second control signal to the second voltage generating module based on the relationship between the voltage at the first end of the capacitor and the preset threshold voltage. The second voltage signal generating module outputs a second voltage to the control end of the input transistor, that is, the control end of the input transistor is directly electrically connected to the ground node. Since the second voltage output by the second voltage signal generating module is less than the first voltage output by the first voltage signal generating module, the on-current (second charging current) of the input transistor increases, thereby improving the charging rate of the capacitor.

[0043] In a specific embodiment, in combination with Figure 2 The first voltage signal generating module 10 includes a first switch unit 11 and a first resistor unit 12; the first switch unit 11 is configured to be turned on when receiving a first control signal; the first resistor unit 12 is configured to generate a first voltage at the control end of the input transistor M according to the input voltage.

[0044] Among them, the first switch unit 11 includes a first transistor M1, the first resistor unit 12 includes a first resistor R1 and a second resistor R2, the control end of the first transistor R1 is electrically connected to the first control signal generating module 30, the first end of the first transistor M1 is electrically connected to the first end of the second resistor R2, the second end of the first transistor M1 is electrically connected to the ground node, the second end of the second resistor R2 is electrically connected to the control end of the input transistor M and the first end of the first resistor R1 respectively, and the second end of the first resistor R1 is electrically connected to the input voltage node Vin.

[0045] Specifically, the first control signal generating module 30 includes a single chip microcomputer. When the single chip microcomputer receives a power-on indication signal (i.e., a start signal) of the network device triggered by a user, the single chip microcomputer outputs a first control signal to the first voltage signal generating module 10 and the second voltage signal generating module 20. Since the second control signal generating module 40 is electrically connected to the first end of the capacitor C, the voltage at the first end of the capacitor C is zero in the initial stage of powering on the network device. Therefore, the second control signal generating module 40 does not output the second control signal. When the second control signal generating module 40 does not output the second control signal, the second voltage signal generating module 20 is in an off state, the second voltage signal generating module 20 does not output the second voltage, and the control end of the input transistor M receives the first voltage output by the first voltage signal generating module 10.

[0046] At this time, the first switch unit 11 in the first voltage signal generating module 10 receives the first control signal, and the first switch unit 11 is turned on, so that the first resistance unit 12 is connected in series between the input voltage node Vin and the ground node, and the first voltage acting on the control terminal of the input transistor is determined according to the resistance value of the resistor included in the first resistance unit 12.

[0047] Exemplarily, the first switch unit 11 includes a first transistor M1, which is an NMOS tube. The first resistor unit 12 includes a first resistor R1 and a second resistor E2. When the first control signal generating module 30 receives a power-on indication signal of a network device triggered by a user, the first control signal output by the first control signal generating module 30 is at a high level, and the first transistor M1 is turned on. At this time, the first resistor R1 and the second resistor R2 are connected in series between the input voltage node Vin and the ground node. Since the control end of the input transistor M is electrically connected to the second end of the second resistor R2, the first voltage applied by the first voltage signal generating module 10 to the control end of the input transistor M satisfies: When the input voltage of the input node Vin is a fixed value, in the initial stage of power-on, the drain voltage of the input transistor is zero, and the absolute value of the source-drain voltage of the input transistor M is the input voltage of the input voltage node (which is a fixed value). Combined with the characteristics of the transistor, the on-current of the input transistor is related to the gate-source voltage of the input transistor, and corresponding to different source-drain voltage values, the on-current of the input transistor working in the non-saturation region is variable, and the on-current of the input transistor working in the saturation region is fixed. Therefore, by adjusting the resistance value of the first resistor R1 and the resistance value of the second resistor R2, the first voltage acting on the control terminal of the input transistor M can be changed, and then the gate-source voltage of the input transistor M can be changed, so that the input transistor M is in the startup stage, the input transistor works in the saturation region, and the on-current of the input transistor is less than the surge current, that is, the first charging current is less than the surge current.

[0048] It should be noted that the surge current is determined based on the operating current of the network device. Generally, the surge current is 2-2.5 times the operating current of the network device.

[0049] In a specific embodiment, in combination with Figure 2 The second voltage signal generating module 20 includes a control unit 21 and a second switch unit 22; the control unit 21 is configured to output a target control signal to the second switch unit 22 according to the first control signal and the second control signal; the second switch unit 22 is configured to be turned on when the target control signal is at a high level, and generate a second voltage at the control end of the input transistor M.

[0050] Among them, the control unit 21 includes an AND gate, the second switch unit 22 includes a second transistor M2, the first input end of the AND gate is electrically connected to the first control signal generating module 30, the second input end of the AND gate is electrically connected to the second control signal generating module 40, the output end of the AND gate is electrically connected to the control end of the second transistor M2, the first end of the second transistor M2 is electrically connected to the ground node, and the second end of the second transistor M2 is electrically connected to the control end of the input transistor M.

[0051] Specifically, the first control signal generating module 30 includes a single chip microcomputer. When the single chip microcomputer receives a power-on indication signal (i.e., a start signal) of a network device triggered by a user, the single chip microcomputer outputs a first control signal to the first voltage signal generating module 10 and the second voltage signal generating module 20. The second control signal generating module 40 is electrically connected to the first end of the capacitor C. In the initial stage of power-on, the voltage at the first end of the capacitor C is zero, and the input transistor M charges the capacitor C with a first input current. As the power-on time increases, the surge impact generated by power-on will decrease, and the voltage at the first end of the capacitor C will increase. When the voltage at the first end of the capacitor C increases to a voltage greater than a preset threshold voltage, the second control signal generating module 40 outputs a second control signal. At this time, the control unit 21 of the second voltage signal generating module 20 receives the first control signal and the second control signal, and the control unit 21 outputs a target control signal, and the second switch unit 22 is turned on, that is, the second switch unit 22 electrically connects the control end of the input transistor M to the ground node through the second switch unit 21, that is, the second voltage is zero.

[0052] Exemplarily, the control unit includes an AND gate, the second switch unit includes a second transistor, the second transistor is an NMOS tube, when the first control signal generating module 30 receives the power-on indication signal of the network device triggered by the user, the first control signal generating module 30 outputs a high level of the first control signal, when the voltage at the first terminal of the capacitor C increases to be greater than the preset threshold voltage, the second control signal output by the second control signal generating module 40 is a high level, the AND gate outputs a high level, the second transistor M2 is turned on, at this time, the control terminal of the input transistor M is connected to the ground node through the second transistor M2, therefore, the second voltage applied by the second voltage signal generating module 20 to the control terminal of the input transistor M is zero. Therefore, when the voltage at the first terminal of the capacitor C is greater than the preset threshold voltage, by adjusting the control terminal of the input transistor M from the first voltage to the second voltage, the second voltage is less than the first voltage, the gate-source voltage of the input transistor is increased, and then the on-current of the input transistor is increased, that is, the on-current of the input transistor is the second charging current, the second charging current is greater than the first charging current, so as to improve the charging efficiency of the circuit to the capacitor after the power-on surge impact is reduced.

[0053] In a specific embodiment, in combination with Figure 2 The second control signal generating module 40 includes a second resistance unit 41 and a trigger unit 42; the second resistance unit 41 is configured to output a third voltage to the trigger unit 42 according to the first terminal voltage of the capacitor; the trigger unit 42 is configured to output a second control signal to the second voltage signal generating module 20 when the third voltage meets a preset threshold voltage.

[0054] Among them, the second resistance unit 41 includes a third resistor R3 and a fourth resistor R4, the trigger unit 42 includes a Schmitt trigger, the first end of the third resistor R1 is electrically connected to the first end of the capacitor C, the second end of the third resistor R3 is electrically connected to the input end of the Schmitt trigger and the first end of the fourth resistor R4 respectively, the second end of the fourth resistor R4 is electrically connected to the ground node, and the output end of the Schmitt trigger is electrically connected to the second control signal generating module 20.

[0055] Specifically, the second control signal generating module 40 includes a second resistor unit 41 and a trigger unit 42. In the initial stage of power-on, the voltage at the first end of the capacitor is zero, and the divided voltage of the third resistor R3 and the fourth resistor R4 included in the second resistor unit 41 is zero. As the power-on time increases, the surge impact generated by power-on will decrease, and the voltage at the first end of the capacitor C will increase. When the voltage at the first end of the capacitor C increases to be greater than the preset threshold voltage, the divided voltage of the third resistor R3 and the fourth resistor R4 included in the second resistor unit 41 is related to the voltage at the first end of the capacitor C. Therefore, by setting the resistance values ​​of the third resistor R3 and the fourth resistor R4, when the voltage at the first end of the capacitor C meets the preset threshold voltage, the third voltage output by the second resistor unit 41 to the trigger unit 42 can trigger the trigger unit 42 to output the second control signal.

[0056] It should be noted that the value of the preset threshold voltage is related to the resistance values ​​of the third resistor and the fourth resistor included in the second resistor unit, and is also related to the curve of the surge current.

[0057] Exemplarily, when the third resistor R3 is set to 5.1KΩ and the fourth resistor R4 is set to 1.1KΩ, when the voltage at the first end of the capacitor is about 9V, the surge current tends to be flat, the Schmidt NOT gate is just at the trigger threshold of about 1.6V, the second transistor is turned on, the absolute value of the gate-source voltage of the input transistor is the maximum value, the input transistor is fully turned on, and the on-current of the input transistor is the maximum, that is, the second charging current is the maximum.

[0058] In the surge suppression circuit provided by the embodiment of the present disclosure, since the index parameters of the input transistor are known, the resistance values ​​of the first resistor and the second resistor can be adjusted according to the index parameters of the input transistor and the input voltage of the input voltage node, and then the voltage division value of the first resistor and the second resistor can be adjusted to ensure that the absolute value of the on-current of the input transistor during power-on is less than the surge current value required by the design index. And according to the index parameters of the input transistor, the resistance values ​​of the third resistor and the fourth resistor are adjusted, and then the voltage division value of the third resistor and the fourth resistor is adjusted. When the absolute value of the source-drain voltage of the input transistor is less than a certain value, the Schmidt NOT gate is triggered to maximize the absolute value of the gate-source voltage of the input transistor, and the input transistor is fully turned on, thereby increasing the charging rate of the capacitor.

[0059] On the basis of the above embodiments, the embodiments of the present disclosure further provide a network device, including the surge suppression circuit described in any one of the above embodiments, and having the beneficial effects described in any one of the above embodiments, which will not be specifically described in the embodiments of the present disclosure.

[0060] The present application also provides a computer device, including the network device described in the above embodiment. Figure 3 , Figure 3This is a basic structural block diagram of the computer device in this embodiment.

[0061] The computer device includes a memory 510 and a processor 520 that are connected to each other through a system bus. It should be noted that the figure only shows a computer device with components 510-520, but it should be understood that it is not required to implement all the components shown, and more or fewer components can be implemented instead. Among them, those skilled in the art can understand that the computer device here is a device that can automatically perform numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes but is not limited to microprocessors, application specific integrated circuits (Application Specific Integrated Circuit, ASIC), programmable gate arrays (Field-Programmable Gate Array, FPGA), digital processors (Digital Signal Processor, DSP), embedded devices, etc.

[0062] Computer devices can be computing devices such as desktop computers, notebooks, PDAs, and cloud servers. Computer devices can interact with users through keyboards, mice, remote controls, touch pads, or voice control devices.

[0063] The memory 510 includes at least one type of readable storage medium, and the readable storage medium includes a non-volatile memory or a volatile memory, such as a flash memory, a hard disk, a multimedia card, a card-type memory (e.g., SD or DX memory, etc.), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a programmable read-only memory (PROM), a magnetic memory, a magnetic disk, an optical disk, etc., and the RAM may include a static RAM or a dynamic RAM. In some embodiments, the memory 510 may be an internal storage unit of a computer device, such as a hard disk or a memory of the computer device. In other embodiments, the memory 510 may also be an external storage device of a computer device, such as a plug-in hard disk, a smart memory card (SMC), a secure digital (SD) card, or a flash card (Flash Card), etc., equipped on the computer device. Of course, the memory 510 may also include both an internal storage unit of the computer device and an external storage device thereof. In this embodiment, the memory 510 is generally used to store an operating system and various application software installed on the computer device, such as the program code of the above method, etc. In addition, the memory 510 may also be used to temporarily store various data that have been output or are to be output.

[0064] The processor 520 is generally used to perform the overall operation of the computer device. In this embodiment, the memory 510 is used to store program codes or instructions, the program code includes computer operation instructions, and the processor 520 is used to execute the program codes or instructions stored in the memory 510 or process data, such as running the program code of the above method.

[0065] In this article, the bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus system can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0066] Another embodiment of the present application also provides a computer-readable medium, which may be a computer-readable signal medium or a computer-readable medium. A processor in a computer reads a computer-readable program code stored in the computer-readable medium, so that the processor can execute the functional actions specified in each step or a combination of steps in the above method; and generate a device for implementing the functional actions specified in each block or a combination of blocks in the block diagram.

[0067] Computer-readable media include but are not limited to electronic, magnetic, optical, electromagnetic, infrared memory or semiconductor systems, devices or apparatuses, or any appropriate combination of the foregoing, the memory is used to store program codes or instructions, the program codes include computer operating instructions, and the processor is used to execute the program codes or instructions of the above methods stored in the memory.

[0068] For the definitions of memory and processor, please refer to the description of the aforementioned computer device embodiment and will not be repeated here.

[0069] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0070] Each functional unit or module in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0071] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor (processor) to perform all or part of the steps of each embodiment method of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), disk or optical disk and other media that can store program code.

[0072] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0073] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for purposes of illustration only and are not intended to limit the scope of the present application.

[0074] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. A surge suppression circuit, characterized in that: It includes: an input transistor, a capacitor, a first voltage signal generating module, a second voltage signal generating module, a first control signal generating module and a second control signal generating module, wherein the input transistor and the capacitor are connected in series between an input voltage node and a chip power supply; The first voltage signal generating module is configured to generate a first voltage at the control terminal of the input transistor according to the input voltage of the input voltage node when receiving the first control signal output by the first control signal generating module, so that the input transistor charges the capacitor with a first charging current, and the first charging current is less than the surge current; The second voltage signal generating module is configured to generate a second voltage at the control terminal of the input transistor when receiving the first control signal output by the first control signal generating module and the second control signal output by the second control signal generating module, so that the input transistor charges the capacitor with a second charging current, and the second charging current is greater than the first charging current; The first control signal generating module is configured to output a first control signal to the first voltage signal generating module and the second voltage signal generating module when receiving a power-on indication signal; The second control signal generating module is configured to output a second control signal to the second voltage signal generating module when the voltage at the first terminal of the capacitor meets a preset threshold voltage; The second control signal generating module includes a second resistance unit and a trigger unit; The second resistance unit is configured to output a third voltage to the trigger unit according to the first terminal voltage of the capacitor; The trigger unit is configured to output a second control signal to the second voltage signal generating module when the third voltage meets a preset threshold voltage; The second resistance unit includes a third resistor and a fourth resistor, the trigger unit includes a Schmitt trigger, the first end of the third resistor is electrically connected to the first end of the capacitor, the second end of the third resistor is electrically connected to the input end of the Schmitt trigger and the first end of the fourth resistor respectively, the second end of the fourth resistor is electrically connected to the ground node, and the output end of the Schmitt trigger is electrically connected to the second control signal generating module; The first voltage signal generating module includes a first switch unit and a first resistor unit; The first switch unit is configured to be turned on when receiving the first control signal; The first resistance unit is configured to generate a first voltage at a control terminal of the input transistor according to the input voltage; The first switch unit includes a first transistor, the first resistance unit includes a first resistor and a second resistor, the control end of the first transistor is electrically connected to the first control signal generating module, the first end of the first transistor is electrically connected to the first end of the second resistor, the second end of the first transistor is electrically connected to a ground node, the second end of the second resistor is electrically connected to the control end of the input transistor and the first end of the first resistor, respectively, and the second end of the first resistor is electrically connected to an input voltage node.

2. The circuit according to claim 1, characterized in that The second voltage signal generating module includes a control unit and a second switch unit; The control unit is configured to output a target control signal to the second switch unit according to the first control signal and the second control signal; The second switch unit is configured to be turned on when the target control signal is at a high level, so as to generate a second voltage at the control terminal of the input transistor.

3. The circuit according to claim 2, characterized in that The control unit includes an AND gate, the second switch unit includes a second transistor, a first input end of the AND gate is electrically connected to the first control signal generating module, a second input end of the AND gate is electrically connected to the second control signal generating module, an output end of the AND gate is electrically connected to the control end of the second transistor, a first end of the second transistor is electrically connected to a ground node, and a second end of the second transistor is electrically connected to the control end of the input transistor.

4. The circuit according to claim 3, characterized in that The input transistor is a PMOS transistor, and the first transistor and the second transistor are NMOS transistors.

5. The circuit according to claim 1, characterized in that The first control signal generating module includes a single chip microcomputer.

6. A network device, characterized in that: The invention comprises the surge suppression circuit as claimed in any one of claims 1 to 5.

Images