An ECO method based on adaptive learning

Abstract

The present invention proposes an ECO method based on adaptive learning, which is applied to the ECO operation of netlists at different stages in the chip design process. The method obtains the first netlist that has completed ECO in the previous stage and the second netlist to be ECOed in the current stage; based on the structural similarity between the first netlist and the second netlist, the netlist modification position involved in the ECO in the previous stage is determined, and the input boundary and output boundary are delineated in the first netlist; the matching signal with the input boundary and output boundary delineated in the first netlist is searched in the second netlist; the boundary range to be ECOed in the second netlist is delineated according to these matching signals; and the ECO operation is performed within the delineated boundary range. The method improves the efficiency and accuracy of ECO.

Description

Technical Field

[0001] The invention belongs to the field of ECO technology, and in particular relates to an ECO method based on adaptive learning. Background Art

[0002] ECO (Engineering Change Order) refers to the process of directly modifying integrated circuits in the digital chip design process, that is, the process of modifying the gate-level netlist at each design stage (synthesis stage, DFT stage, PNR stage, etc.) so that the modified circuit logic function is consistent with the expected one.

[0003] When designing chips, chip design manufacturers usually start from RTL, perform logic synthesis on RTL to obtain a synthesized netlist, then add DFT settings such as scan chain to obtain a DFT netlist, and then perform layout and routing to obtain a PNR netlist. These netlists at different stages often have strong similarities. However, the traditional ECO method is to perform ECO on the netlist of any stage to make it equivalent to the new RTL logic after the change, but this traditional method does not take into account the similarity of the netlists of adjacent stages, such as the similarity between the DFT netlist and the synthesized netlist, which makes the ECO results perform poorly in some cases. For example, in a certain stage, many hierarchical structures in the netlist are broken up and become flattened.

[0004] The ECO methods in the prior art often lack adaptability. ECO generally involves the modification of netlists at multiple stages. Traditional ECO methods usually only focus on the modification of the netlist at the current stage, while ignoring the correlation and impact with netlists at other stages. This may cause the ECO of netlists at subsequent stages to be treated as completely independent ECO tasks, and it is impossible to refer to the completed ECO to improve quality and reduce time, thereby increasing design costs and risks. With the increase in the complexity of chip design, the number of logic modules and circuit units in the netlist has increased dramatically, making the ECO process more complicated and cumbersome. Traditional ECO methods are often inefficient and error-prone when dealing with a large number of modifications. Summary of the invention

[0005] The present invention provides an ECO method based on adaptive learning, which is used in the ECO of netlists at various stages in chip design. The purpose is to utilize the similarity of netlists at adjacent stages and quickly implement the ECO of the netlist at the current stage according to the ECO solution of the netlist at the previous stage.

[0006] The scheme of the present invention is as follows:

[0007] In a first aspect, the present invention provides an ECO method based on adaptive learning, the method comprising the following steps:

[0008] Step S1, obtaining a first netlist that has completed ECO in the previous stage and a second netlist that needs to be ECO in the current stage.

[0009] The stages include, in order from front to back, a synthesis stage, a DFT stage and a PNR stage, and the corresponding stage netlists are a synthesis netlist, a DFT netlist and a PNR netlist.

[0010] Step S2, according to the structural similarity between the first netlist and the second netlist, determining the location of the netlist modification involved in the previous stage ECO, and delineating the input boundary and the output boundary in the first netlist.

[0011] Furthermore, in step S2, determining the position of the netlist modification involved in the previous stage of ECO according to the structural similarity between the first netlist and the second netlist includes the following steps:

[0012] S21, comparing the first netlist and the second netlist to identify structural differences between the two.

[0013] S22, based on the structural differences, locate the logic module or circuit unit specifically modified by the ECO in the previous stage.

[0014] S23, analyzing the modified logic module or circuit unit to determine its corresponding input signal and output signal.

[0015] The input boundary and the output boundary completely include the logic module or circuit unit modified by the ECO in the previous stage, and the circuit elements directly related thereto.

[0016] In step S2, defining input boundaries and output boundaries in the first netlist includes the following steps:

[0017] S24, based on the input signal and the output signal determined in step S23, identifying the circuit elements directly connected to these signals in the first netlist;

[0018] S25, forming an input boundary with the circuit elements directly connected to the input signal and their upstream connections;

[0019] S26, forming an output boundary with the circuit elements directly connected to the output signal and their downstream connections.

[0020] Step S3: searching, in the second netlist, for matching signals with input boundaries and output boundaries defined in the first netlist.

[0021] In step S3, when searching for matching signals with the input boundaries and output boundaries defined in the first netlist, if direct matching fails, the search range in the second netlist is gradually expanded until a signal matching the input boundaries and output boundaries in the first netlist is found.

[0022] For the input boundary, if the matching signal is in the main input PI direction, the search range is expanded in the PI direction;

[0023] For the output boundary, if the matching signal is in the main output PO direction, the search range is expanded in the PO direction.

[0024] Step S4: defining a boundary range to be ECOed in the second netlist according to the matching signal.

[0025] If the ECO of the previous stage involves the modification of multiple logic modules or circuit units, when determining the position of the netlist modification involved in the ECO of the previous stage, all modified logic modules or circuit units are identified, and for each modified logic module or circuit unit, step S23 is respectively executed to determine its corresponding input signal and output signal;

[0026] Based on the input signals and output signals of all modified logic modules or circuit units, input boundaries and output boundaries are comprehensively defined in the first netlist.

[0027] Step S5, performing ECO in the boundary range to be ECOed in the second netlist.

[0028] No ECO is performed on the areas outside the boundary range to be ECOed in the second netlist.

[0029] The method further comprises a verification step for verifying the functional correctness of the second netlist after ECO, the verification step comprising:

[0030] Use simulation tools to perform functional simulation on the second netlist after ECO to confirm that its functionality is consistent with expectations before ECO.

[0031] After the functional simulation passes verification, physical verification is performed to ensure that the netlist after ECO meets the physical design constraints.

[0032] In a second aspect, the present invention provides an electronic design automation system, the system comprising: a memory for storing netlists at different stages; and a processor for executing an ECO method based on adaptive learning as described in the first aspect.

[0033] In a third aspect, the present invention provides a computer-readable storage medium comprising instructions, which, when executed by a computer, enables the computer to execute an ECO method based on adaptive learning as described in the first aspect.

[0034] Compared with the prior art, the present invention has the following beneficial effects:

[0035] The present invention solves the problem that traditional ECO algorithms cannot obtain good results in certain specific situations, including but not limited to when the logic levels of the chip netlist are severely ungrouped or even flattened. The traditional fully automatic ECO algorithm needs to add a large number of new instances, and the backend may not be able to accept such a large ECO change. The solution proposed by the present invention can utilize the similarity of the netlists of adjacent stages and use the algorithm to learn the ECO changes of adjacent stages, thereby obtaining good ECO results and greatly reducing the ECO time. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 The present invention is a flowchart of an ECO method based on adaptive learning. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention is described clearly and completely below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Example 1

[0038] like Figure 1 FIG. 1 is a flow chart of an ECO method based on adaptive learning in this embodiment, and the method includes the following steps:

[0039] Step S1, obtaining a first netlist that has completed ECO in the previous stage and a second netlist that needs to be ECO in the current stage.

[0040] The stages include, in order from front to back, a synthesis stage, a DFT stage and a PNR stage, and the corresponding stage netlists are a synthesis netlist, a DFT netlist and a PNR netlist.

[0041] It should be noted that, normally, designing a chip requires several steps of RTL -> integrated netlist -> DFT netlist -> PNR netlist. They are all drawings of the same design, but just different stages. However, the traditional flow does not take into account the structural similarity of netlists at different stages, wasting this information. The ECO method based on adaptive learning (Learning ECO) of this embodiment uses the structural similarity of netlists at different stages to perform some training and narrow the scope of the solution.

[0042] For example, for a fully flattened netlist, if you make a modification to any small area, if the tool cannot quickly locate where the modification is, it must search a large area in the entire netlist to find the modification. However, if structural similarity is used to obtain the scope of ECO modification on the DFT netlist, and no modifications are made to other places, then I can use structural similarity to gradually compare the DFT netlist and the PNR netlist, and find the corresponding signal on the PNR netlist for each signal on the DFT.

[0043] Step S2, according to the structural similarity between the first netlist and the second netlist, determining the location of the netlist modification involved in the previous stage ECO, and delineating the input boundary and the output boundary in the first netlist.

[0044] In step S2, according to the structural similarity between the first netlist and the second netlist, determining the location of the netlist modification involved in the previous stage of ECO includes the following steps:

[0045] S21, comparing the first netlist and the second netlist to identify structural differences between the two.

[0046] The signals matching the input boundary and the output boundary can be matched according to the similarity, which can be achieved through engineering experience or direct diff, and is not specifically limited in this embodiment.

[0047] S22, based on the structural differences, locate the logic module or circuit unit specifically modified by the ECO in the previous stage.

[0048] S23, analyzing the modified logic module or circuit unit to determine its corresponding input signal and output signal.

[0049] The input boundary and the output boundary completely include the logic module or circuit unit modified by the ECO in the previous stage, and the circuit elements directly related thereto.

[0050] A simple method to determine the location of netlist modifications involved in the previous stage of ECO. For example, a module contains sub module A and sub module B. If ECO was performed on sub module B in the previous stage, then this stage only needs to consider operations within the scope of sub module B. Sub module A and those outside the module do not need to be considered.

[0051] However, in complex situations, for example, in order to achieve optimization effects, the designer dismantles the hierarchical structure, such as dismantling sub module B and breaking it up into the upper module (this operation is called ungroup). At this time, sub module B loses its clear boundaries. When performing ECO, the entire module needs to be considered. In extreme cases, all hierarchical structures are broken up. This situation is called flatten all. At this time, any ECO must match the algorithm operation globally (the entire chip).

[0052] In the above process, the "Learning ECO" we mentioned is essentially a heuristic method based on historical data or adjacent stage netlist information to predict and expand signal boundaries. This method can significantly reduce the solution space that the ECO algorithm needs to search, especially when dealing with large and complex designs or performing operations such as ungroup and flatten, the performance of traditional algorithms may drop sharply. By utilizing the similarities between netlists, the Learning algorithm can guide the ECO algorithm to find the optimal solution more efficiently, thereby improving the efficiency and quality of the entire design process. In step S2, the input boundary and the output boundary are defined in the first netlist, including the following steps:

[0053] S24, based on the input signal and the output signal determined in step S23, identifying the circuit elements directly connected to these signals in the first netlist;

[0054] S25, forming an input boundary with the circuit elements directly connected to the input signal and their upstream connections;

[0055] S26, forming an output boundary with the circuit elements directly connected to the output signal and their downstream connections.

[0056] Step S3: searching, in the second netlist, for matching signals with input boundaries and output boundaries defined in the first netlist.

[0057] In step S3, when searching for matching signals with the input boundaries and output boundaries defined in the first netlist, if direct matching fails, the search range in the second netlist is gradually expanded until a signal matching the input boundaries and output boundaries in the first netlist is found.

[0058] For the input boundary, if the matching signal is in the main input PI direction, the search range is expanded in the PI direction;

[0059] For the output boundary, if the matching signal is in the main output PO direction, the search range is expanded in the PO direction.

[0060] It should be noted that the input boundary is upstream of the ECO point (the signal comes from here), and the output boundary is downstream of the ECO point (the signal is transmitted through the ECO point). By drawing these two boundaries, the ECO point is in the middle of the two boundaries, and the boundary range of the ECO is determined.

[0061] Step S4: defining a boundary range to be ECOed in the second netlist according to the matching signal.

[0062] If the ECO of the previous stage involves the modification of multiple logic modules or circuit units, when determining the position of the netlist modification involved in the ECO of the previous stage, all modified logic modules or circuit units are identified, and for each modified logic module or circuit unit, step S23 is respectively executed to determine its corresponding input signal and output signal;

[0063] Based on the input signals and output signals of all modified logic modules or circuit units, input boundaries and output boundaries are comprehensively defined in the first netlist.

[0064] Step S5, performing ECO in the boundary range to be ECOed in the second netlist.

[0065] No ECO is performed on the areas outside the boundary range to be ECOed in the second netlist.

[0066] The method further comprises a verification step for verifying the functional correctness of the second netlist after ECO, the verification step comprising:

[0067] Use simulation tools to perform functional simulation on the second netlist after ECO to confirm that its functionality is consistent with expectations before ECO.

[0068] After the functional simulation passes verification, physical verification is performed to ensure that the netlist after ECO meets the physical design constraints. Example 2

[0069] This embodiment provides an electronic design automation system, which includes: a memory for storing netlists at different stages; and a processor for executing the ECO method based on adaptive learning described in Embodiment 1.

[0070] The memory includes flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory, etc.), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, disk, optical disk, etc. The memory can be an internal storage unit of a computer device, such as the hard disk or memory of the computer device, or an external storage of a computer device, such as a plug-in hard disk equipped on the computer device, a smart memory card (Smart Media Card, SMC),

[0071] Secure Digital (SD) Card, Flash Card, etc. Example 3

[0072] This embodiment provides a computer-readable storage medium containing instructions. When the instructions are executed by a computer, the computer executes the ECO method based on adaptive learning described in Embodiment 1.

[0073] The present invention is described by specific embodiments, and it should be understood by those skilled in the art that various changes and equivalent substitutions may be made to the present invention without departing from the scope of the present invention. In addition, various modifications may be made to the present invention for specific situations or materials without departing from the scope of the present invention. Therefore, the present invention is not limited to the disclosed specific embodiments, but should include all implementation methods falling within the scope of the claims of the present invention.

Claims

1. An ECO method based on adaptive learning, It is characterized in that The method is used in the ECO of the netlist at each stage in chip design, and the method comprises the following steps: Step S1, obtaining a first netlist that has completed ECO in the previous stage and a second netlist to be ECOed in the current stage; the stages, in order from front to back, at least include: a synthesis stage, a DFT stage, and a PNR stage, and the corresponding stage netlists are: a synthesis netlist, a DFT netlist, and a PNR netlist; Step S2, determining the location of the netlist modification involved in the previous stage of ECO according to the structural similarity between the first netlist and the second netlist, and delineating the input boundary and the output boundary in the first netlist; Step S3, searching, in the second netlist, for matching signals with input boundaries and output boundaries defined in the first netlist; Step S4, defining a boundary range to be ECOed in the second netlist according to the matching signal; Step S5, performing ECO in the boundary range to be ECOed in the second netlist.

2. The ECO method based on adaptive learning according to claim 1, It is characterized in that No ECO is performed on the areas outside the boundary range to be ECOed in the second netlist.

3. The ECO method based on adaptive learning according to claim 1, It is characterized in that In step S2, according to the structural similarity between the first netlist and the second netlist, determining the location of the netlist modification involved in the previous stage of ECO includes the following steps: S21, comparing the first netlist and the second netlist to identify structural differences between the two; S22, based on the structural differences, locate the logic module or circuit unit specifically modified by the ECO in the previous stage; S23, analyzing the modified logic module or circuit unit to determine its corresponding input signal and output signal.

4. The ECO method based on adaptive learning according to claim 3, It is characterized in that The input boundary and the output boundary completely include the logic module or circuit unit modified by the ECO in the previous stage, and the circuit elements directly related thereto; the step S2 of delineating the input boundary and the output boundary in the first netlist includes the following steps: S24, based on the input signal and the output signal determined in step S23, identifying the circuit elements directly connected to these signals in the first netlist; S25, forming an input boundary with the circuit elements directly connected to the input signal and their upstream connections; S26, forming an output boundary with the circuit elements directly connected to the output signal and their downstream connections.

5. The ECO method based on adaptive learning according to claim 4, It is characterized in that In the step S3, when searching for a signal matching the input boundary and the output boundary defined in the first netlist, if direct matching fails, the search range in the second netlist is gradually expanded until a signal matching the input boundary and the output boundary in the first netlist is found; For the input boundary, if the matching signal is in the main input PI direction, the search range is expanded in the PI direction; For the output boundary, if the matching signal is in the main output PO direction, the search range is expanded in the PO direction.

6. The ECO method based on adaptive learning according to claim 5, It is characterized in that If the ECO of the previous stage involves the modification of multiple logic modules or circuit units, when determining the position of the netlist modification involved in the ECO of the previous stage, all modified logic modules or circuit units are identified, and for each modified logic module or circuit unit, step S23 is respectively executed to determine its corresponding input signal and output signal; Based on the input signals and output signals of all modified logic modules or circuit units, input boundaries and output boundaries are comprehensively defined in the first netlist.

7. An ECO method based on adaptive learning according to any one of claims 1 to 6, It is characterized in that The method further comprises a verification step for verifying the functional correctness of the second netlist after ECO, the verification step comprising: Use formal verification tools to perform functional simulation on the second netlist after ECO to confirm that its functionality is consistent with expectations before ECO.

8. An electronic design automation system, It is characterized in that The system comprises: a memory for storing netlists at different stages; and a processor for executing an ECO method based on adaptive learning according to any one of claims 1 to 7.

9. A computer-readable storage medium comprising instructions, which, when executed by a computer, enables the computer to execute an ECO method based on adaptive learning according to any one of claims 1 to 7.

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