Current controlled buffer using analog biasing

Abstract

This application relates to current-controlled buffers using analog biasing. A semiconductor device includes a pair of transistors configured to perform buffering of input data to an output. The semiconductor device also includes a first transistor configured to receive a common mode of the output at a gate terminal of the first transistor. The semiconductor device further includes a current source configured to control a tail current from the pair of transistors. Additionally, the semiconductor device includes a second transistor configured to adjust the tail current based at least in part on a change in a reference voltage used by the pair of transistors to buffer the input data. Moreover, the semiconductor device includes a third transistor configured to adjust the tail current based at least in part on a change in a locally generated reference voltage based at least in part on process and temperature variations.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to U.S. Application No. 63 / 481,482, filed January 25, 2023, entitled “Current-Controlled Buffer Using Analog Bias,” the entirety of which is incorporated herein by reference for all purposes. TECHNICAL FIELD

[0003] Embodiments of the present disclosure generally relate to semiconductor devices. More specifically, embodiments of the present disclosure relate to current-controlled buffers controlled using analog bias of semiconductor devices, such as memory devices. BACKGROUND

[0004] Generally, computing systems can include electronic devices that communicate information via electrical signals in operation. For example, a computing system can include a processor communicatively coupled to a memory device, such as a dynamic random access memory (DRAM) device. In this way, the processor can communicate with the memory device to, for example, retrieve executable instructions, retrieve data to be processed by the processor, and / or store data output from the processor. To perform these operations, the processor and the memory device can exchange command address (CA) bits to indicate the type of operation to be performed and the memory location. The CA bits can be buffered in one or more CA buffers. The CA buffers can use current control and programmable current sources to compensate for process variations of transistors on-chip. However, each chip is manually programmed based on the process and reference voltage of the chip. This programming process requires a significant amount of time. Further, the digital circuitry used to implement the programming and control can consume a relatively large amount of excess chip space. Additionally, the programming can not account for temperature that can lead to potential degradation of performance of the CA buffers over time. Further, common mode noise can degrade performance over time and / or at higher frequencies. In some cases, multiple CA buffers can be programmed together to save programming time and / or implementation area consumption. However, this grouping cannot mitigate variations across the CA buffers.

[0005] Embodiments of the present disclosure can be directed to one or more of the issues raised above. SUMMARY

[0006] One aspect of the present application relates to a semiconductor device comprising: a pair of transistors configured to implement a buffer of input data to an output; a first transistor configured to receive a common mode of the output at a gate terminal of the first transistor; a current source configured to control a tail current from the pair of transistors; a second transistor configured to adjust the tail current based at least in part on a change in a reference voltage used by the pair of transistors to buffer the input data; and a third transistor configured to adjust the tail current based at least in part on a change in a locally generated reference voltage, the change based at least in part on process and temperature variations.

[0007] Another aspect of the present application relates to a method of operating a semiconductor device comprising: sampling a common mode of an output of a data buffer of the semiconductor device as a sampled common mode; transmitting the sampled common mode to a gate of a first transistor coupled to a first leg of a current mirror; providing a charge to a second leg of the current mirror based at least in part on the sampled common mode; dissipating, by a second transistor, a first portion of the charge via a first path from the second leg by using a reference voltage of the data buffer coupled to a gate terminal of the second transistor; dissipating, by a third transistor, a second portion of the charge via a second path from the second leg by using a locally generated reference voltage coupled to a gate terminal of the third transistor; using a third portion of the charge to control a tail current of the data buffer.

[0008] Yet another aspect of the present application relates to a data buffer comprising: a first input transistor configured to receive input data at a gate terminal of the first input transistor; a second input transistor configured to receive a reference voltage at a gate terminal of the second input transistor; a common mode transistor configured to receive a common mode between first terminals of the first and second input transistors, wherein the common mode transistor is configured to receive the common mode at a gate terminal of the common mode transistor; a current source configured to control a tail current from second terminals of the first and second input transistors; a first control transistor configured to receive the reference voltage at a gate terminal of the first control transistor; a second control transistor configured to receive a locally generated reference voltage at a gate terminal of the second control transistor; and a current mirror comprising: a first leg coupled to the common mode transistor; and a second leg coupled to the first control transistor, the second control transistor, and the current source. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1is a simplified block diagram illustrating certain features of a memory device having a bank control in accordance with embodiments of the present disclosure, the bank control including a command address input circuit having a command address buffer;

[0010] Figure 2 is a command address buffer using digital control in accordance with embodiments of the present disclosure Figure 1 is a circuit diagram of a command address buffer of

[0011] Figure 3 is a command address buffer using analog bias based control in accordance with embodiments of the present disclosure Figure 1 is a circuit diagram of a command address buffer of

[0012] Figure 4 is a flowchart of a process utilized by the command address buffer of Figure 3 DETAILED DESCRIPTION

[0013] One or more specific embodiments will be described below. To provide a concise description of these embodiments, all features of an actual implementation can not be described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which can vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

[0014] ​As previously discussed, digitally controlled command / address (CA) buffers can require relatively long times to perform training and programming. In addition, this control scheme can consume excess space for digital implementation and tracking, and can not be able to take into account some parameters (e.g., temperature) without adding more circuitry. Further, due to lack of common mode noise control, digitally controlled CA buffers can degrade over time and / or at high frequencies. Instead, an analog bias-based current controlled CA buffer provides enhancements over digitally controlled buffers. For example, an analog bias-based current controlled CA buffer can be implemented without lengthy silicon testing and programming timing, enabling a semiconductor product using an analog bias-based current controlled CA buffer to be delivered faster than a semiconductor product using a digitally controlled CA buffer. In addition, since the current control of an analog bias-based current controlled CA buffer does not rely on digital control, an analog bias-based current controlled CA buffer can require less silicon area due to lack of digital logic implementation or signal tracking between digital logic implementation and the analog bias-based current controlled CA buffer. Further, an analog bias-based current controlled CA buffer provides control over common mode across process, temperature, and reference voltage variations. In addition, since each analog bias-based current controlled CA buffer can be controlled locally with relatively less area consumed, each analog bias-based current controlled CA buffer can be driven independently to compensate for different conditions (e.g., temperature) between different analog bias-based current controlled CA buffers in a single device. An analog bias-based current controlled CA buffer can also have enhanced high frequency response when common mode noise is attenuated with an analog loop control. Additionally, an analog bias-based current controlled CA buffer can also provide enhanced eye opening in the data eye of the buffered data when compared to a digitally controlled CA buffer.

[0015] Reference is now made to the following descriptions, Figure 1 is a simplified block diagram illustrating certain features of the memory device 10. In particular, Figure 1 The block diagram of FIG. 1 is a functional block diagram illustrating certain functionality of the memory device 10. According to one embodiment, the memory device 10 can be a double data rate type five synchronous dynamic random access memory (DDR5 SDRAM) device. Various features of DDR5 SDRAM allow for reduced power consumption, more bandwidth, and more storage capacity compared to previous generations of DDR SDRAM.

[0016] Memory device 10 can include a number of memory banks 12. For example, memory banks 12 can be DDR5 SDRAM memory banks. Memory banks 12 can be provided on one or more chips (e.g., SDRAM chips) arranged on a dual in-line memory module (DIMM). As will be appreciated, each DIMM can include a number of SDRAM memory chips (e.g., x8 or x16 memory chips). Each SDRAM memory chip can include one or more memory banks 12. Memory device 10 represents a portion of a single memory chip (e.g., SDRAM chip) having a number of memory banks 12. For DDR5, memory banks 12 can be further arranged to form memory bank groups. For example, for an 8 gigabyte (Gb) DDR5 SDRAM, a memory chip can include 16 memory banks 12 arranged into 8 memory bank groups, each memory bank group including 2 memory banks. For example, for a 16 Gb DDR5 SDRAM, a memory chip can include 32 memory banks 12 arranged into 8 memory bank groups, each memory bank group including 4 memory banks. Various other configurations, organizations, and sizes of memory banks 12 on memory device 10 can be utilized depending on the application and design of the overall system.

[0017] Memory device 10 can include a command interface 14 and an input / output (I / O) interface 16. Command interface 14 is configured to provide a number of signals (e.g., signals 15) from an external (e.g., host) device (not shown) such as a processor or controller. The processor or controller can provide various signals 15 to memory device 10 to facilitate the transmission and reception of data to be written to or read from memory device 10.

[0018] As will be appreciated, command interface 14 can include a number of circuits (e.g., clock input circuit (CIC) 18 and command address input circuit (CAIC) 20, for example, to ensure proper handling of signals 15. Command interface 14 can receive one or more clock signals from an external device. Generally, double data rate (DDR) memory utilizes a system clock signal in a differential pair, a true clock signal Clk_t and a bar / complimentary clock signal Clk_c. A positive clock edge of DDR refers to the point at which the rising true clock signal Clk_t crosses the falling complimentary clock signal Clk_c, while a negative clock edge indicates a transition of the falling true clock signal Clk_t and a rising of the complimentary clock signal Clk_c. Commands (e.g., read commands, write commands, etc.) are typically keyed on the positive edge of the clock signal and data is transmitted or received on both the positive and negative clock edges.

[0019] Clock input circuit 18 receives true clock signal Clk_t / and complementary clock signal Clk_c and generates an internal clock signal CLK. Internal clock signal CLK is supplied to an internal clock generator, such as a delay locked loop (DLL) circuit 30. DLL circuit 30 generates a phase controlled internal clock signal LCLK based on the received internal clock signal CLK. Phase controlled internal clock signal LCLK is supplied to, for example, I / O interface 16 and used as a timing signal for determining the output timing of read data. In some embodiments, clock input circuit 18 can include circuitry that splits the clock signal into multiple (e.g., 4) phases. Clock input circuit 18 can also include phase detection circuitry to detect which phase receives the first pulse when the sets of pulses occur too frequently to enable clock input circuit 18 to reset between the sets of pulses.

[0020] Internal clock signal / phase CLK can also be provided to various other components within memory device 10 and can be used to generate various additional internal clock signals. For example, internal clock signal CLK can be provided to command decoder 32. Command decoder 32 can receive command signals from command bus 34 and can decode the command signals to provide various internal commands. For example, command decoder 32 can provide command signals to DLL circuit 30 over bus 36 to coordinate the generation of phase controlled internal clock signal LCLK. Phase controlled internal clock signal LCLK can be used, for example, to clock data through IO interface 16.

[0021] Furthermore, command decoder 32 can decode commands (e.g., read commands, write commands, mode register set commands, activate commands, etc.) and provide access to a particular bank 12 corresponding to the command via bus path 40. As will be appreciated, memory device 10 can include various other decoders (e.g., row decoders and column decoders) to facilitate access to banks 12. In one embodiment, each bank 12 includes a bank control block 22 that provides the necessary decoding (e.g., row decoders and column decoders), as well as other features (e.g., timing control and data control) to facilitate performing commands to and from bank 12.

[0022] Memory device 10 performs operations, such as read and write commands, based on command / address signals received from an external device, such as a processor. In one embodiment, the command / address bus can be a 14-bit bus that accommodates command / address signals (CA<13:0>). The command / address signals to command interface 14 are clocked using clock signals (Clk_t and Clk_c). The command interface can include a CAIC 20 configured to receive and transmit commands, such as through a command decoder 32, to provide access to memory banks 12. For example, CAIC 20 can include a number of command / address (CA) buffers 21 that are used to buffer CA bits received and / or transmitted using CAIC 20. In addition, command interface 14 can receive a chip select signal (CS_n). The CS_n signal enables memory device 10 to process commands on the incoming CA<13:0> bus. Access to a particular memory bank 12 within memory device 10 is encoded with the command on the CA<13:0> bus.

[0023] In addition, command interface 14 can be configured to receive a number of other command signals. For example, a die termination command / address (CA_ODT) signal can be provided to facilitate proper impedance matching within memory device 10. A reset command (RESET_n) can be used to reset command interface 14, status registers, state machines, and the like, such as during power-up. Command interface 14 can also receive a command / address inversion (CAI) signal, which can be provided to invert the state of command / address signals CA<13:0> on the command / address bus, for example, depending on the command / address routing used for a particular memory device 10. A mirror (MIR) signal can also be provided to facilitate mirror functionality. The MIR signals can be used to multiplex signals so that they can be swapped to enable a particular routing of signals to memory device 10 based on the configuration of a number of memory devices in a particular application. Various signals to facilitate testing of memory device 10, such as a test enable (TEN) signal, can also be provided. For example, the TEN signal can be used to place memory device 10 in a test mode for connectivity testing.

[0024] Command interface 14 can also be used to provide an alert signal (ALERT_n) to a system processor or controller for certain errors that can be detected. For example, if a cyclic redundancy check (CRC) error is detected, an alert signal (ALERT_n) can be transmitted from memory device 10. Other alert signals can also be generated. In addition, the bus and pin used to transmit the alert signal (ALERT_n) from memory device 10 can be used as an input pin during certain operations, such as a connectivity test mode performed using the TEN signal, as described above.

[0025] With the transmission and reception of data signals 44 over the IO interface 16, data can be sent to and from the memory device 10 using the command and timing signals discussed above. More specifically, data can be sent to or retrieved from the memory bank 12 over a data path 46, which includes a plurality of bidirectional data buses. Data IO signals, commonly referred to as DQ signals, are typically transmitted and received in one or more bidirectional data buses. For certain memory devices, such as DDR5 SDRAM memory devices, the IO signals can be divided into high and low bytes. For example, for an x16 memory device, the IO signals can be divided into high and low IO signals (e.g., DQ<15:8> and DQ<7:0>) corresponding to high and low bytes of data signals, for example.

[0026] To allow for higher data rates within the memory device 10, certain memory devices, such as DDR memory devices, can utilize a data strobe signal, commonly referred to as a DQS signal. The DQS signal is driven by an external processor or controller sending data (e.g., for a write command) or by the memory device 10 (e.g., for a read command). For read commands, the DQS signal is effectively an additional data output (DQ) signal with a predetermined pattern. For write commands, the DQS signal is used as a clock signal to capture corresponding input data. Like the clock signals (Clk_t and Clk_c), the DQS signal can be provided as a differential pair of data strobe signals (DQS_t and DQS_c) to provide differential pair signaling during reads and writes. For certain memory devices, such as DDR5 SDRAM memory devices, the differential pair of DQS signals can be divided into high and low data strobe signals (e.g., UDQS_t and UDQS_c; LDQS_t and LDQS_c) corresponding to high and low bytes of data sent to or from the memory device 10, for example.

[0027] Impedance (ZQ) calibration signals can also be provided to the memory device 10 over the IO interface 16. The ZQ calibration signals can be provided to a reference pin and can be used to tune the output drivers and ODT values by adjusting the pull-up and pull-down resistors of the memory device 10 across process, voltage, and temperature (PVT) values. As PVT characteristics can affect the ZQ resistor values, the ZQ calibration signals can be provided to the ZQ reference pin for adjusting the resistance to calibrate the input impedance to a known value. As will be appreciated, a precision resistor is typically coupled between the ZQ pin on the memory device 10 and GND / VSS external to the memory device 10. This resistor acts as a reference for adjusting the drive strength of the internal ODT and IO pins.

[0028] Additionally, a loopback data signal (LBDQ) and a loopback strobe signal (LBDQS) can be provided to memory device 10 via I / O interface 16. The loopback data signal and loopback strobe signal can be used during testing or debugging phases to configure memory device 10 in a mode where signals loop back through memory device 10 via the same pin. For example, the loopback signal can be used to configure memory device 10 to test the data output (DQ) of memory device 10. Loopback may include both LBDQ and LBDQS, or may only include the loopback data pin. This is typically intended for monitoring data captured by memory device 10 at I / O interface 16. LBDQ can indicate data operations of the target memory device (e.g., memory device 10) and can therefore be analyzed to monitor (e.g., debug and / or perform diagnostics on) the data operations of the target memory device. Similarly, LBDQS can indicate strobe operations (e.g., timing of data operations) of the target memory device (e.g., memory device 10) and can therefore be analyzed to monitor (e.g., debug and / or perform diagnostics on) the strobe operations of the target memory device.

[0029] As will be understood, various other components, such as power supply circuitry (for receiving external VDD and VSS signals), mode registers (for defining various modes of programmable operation and configuration), read / write amplifiers (for amplifying signals during read / write operations), and temperature sensors (for sensing the temperature of the memory device 10), may also be incorporated into the memory device 10. Therefore, it should be understood that... Figure 1 The block diagram is provided only to highlight certain functional features of the memory device 10 to aid in the subsequent detailed description. Furthermore, although the memory device 10 is discussed above as a DDR5 device, it can be any suitable device (e.g., a low-power double data rate (LPDDR) device, a double data rate type 4 DRAM (DDR4), a ferroelectric RAM device, or a combination of different types of memory devices). In fact, in some embodiments, the CA buffer 21 can be used in other semiconductor devices or even the memory device 10 to buffer any data value. In other words, the applicability of the CA buffer 21 to semiconductor devices extends beyond its use solely in the memory device 10 and / or solely as a buffer for CA bits.

[0030] Figure 2 It is possible Figure 1 A circuit diagram of an embodiment of CA buffer 50, one of the CA buffers 21. Although in Figure 2The illustrated embodiment of an example of CA buffer 50 is shown with particular circuitry, but CA buffer 21 can include additional circuitry, such as additional copies of the illustrated CA buffer 50 and / or additional stages in CA buffer 21. Moreover, the illustrated embodiment of CA buffer 50 can depict a current mode logic (CML) structure with fixed resistor loads via resistors 52 and 54, but can have any suitable physical structure. CA buffer 50 also includes a programmable tail current 56 that can be programmed using a programmable current generator 58. Programmable current generator 58 can use one or more programmable current sources 60 (individually referred to as current sources 60A, 60B, 60C, 60D, 60E, and 60F).

[0031] Programmable current generator 58 can be used to compensate for process variations and / or reference voltage (Vref) 62 changes. For example, programmable current generator 58 uses a process control signal 64 to vary tail current 56 to compensate for process variations for a chip implementing memory device 10. For example, process control signal 64 can turn more current sources 60 on for slow corners and fewer current sources 60 on for fast corners.

[0032] Programmable current generator 58 can also be used to compensate for variations in Vref 62 using a Vref control signal 66. When Vref 62 changes, tail current 56 can change due to insufficient saturation margin. The input pair of NMOS transistors 68 and 70 can exit saturation mode, which can result in a decrease in drive strength. NMOS transistor 68 has its gate terminal connected to Vref 62, and NMOS transistor 70 has a gate terminal connected to incoming data 72 (e.g., a CA bit). Changes in Vdg of NMOS transistors 68 and / or 70 can change positive output 74 and / or negative output 76. To compensate for these issues, programming of Vref control signal 66 can be used to vary tail current 56 as well as changes in Vref 62. For example, for each step value between a minimum value of Vref 62 and a maximum value of Vref 62 (e.g., 25 mV), a corresponding value of tail current 56 and / or Vref control signal 66 can be used. In other words, the amount of tail current 56 can be decreased as Vref 62 is increased to provide greater and / or consistent drive strength throughout the range of possible Vref 62 values. By decreasing tail current 56 as Vref 62 is increased, the output common mode of positive output 74 and negative output 76 is also adjusted higher. This increase in common mode causes the input pair of NMOS transistors 68 and 70 to remain saturated and have increased drive strength.

[0033] While increasing common mode can increase some aspects of operation of CA buffer 50, CA buffer 50 has no direct control over common mode, which can lead to common mode swing. Additionally, CA buffer 50 can have other drawbacks. Specifically, training and programming Vref control signal 66 and / or process control signal 64 of CA buffer 50 for process and Vref 62 variations in each chip can require a relatively large amount of test time. Furthermore, while CA buffer 50 can compensate for Vref 62 variations and process variations, CA buffer 50 does not compensate for temperature variations without adding additional local temperature sensor circuitry to monitor temperature. Additionally, the monitored temperature also needs to be compensated for in programming, which requires additional training time and semiconductor space to implement. Even without temperature monitoring capability, CA buffer 50 requires additional digital logic to program the current source based on Vref 62. Furthermore, routing digital signals between logic implementation and CA buffer 50 will consume many routing areas. To reduce some area issues, multiple CA buffers 50 can share the same code / implementation / programming. However, due to the lower flexibility in compensating for conditions of CA buffer 50 in different ways, any stress / thermal differences between CA buffers 50 in silicon will result in degraded performance.

[0034] To address some of these issues, an analog bias control embodiment of CA buffer 21 can be used. For example, Figure 3 is a circuit diagram of CA buffer 100 that can be used as at least one of Figure 1 CA buffer 21. While specific circuitry is shown in the illustrated embodiment of the example of CA buffer 100 in Figure 3 CA buffer 21 can include additional circuitry, such as additional copies of the illustrated CA buffer 100 and / or additional stages in CA buffer 21. A portion 101 of CA buffer 100 can be similar to CA buffer 50, with the only difference being that programmable current generator 58 is omitted, and instead common mode 102 can be sampled from between positive output 74 and negative output 76. In portion 103, common mode 102 is transmitted to the gate of NMOS transistor 104. NMOS transistor 104 is coupled to first leg 106 of current mirror 108, and between first leg 106 and ground. Second leg 110 is connected as feedback to current source 113 that sets tail current 56 via path 112. Thus, the amount of current in tail current 56 is based at least in part on the common mode voltage. The amount of charge on path 112 is affected by the amount of charge on paths 114 and 116 from second leg 110. In other words, the charge on second leg 110 can be at least partially dissipated to ground based on Vref 62 through path 114 and based on process and temperature through path 116 to compensate for this process, temperature, and Vref 62 variations.

[0035] NMOS transistor 118 is coupled to path 114 between second leg 110 and ground. A gate terminal of NMOS transistor 118 is coupled to Vref 62. As Vref 62 increases, more charge is dissipated to ground via NMOS transistor 118, thereby reducing tail current 56. Common mode 102 is then raised in a controlled manner that is based at least in part on the size / strength of NMOS transistor 118. In other words, CA buffer 100 performs Vref 62 compensation similar to CA buffer 50, but with some common mode 102 control.

[0036] NMOS transistor 120 is coupled to path 116 between second leg 110 and ground. A gate terminal of NMOS transistor 120 is coupled to a locally generated reference voltage (VR) 122 for controlling process and temperature effects. VR 122 compensates for process and temperature effects by controlling current such that common mode 102 remains consistent across different processes and temperatures by sourcing VR 122 between two resistors 124 and 126, and controlling NMOS transistor 120 with VR 122. Specifically, current through NMOS transistor 120 is dependent on process corner and temperature. Using this dependency, in fast corners, VR 122 and NMOS transistor 120 dissipate more charge, resulting in a decrease in tail current 56, while in slow corners, VR 122 and NMOS transistor 120 dissipate less charge to increase tail current 56 to control common mode 102 output.

[0037] An output voltage of common mode 102 can be equal to or based at least on a portion of VR 122 and Vref 62. The portion of Vref 62 is a percentage of Vref 62, where the percentage is based at least in part on a ratio between NMOS transistor 120 and NMOS transistor 118. In other words, a multiplication operation using the ratio multiplied by Vref 62 is used to weight Vref 62. Further, a relationship between currents on paths 112, 114, and 116 can be based at least in part on a relationship of resistances of resistors 128, 130, and / or 132.

[0038] Figure 4 is utilized Figure 3A flowchart of a process 200 of the CA buffer 100. The process 200 includes sampling a common mode 102 of an output of a data buffer (the CA buffer 100) of a semiconductor device (block 202). The output can include a differential signal to represent data (e.g., CA bits). The CA buffer 100 also transmits the sampled common mode to a gate of a first transistor (NMOS transistor 104) of a first leg 106 coupled to the current mirror 108 (block 204). The CA buffer 100 uses the current mirror 108 to provide a certain amount of charge to a second leg 110 of the current mirror 108 based at least in part on the sampled common mode 102 (block 206). Further, the CA buffer 100 dissipates a first portion of the charge through a second transistor (NMOS transistor 118) via a first path (path 114) from the second leg 110 by using a reference voltage (Vref 62) of the data buffer coupled to a gate terminal of the second transistor to control the second transistor (block 208). Thus, the first portion can change as Vref 62 changes. In addition, the CA buffer 100 dissipates a second portion of the charge through a third transistor (NMOS transistor 120) via a second path (path 116) from the second leg 110 by using a locally generated reference voltage (VR 122) coupled to a gate terminal of the third transistor to control the third transistor (block 210). As previously described, the VR 122 can be generated between resistors 124 and 126 coupled in series between a voltage supply (VDD) and ground. In addition, since the VR 122 varies with temperature and process corners of a chip of the semiconductor device, the second portion varies with temperature and process corner variations. Further, the CA buffer 100 uses a third portion of the charge to control a tail current 56 of the data buffer (the CA buffer 100) (block 212). For example, the control of the tail current 56 can be performed via a third path (e.g., path 112) from the second leg 110 of the current mirror 108. Since the amount of charge dissipated from the second leg varies with Vref 62 changes, temperature changes, and process corner changes, the third portion (and the tail current 56) varies with Vref 62 changes, temperature changes, and process corner changes.

[0039] As previously described, using the analog bias-based current-controlled CA buffer 100 can provide tangible benefits over the CA buffer 50. For example, the CA buffer 100 can be implemented without lengthy silicon testing and programming timing, making semiconductor products using the CA buffer 100 delivered faster than semiconductor products using the CA buffer 50. Further, because the current control of the CA buffer 100 does not rely on digital control, the CA buffer 100 can require less silicon area due to the absence of digital logic implementation or signal tracking between the digital logic implementation and the CA buffer 100. Further, the CA buffer 100 provides control over the common mode 102 across process, temperature, and Vref 62 variations. Further, because each CA buffer 100 can be controlled locally with relatively little area consumed, each CA buffer 100 can be independently driven to compensate for different conditions (e.g., temperature) between different CA buffers 100 in a single device. The CA buffer 100 can also have enhanced high frequency response because common mode noise is attenuated by the analog loop control. Additionally, the CA buffer 100 can also provide enhanced eye opening in the data eye of the buffered data when compared to the CA buffer 50.

[0040] While the disclosure can be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the disclosure as defined by the following appended claims.

[0041] The technology presented and claimed herein is to be understood as to encompass all forms of the technology that fall within the scope of the claims. Numerous specific details are set forth herein to provide a thorough understanding of the technology. However, those of ordinary skill in the art will understand that the technology can be practiced without resorting to the details that are presented. In some instances, well-known structures and components are shown in block diagram form, rather than in detail, in order to avoid obscuring the technology. Where certain details are presented with respect to the technology, it is to be understood that the disclosure is to be understood to be limited to the certain presentation of details solely for purposes of providing a state-of-the-art disclosure. In this regard, details presented in the course of description of the technology should not be interpreted to imply that they are required elements or limitations of the technology. In this regard, the technology recited herein is intended to be as broad and general as the claims themselves. In some instances, well-known structures and components are shown in block diagram form, rather than in detail, in order to avoid obscuring the technology. Where certain details are presented with respect to the technology, it is to be understood that the disclosure is to be understood to be limited to the certain presentation of details solely for purposes of providing a state-of-the-art disclosure. In this regard, details presented in the course of description of the technology should not be interpreted to imply that they are required elements or limitations of the technology. In this regard, the technology recited herein is intended to be as broad and general as the claims themselves.

Claims

1. A semiconductor device comprising: a pair of transistors configured to implement a buffer of input data to an output; a first transistor configured to receive a common mode of the output at a gate terminal of the first transistor; a current source configured to control a tail current from the pair of transistors; a second transistor configured to adjust the tail current based at least in part on a change in a reference voltage used by the pair of transistors to buffer the input data; and a third transistor configured to adjust the tail current based at least in part on a change in a locally generated reference voltage, the change based at least in part on process and temperature variations.

2. The semiconductor device of claim 1, wherein one of the pair of transistors is configured to receive the reference voltage at its respective gate terminal.

3. The semiconductor device of claim 1, comprising a pair of series connected resistors between a power supply and ground, wherein the locally generated reference voltage is configured to be generated between the pair of series connected resistors.

4. The semiconductor device of claim 1, wherein a gate terminal of the third transistor is configured to be coupled to the locally generated reference voltage.

5. The semiconductor device of claim 1, wherein a voltage of the common mode is equal to the locally generated reference voltage plus a reference voltage after weighting, wherein the weighting is a ratio of sizes between the third transistor and the second transistor multiplied by the reference voltage.

6. The semiconductor device of claim 1, wherein a current through the second and third transistors is based at least in part on a current through the first transistor due to the common mode.

7. The semiconductor device of claim 6, wherein the first transistor is coupled to a first leg of a current mirror and the second and third transistors are coupled to a second leg of the current mirror.

8. The semiconductor device of claim 7, comprising a control path from the second leg of the current mirror to the current source, the control path configured to adjust the tail current based at least in part on the common mode, the reference voltage, and the locally generated reference voltage.

9. The semiconductor device of claim 8, wherein an amount of charge through the control path is based at least in part on dissipation of charge on the second leg of the current mirror through the second and third transistors.

10. A method of operating a semiconductor device comprising: sampling a common mode of an output of a data buffer of the semiconductor device as a sampled common mode; transmitting the sampled common mode to a gate of a first transistor coupled to a first leg of a current mirror; providing charge to a second leg of the current mirror based at least in part on the sampled common mode; dissipating a first portion of the charge through a second transistor via a first path from the second leg by controlling the second transistor using a reference voltage of the data buffer coupled to a gate terminal of the second transistor; a second portion of the charge is dissipated through a third transistor via a second path from the second leg by controlling the third transistor using a locally generated reference voltage coupled to a gate terminal of the third transistor; and a third portion of the charge is used to control a tail current of the data buffer.

11. The method of claim 10, wherein output data from the output of the data buffer comprises command / address bits.

12. The method of claim 10, wherein the first portion varies with changes in the reference voltage of the semiconductor device.

13. The method of claim 10, wherein the second portion varies with temperature and process corners of the semiconductor device.

14. The method of claim 10, wherein the third portion varies with changes in the reference voltage, changes in temperature, and for different process corners of the semiconductor device.

15. The method of claim 10, comprising generating the locally generated reference voltage between two resistors coupled in series between a supply voltage and ground.

16. The method of claim 10, wherein using the third portion of the charge to control the tail current of the data buffer comprises using a third path from the second leg of the current mirror.

17. A data buffer, comprising: a first input transistor configured to receive input data at a gate terminal of the first input transistor; a second input transistor configured to receive a reference voltage at a gate terminal of the second input transistor; a common mode transistor configured to receive a common mode between first terminals of the first and second input transistors, wherein the common mode transistor is configured to receive the common mode at a gate terminal of the common mode transistor; a current source configured to control a tail current from second terminals of the first and second input transistors; a first control transistor configured to receive the reference voltage at a gate terminal of the first control transistor; a second control transistor configured to receive a locally generated reference voltage at a gate terminal of the second control transistor; and a current mirror, comprising: a first leg coupled to the common mode transistor; and a second leg coupled to the first control transistor, the second control transistor, and the current source.

18. The data buffer of claim 17, wherein the first control transistor is configured to adjust the tail current based at least in part on changes in the reference voltage.

19. The data buffer of claim 17, wherein the second control transistor is configured to adjust the tail current based at least in part on changes in the locally generated reference voltage.

20. The data buffer of claim 19, wherein the changes in the locally generated reference voltage are based at least in part on process and temperature variations. ​ ​

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