Power semiconductor device and method of manufacturing the same

Abstract

In at least one embodiment, a power semiconductor device (1) comprises a semiconductor body (2), a gate electrode (31), and an extraction electrode (34), wherein the semiconductor body (2) comprises a source region (21) having a first conductivity type, a well region (22) having a second conductivity type different from the first conductivity type at the gate electrode (31), a drift region (23) having the first conductivity type, and a barrier region (28) having the first conductivity type, the barrier region (28) being located between the drift region (23) and the extraction electrode (34).

Description

Technical Field

[0001] A power semiconductor device is provided. A method for manufacturing this power semiconductor device is also provided. Background Technology

[0002] Document US 9 825 158 B2 discloses an insulated gate bipolar transistor.

[0003] Document US 8 210 098 B2 relates to a trench insulated gate bipolar transistor.

[0004] Documents EP 2 953 166 A1, US 2017 / 033206 A1, US 2019 / 019861 A1, US 2016 / 359026 A1 and US 2016 / 247910 A1 relate to semiconductor devices.

[0005] The problem to be solved is to provide a power semiconductor device with improved electrical behavior. Summary of the Invention

[0006] The embodiments disclosed herein relate to power semiconductor devices and methods as defined in the independent patent claims. Further exemplary developments constitute the subject matter of the dependent claims.

[0007] For example, power semiconductor devices include lead-out electrodes that are separated from the drift region by a barrier region. The barrier region allows for a trade-off between improved long-term stability (particularly in terms of robustness to gate insulator degradation) and improved static losses.

[0008] In at least one embodiment, the power semiconductor device includes a semiconductor body, a gate electrode, and a lead-out electrode, wherein the semiconductor body includes:

[0009] - A source region having a first conductivity type, with the source electrode located at the source region.

[0010] - A well region having a second conductivity type different from the first conductivity type, the well region being located at the gate electrode.

[0011] - Drift region, said drift region having a first conductivity type, and

[0012] - A barrier region having the first conductivity type, the barrier region being located between the drift region and the lead-out electrode, and the lead-out electrode being assigned to the barrier region.

[0013] For example, assigning a lead electrode to the barrier region can mean that, in a top view of the top side of the semiconductor body, the corresponding lead electrode is located within a closed loop formed by the assigned barrier region. Alternatively or additionally, the corresponding lead electrode is the electrode that is in direct electrical contact with the semiconductor body and is closest to the barrier region.

[0014] The gate electrode is insulated from the semiconductor body by a gate insulator. The gate insulator is made of any electrically insulating material, which can be an oxide. For example, the gate insulator can be at least one of the following materials: SiO2, Si3N4, Al2O3, Y2O3, ZrO2, HfO2, La2O3, Ta2O5, TiO2. Therefore, the gate insulator can also be referred to as a gate oxide. For example, the thickness of the gate insulator is at least 50 nm and / or at most 0.5 μm.

[0015] For example, the semiconductor body is made of silicon (Si). However, the semiconductor body can also be made of wide-bandgap semiconductor materials such as SiC, Ga2O3, or GaN.

[0016] The first conductivity type is, for example, n-conductive, and therefore the source region, drift region, and barrier region are n-doped. In this case, the second conductivity type is p-conductive, and therefore the well region is p-doped. Otherwise, the first conductivity type is p-conductive, and the second conductivity type is n-conductive. In the following text, the focus is on the first case, i.e., the first conductivity type is n-conductive, and the second conductivity type is p-conductive; however, all the following statements similarly apply to the case where the first conductivity type is p-conductive and the second conductivity type is n-conductive. It is possible for the maximum doping concentration of the well region to be less than the maximum doping concentration of the source region and / or for the maximum doping concentration of the well region to be greater than the maximum doping concentration of the drift region.

[0017] When the power semiconductor device is in the ON state, the well region is configured to cooperate with the gate insulator and gate electrode to provide the channel region. For example, the well region is in direct contact with the gate insulator. Therefore, the channel region is part of the well region and can have the same doping concentration. During operation, and in the case where the second conductivity type is p-conductivity, electrons flow from the source region to the drift region along the gate insulator in the channel region. The channel region has a thickness, for example, in the nanometer range, such as 1 nm to 50 nm, in a direction perpendicular to the interface between the gate insulator and the well region.

[0018] According to at least one embodiment, the power semiconductor device is configured with a maximum voltage of at least 0.6 kV, at least 1.2 kV, or at least 3 kV. This voltage is applied, for example, between the drain electrode and the emitter electrode, or between the source electrode and the drain electrode, during normal use of the device. That is, by having corresponding voltages at the gate electrode and between the source / emitter electrode and the drain / collector electrode, the current through the power semiconductor device can be controlled, particularly the current can be turned on and off.

[0019] Power semiconductor devices are used, for example, in power modules in vehicles to convert direct current from batteries or fuel cells into alternating current for electric motors, such as in hybrid or plug-in electric vehicles, or in railways, such as commuter trains.

[0020] According to at least one embodiment, the power semiconductor device is a metal-insulator-semiconductor field-effect transistor (MISFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), or a reverse-biased insulated-gate bipolar transistor (RC-IGBT).

[0021] According to at least one embodiment, the semiconductor body further includes a lead-out region. For example, the lead-out region is located at a lead-out electrode. It is possible that the lead-out electrode contacts the semiconductor body only through the lead-out region. Therefore, the lead-out region can be located between the barrier region and the lead-out electrode, and can be in direct contact with both the barrier region and the lead-out electrode. The lead-out region has a second conductivity type.

[0022] According to at least one embodiment, the semiconductor body further includes a deeply doped region having a second conductivity type. For example, the deeply doped region is located between at least a portion of the barrier region and the drift region. It is possible that the deeply doped region is located directly at the barrier region, and the barrier region separates the deeply doped region from the lead-out region and the lead-out electrode. Furthermore, it is possible that a portion of the drift region is located between the barrier region and the deeply doped region, such that the deeply doped region can be sandwiched between different portions of the drift region.

[0023] According to at least one embodiment, the depth of the deep-doped region into the semiconductor body is equal to or greater than the depth of the well region. For example, the depth of the deep-doped region exceeds the depth of the well region by at least 1.5 times or at least 2 times and / or at most 20 times or at most 10 times.

[0024] The term "depth" can refer to the extent of the corresponding portion in a direction perpendicular to the top side of the semiconductor body. For example, the top side is opposite to the collector or drain electrode of a power semiconductor device.

[0025] According to at least one embodiment, the bottom side of the barrier region may be completely or entirely free of deeply doped regions. The bottom side is the side of the barrier region that faces away from the top side. In other words, the region below the barrier region may be completely or partially free of deeply doped regions.

[0026] According to at least one embodiment, the semiconductor body further includes a reinforcement region having a first conductivity type. For example, the reinforcement region is located directly on the bottom side of the well region, such that the reinforcement region is located between the drift region and the well region. That is, the reinforcement region can be assigned to the well region. If no reinforcement region is present, the well region can be in direct contact with the drift region, for example, on the bottom side of the well region.

[0027] According to at least one embodiment, the gate electrode is partially or completely housed in a trench. For example, the trench is completely filled by the gate electrode and a gate insulator located between the gate electrode and the semiconductor body.

[0028] According to at least one embodiment, the gate electrode and the trench extend deeper into the semiconductor body than the well region. For example, the depth to the gate electrode exceeds the depth of the well region by at least 1.5 times or at least 2 times and / or up to 10 times or up to 5 times.

[0029] According to at least one embodiment, the depth of the deep doped region is equal to or greater than the depth of the gate electrode.

[0030] According to at least one embodiment, as seen in a top view of the semiconductor body, the gate electrode comprises 2N stripes or 2N+1 stripes, where N is a natural number greater than or equal to 1. For example, 2 ≤ N ≤ 200 or 5 ≤ N ≤ 50 applies. These stripes define N active cells of the power semiconductor device. In other words, each of the active cells comprises two stripes and an associated source region and a well region.

[0031] According to at least one embodiment, the lead electrode includes a plurality of contact points. For example, as can be seen in a top view of the semiconductor body, in each case the contact points are arranged between two adjacent active cells. It is possible that the contact points between the respective two active cells are arranged along an arrangement line, which may be a straight line. For example, in the top view, the arrangement line is a mirror-symmetric line between two designated active cells.

[0032] According to at least one embodiment, the contact points fill at most 10% or at most 5% of the length of the arrangement line. Therefore, the contact points constitute only a small portion of the arrangement line.

[0033] According to at least one embodiment, the length of each contact point along the arrangement line is at most 70%, at most 50%, or at most 30% of the distance between adjacent active units. This may alternatively or additionally apply to the width of the contact points perpendicular to the arrangement line.

[0034] According to at least one embodiment, the source region and the lead-out electrode are configured to be at the same potential. For example, the source region is in ohmic contact with the lead-out electrode. Therefore, the lead-out electrode and the source electrode may be electrically short-circuited.

[0035] Another method for manufacturing a power semiconductor device is provided. For example, this method produces a power semiconductor device as shown in at least one of the embodiments described above. Therefore, the characteristics of the power semiconductor device are also disclosed in this method, and vice versa.

[0036] In at least one embodiment, the method includes the following steps, for example, in the following order:

[0037] Provides a semiconductor body having a drift region of a first conductivity type.

[0038] Create enhancement regions and / or barrier regions with the first conductivity type.

[0039] Create a well region and / or an exit region with a second conductivity type different from the first conductivity type.

[0040] Create a source region with a first conductivity type, and

[0041] A gate electrode is applied at the well region and the lead-out electrode, and the barrier region is located between the drift region and the lead-out electrode.

[0042] According to at least one embodiment, enhancement regions and barrier regions are created simultaneously. That is, enhancement regions and barrier regions can be produced using the same doping step, such as ion implantation to introduce doping.

[0043] According to at least one embodiment, a well region and an extraction region are created simultaneously. That is, the well region and the extraction region can be produced using the same doping steps, for example, by implanting ions to introduce doping.

[0044] For example, the enhancement region and barrier region on one side and the well region and extraction region on the other side respectively have the same dopant and / or the same maximum doping concentration and / or the same doping depth distribution.

[0045] The power semiconductor devices and methods described herein will now be explained in more detail with reference to the accompanying drawings and exemplary embodiments. Identical parts are indicated by the same reference numerals in the various figures. However, the relationships between parts are not shown to scale, and some elements may be exaggerated to aid understanding. Attached Figure Description

[0046] In the attached diagram:

[0047] Figure 1 This is a schematic perspective view of an exemplary embodiment of the power semiconductor device described herein.

[0048] Figure 2 and Figure 3 yes Figure 1 A schematic cross-sectional view of a power semiconductor device.

[0049] Figure 4 and Figure 5 This is a schematic cross-sectional view of a modified power semiconductor device.

[0050] Figure 6 and Figure 7 yes Figure 4 and Figure 5 A schematic diagram illustrating the switching process of a variant of a power semiconductor device.

[0051] Figure 8 and Figure 9 This is a diagram illustrating comparative data on the long-term switching stability of exemplary and variant power semiconductor devices described herein.

[0052] Figure 10 and Figure 11 This is an illustration of comparative data for exemplary and variant power semiconductor devices described herein.

[0053] Figure 12 This is a schematic perspective view of a modified power semiconductor device.

[0054] Figures 13 to 15 This is a schematic cross-sectional view of an exemplary embodiment of the power semiconductor device described herein.

[0055] Figure 16 This is a schematic top view of an exemplary embodiment of the power semiconductor device described herein, and

[0056] Figure 17 This is a block diagram of an exemplary embodiment of the method for manufacturing the power semiconductor device described herein. Detailed Implementation

[0057] Figures 1 to 3 An exemplary embodiment of a power semiconductor device 1 is shown. The power semiconductor device 1 includes a semiconductor body 2, which is made of, for example, Si or SiC. Within the semiconductor body 2, a drift region 23 is present, which can extend laterally across the entire semiconductor body 2, i.e., extending in a direction parallel to the top side 20 of the semiconductor body 2, for example. The drift region 23 is of a first conductivity type, for example, the drift region is n-doped.

[0058] Furthermore, at the top side 20, the semiconductor body 2 includes a source region 21, which is also of the first conductivity type but has a higher maximum doping concentration than the drift region 23. The source region 21 is electrically contacted via a source electrode 32. The source electrode 32 can be applied to the top side 20 of the semiconductor body 2, or it can be partially or completely located in a recess formed in the semiconductor body 2 on the top side 20.

[0059] The source region 21 can be divided into multiple sub-regions. However, since all sub-regions operate in the same way and may be at the same potential, for simplicity, only one source region 21 will be explicitly mentioned below, although independent sub-regions or even electrically independent source regions (not shown) may exist. The same applies to all other regions of the semiconductor body 2.

[0060] Furthermore, the semiconductor body 2 includes a well region 22, for example, below the source region 21. The well region 22 is of a second conductivity type; for example, the well region 22 is p-doped. The well region 22 is located at the gate electrode 31 housed in a trench. The gate electrode 34 is electrically isolated from the semiconductor body 2 by a gate insulator 4; for simplicity, the gate insulator 4 is only partially present in the trench. Figure 1 As shown in the diagram. Alternatively, the trenches can extend parallel to each other.

[0061] Along the gate electrode 34, a channel region 220 is formed during the operation of the power semiconductor device 1, in which charge carrier conduction occurs. The gate electrode 34 extends deeper into the semiconductor body 2 than the well region 22. Active cells 5 are formed through two trenches and a source region 21 having, for example, two sub-regions, and through the well region 22 located between the two trenches. Multiple active cells 5 may exist, such as... Figure 1 As shown, there may be only one active unit 5.

[0062] Alternatively, a plug 24 is provided for electrical contact with the trap region 22. The plug 24 may be located below the source electrode 32 and may be electrically contacted by the source electrode 32 such that the source region 21 and the plug 24 are at the same potential. Such a plug 24 may also be present in all other exemplary embodiments.

[0063] As a further option, the semiconductor body 2 includes an enhancement region 26 having a first conductivity type. The enhancement region 26 is located on the side of the well region 22 away from the top side 20. For example, the enhancement region 26 extends entirely between the two designated trenches, as shown in section AA′, see... Figure 2 The gate electrode 31 may extend deeper into the semiconductor body 2 than the enhancement region 26. The maximum doping concentration of the enhancement region 26 may exceed the maximum doping concentration of the drift region 23.

[0064] For example, the power semiconductor device 1 is an insulated gate bipolar transistor, or IGBT for short. Therefore, on the side of the drift region 23 away from the well region 22, there exists a collector region 25, which is also of the second conductivity type. At the collector region 25, there is a collector electrode 33. Furthermore, as an alternative, a buffer zone (not shown) of the first conductivity type can exist between the drift region 23 and the collector region 25. The doping concentration of this buffer zone can be higher than the doping concentration of the drift region 23.

[0065] Otherwise, if the power semiconductor device 1 is a field-effect transistor, then there is a drain region 251 instead of a collector region 25, and the collector electrode 33 is replaced by the drain electrode 331. This is in Figure 1 This is illustrated by parentheses around reference numerals 251 and 331 in the accompanying drawings. In contrast to the collector region 25, the drain region 251 has a first conductivity type.

[0066] In other figures, collector region 25 and collector electrode 33 or drain region 251 and drain electrode 331 are not shown, and the corresponding devices may be IGBTs or field-effect transistors.

[0067] In a top view of the top side 20, the gate electrode 31 may include multiple strips 51, with two strips 51 defining one of the active units 5. Between the two strips 51 of the respective active unit 5, there is a line strip 53 of the source electrode 32. Optionally, the line strip 53 and the plug 24 may be aligned.

[0068] exist Figures 1 to 3 In one embodiment, the plurality of active elements 5 are arranged in a strip array; in other words, the active elements 5 have a main extending direction parallel to the top surface 20 and / or parallel to each other. In another exemplary embodiment not shown in the figures, the plurality of active elements 5 may also be arranged in a cell array. That is, the active elements 5 may be arranged in a two-dimensional grid, as seen in the top view of the top side 20, for example, in a rectangular or hexagonal grid.

[0069] Furthermore, the power semiconductor device 1 includes a lead-out electrode 34. The lead-out electrode 34 may include a plurality of contact points 52 located between adjacent active cells 5, or the lead-out electrode 34 may be composed of these contact points 52. Alternatively, if there is only one active cell 5, the lead-out electrode 34 may be located on the side of the trench away from the source electrode 32. Furthermore, near the lead-out electrode 34, the semiconductor body 2 includes a barrier region 28 having a first conductivity type. The barrier region 28 may form a well, and the lead-out electrode 34 is located within the well. Therefore, in the intended use of the power semiconductor device 1, all current arriving at and / or originating from the lead-out electrode 34 must pass through the barrier region 28.

[0070] Alternatively, if there are multiple lead-out electrodes 34 and / or multiple corresponding contact points 52, then only one or some of the lead-out electrodes 34 and / or contact points 52 need to be provided with a barrier region 28. In other words, there can be a mixture of lead-out electrodes 34 and / or corresponding contact points 52 provided with a barrier region 28 and lead-out electrodes 34 and / or contact points 52 without a barrier region. However, preferably, all lead-out electrodes 34 and / or corresponding contact points 52 are provided with at least one barrier region 28.

[0071] Alternatively, the semiconductor body 2 may include a lead-out region 27 having a second conductivity type directly at the lead-out electrode 34. The lead-out electrode 34 may be in direct contact only with the lead-out region 27. On the side of the lead-out region 27 facing away from the lead-out electrode 34, the lead-out region 27 may be entirely surrounded by a barrier region 28, as detailed in [see details]. Figure 2 and Figure 3 The cross sections AA′ and BB′ are shown. Therefore, the barrier region 28 can form a well, and the extraction region 27 is located in the well.

[0072] As a further option, the semiconductor body 2 includes a deeply doped region 29 having a second conductivity type. For example, the deeply doped region 29 is positioned along the arrangement line of the contact point 52. Therefore, the side of the barrier region 28 facing the trench with the gate electrode 31 may not have the deeply doped region 29. Furthermore, as... Figure 3 As shown, the bottom side of the barrier region 28, away from the top side 20, can also be free of deeply doped regions 29. In the direction parallel to the trench, see... Figure 3 In the cross section BB′, the deeply doped region 29 can be directly adjacent to the barrier region 28.

[0073] For example, for the maximum doping concentration in different regions of semiconductor body 2, the following apply individually or in any combination:

[0074] -Source region 21, plug 24, deeply doped region 29, collector region 25 and / or drain region 251: at least 1x10 18 cm -3 Or at least 5x10 18 cm -3 Or at least 1x10 19 cm -3 And / or up to 5x10 20 cm -3 Or at most 2x10 20 cm -3 Or at most 1x10 20 cm -3 ;

[0075] - Trap region 22, enhancement region 26, lead-out region 27 and / or barrier region 28, at least 5x10 16 cm-3 Or at least 1x10 17 cm -3 And / or up to 5x10 19 cm -3 Or at most 5×10 18 cm -3 ;

[0076] - Drift region 23, depending on the voltage level of power semiconductor device 1, is at least 1x10 11 cm -3 Or at least 1x10 12 cm -3 or at least 1×10 13 cm -3 and / or up to 1×10 17 cm -3 Or at most 5×10 16 cm -3 Or at most 1×10 16 cm -3 .

[0077] For example, the maximum doping concentration of the deep doped region 29 exceeds the maximum doping density of the well region 22 by at least twice. Alternatively or additionally, the maximum doping concentration of the enhancement region 26 exceeds the maximum doping density of the drift region 23 by at least 10 times or at least 100 times.

[0078] refer to Figure 2 The diagram illustrates multiple active cells 5. In an alternative view, a unit cell 6 may be defined, comprising half of each of two adjacent active cells 5 and a structure including regions 27, 28, 29 and lead-out electrodes 34. The power semiconductor device 1 may include multiple units 6 arranged in an array of stripes as described above for the active cells 5.

[0079] The barrier region 28 allows for a trade-off between improved long-term stability (particularly in terms of robustness to gate insulator degradation) and improved static losses. The barrier region can therefore work in conjunction with the lead-out region 27 and the deeply doped region 29. The function of the barrier region 28 is explained in more detail below with respect to variations 10 and 11 of the semiconductor device.

[0080] exist Figure 4 In, it is shown Figures 1 to 3 A first variant 10 of the power semiconductor device 1. The main difference between devices 1 and 10 is that variant 10 has no barrier region. Furthermore, the first variant device 10 does not include a lead-out region and does not include separate contact points for lead-out electrodes. Figure 5 The diagram shows... Figure 4 The collision ionization during the shutdown of variant 10.

[0081] Alternatively, the enhancement region 26 and the well region 22 can be on opposite sides of the trench. In other words, the trench, and therefore the gate electrode 31, can extend from the top side 20 through the enhancement region 26 and the well region 22. The field oxide 42 separates the source electrode 32 from the semiconductor body, and the source electrode 32 extends on the top side 20. These features can also be implemented individually or collectively in the power semiconductor device 1 described herein. In addition, with Figures 1 to 3 The same content can also be applied to Figure 4 ,vice versa.

[0082] For example, the long-term performance stability of IGBTs requires robustness against gate insulator degradation. Dynamic avalanche during high-current turn-off events can lead to gate insulator degradation: the charge carriers generated by dynamic avalanche may have sufficient energy to be injected into the gate insulator, thereby changing the gate capacitance and consequently altering the device's switching characteristics (such as switching speed), potentially causing threshold voltage instability. See also the peak P generated by avalanche near the gate insulator at the bottom of the trench. Figure 5 Degradation is a design challenge for trench IGBTs.

[0083] exist Figure 6 In, it is shown Figure 4 The current-voltage curves during the turn-off period of the IGBT configured with a voltage of 3.3kV are shown, and Figure 7 The integrated avalanche generation Aint and maximum avalanche generation Amax during the shutdown period are shown. Therefore, it can be seen that significant avalanche generation occurred during the shutdown period.

[0084] One way to improve robustness to gate oxide degradation in IGBTs is to reduce the anode dose. However, reducing the anode dose can also negatively impact static losses and short-circuit safe operating area (SOA) capability. Another solution is to implement protective structures, such as deeply doped regions like deep p-wells (e.g., deep p-wells). Figure 4 (as shown), and / or form pseudo-trenches. In this way, dynamic avalanche generation near the active trench can be reduced, but this method is insufficient to ensure long-term stability for demanding applications with high-frequency and harsh switching conditions.

[0085] A more effective way to reduce degradation would be to include additional electrical contacts, such as lead-out electrodes 34, at a distance from the active cell 5. These additional contacts are biased in a manner that allows a portion of the plasma to be drawn out during turn-off, effectively diverting carriers away from the active trench and thus reducing avalanche generation near the gate oxide. For example, an emitter-biased contact directly connected to the p-well would deflect a considerable current from the back side while significantly reducing plasma during turn-off.

[0086] However, directly connecting the deeply doped region 29 to the emitter contact 34 may be an impractical solution, as this would significantly increase static losses. This undesirable effect is due to the additional contact providing extra outlets for charge carriers, thereby reducing plasma density and consequently decreasing conductivity when the same collector-emitter voltage is applied.

[0087] Using the power semiconductor device 1 described herein, a trade-off between improved long-term performance stability (i.e., robustness to gate insulator degradation) and improved static losses can be achieved. Unlike other solutions, the additional lead-out contact 34 is effectively shielded by the barrier region 28, which reduces the adverse effects of the contact 34 on the on-state while maintaining the benefits of reduced turn-off losses and improved robustness to gate oxide degradation.

[0088] Using the power semiconductor device 1 described herein, such as a 3.3kV trench IGBT, improved robustness to degradation can be achieved compared to alternative solutions, with only a limited increase in static losses. The power semiconductor device 1 can be manufactured without requiring highly advanced technology development, as the only necessary change is, for example, a change in the mask layout for the photolithography step performed to form contact points to the top surface.

[0089] Figure 8 and Figure 9 The results of repeated reverse bias safe working area (RBSOA) tests are shown to support the findings of this paper. Figure 1 The described power semiconductor device 1 (refer to) Figure 8 ) and similar Figure 4 The variant design without a barrier region described in the text 10 (see reference) Figure 9 Compare the robustness of both to degradation.

[0090] exist Figure 8 and Figure 9 In this study, the increase in maximum current overshoot during the turn-on period is measured every 1000 turn-off pulses i (up to a maximum of 100k pulses). Figure 8 and Figure 9 In the experiment, the results were repeated under increasingly stringent shutdown conditions, reaching a maximum of 1.39 times the nominal voltage U (2.5kV) and 2.25 times the nominal current C (337.5A). The upper and lower limits of the C-axis were located at + / -10% offset from the initial maximum current overshoot.

[0091] The power semiconductor device 1 described herein showed no signs of degradation even under the most demanding test conditions, while device 10 showed an increasing degradation effect with increasing turn-off voltage. Figure 8 and Figure 9The results demonstrate that the barrier region 28 does not limit the effectiveness of the lead electrode 34 in terms of robustness to degradation.

[0092] Figure 10 The probability plots of the turn-on voltage VCEsat at room temperature are shown for three device splits processed in parallel within the same batch. The power semiconductor device 1 described herein provides an improvement of approximately 200 mV in VCEsat compared to a second variant device 11 where the lead-out contacts are not fully surrounded by the barrier region. For reference, a first variant device 10, which lacks lead-out contacts due to degradation, is also included in the analysis.

[0093] Therefore, the presence of a barrier region 28 completely surrounding the lead-out electrode 34 allows for a significant reduction in VCEsat, compared to device 11 where the lead-out layer is directly connected to the deep p-well. The power semiconductor device 1 described herein does indeed still have higher static losses than device 10 without additional lead-out contacts, but to a lesser extent.

[0094] exist Figure 11 In the middle, it will be similar to Figure 4 The device 10 without lead-out contacts is compared to the device 11 where the lead-out contacts are not completely surrounded by the barrier region; both devices 10 and 11 are configured as 6.5 kV trench IGBTs. With the additional lead-out electrode 34 present, a higher voltage VCEsat is required to achieve the plasma density needed to reach the nominal turn-on current. On the other hand, the turn-off loss Eoff is reduced.

[0095] The power semiconductor device 1 described herein has lower switching losses than the device 10 without lead-out contacts, but slightly higher switching losses than the device 11. Therefore, the power semiconductor device 1 described herein effectively advances the technology curve in the region optimized for high-frequency applications without reducing anode injection efficiency and potentially reducing short-circuit capability.

[0096] For comparison, in Figure 12 The image shows the emitter side of variant 11 of the trench IGBT referenced above. The emitter bias contact 34 is directly connected to the deeply doped region 29 between the active cells 5. This additional contact 34 can be considered a hole extraction contact. It helps improve robustness to degradation but has a significant adverse effect on static losses.

[0097] exist Figure 13 Another example of the power semiconductor device 1 is shown, in which there is no trench gate electrode, but a gate electrode 31 is applied on the top side 20. Therefore, Figure 13 The power semiconductor device 1 has a planar design.

[0098] exist Figure 13 As can be seen, the optional enhancement region 26 and barrier region 28 can have the same doping distribution. This can be achieved by producing enhancement region 26 and barrier region 28 in the same process steps. The same applies to well region 22 and optional extraction region 27. Furthermore, as an option, the presence of deeply doped regions is not required.

[0099] In addition to this, with Figures 1 to 12 The same content can also be applied to Figure 13 ,vice versa.

[0100] Figure 14 and Figure 15 The cross section corresponds to Figure 3 The expression. In Figure 14 The diagram shows that drift region 23 can extend between deeply doped region 29 and barrier region 28. According to... Figure 15 There is no lead-out region, but the barrier region 28 is in direct contact with the lead-out electrode 34.

[0101] In addition to this, with Figures 1 to 13 The same content can also be applied to Figure 14 and Figure 15 ,vice versa.

[0102] exist Figure 16 The diagram shows a top view of an exemplary embodiment of the power semiconductor device 1. It can be seen that the lead-out electrode 34 is formed by a plurality of contact points 52. The contact points 52 can be relatively small, for example, having a size of at most 4 μm x 4 μm or at most 2 μm x 2 μm. In the top view of the top side 20, the contact points 52 are arranged along a straight line that is a mirror axis of symmetry with respect to the adjacent active cell 5. For example, the contact points 52 occupy at most 5% of this straight line.

[0103] In addition to this, with Figures 1 to 15 The same content can also be applied to Figure 16 ,vice versa.

[0104] exist Figure 17 The diagram shows a block diagram of a method for producing a power semiconductor device 1. In method step S1, a semiconductor body 2 is provided. For example, in method step S1, the semiconductor body 2 includes a drift region 23 having a first conductivity type.

[0105] According to subsequent method step S2, an enhancement region 26 and a barrier region 28 with a first conductivity type are created. For example, enhancement region 26 and barrier region 28 are created simultaneously.

[0106] In method step S3, a well region 22 and a lead-out region 27 with a second conductivity type are then created. The well region 22 and the lead-out region 27 can also be created simultaneously.

[0107] Then, in method step S4, a source region 21 with a first conductivity type is created, followed by method step S5, in which a gate electrode 31 is applied to a well region 22, and a lead-out electrode 34 is applied to a lead-out region 27 and / or a barrier region 28.

[0108] Despite Figure 17 Method step S3 follows method step S2, but alternatively, method step S2 may also follow method step S3. Furthermore, method step S4 may be completed before method steps S2 and / or S3.

[0109] In addition to this, with Figures 1 to 16 The same content can also be applied to Figure 17 ,vice versa.

[0110] Unless otherwise stated, the portions shown in the accompanying drawings are exemplarily arranged one on top of the other in the specified order. Portions that do not touch in the drawings are exemplarily spaced apart from each other. If lines are drawn parallel to each other, the corresponding surfaces may be oriented parallel to each other. Similarly, unless otherwise stated, the positions of the drawn portions relative to each other are correctly reproduced in the accompanying drawings.

[0111] The term "and / or" describes only the relationships used to describe related objects and indicates that there may be three relationships. For example, A and / or B may represent the following three cases: only A exists, both A and B exist, and only B exists; if there are more than three entities, the same rule applies similarly.

[0112] The power semiconductor devices described herein are not limited to the description based on exemplary embodiments. Rather, the power semiconductor devices include any new features and any combination of features, including any combination of features in the patent claims, even if the feature or combination itself is not expressly specified in the patent claims or exemplary embodiments.

[0113] This patent application claims priority to European Patent Application 21216358.8, the disclosure of which is incorporated herein by reference.

[0114] List of reference numerals

[0115] 1 Power semiconductor devices

[0116] 2 Semiconductor body

[0117] 20 Top side

[0118] 21 Source Region

[0119] 22 Tunnel Area

[0120] 23 Drift Zone

[0121] 24 Plugs

[0122] 25 Collector Region

[0123] 251 Drain Region

[0124] 26 Enhanced Zones

[0125] 27 Leading Area

[0126] 28 Barrier Zone

[0127] 29 Deeply Doped Region

[0128] 31 Gate electrode

[0129] 32 source electrodes

[0130] 33 Collector Electrode

[0131] 331 Drain electrode

[0132] 34 Lead-out electrodes

[0133] 35 Drain electrode

[0134] 4 Gate Insulator

[0135] 42 field oxides

[0136] 5 active units

[0137] 51. Strip of gate electrode

[0138] 52 Contact points of the lead-out electrodes

[0139] 53 Source electrode strip

[0140] Unit 6

[0141] 10. The first variant of power semiconductor devices

[0142] 11. The second variant of power semiconductor devices

[0143] Aint is the generated integrated avalanche, measured in cm. -2 s -1

[0144] Amax is the maximum avalanche occurrence, measured in cm. -3 s -1

[0145] C represents current, measured in amperes (A).

[0146] Eoff represents the energy loss during shutdown, measured in J.

[0147] I. Pulse count (in thousands)

[0148] I Collision Ionization cm -3 s -1

[0149] N doping concentration cm -3

[0150] P Avalanche Peak

[0151] S.. Method Steps

[0152] T is time, in seconds.

[0153] U represents voltage, measured in volts (V).

[0154] X and Y horizontal and vertical coordinates, in μm.

Claims

1. A power semiconductor device (1) comprising a semiconductor body (2), a gate electrode (31), a source electrode (32) and an extraction electrode (34), the gate electrode (31) being separated from the semiconductor body (2) by an electrically insulating gate insulator, wherein the semiconductor body (2) comprising: - a source region (21) of a first conductivity type, the source region (21) being directly at the source electrode (32) and directly at the gate insulator, - a well region (22) of a second conductivity type different from the first conductivity type, the well region (22) being directly at the gate insulator and directly at the source region (21), - a drift region (23) of the first conductivity type, the drift region (23) electrically following the well region (22) on a side away from the source region (21) and being directly at the gate insulator, - an extraction region (27) directly at the extraction electrode (34), the extraction region (27) having the second conductivity type, and - a barrier region (28) assigned to the extraction electrode (34) and having the first conductivity type, the barrier region (28) being directly between the drift region (23) and the extraction electrode (34) such that the extraction region (27) is between the barrier region (28) and the extraction electrode (34) and the extraction region (27) is entirely surrounded by the barrier region (28), the barrier region (28) forming a well, the extraction region (27) being located in the well, and the barrier region (28) being away from the gate insulator, wherein the well region (22) and the extraction region (27) have the same maximum doping concentration and / or the same doping depth profile, wherein the semiconductor body (2) further comprises a deep doped region (29) of the second conductivity type between at least a portion of the drift region (23) and the barrier region (28), wherein the deep doped region (29) has a depth into the semiconductor body (2) that exceeds a depth of the well region (22), wherein a bottom side of the barrier region (28) is at least partially free of the deep doped region (29).

2. The power semiconductor device (1) according to claim 1, wherein the deep doped region (29) being directly at least at some lateral sides of the barrier region (28), wherein a maximum doping concentration of the deep doped region (29) exceeds a maximum dopant concentration of the well region (22) by at least a factor of two.

3. The power semiconductor device (1) according to claim 1 or 2, wherein the semiconductor body (2) further comprising an enhancement region (26) of the first conductivity type, wherein the enhancement region (26) is directly at a bottom side of the well region (22) such that the enhancement region (26) is between the drift region (23) and the well region (22), wherein a maximum doping concentration of the enhancement region (26) exceeds a maximum dopant concentration of the drift region (23) by at least a factor of two.

4. The power semiconductor device (1) according to claim 1 or 2, wherein The gate electrode (31) is accommodated in a trench, wherein the gate electrode (31) extends deeper into the semiconductor body (2) than the well region (22).

5. The power semiconductor device (1) according to claim 1 or 2, wherein The deep doped region (29) extends at least as far into the semiconductor body (2) as the gate electrode (31).

6. The power semiconductor device (1) according to claim 1 or 2, wherein, The gate electrode (31) comprises 2N strips (51) when seen in a top view of the semiconductor body (2), N being a natural number greater than or equal to 1, wherein the 2N strips (51) define N active cells (5) of the power semiconductor device (1).

7. The power semiconductor device (1) according to claim 6, wherein The source electrode (32) comprises N lines, wherein each of the N lines is assigned to one of the N active cells (5) and is located between a respective two strips (51) of the gate electrode (31) when seen in a top view of the semiconductor body (2).

8. The power semiconductor device (1) according to claim 7, wherein N is a natural number greater than or equal to 2, wherein the extraction electrode (34) comprises a plurality of contact points (52), wherein the contact points (52) are arranged between two adjacent active cells (5) in each case when seen in a top view of the semiconductor body (2).

9. The power semiconductor device (1) according to claim 8, wherein The contact points (52) are arranged along a straight line when seen in a top view of the semiconductor body (2), wherein the contact points (52) occupy at most 5% of the straight line, and wherein each of the contact points (52) is at most 50% as long as the distance between the adjacent active cells (5) along the straight line.

10. The power semiconductor device (1) according to claim 1 or 2, wherein The semiconductor body (2) further comprises a plug (24) of the second conductivity type, wherein the plug (24) is configured to electrically contact the well region (22), wherein the source region (21), the plug (24) and the extraction electrode (34) are configured to be at the same electrical potential.

11. The power semiconductor device (1) according to claim 1 or 2, which is an Insulated Gate Bipolar Transistor, IGBT, configured such that a voltage between a drain electrode and an emitter electrode of the IGBT is at least 0.65 kV.

12. A method of manufacturing a power semiconductor device (1) according to at least claim 3, the method comprising: providing the semiconductor body (2) comprising the drift region (23) of the first conductivity type, simultaneously creating the enhancement region (26) and the barrier region (28) of the first conductivity type, simultaneously creating the well region (22) and the extraction region (27) of the second conductivity type different from the first conductivity type, creating a source region (21) of the first conductivity type, and The source electrode (32) is applied at the source region (21), the gate electrode (31) is applied at the well region (22), and the lead-out electrode (34) is applied at the lead-out region (27), with the barrier region (28) being located directly between the drift region (23) and the lead-out electrode (34).

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