Display device

Abstract

The present application relates to a display device. The display device includes a multiplexer located in a first area of a non-display area and including K MUX transistors commonly connected to a data channel line and to K data lines; a pseudo multiplexer provided in a third area of the non-display area and including K pseudo MUX transistors corresponding to the K MUX transistors; and K MUX control lines and K pseudo MUX control lines located in a second area between the first area and the third area, the K MUX control lines being connected to the K MUX transistors and the K pseudo MUX control lines being connected to the K pseudo MUX transistors, wherein the second area includes a first partial area adjacent to the first area and having the K MUX control lines thereon and a second partial area adjacent to the third area and having the K pseudo MUX control lines thereon.

Description

Technical Field

[0001] This disclosure relates to a display device. Background Technology

[0002] As display resolutions increase, a large number of signal lines are required, complicating wiring designs. To mitigate this, multiplexers are used to connect multiple data lines to each channel of the data drive circuitry.

[0003] The use of multiplexers causes electromagnetic interference (EMI), and in order to mitigate this, dummy multiplexers are used near the multiplexers.

[0004] The descriptions provided in the background section should not be considered prior art simply because they are mentioned in or associated with the background section. The background section may include information describing one or more aspects of the subject matter art. Summary of the Invention

[0005] However, as the inventors of this disclosure recognize, in the past, parasitic capacitances causing RC delays occurred due to the overlap between the control signal lines of the dummy multiplexer and the control signal lines of the multiplexer. Consequently, a defect arose where the control signal of the multiplexer was not properly supplied to the charging system of the multiplexer.

[0006] Therefore, this disclosure relates to a display device that substantially eliminates one or more problems caused by the limitations and deficiencies of related technologies.

[0007] The advantage of this disclosure is that it provides a display device that can prevent (or reduce) the occurrence of RC delay caused by the overlap between the control signal lines of the transmission pseudo-multiplexer and the control signal lines of the transmission multiplexer.

[0008] Further features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description, or may be learned by practice of this disclosure. These and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description, the claims, and the accompanying drawings.

[0009] To achieve these and other advantages, and in accordance with the purposes of this disclosure, as implemented and broadly described herein, a display device includes: a display panel comprising an array substrate defining a display area in which pixels and data lines connected to the pixels are arranged, and a non-display area surrounding the display area; a multiplexer disposed in a first region of the non-display area and comprising K (K is an integer of 2 or greater) MUX transistors, wherein the sources of the K MUX transistors are commonly connected to data channel lines, and the drains of the K MUX transistors are respectively connected to K data lines; and a pseudo-multiplexer disposed in a third region of the non-display area and comprising components configured to be respectively The system includes K pseudo-MUX transistors corresponding to the K MUX transistors; and K MUX control lines and K pseudo-MUX control lines arranged in a second region of the non-display area between the first region and the third region of the non-display area. The K MUX control lines are respectively connected to the gates of the K MUX transistors, and the K pseudo-MUX control lines are respectively connected to the gates of the K pseudo-MUX transistors. The second region includes a first portion adjacent to the first region where the K MUX control lines are arranged, and a second portion adjacent to the third region where the K pseudo-MUX control lines are arranged.

[0010] In another aspect, a display device includes: a multiplexer located in a display panel and connected between a data line and a data channel line; a pseudo-multiplexer located in the display panel and spaced apart from the multiplexer in a first direction; and a MUX control line and a pseudo-MUX control line located between the multiplexer and the pseudo-multiplexer, the MUX control line extending along a second direction intersecting the first direction and connected to the multiplexer, and the pseudo-MUX control line extending along the second direction and connected to the pseudo-multiplexer, wherein the MUX control line is disposed between the multiplexer and the pseudo-MUX control line.

[0011] It should be understood that both the above general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of this disclosure. The drawings illustrate embodiments of the disclosure and, together with this specification, serve to explain the principles of the disclosure. In the drawings:

[0013] Figure 1 This is a view that schematically illustrates the configuration of a display device according to an exemplary embodiment of the present disclosure.

[0014] Figure 2 This is a circuit diagram illustrating the configuration of pixels according to an exemplary embodiment of the present disclosure;

[0015] Figure 3 This is a cross-sectional view illustrating an example of a display panel according to an exemplary embodiment of the present disclosure;

[0016] Figure 4 This is a schematic plan view illustrating a portion of a multiplexer circuit according to an exemplary embodiment of the present disclosure;

[0017] Figure 5 This is a circuit diagram illustrating the circuit configuration of a multiplexer circuit portion according to an exemplary embodiment of the present disclosure;

[0018] Figure 6 It is along Figure 4 A cross-sectional view taken from line VI-VI';

[0019] Figure 7 It is along Figure 4 A cross-sectional view taken from line VII-VII'; and

[0020] Figure 8 This is a timing diagram of the signals of a driver multiplexer and a pseudo multiplexer according to one embodiment of the present disclosure.

[0021] Throughout the accompanying drawings and detailed embodiments, unless otherwise described, it should be understood that the same reference numerals denote the same elements, features, and structures. For clarity, illustrative purposes, the relative sizes and depictions of these elements may be exaggerated. Detailed Implementation

[0022] Now, reference will be made in detail to embodiments of this disclosure, examples of which may be illustrated in the accompanying drawings. The described process steps and / or operations are exemplary; however, the order of steps and / or operations is not limited to the order set forth herein and may be varied in accordance with those known in the art, except for steps and / or operations that must occur in a specific order. The names of the corresponding elements used in the following description may be chosen merely for convenience in drafting the specification and may therefore differ from the names used in actual products.

[0023] The advantages and features of this disclosure, as well as its implementation methods, will become clear from the following detailed description of the embodiments with reference to the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms, and only these embodiments allow this disclosure to be complete. This disclosure is intended to fully inform those skilled in the art of this disclosure of its scope, and this disclosure may be defined by the scope of the claims.

[0024] The shapes, sizes, proportions, angles, quantities, etc., disclosed in the accompanying drawings for the purpose of illustrating embodiments of this disclosure are illustrative, and this disclosure is not limited to the illustrative content.

[0025] Furthermore, in describing this disclosure, a detailed description of the relevant known art may be omitted if it is determined that such detailed description unnecessarily obscures the subject matter of this disclosure. When words such as "comprising," "including," "having," and "compose" are used in this disclosure, other parts may be added unless "only" is used. When a component is represented in the singular, it also includes the case of including a plural, unless specifically stated otherwise.

[0026] Any implementation described as an "example" in this article is not necessarily to be interpreted as having priority over or superiority over other implementations.

[0027] When interpreting a component, it is interpreted as including a margin range, even without a separate explicit description.

[0028] When describing positional relationships, for example, when the positional relationship between two components is described as "on," "above," "above," "below," "beside," "under," etc., one or more other components may be positioned between such two components, unless "exactly" or "just right" is used.

[0029] When describing time relationships, such as when time priorities are described as "after", "following", "before", etc., non-continuous situations can be included unless "exactly" or "directly" is used.

[0030] Terms such as “below,” “under,” “above,” and “above” may be used herein to describe the relationships between items as illustrated in the accompanying figures. It should be understood that these terms are spatially relative and based on the orientation depicted in the figures.

[0031] In describing the components of this disclosure, terms such as "first," "second," "A," "B," "(a)," and "(b)" may be used. These terms are only used to distinguish a component from other components, and the nature, order, sequence, or number of components is not limited by the terms. Furthermore, when describing a component as being "connected," "joined," or "in contact" with another component, the component may be directly connected or in contact with the other component; however, it should be understood that other components may be "inserted" between components.

[0032] The term “at least one” should be understood to include any and all combinations of one or more of the associated listed items. For example, “at least one of the first, second, and third elements” means, in addition to each individual element (the first, second, and third elements), combinations of all three listed elements, and combinations of any two of the three elements.

[0033] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It should also be further understood that terms such as those defined in a general dictionary should be interpreted as having a meaning consistent, for example, with their meaning in the context of the relevant field, and should not be interpreted in an idealized or overly formal sense unless so explicitly defined herein. For example, the terms “part” or “unit” can be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit device, or any structure constructed to perform the described functions as would be understood by one of ordinary skill in the art.

[0034] The corresponding features of the various embodiments of this disclosure may be partially or wholly connected or combined with each other, and may be technically interlocked and driven differently, and the various embodiments may be implemented independently of each other or may be implemented together in a related relationship.

[0035] In the following description, embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. Furthermore, in the following embodiments, the same and similar reference numerals are assigned to the same and similar parts, and detailed descriptions thereof may be omitted.

[0036] Figure 1 This is a view that schematically illustrates the configuration of a display device according to an exemplary embodiment of the present disclosure, and Figure 2 This is a circuit diagram illustrating the configuration of pixels according to an exemplary embodiment of the present disclosure.

[0037] Reference Figure 1 and Figure 2 The display device 10 according to an exemplary embodiment of the present disclosure may include a display panel 100 and a driving circuit portion for driving the display panel 100.

[0038] Here, the driving circuit section may include, for example, a gate driving circuit section 210, a data driving circuit section 220, and a multiplexer circuit section 300. The implementation is not limited thereto. As an example, it may also include one or more components.

[0039] The display panel 100 may include a display area AA and a non-display area NA that is adjacent to or partially or completely surrounds the display area AA.

[0040] In the display area AA of the display panel 100, pixels P arranged along multiple horizontal lines (or row lines) and multiple vertical lines (or column lines) can be disposed on the substrate. The terms "horizontal" and "vertical" are based on... Figure 1 The directions shown can be changed depending on the actual direction.

[0041] An image can be displayed on the display panel 100 using multiple pixels P.

[0042] Here, multiple pixels P can be pixels displaying different colors; for example, they can include red, green, and blue pixels P displaying red, green, and blue respectively, but are not limited to this. As an example, white pixels displaying white can also be included. Pixels displaying colors other than red, green, blue, and white are also possible.

[0043] In the display panel 100, various signal lines for transmitting drive signals for driving pixels P can be formed on the substrate.

[0044] In this respect, for example, multiple data lines DL that transmit data signals (or data voltages) as image signals can extend vertically and be connected to pixels P corresponding to the vertical lines. Additionally, multiple gating lines GL that transmit gating signals (or gating voltages) can extend horizontally and be connected to pixels P corresponding to the horizontal lines.

[0045] A pixel P can be defined by multiple intersecting data lines DL and gating lines GL.

[0046] Reference Figure 2 Each pixel P can be equipped with a switching transistor Ts connected to the gate line GL and the data line DL, as well as a liquid crystal capacitor Clc. The liquid crystal capacitor Clc can be configured with corresponding pixel electrodes and a common electrode, and a liquid crystal layer interposed between the pixel electrodes and the common electrode.

[0047] Additionally, pixel P may include a storage capacitor Cst to store the data signal input therein.

[0048] For the structure of the display panel 100, please refer to... Figure 3 . Figure 3This is a cross-sectional view schematically illustrating an example of a display panel according to an exemplary embodiment of the present disclosure.

[0049] In addition, Figure 3 For ease of explanation, an in-plane switching (IPS) type display panel 100 is shown as an example. However, the display panel 100 of this embodiment can be any type of display panel, including IPS type, vertical orientation (VA) type, or twisted nematic (TN) type.

[0050] Reference Figures 1 to 3 The display panel 100 may include an array substrate (or lower substrate) 101 and an opposing substrate (or upper substrate) 181 facing each other, and a liquid crystal layer 195 inserted between the array substrate 101 and the opposing substrate 181.

[0051] Furthermore, although not specifically shown, a backlight unit for providing light can also be provided. As an example, the backlight unit can be located below the array substrate 101, but is not limited thereto.

[0052] In the array substrate 101, multiple gate lines GL extending along a first direction, such as the horizontal direction (or the row direction), can be formed on the first substrate 111.

[0053] The gate insulating layer 130, which is an insulating layer made of insulating material, can be formed below the gate line GL. As an example, the gate insulating layer 130 can be a single layer or multiple layers of silicon oxide (SiO2). x or silicon nitride (SiN) x It can be formed by atomic layer deposition (ALD) or metal-organic chemical vapor deposition (MOCVD), but is not limited thereto. Additionally, an interlayer insulating layer 135, which is an insulating layer made of insulating material, can be formed on the gate line GL.

[0054] Multiple data lines DL extending along a second direction, such as the vertical direction (or column direction), can be formed on the interlayer insulating layer 135.

[0055] In each pixel P, a switching transistor Ts can be formed that is connected to the gate line GL and the data line DL.

[0056] The switching transistor Ts may have a gate 131 connected to the gate line GL, a semiconductor layer 121 located below the gate insulating layer 130, and a source 141 and a drain 143 located on the interlayer insulating layer 135 and spaced apart from each other. Here, the source 141 may be connected to the data line DL.

[0057] Here, the semiconductor layer 121 may include a channel region corresponding to the gate 131 and source and drain regions on both sides of the channel region. For example, the semiconductor layer 121 may be formed of a material selected from oxide semiconductor materials, amorphous silicon (Si) semiconductor materials or polycrystalline semiconductor materials, but this disclosure is not limited thereto.

[0058] The source 141 and drain 143 can be connected to the source and drain regions of the semiconductor layer 121 through corresponding contact holes CH1 and CH2 formed in the interlayer insulating layer 135 and the gate insulating layer 130.

[0059] In each pixel P, a pixel electrode 151 may be formed that is connected to the drain 143 of the switching transistor Ts. The pixel electrode 151 may be formed of a transparent conductive material such as ITO, IZO or ITZO, but is not limited thereto.

[0060] Alternatively, the pixel electrode 151 can be formed on the drain 143, wherein at least one insulating layer is interposed between the pixel electrode 151 and the drain 143. In this case, a contact hole can be formed in the insulating layer formed between the pixel electrode 151 and the drain 143, and the pixel electrode 151 can be configured to contact the drain 143 through the contact hole.

[0061] Passivation layer 161, which is an insulating layer made of an insulating material, can be formed on pixel electrode 151 and switching transistor Ts. For example, passivation layer 161, which is a dielectric (e.g., inorganic dielectric), can be made of silicon oxide (SiO2). x ) membrane, silicon nitride (SiN) x ) membrane or silicon oxynitride (SiO) x N y It consists of a single layer or multiple layers of membranes made of membranes, etc.

[0062] A common electrode 171 facing the pixel electrode 151 can be formed on the passivation layer 161. The common electrode 171 can be formed of a transparent conductive material such as ITO, IZO or ITZO, but is not limited to this.

[0063] The common electrode 171, together with the pixel electrode 151, can drive the liquid crystal layer 195 by forming a fringe field, which is an in-plane electric field (or a horizontal electric field).

[0064] The common electrode 171 may include a plurality of strip electrode patterns 172 corresponding to each pixel P and facing the pixel electrode 151, and openings 173 may be formed between the electrode patterns 172 and between the electrode patterns 172 and the remainder of the common electrode 171.

[0065] Here, the plurality of electrode patterns 172 can be formed to extend along the extension direction of the data line DL. In addition, the plurality of electrode patterns 172 may include a first electrode pattern 172a located near the data line DL and on the outermost side of the pixel P, and a second electrode pattern 172b located inside the first electrode pattern 172a.

[0066] Here, as an example, the first electrode pattern 172a may have a width greater than the width of the data line DL and may cover the data line DL below it, but is not limited thereto. As an example, the first electrode pattern 172a may overlap with at least a portion of the data line DL. As an example, the first electrode pattern 172a may also have a width the same as the width of the data line DL, or even a width smaller than the width of the data line DL.

[0067] When the first electrode pattern 172a is formed in this manner, electrical interference between the data line DL and the pixel electrode 151 can be reduced or prevented.

[0068] Additionally, the second electrode pattern 172b located on the inner side can be formed to have a width smaller than that of the first electrode pattern 172a, but is not limited thereto. As an example, the width of the second electrode pattern 172b can also be greater than or equal to the width of the first electrode pattern 172a.

[0069] Furthermore, as another example of the arrangement structure of the common electrode 171 and the pixel electrode 151, the common electrode 171 can be formed such that the portion of the common electrode 171 corresponding to the pixel electrode 151 has a plate shape, and the pixel electrode 151 can be formed on the common electrode 171 with an insulating layer therebetween, and includes multiple electrode patterns.

[0070] As another example, each of the common electrode 171 and the pixel electrode 151 may be formed with an electrode pattern, and in this case, the electrode pattern of the common electrode 171 and the electrode pattern of the pixel electrode 151 may be arranged alternately, and the common electrode 171 and the pixel electrode 151 may be located in the same layer or may be positioned such that there is an insulating layer between them.

[0071] Furthermore, although not specifically shown, as an example, the common electrode 171 can be configured to function as a touch electrode. In this case, for example, the common electrode 171 can function as an electric field generating electrode that is subjected to a common voltage and drives the liquid crystal during a display period, and as a touch electrode that is subjected to a touch driving signal during a touch detection period between display periods. Thus, the common electrode 171 can function as an in-cell touch electrode. The implementation is not limited to this, and the common electrode 171 may not be used as a touch electrode.

[0072] Furthermore, although not specifically shown, in the array substrate 101, an alignment layer (or first alignment layer) for aligning the liquid crystal molecules of the liquid crystal layer 195 can be formed on the common electrode 171.

[0073] In the opposing substrate 181 located above the array substrate 101, a color filter pattern 187 can be formed on the inner surface of the second substrate 185. At this point, for example, red, green, and blue color filter patterns 187 corresponding to red, green, and blue pixels P can be formed. The colors of the color filter pattern 187 are not limited to this and can be changed according to the color of the pixels.

[0074] Furthermore, in the opposing substrate 181, the black background BM can be formed along the boundary between adjacent pixels P. The black background BM can be arranged to cover at least a portion of the non-display array elements (such as data lines DL, gate lines GL, and switching transistors Ts) formed on the array substrate 101.

[0075] An opening can be formed in the black background BM corresponding to pixel P, and the color filter pattern 187 corresponding to each pixel P can fill the opening in the black background BM and cover the edge of the black background BM.

[0076] A cover layer 189, which is an insulating layer made of insulating material, can be formed on the color filter pattern 187. The cover layer 189 can planarize the surface of the second substrate 185 on which the color filter pattern 187 is formed.

[0077] Furthermore, although not specifically shown, an alignment layer (or second alignment layer) for aligning the liquid crystal molecules of the liquid crystal layer 195 may be formed on the capping layer 189.

[0078] Refer again Figure 1 The gate drive circuit section 210 can generate gating signals and apply them sequentially to the gating line GL. For example, in the figure, the gating signals can be output sequentially from top to bottom in the vertical direction. The sequence of output gating signals is not limited to this and can be changed according to different designs.

[0079] As an example, the gate driving circuit portion 210 can be directly formed on the array substrate 101 of the display panel 100 in a GIP (gate in board) type. For example, the gate driving circuit portion 210 can be formed during the formation of the array elements. The implementation is not limited to this. As an example, the gate driving circuit portion 210 can be formed in a separate process other than the formation of the array elements.

[0080] As another example, the gate drive circuit section 210 may be configured with at least one gate IC. As an example, the gate drive circuit section 210 may be connected to the display panel 100, for example, by a tape-on-board (TAB) method, a chip-on-glass (COG) method, a chip-on-board (COP) method, or a chip-on-film (COF) method.

[0081] The data drive circuit section 220 can convert digital data signals into data voltages as analog data signals and output them to the display panel 100.

[0082] At this point, the data drive circuit section 220 can output data signals through each of the multiple output channels (or output terminals), and can output M (M is an integer of 2 or greater) data signals respectively applied to, for example, M data lines DL adjacent to each other in the display panel 100 during the horizontal time period of each horizontal line.

[0083] Furthermore, in this exemplary embodiment, for ease of explanation, a case is given in which each output channel of the data driving circuit section 220 outputs two data signals applied to two adjacent data lines DL.

[0084] The data signal output can be applied to the non-display area NA formed in the display panel 100 or to the corresponding data channel line (or data transmission line) DCL connected to the non-display area NA. The data channel line DCL can be connected to the corresponding output channel of the data drive circuit section 220.

[0085] Furthermore, the data driving circuit section 220 may be configured with at least one data IC. In this case, as an example, the data IC of the data driving circuit section 220 may be connected to a non-display area NA on a corresponding side of the display panel 100 (or array substrate 101), or it may be directly mounted on the non-display area NA. As an example, the data IC of the data driving circuit section 220 may be mounted on a flexible circuit film and connected to the non-display area NA on a corresponding side of the display panel 100 (or array substrate 101).

[0086] The multiplexer circuit portion 300 can be formed in the non-display area NA of the array substrate 101 of the display panel 100. The multiplexer circuit portion 300 can be formed together with the array elements of the array substrate 101 during the formation process, but is not limited thereto. As an example, the multiplexer circuit portion 300 can also be formed in a separate process other than the formation process of the array elements of the array substrate 101.

[0087] The multiplexer circuit section 300 may include a plurality of multiplexer MUXs. Each of the plurality of multiplexer MUXs may connect its input terminal to a corresponding one of the plurality of data channel lines DCL, such that each multiplexer MUX may receive a data signal output from a corresponding output channel of the data drive circuit section 220.

[0088] Additionally, each multiplexer MUX can connect its output terminal to two data lines DL, for example, to the first data line DL1 and the second data line DL2.

[0089] Therefore, the multiplexer MUX can alternately output the two data signals input to it to the first data line DL1 and the second data line DL2 through its switching operation.

[0090] Thus, the multiplexer MUX can perform a switching operation to alternately connect the corresponding output channels of the data driver circuit section 220 to the adjacent first data line DL1 and second data line DL2. Consequently, the multiplexer MUX can sequentially apply the first data signal and the second data signal, which are two data signals output from the output channels of the data driver circuit section 220, to the corresponding first data line DL1 and second data line DL2.

[0091] By using the multiplexer MUX described above, the number of output channels in the data drive circuit section 220 can be reduced, and the number of pad electrodes and transmission lines for receiving data signals in the display panel 100 can also be reduced.

[0092] Furthermore, the multiplexer circuit section 300 may be equipped with a pseudo-multiplexer having substantially the same structure as the multiplexer MUX. The pseudo-multiplexer can be used to reduce EMI generated according to the switching operation of the multiplexer MUX, and can use a control signal having a waveform (or phase) opposite to the waveform (or phase) of the control signal used to switch the multiplexer MUX.

[0093] In this exemplary embodiment, the control line for transmitting the control signal of the dummy multiplexer can be configured not to overlap with the control line for transmitting the control signal of the multiplexer MUX. Therefore, the parasitic capacitance between the control line of the multiplexer MUX and the control line of the dummy multiplexer can be reduced or minimized (or prevented). Consequently, the RC delay of the control signal of the multiplexer MUX due to parasitic capacitance can be improved, resulting in normal transmission of the control signal of the multiplexer MUX and mitigating charging system defects of the multiplexer MUX.

[0094] The arrangement of pseudo multiplexers and multiplexer MUXs is described in more detail below.

[0095] Figure 4This is a plan view schematically illustrating a portion of a multiplexer circuit according to an exemplary embodiment of the present disclosure. Figure 5 This is a circuit diagram illustrating the circuit configuration of a multiplexer circuit portion according to an exemplary embodiment of the present disclosure. Figure 6 It is along Figure 4 The cross-sectional view taken from line VI-VI' illustrates the structure of the first MUX transistor of the multiplexer. Figure 7 It is along Figure 4 The cross-sectional view taken from line VII-VII' illustrates the structure of the first pseudo-MUX transistor of the pseudo-multiplexer.

[0096] Reference Figures 4 to 7 Together Figure 1 In the multiplexer circuit section 300 (or the area in which the multiplexer circuit section 300 is formed) according to this exemplary embodiment, a plurality of multiplexers MUX and a plurality of pseudo multiplexers MUXp, a plurality of control lines CL and voltage lines PL can be arranged.

[0097] For ease of explanation, in the non-display area NA of the display panel 100, the area where the multiplexer circuit portion 300 is formed can be referred to as the circuit area CA, and the circuit area CA can include a first area CA1, a second area CA2, and a third area CA3 defined therein that are different from each other (or do not overlap). In this case, the first area CA1 can be the area close to the display area AA of the display panel 100, and the third area CA3 can be the area close to one end of the display panel 100 (or the data driving circuit portion 220), and the second area CA2 can be located between the first area CA1 and the third area CA3.

[0098] Multiple multiplexers (MUX) can be arranged, for example, in the first region CA1 of the circuit region CA.

[0099] Each of the multiplexers (MUX) may include a first MUX transistor Tm1 and a second MUX transistor Tm2. The first MUX transistor Tm1 and the second MUX transistor Tm2 are two switching elements corresponding to and connected to a first data line DL1 and a second data line DL2, respectively, which receive a first data signal and a second data signal from each multiplexer (MUX). The first MUX transistor Tm1 and the second MUX transistor Tm2 may be jointly connected to the data channel line DCL, which transmits the first and second data signals.

[0100] The drain Dm1, which serves as the output terminal (or output electrode) of the first MUX transistor Tm1, can be connected to the corresponding first data line DL1, and the source Sm1, which serves as the input terminal (or input electrode) of the first MUX transistor Tm1, can be connected to the data channel line DCL. Additionally, the gate Gm1, which serves as the control terminal (or control electrode) of the first MUX transistor Tm1, can be connected to the first MUX control line CLm1.

[0101] Therefore, the first MUX transistor Tm1 can be turned on / off by the first MUX control signal CSm1 applied to the first MUX control line CLm1, and in the on state of the first MUX transistor Tm1, the corresponding first data signal can be output to the first data line DL1.

[0102] Referring to the stacked structure of the first MUX transistor Tm1 Figure 6 The first MUX transistor Tm1 can have the same pixel as described above ( Figure 3 The switching transistor in P) Figure 3 Similar to, but not limited to, structures like (Ts).

[0103] At this point, the semiconductor layer SEm1 can be formed on the first substrate 111 of the array substrate 101. The gate Gm1 can be formed on the gate insulating layer 130 on the semiconductor layer SEm1. The source Sm1 and drain Dm1 can be formed on the interlayer insulating layer 135 on the gate Gm1.

[0104] Each of the source Sm1 and drain Dm1 can contact the semiconductor layer SEm1 through corresponding contact holes CHm1 and CHm2 formed in the gate insulating layer 130 and the interlayer insulating layer 135.

[0105] Furthermore, the gate Gm1 can be connected to the first MUX control line CLm1 through the contact hole CHm3 formed in the interlayer insulating layer 135.

[0106] Furthermore, as an example, the source Sm1 can be connected to the data channel line DCL. As an example, the source Sm1 can be directly connected to the data channel line DCL on the same layer. As an example, the source Sm1 can be connected to the data channel line DCL through a contact hole CHm4 in an insulating layer (e.g., interlayer insulating layer 135) formed therebetween.

[0107] The drain Dm2, which serves as the output terminal (or output electrode) of the second MUX transistor Tm2, ​​can be connected to the corresponding second data line DL2, and the source Sm2, which serves as the input terminal (or input electrode) of the second MUX transistor Tm2, ​​can be connected to the data channel line DCL. Additionally, the gate Gm2, which serves as the control terminal (or control electrode) of the second MUX transistor Tm2, ​​can be connected to the second MUX control line CLm2.

[0108] Therefore, the second MUX transistor Tm2 can be turned on / off by the second MUX control signal CSm2 applied to the second MUX control line CLm2, and in the on state of the second MUX transistor Tm2, ​​the corresponding second data signal can be output to the second data line DL2.

[0109] The stacking structure of the second MUX transistor Tm2 can be substantially the same as the stacking structure of the first MUX transistor Tm1 described above, but is not limited thereto.

[0110] Multiple pseudo-multiplexers MUXp can be arranged, for example, in the third region CA3 of the circuit region CA.

[0111] Within the multiplexer circuit section 300, the same number of pseudo multiplexers MUXp as the multiplexer MUX can be set, but it is not limited to this.

[0112] The pseudo multiplexer MUXp can be arranged in a one-to-one correspondence with the multiplexer MUX, but is not limited to this. For example, the pseudo multiplexer MUXp and the multiplexer MUX can be arranged to face each other substantially, with the second region CA2 located between them.

[0113] A pseudo-multiplexer MUXp can be a component that is essentially independent of the input and output of data signals. For example, a pseudo-multiplexer MUXp can be similar to or the same as a multiplexer MUX in terms of structure and electrical properties, and its switching operation can be the reverse of that of a multiplexer MUX.

[0114] The pseudo-multiplexer MUXp can electrically short-circuit its input and output terminals, and its input and output terminals can be configured to commonly receive, for example, a DC voltage of 0V or less, or a voltage less than the minimum data signal, instead of a data signal. In this exemplary embodiment, for ease of illustration, the case of applying ground voltage GND is taken as an example. As another example, the input and output terminals of the pseudo-multiplexer MUXp can receive voltages less than 0V (e.g., a low-gating voltage VGL).

[0115] The pseudo-multiplexer MUXp may include a first pseudo-MUX transistor Tp1 and a second pseudo-MUX transistor Tp2, which are configured as two switching elements corresponding to the first MUX transistor Tm1 and the second MUX transistor Tm2, ​​respectively. The first pseudo-MUX transistor Tp1 and the second pseudo-MUX transistor Tp2 may be connected together to a voltage line PL that transmits, for example, ground voltage GND.

[0116] The source Sp1 and drain Dp1, which serve as the input terminal (or input electrode) and output terminal (or output electrode) of the first pseudo-MUX transistor Tp1, respectively, can be short-circuited and connected together to the voltage line PL. Additionally, the gate Gp1, which serves as the control terminal (or control electrode) of the first pseudo-MUX transistor Tp1, can be connected to the first pseudo-MUX control line CLp1.

[0117] Therefore, the first pseudo-MUX transistor Tp1 can be turned on / off by the first pseudo-MUX control signal CSp1 applied to the first pseudo-MUX control line CLp1. Furthermore, since the source Sp1 and drain Dp1 of the first pseudo-MUX transistor Tp1 are short-circuited, there is essentially no change in signal input / output due to the change in the on / off state of the first pseudo-MUX transistor Tp1.

[0118] Here, the first pseudo-MUX control signal CSp1 has a waveform (or phase) opposite to that of the first MUX control signal CSm1, such that the on / off state of the first pseudo-MUX transistor Tp1 can be opposite to that of the corresponding first MUX transistor Tm1. In other words, when the first pseudo-MUX transistor Tp1 is in the on / off state, the first MUX transistor Tm1 is in the off / on state.

[0119] Referring to the stacked structure of the first pseudo-MUX transistor Tp1 Figure 7 The first pseudo-MUX transistor Tp1 can be formed in a structure similar to the first MUX transistor Tm1 described above, but is not limited thereto.

[0120] At this point, the semiconductor layer SEp1 can be formed on the first substrate 111 of the array substrate 101. The gate Gp1 can be formed on the gate insulating layer 130 on the semiconductor layer SEp1. The source sp1 and drain Dp1 can be formed on the interlayer insulating layer 135 on the gate Gp1.

[0121] The source Sp1 and drain Dp1 can contact the semiconductor layer SEp1 through corresponding contact holes CHp1 and CHp2 formed in the gate insulating layer 130 and the interlayer insulating layer 135.

[0122] Furthermore, although not specifically shown, the gate Gp1 can be connected to the first pseudo-MUX control line CLp1, for example, directly or through a contact hole in an insulating layer (e.g., interlayer insulating layer 135) formed therebetween.

[0123] The source Sp1 and drain Dp1 can be formed of the same material on the same layer as the voltage line PL, and can be as follows: Figure 4 The diagram shows branches and extensions from, but is not limited to, the voltage line PL. As an example, the source Sp1 and drain Dp1 may be formed of a different material than the voltage line PL and / or formed on a different layer than the voltage line PL.

[0124] The source Sp2 and drain Dp2, which serve as the input terminal (or input electrode) and output terminal (or output electrode) of the second pseudo-MUX transistor Tp2, respectively, can be short-circuited and connected together to the voltage line PL. Additionally, the gate Gp2, which serves as the control terminal (or control electrode) of the second pseudo-MUX transistor Tp2, can be connected to the second pseudo-MUX control line CLp2.

[0125] Therefore, the second pseudo-MUX transistor Tp2 can be turned on / off by the second pseudo-MUX control signal CSP2 applied to the second pseudo-MUX control line CLp2. Furthermore, since the source Sp2 and drain Dp2 of the second pseudo-MUX transistor Tp2 are short-circuited to each other, there is essentially no electrical change or operation caused by the change in the on / off state of the second pseudo-MUX transistor Tp2.

[0126] Here, the second pseudo-MUX control signal CSp2 has a waveform (or phase) opposite to that of the second MUX control signal CSm2, such that the on / off state of the second pseudo-MUX transistor Tm2 can be opposite to that of the corresponding second MUX transistor Tp2. In other words, when the second pseudo-MUX transistor Tp2 is in the on / off state, the second MUX transistor Tm2 is in the off / on state.

[0127] The stacking structure of the second pseudo-MUX transistor Tp2 can be substantially the same as the stacking structure of the first pseudo-MUX transistor Tp1, but is not limited thereto.

[0128] Multiple control lines CL can be arranged in, for example, a second region CA2 of circuit region CA.

[0129] The multiple control lines CL set in the second region CA2 may include a first MUX control line CLm1 and a second MUX control line CLm2 that respectively transmit the first MUX control signal CSm1 and the second MUX control signal CSm2, and a first pseudo MUX control line CLp1 and a second pseudo MUX control line CLp2 that respectively transmit the first pseudo MUX control signal CSP1 and the second pseudo MUX control signal CSP2.

[0130] Multiple control lines CL can be formed, for example, extending in the horizontal direction (or the first direction) of the figure.

[0131] Furthermore, in this exemplary embodiment, the voltage line PL is set in the third region CA3 as an example. However, the voltage line PL can also be set in the second region CA2.

[0132] like Figure 4 and Figure 6 As shown, the multiple control lines CL can be formed of the same material as the sources Sm1, Sm2, Sp1, and Sp2 and the drains Dm1, Dm2, Dp1, and Dp2 of the first MUX transistor Tm1, the second MUX transistor Tm2, ​​the first dummy MUX transistor Tp1, and the second dummy MUX transistor Tp2, and are formed in the same layer as them. The implementation is not limited to this.

[0133] Here, the second region CA2, in which multiple control lines CL are arranged, can be divided into a first part region CA21 and a second part region CA22 that are different from each other (or do not overlap). The first part region CA21 may be the region adjacent to the first region CA1, and the second part region CA22 may be the region adjacent to the third region CA3.

[0134] In this configuration, the first MUX control line CLm1 and the second MUX control line CLm2 can be located in the first region CA21. Additionally, the first pseudo-MUX control line CLp1 and the second pseudo-MUX control line CLp2 can be located in the second region CA22.

[0135] Thus, in this exemplary embodiment, the first MUX control line CLm1 and the second MUX control line CLm2 connected to the multiplexer MUX can be located in a first partial region CA21 adjacent to the first region CA1 in which the multiplexer MUX is located, and the first pseudo MUX control line CLp1 and the second pseudo MUX control line CLp2 connected to the pseudo multiplexer MUXp can be located in a second partial region CA22 adjacent to the third region CA3 in which the pseudo multiplexer MUXp is located.

[0136] Therefore, the signal transmission paths of the MUX control lines CLm1 and CLm2 connected to the multiplexer MUX can be kept separate from the signal transmission paths of the pseudo-MUX control lines CLp1 and CLp2 connected to the pseudo-multiplexer MUXp. This reduces or minimizes (or prevents) the parasitic capacitance between the MUX control lines CLm1 and CLm2 and the pseudo-MUX control lines CLp1 and CLp2.

[0137] At this point, the gate Gm1 of the first MUX transistor Tm1 connected to the first MUX control line CLm1 can have, for example, in a second direction toward the first region CA1 (i.e., Figure 4 The shape extends downwards (in the first direction), and this second direction is perpendicular to the vertical direction, which is the horizontal direction. In other words, the gate Gm1 of the first MUX transistor Tm1 can extend in the second direction while contacting the first MUX control line CLm1 through the corresponding contact hole CHm3.

[0138] Additionally, the gate Gm2 of the second MUX transistor Tm2 connected to the second MUX control line CLm2 can have a direction that faces the first region CA1 (i.e., Figure 4 The shape extends in the second direction (the downward direction in the middle). In other words, the gate Gm2 of the second MUX transistor Tm2 can extend in the second direction while contacting the second MUX control line CLm2 through the corresponding contact hole.

[0139] On the other hand, the gate Gp1 of the first pseudo-MUX transistor Tp1, connected to the first pseudo-MUX control line CLp1, can have a shape that extends, for example, into the third region CA3 in a vertical direction perpendicular to the first direction, which is the horizontal direction. In other words, the gate Gp1 of the first pseudo-MUX transistor Tp1 can extend upward in a third direction opposite to the second direction while contacting the first pseudo-MUX control line CLp1 through a corresponding contact hole. Therefore, the gate Gp1 of the first pseudo-MUX transistor Tp1 can be spaced apart from the first MUX control line CLm1 and the second MUX control line CLm2, without overlapping with them, thereby reducing or minimizing parasitic capacitance.

[0140] The gate Gp2 of the second pseudo-MUX transistor Tp2, connected to the second pseudo-MUX control line CLp2, can have a shape extending into the third region CA3. In other words, the gate Gp2 of the second pseudo-MUX transistor Tp2 can extend upward in a third direction opposite to the second direction while contacting the second pseudo-MUX control line CLp2 through a corresponding contact hole. Therefore, the gate Gp2 of the second pseudo-MUX transistor Tp2 can be spaced apart from the first MUX control line CLm1 and the second MUX control line CLm2, without overlapping with them, thereby reducing or minimizing parasitic capacitance.

[0141] As described above, in the exemplary embodiments of this disclosure, the multiplexer MUX and the pseudo multiplexer MUXp can be located on opposite sides, wherein the area where the MUX control lines CLm1 and CLm2 and the pseudo MUX control lines CLp1 and CLp2 are provided is located between the multiplexer MUX and the pseudo multiplexer MUXp, and at this time, the MUX control lines CLm1 and CLm2 can be arranged near the multiplexer MUX, while the pseudo MUX control lines CLp1 and CLp2 can be arranged near the pseudo multiplexer MUXp.

[0142] Therefore, the signal transmission paths of the MUX control lines CLm1 and CLm2 connected to the multiplexer MUX do not overlap with the signal transmission paths of the pseudo-MUX control lines CLp1 and CLp2 connected to the pseudo-multiplexer MUXp. Thus, the parasitic capacitance between the MUX control lines CLm1 and CLm2 and the pseudo-MUX control lines CLp1 and CLp2 can be reduced or minimized (or prevented).

[0143] Therefore, the RC delay of the control signal of the multiplexer MUX due to parasitic capacitance can be reduced. As a result, the control signal of the multiplexer MUX can be transmitted normally, which improves the charging system defects of the multiplexer MUX.

[0144] Further references are provided below. Figure 8 The operation of the multiplexer MUX and pseudo multiplexer MUXp in this exemplary implementation is described. Figure 8 This is a timing diagram of the signals of a driver multiplexer and a pseudo multiplexer according to an exemplary embodiment of this disclosure.

[0145] In addition, Figure 8 For ease of explanation, the driver display panel will be described in the following text. Figure 1 The case of the first and second horizontal lines of 100 is taken as an example.

[0146] Reference Figure 8 Together Figure 1 , Figure 2 , Figure 4 and Figure 5During the first horizontal time period H1 when the gating signal Vg1 is applied to the gating line GL of the corresponding first horizontal line, the first MUX control signal CSm1 and the second MUX control signal CSm2 can sequentially have a turn-on voltage (e.g., a high voltage), and correspondingly, the first MUX transistor Tm1 and the second MUX transistor Tm2 can sequentially turn on. Although in Figure 8 The turn-on voltage is exemplified as a high voltage, but the implementation is not limited to this. Depending on the type of transistor, the turn-on voltage can be either high or low.

[0147] Here, during the period when the first MUX transistor Tm1 is turned on, the first data signal DA11 transmitted to the multiplexer MUX can be output to the corresponding first data line DL1 through the first MUX transistor Tm1, and transmitted to the pixel P of the first horizontal line connected to the first data line DL1.

[0148] Subsequently, during the period when the second MUX transistor Tm2 is turned on, the second data signal DA12 transmitted to the multiplexer MUX can be output to the corresponding second data line DL2 through the second MUX transistor Tm2, ​​and transmitted to the pixel P of the first horizontal line connected to the second data line DL2.

[0149] Next, during the second horizontal time period H2 when the gating signal Vg2 is applied to the gating line GL of the corresponding second horizontal line, the first MUX control signal CSm1 and the second MUX control signal CSm2 can sequentially have a turn-on voltage, and thus the first MUX transistor Tm1 and the second MUX transistor Tm2 can sequentially turn on.

[0150] Here, during the period when the first MUX transistor Tm1 is turned on, the first data signal DA21 transmitted to the multiplexer MUX can be output to the corresponding first data line DL1 through the first MUX transistor Tm1, and transmitted to the pixel P of the second horizontal line connected to the first data line DL1.

[0151] Subsequently, during the period when the second MUX transistor Tm2 is turned on, the second data signal DA22 transmitted to the multiplexer MUX can be output to the corresponding second data line DL2 through the second MUX transistor Tm2, ​​and transmitted to the pixel P of the second horizontal line connected to the second data line DL2.

[0152] Furthermore, the pseudo multiplexer MUXp can operate in the opposite way to the multiplexer MUX described above.

[0153] In this respect, the first pseudo MUX control signal CSp1 may have a phase opposite to that of the corresponding first MUX control signal CSm1, and the second pseudo MUX control signal CSp2 may have a phase opposite to that of the corresponding second MUX control signal CSm2.

[0154] Therefore, in each of the first horizontal time period H1 and the second horizontal time period H2, the first pseudo-MUX transistor Tp1 can alternate between being turned on and off in the opposite manner to the corresponding first MUX transistor Tm1.

[0155] In addition, during the first horizontal time period H1 and the second horizontal time period H2, the second pseudo-MUX transistor Tp2 can alternate between being on and off in a manner opposite to that of the second MUX transistor Tm2.

[0156] Thus, since the multiplexer MUX and the pseudo-multiplexer MUXp perform opposite switching operations, the EMI caused by the switching operation of the multiplexer MUX can be eliminated by the opposite switching operation of the pseudo-multiplexer MUXp. As a result, the EMI caused by the multiplexer MUX can be reduced even when using the multiplexer MUX.

[0157] Furthermore, in the above embodiments of this disclosure, the case described as an example is that the multiplexer and the pseudo-multiplexer have the same number of transistors and the MUX control lines and pseudo-MUX control lines are arranged in the same number, but this embodiment is not limited to this. For example, the number of MUX transistors included in the multiplexer and the number of pseudo-MUX transistors included in the pseudo-multiplexer may be different from each other, and / or the number of MUX control lines and the number of pseudo-MUX control lines may be different from each other.

[0158] Furthermore, in the exemplary embodiments described above in this disclosure, a liquid crystal display device equipped with a multiplexer and a pseudo-multiplexer is described as an example.

[0159] However, embodiments of this disclosure can be applied to all types of display devices equipped with multiplexers and pseudo-multiplexers, including liquid crystal displays. For example, embodiments of this disclosure can be applied to light-emitting display devices using organic light-emitting diodes containing organic materials or inorganic light-emitting diodes containing inorganic materials, quantum dot display devices, LED display devices, micro LED display devices, electrophoretic display devices, etc.

[0160] As described above, according to an exemplary embodiment of this disclosure, the multiplexer and the pseudo multiplexer can be arranged on opposite sides of the area in which the MUX control line and the pseudo MUX control line are arranged, and at this time, the MUX control line can be arranged near the multiplexer, and the pseudo MUX control line can be arranged near the pseudo multiplexer.

[0161] Therefore, the signal transmission paths of the MUX control lines connected to the multiplexer and the pseudo MUX control lines connected to the pseudo multiplexer do not overlap, which reduces or minimizes (or prevents) the parasitic capacitance between the MUX control lines and the pseudo MUX control lines.

[0162] Therefore, the RC delay of the multiplexer's control signal caused by parasitic capacitance can be reduced, resulting in normal transmission of the multiplexer's control signal and improvement of the multiplexer's charging system defects.

[0163] Those skilled in the art will understand that various modifications and variations can be made to this disclosure without departing from its spirit or scope. Therefore, this disclosure is intended to cover all modifications and variations thereof, provided that they fall within the scope of the appended claims and their equivalents.

[0164] Cross-references to related applications

[0165] This application claims priority and benefit to Korean Patent Application No. 10-2023-0011087, filed in Korea on January 27, 2023, the entire contents of which are hereby incorporated by reference for all purposes, as if fully set forth herein.

Claims

1. A display device, the display device comprising: The display panel includes an array substrate, in which a display area is defined, wherein pixels are arranged and data lines connected to the pixels are arranged, and a non-display area is adjacent to the display area. A multiplexer is disposed in a first contiguous region of the non-display area and includes K MUX transistors, where K is an integer of 2 or greater, wherein the sources of the K MUX transistors are connected to a common data channel line and the drains of the K MUX transistors are respectively connected to K data lines; A pseudo-multiplexer, disposed in a third consecutive region of the non-display area excluding the first consecutive region, and comprising K pseudo-MUX transistors respectively configured to correspond to the K MUX transistors; and K MUX control lines and K pseudo MUX control lines are arranged in a second continuous region of the non-display area, located between the first and third continuous regions of the non-display area. The K MUX control lines are respectively connected to the gates of the K MUX transistors, and the K pseudo MUX control lines are respectively connected to the gates of the K pseudo MUX transistors. The second continuous region includes a first portion of the region adjacent to the first continuous region and in which the K MUX control lines are arranged, and a second portion of the region adjacent to the third continuous region and in which the K pseudo-MUX control lines are arranged. The MUX transistors and pseudo-MUX transistors corresponding to each other are arranged to face each other, wherein the second continuous region is located between the corresponding MUX transistors and pseudo-MUX transistors.

2. The display device according to claim 1, wherein, The gate contact of the MUX transistor corresponds to the MUX control line and extends in a direction toward the first continuous region.

3. The display device according to claim 1, wherein, The gate contact of the pseudo-MUX transistor corresponds to the pseudo-MUX control line and extends toward the third continuous region.

4. The display device according to claim 1, wherein, The MUX control signal and the pseudo-MUX control signal applied to the MUX control line and the pseudo-MUX control line, which are respectively connected to the MUX transistor and the pseudo-MUX transistor, have opposite phases.

5. The display device according to claim 1, wherein, The source and drain of the pseudo-MUX transistor are short-circuited.

6. The display device according to claim 5, wherein, The source and drain of the pseudo-MUX transistor are connected to a voltage line to which a DC voltage of 0V or lower is applied.

7. The display device according to claim 5, wherein, The source and drain of the pseudo-MUX transistor are connected to a voltage line to which a low selection voltage is applied in the display panel.

8. The display device according to claim 1, wherein, The display panel is a liquid crystal display panel or a light-emitting display panel including light-emitting diodes.

9. The display device according to claim 1, wherein, The first continuous region is closer to the display area than the third continuous region.

10. A display device, the display device comprising: A multiplexer, located in the display panel and connected between a data line and a data channel line; A pseudo-multiplexer, the pseudo-multiplexer being located in the display panel and spaced apart from the multiplexer along a first direction in which the data line extends; as well as A MUX control line and a pseudo-MUX control line are located between the multiplexer and the pseudo-multiplexer. The MUX control line extends along a second direction intersecting the first direction and connects to the multiplexer. The pseudo-MUX control line extends along the second direction and connects to the pseudo-multiplexer. The MUX control line is located between the multiplexer and the pseudo-MUX control line. The multiplexer is disposed in a first continuous area of ​​the non-display area of ​​the display panel, the pseudo-multiplexer is disposed in a third continuous area of ​​the non-display area excluding the first continuous area, and the MUX control line and the pseudo-MUX control line are arranged in a second continuous area of ​​the non-display area located between the first and third continuous areas of the non-display area. The corresponding multiplexers and pseudo multiplexers are arranged to face each other, wherein the second continuous region is located between the corresponding multiplexers and pseudo multiplexers.

11. The display device according to claim 10, wherein, The multiplexer includes K MUX transistors, each connected to K data lines and each connected to K MUX control lines, where K is an integer of 2 or greater. The gate of the MUX transistor is in contact with the corresponding MUX control line and extends in the first direction.

12. The display device according to claim 11, wherein, The gate of the MUX transistor does not overlap with the pseudo-MUX control line.

13. The display device according to claim 10, wherein, The pseudo multiplexer includes K pseudo MUX transistors respectively connected to K pseudo MUX control lines, and The gate of the pseudo-MUX transistor contacts the corresponding pseudo-MUX control line and extends in the first direction.

14. The display device according to claim 13, wherein, The gate of the pseudo-MUX transistor does not overlap with the MUX control line.

15. The display device according to claim 10, wherein, The MUX control signal and the pseudo MUX control signal applied to the corresponding MUX control line and the pseudo MUX control line respectively have opposite phases.

16. The display device according to claim 10, wherein, The input and output terminals of the pseudo-multiplexer are short-circuited.

17. The display device according to claim 16, wherein, The input and output terminals of the pseudo-multiplexer are connected to a voltage line to which a DC voltage of 0V or lower is applied.

18. The display device according to claim 10, wherein, The display panel is a liquid crystal display panel or a light-emitting display panel including light-emitting diodes.

19. The display device according to claim 10, wherein, The pseudo-multiplexer is positioned closer to the external part of the display panel than the multiplexer.

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