Storage unit, storage array, electronic device and data processing method

Abstract

The present application relates to a storage unit, a storage array, an electronic device and a data processing method. The storage unit includes a first transistor and a second transistor. The first transistor is configured as follows: the first end is used to be electrically connected to the first bit line via the first storage device, the second end is used to be electrically connected to the source line, and the control end is used to be electrically connected to the first word line; the second transistor is configured as follows: the first end is used to be electrically connected to the second bit line via the second storage device, the second end is electrically connected to the first end of the first transistor, the control end is used to be electrically connected to the second word line, and the substrate is electrically connected to the substrate of the first transistor and is used to be electrically connected to the write source line. At least it can reduce the area waste caused by the transistor spacing.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a storage unit, a storage array, an electronic device and a data processing method. Background Art

[0002] With the development of data storage technology and the popularization of storage chips in big data, Internet of Things, dedicated hardware, cloud computing and other fields, the market's requirements for storage density and performance of non-volatile memory are constantly increasing. The electrical performance and reliability of the current mainstream flash memory are highly sensitive to device size, and its size is limited by physical laws such as charge discontinuity. Therefore, further improvement of its storage density and performance is limited, making it difficult to meet future non-volatile storage needs.

[0003] Resistive Random Access Memory (RRAM) can switch between high-resistance and low-resistance states according to the voltage difference between two electrodes. It has many advantages such as high storage density, fast erase and write speed, easy miniaturization and integration, and low power consumption. It has become an emerging non-volatile memory with great application prospects.

[0004] However, the storage density of the memory chip using the resistive memory in the related art is mainly limited by the transistor area and the transistor spacing. Since the memory device needs a certain current when performing a write operation, the write current requires the transistor to have a large gate width, which makes it difficult to reduce the transistor area. Summary of the invention

[0005] Based on this, it is necessary to provide a storage unit, a storage array, an electronic device and a data processing method to address the above technical problems.

[0006] In a first aspect, the present application provides a storage unit, which includes a first transistor and a second transistor. The first transistor is configured as follows: the first end is used to be electrically connected to a first bit line via a first storage device, the second end is used to be electrically connected to a source line, and the control end is used to be electrically connected to a first word line; the second transistor is configured as follows: the first end is used to be electrically connected to a second bit line via a second storage device, the second end is electrically connected to a first end of the first transistor, the control end is used to be electrically connected to a second word line, and a substrate is electrically connected to a substrate of the first transistor and is used to be electrically connected to a write source line.

[0007] In some embodiments, the first storage device and the second storage device each have at least two changeable storage states.

[0008] In some of the embodiments, the first memory device is selected from a resistive memory, a phase change memory and a combination thereof.

[0009] In some of the embodiments, the second memory device is selected from a resistive memory, a phase change memory and a combination thereof.

[0010] In some embodiments, the first transistor and the second transistor are both metal-oxide semiconductor field effect transistors.

[0011] In some of these embodiments, the storage unit is configured to:

[0012] During the erase / reset state: providing a write first data signal to the write source line, and connecting the first bit line and the second bit line to the ground terminal, so that the parasitic PN junction in the substrate of the first transistor and the substrate of the second transistor is opened, and the first data is written to the first storage device and the second storage device;

[0013] During the write state: a turn-on voltage is applied to the first word line, the first transistor is turned on, a write second data signal is provided to the first bit line, and the second data is written to the first storage device, and / or a turn-on voltage is applied to the second word line, the second transistor is turned on, a write second data signal is provided to the second bit line, and the second data is written to the second storage device.

[0014] In some of these embodiments, the storage unit is configured to:

[0015] During the read state: applying a turn-on voltage to the first word line, turning on the first transistor, and reading data stored in the first memory device via the first bit line; and / or

[0016] A turn-on voltage is applied to the second word line to turn on the second transistor, and data stored in the second storage device is read through the second bit line.

[0017] In a second aspect, the present application further provides a memory array, comprising a plurality of memory areas arranged in rows and columns; the memory areas comprise a plurality of memory cells as described in any of the foregoing embodiments; the memory cells in the memory areas are configured as follows: substrates are all electrically connected to the same common write source line, first bit lines of memory cells in the same row are all connected to the same first common bit line, second bit lines of memory cells in the same row are all connected to the same second common bit line, first bit lines of memory cells in different rows are all connected to different first common bit lines, second bit lines of memory cells in different rows are all connected to different second common bit lines, first common bit lines of memory cells in different rows are insulated from each other, second common bit lines of memory cells in different rows are insulated from each other, and first common bit lines and second common bit lines are insulated from each other; and

[0018] The control ends of the first transistors of the same column of storage cells are all connected to the same first common word line, and the control ends of the first transistors of storage cells in different columns are all connected to different first common word lines; the control ends of the second transistors of the same column of storage cells are all connected to the same second common word line, and the control ends of the second transistors of storage cells in different columns are all connected to different second common word lines; the first common word lines of storage cells in different columns are insulated from each other, the second common word lines of storage cells in different columns are insulated from each other, and the first common word line and the second common word line are insulated from each other.

[0019] In a third aspect, the present application further provides an electronic device, comprising: a storage unit in any of the aforementioned embodiments; or

[0020] A storage array in any of the foregoing embodiments.

[0021] In a fourth aspect, the present application further provides a data processing method for processing data on a storage unit in any of the foregoing embodiments; the data processing method comprises at least one of the following steps:

[0022] During the erase / reset state: providing a write first data signal to the write source line, and connecting the first bit line and the second bit line to the ground terminal, so that the parasitic PN junction in the substrate of the first transistor and the substrate of the second transistor is opened, and the first data is written to the first storage device and the second storage device;

[0023] During the write state: applying a start voltage to the first word line, turning on the first transistor, providing a write second data signal to the first bit line, and writing second data to the first storage device, and / or applying a start voltage to the second word line, turning on the second transistor, providing a write second data signal to the second bit line, and writing second data to the second storage device;

[0024] During the read state: applying an enable voltage to the first word line, turning on the first transistor, and reading data stored in the first storage device via the first bit line, and / or applying an enable voltage to the second word line, turning on the second transistor, and reading data stored in the second storage device via the second bit line.

[0025] In a fifth aspect, the present application further provides a data processing method for processing data on the storage array described in any of the above embodiments; the data processing method comprises at least one of the following steps:

[0026] During the erase / reset state: providing a write first data signal to the common write source line of the selected storage area, and connecting the first common bit line and the second common bit line to the ground terminal, so that the parasitic PN junction in the substrate of the first transistor and the substrate of the second transistor in the selected storage area is opened, and the first data is written to the first storage device and the second storage device in the selected storage area;

[0027] During the write state: applying a start voltage to the first common word line of the selected storage area, turning on the first transistor of the selected storage area, providing a write second data signal to the first common bit line of the selected storage area, and writing the second data to the first storage device of the selected storage area; and / or applying a start voltage to the second common word line of the selected storage area, turning on the second transistor of the selected storage area, providing a write second data signal to the second common bit line of the selected storage area, and writing the second data to the second storage device of the selected storage area;

[0028] During the read state: a turn-on voltage is applied to the first common word line of the selected storage area, the first transistor of the selected storage area is turned on, and the data stored in the first storage device is read via the first common bit line of the selected storage area; and / or, a turn-on voltage is applied to the second common word line of the selected storage area, the second transistor of the selected storage area is turned on, and the data stored in the second storage device is read via the second common bit line of the selected storage area.

[0029] The memory cell, memory array, electronic device and data processing method in the above-mentioned embodiments complete part of the write operation of the resistive memory cell through an independent substrate-leading transistor parasitic PN junction, thereby reducing the area of ​​the transistor, and reduce the area waste caused by the transistor spacing by adopting a cell design in which transistors are connected in series, thereby effectively improving the storage density of the memory array. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings constituting a part of this application are used to provide a further understanding of the present invention. The illustrative embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 is a schematic diagram of a circuit principle of a storage unit in some embodiments;

[0033] Figure 2 is a schematic diagram of a circuit principle of a storage array in some embodiments;

[0034] Figure 3 A schematic diagram of a circuit principle for reading data from some storage cells in a storage array in some embodiments;

[0035] Figure 4 A schematic diagram of a circuit principle for erasing data in some storage cells in a storage array in some embodiments;

[0036] Figure 5 A schematic diagram of a circuit principle for writing data to some storage cells in a storage array in some embodiments;

[0037] Figure 6 A schematic diagram of a circuit principle for writing data to some storage cells in a storage array in some other embodiments;

[0038] Figure 7 It is a schematic diagram of the circuit principle of a storage array in the related art.

[0039] Reference numerals and descriptions:

[0040] N1, a first transistor; N2, a second transistor; R1, a first storage device; R2, a second storage device; BL1, a first bit line; BL2, a second bit line; SL, a source line; WSL, a write source line; WL1, a first word line; WL2, a second word line; CWSL1 / CWSL2, a common write source line; CSL1 / CSL2, a common source line; CBL11, a first common bit line; CBL12, a second common bit line; CWL11 / CWL21, a first word line; CWL12 / CWL22, a second word line; 300, a storage area; 301 / 302 / 101, a storage unit; 102, a spacing structure. DETAILED DESCRIPTION

[0041] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0042] While some exemplary embodiments of the present invention have been described for the purpose of illustration, it should be understood that the present invention may be implemented in other ways not specifically shown in the drawings.

[0043] Please refer to Figure 1In some embodiments, a storage unit is provided, which includes a first transistor N1 and a second transistor N2. The first transistor N1 is configured as follows: a first end is used to be electrically connected to a first bit line BL1 via a first storage device R1, a second end is used to be electrically connected to a source line SL, and a control end is used to be electrically connected to a first word line WL1; the second transistor N2 is configured as follows: a first end is used to be electrically connected to a second bit line BL2 via a second storage device R2, a second end is electrically connected to a first end of the first transistor N1, a control end is used to be electrically connected to a second word line WL2, a substrate is electrically connected to a substrate of the first transistor N1 and is used to be electrically connected to a write source line SL.

[0044] For example, please continue to refer to Figure 1 , the first storage device R1 and the second storage device R2 each have at least two variable storage states. For example, the first storage device R1 and the second storage device R2 each have a first state for writing the first data "0", a second state for writing the second data "1", a third state for reading the first data "0", and a fourth state for reading the second data "1". Of course, in other embodiments of the present application, the data written or read in the first storage device R1 and the second storage device R2 may be other third data different from "0" and "1". For example, the data stored in the first storage device R1 can be judged based on the size of the current read out by the first storage device R1 via the first bit line BL1, and the data stored in the second storage device R2 can be judged based on the size of the current read out by the second storage device R2 via the second bit line BL2.

[0045] For example, the first storage device R1 is selected from resistive random access memory (RRAM), phase change random access memory (PRAM), etc., and combinations thereof. The second storage device R2 is selected from resistive random access memory (RRAM), phase change random access memory (PRAM), etc., and combinations thereof.

[0046] For example, the first transistor N1 and the second transistor N2 are both metal-oxide semiconductor field effect transistors. For example, the first transistor N1 and the second transistor N2 can be advanced process node MOSFETs.

[0047] The specific implementation principle of the embodiment of the present application is illustrated below by taking the case where the first transistor N1 and the second transistor N2 are MOSFETs, and the first storage device R1 and the second storage device R2 are resistive memory.

[0048] Please continue to refer to Figure 1 In some embodiments, the storage unit is configured to perform at least one of the following steps:

[0049] Step S110: During the erase / reset state: provide a write first data signal to the write source line SL, and connect the first bit line BL1 and the second bit line BL2 to the ground, so that the parasitic PN junction in the substrate of the first transistor N1 and the substrate of the second transistor N2 is opened, and the first data is written to the first storage device R1 and the second storage device R2.

[0050] For example, in step S110, a write-0 voltage is applied to the write source line WSL corresponding to the storage unit where the storage device to be written is located, the corresponding two bit lines are grounded GND, the remaining bit lines are applied with a write-0 voltage, and other ports not mentioned are connected to GND, so that the parasitic PN junctions of the first transistor N1 and the second transistor N2 in the storage unit corresponding to the write source line WSL are opened, and "0" is written to the first storage device R1 and the second storage device R2.

[0051] Step S210: During the write state: applying a turn-on voltage to the first word line WL1, turning on the first transistor N1, providing a write second data signal to the first bit line BL1, writing second data to the first storage device R1, and / or applying a turn-on voltage to the second word line WL2, turning on the second transistor N2, providing a write second data signal to the second bit line BL2, and writing second data to the second storage device R2.

[0052] For example, in step S210, if a "1" operation needs to be performed on a designated storage unit, after "0" is written to the first storage device R1 and the second storage device R2 in step S110, the voltage of the first word line WL1 and the second word line WL2 are controlled to turn on the first transistor N1 and the second transistor N2, and then a write "1" signal is applied to the first bit line BL1 and the second bit line BL2 of the storage unit, so that "1" is written to the first storage device R1 and the second storage device R2. The bit lines corresponding to the storage devices that do not need to write "1" are grounded GND, and the other ports not mentioned are connected to GND.

[0053] For example, since the first transistor N1 is individually controlled via the first word line WL1 and the first bit line BL1, and the second transistor N2 is individually controlled via the second word line WL2 and the second bit line BL2, the first transistor N1 and the second transistor N2 can be controlled one by one to write different data to the first storage device R1 and the second storage device R2 respectively; the first transistor N1 and the second transistor N2 can also be controlled at the same time to write the same data to the first storage device R1 and the second storage device R2.

[0054] Step S310: During the read state: applying a turn-on voltage to the first word line WL1, turning on the first transistor N1, and reading the data stored in the first storage device R1 via the first bit line BL1; and / or, applying a turn-on voltage to the second word line WL2, turning on the second transistor N2, and reading the data stored in the second storage device R2 via the second bit line BL2.

[0055] For example, in step S310, when a read operation is required on a designated memory cell, the first transistor N1 and the second transistor N2 of the memory cell to be read can be turned on by first controlling the voltage of the first word line WL1 and the second word line WL2, and then a read voltage signal is applied to the first bit line BL1 and the second bit line BL2 of the memory cell, and the resistance state of the first memory device R1 is read by reading the current of the first bit line BL1, and the resistance state of the second memory device R2 is read by reading the current of the second bit line BL2.

[0056] For example, since the first transistor N1 is individually controlled via the first word line WL1 and the first bit line BL1, and the second transistor N2 is individually controlled via the second word line WL2 and the second bit line BL2, the first transistor N1 and the second transistor N2 can be controlled one by one, and different data can be read out via the first storage device R1 and the second storage device R2, respectively; the first transistor N1 and the second transistor N2 can also be controlled at the same time, and the same data can be read out via the first storage device R1 and the second storage device R2.

[0057] In some embodiments, a memory array is provided, comprising a plurality of memory areas arranged in rows and columns; the memory areas comprise a plurality of memory cells as described in any of the foregoing embodiments; the memory cells in the memory areas are configured as follows: substrates are all electrically connected to the same common write source line, first bit lines of memory cells in the same row are all connected to the same first common bit line, second bit lines of memory cells in the same row are all connected to the same second common bit line, first bit lines of memory cells in different rows are all connected to different first common bit lines, second bit lines of memory cells in different rows are all connected to different second common bit lines, first common bit lines of memory cells in different rows are insulated from each other, second common bit lines of memory cells in different rows are insulated from each other, and first common bit lines and second common bit lines are insulated from each other; and

[0058] The control ends of the first transistors of the same column of storage cells are all connected to the same first common word line, and the control ends of the first transistors of storage cells in different columns are all connected to different first common word lines; the control ends of the second transistors of the same column of storage cells are all connected to the same second common word line, and the control ends of the second transistors of storage cells in different columns are all connected to different second common word lines; the first common word lines of storage cells in different columns are insulated from each other, the second common word lines of storage cells in different columns are insulated from each other, and the first common word line and the second common word line are insulated from each other.

[0059] As an example, see Figure 2 A memory array includes a plurality of memory areas 300 arranged in rows and columns, each memory area 300 includes a plurality of memory cells arranged in rows and columns, and the memory cells in a memory area 300 are configured as follows: substrates are electrically connected to the same common write source line CWSL1, first bit lines of memory cells in the same row are connected to the same first common bit line CBL11, and first bit lines of memory cells in different rows are connected to different first common bit lines CBL11; second bit lines of memory cells in the same row are connected to a second common bit line CBL12, and second bit lines of memory cells in different rows are connected to different second common bit lines CBL12; first common bit lines CBL11 of memory cells in different rows are insulated from each other, and second common bit lines CBL12 of memory cells in different rows are insulated from each other; first common bit lines CBL11 and second common bit lines CBL12 are connected to each other. CBL12 are insulated from each other; the control ends of the first transistors of the same column of storage cells are all connected to the same first common word line CWL11, and the control ends of the first transistors of storage cells in different columns are all connected to different first common word lines CWL11; the control ends of the second transistors of the same column of storage cells are all connected to the same second common word line CWL12, and the control ends of the second transistors of storage cells in different columns are all connected to different second common word lines CWL12; the first common word lines CWL11 of storage cells in different columns are insulated from each other, the second common word lines CWL12 of storage cells in different columns are insulated from each other, and the first common word line CWL11 and the second common word line CWL12 are insulated from each other; the storage cells in different storage areas 300 are connected to different common write source lines, and the common write source lines of different storage areas 300 are insulated from each other.

[0060] It should be noted that although Figure 2 The storage area 300 includes 4 storage units in the example, but this does not constitute a limitation on the number of storage units included in the storage area 300. In some other embodiments, the number of storage units included in the storage area 300 may be 2K, where K is a positive integer.

[0061] Read as follows Figure 3 Taking the data stored in the storage unit 301 in a storage area 300 as an example, the implementation principle of the data reading method in the embodiment of the present application is illustrated.

[0062] Please refer to Figure 3, the selected storage cell 301 in the storage area 300 is configured as follows: the common write source line CWSL1 is grounded GND, the first common word line CWL11 and the second common word line CWL12 are both connected to the DC voltage VDD, the read voltage Vread is provided to the first common bit line CBL11 and the second common bit line CBL12, and the remaining ports are connected to GND, the resistance state of the first storage device R1 in the storage cell 301 can be read via the first common bit line CBL11, and the resistance state of the second storage device R2 in the storage cell 301 can be read via the second common word line CWL12.

[0063] Please refer to Figure 4-Figure 5 , if it is necessary to write 0100 to the selected storage unit 301 and the selected storage unit 302 in the storage area 300, it is necessary to write "0" to the first storage device R1 in the selected storage unit 301, write "1" to the second storage device R2 in the selected storage unit 301, write "0" to the first storage device R1 in the selected storage unit 302, and write "0" to the second storage device R2 in the selected storage unit 301, then the following steps can be performed:

[0064] Step S101': During the erase / reset state, a write first data signal Vwrite0 is provided to the common write source line CWSL1 of the selected storage area 300, and the first common bit line CBL11 and the second common bit line CBL12 are connected to the ground terminal GND, so that the parasitic PN junction in the substrate of the first transistor N1 and the substrate of the second transistor N2 of the selected storage cell 301 and the selected storage cell 302 is opened, so as to write "0" to the first storage device R1 and the second storage device R2 in the selected storage cell 301 and the selected storage cell 302.

[0065] Step S201': After step S101', a start-up voltage VDD can be applied to the second common word line CWL12 of the selected storage cell 301 to turn on the second transistor N2 of the selected storage cell 301, and a write "1" signal Vwrite1 can be applied to the second common word line CWL12 of the selected storage cell 301 to write "1" to the second storage device R2 of the selected storage cell 301. At this time, 0100 is written to the selected storage cell 301 and the selected storage cell 302.

[0066] Please refer to Figure 6 After step S101', a start-up voltage VDD can be applied to the first common word line CWL11 of the selected storage cell 302, turning on the first transistor N1 of the selected storage cell 302, applying a write "1" signal Vwrite1 to the first common bit line CBL11 of the selected storage cell 302, and writing "1" to the first storage device R1 of the selected storage cell 302. At this time, 0001 is written to the selected storage cell 301 and the selected storage cell 302.

[0067] Since each storage device in the embodiment of the present application can be individually controlled via its own independent word line and bit line, the storage array can be controlled to write arbitrary data.

[0068] Please refer to Figure 7 The transistor in the memory cell 101 is used as a gate transistor. When the transistor is turned on, the memory device can be selected for operation; when it is turned off, the unit is not conducting and the memory device cannot be operated. The memory device N1 or the memory device N2 requires a certain current when performing a write operation. This current requires the transistor to have a large gate width, making it difficult to reduce the transistor area. As a result, the volume of the memory cell is relatively large, reducing the storage density of the new memory. In addition, there is a spacing structure 102 between two adjacent columns of memory cells 101, which restricts the further reduction of the memory cell area.

[0069] In the memory cell or memory array provided in the aforementioned embodiment of the present application, a partial write operation of the resistive memory cell is completed by an independent substrate-lead transistor parasitic PN junction, thereby reducing the area of ​​the transistor, and by adopting a cell design in which transistors are connected in series, the area waste caused by the transistor spacing is reduced, thereby effectively improving the storage density of the memory array.

[0070] In some embodiments, the present application also provides an electronic device, comprising the storage unit described in any of the aforementioned embodiments.

[0071] In some embodiments, the present application also provides an electronic device, comprising the storage array described in any of the aforementioned embodiments.

[0072] Based on the same inventive concept, the embodiment of the present application also provides a method for implementing the above-mentioned data processing method. The implementation scheme for solving the problem provided by the method is similar to the implementation scheme recorded in the above-mentioned storage unit or storage array, so the specific limitations in one or more data processing method embodiments provided below can refer to the above-mentioned limitations on the storage unit or storage array, and will not be repeated here.

[0073] In some embodiments, the present application further provides a data processing method for processing data on the storage unit described in any of the above embodiments; the data processing method comprises at least one of the following steps:

[0074] Step S110: During the erase / reset state: providing a write first data signal to the write source line, and connecting the first bit line and the second bit line to the ground terminal, so that the parasitic PN junction in the substrate of the first transistor and the substrate of the second transistor is opened, and the first data is written to the first storage device and the second storage device;

[0075] Step S210: during the write state: applying a start voltage to the first word line, turning on the first transistor, providing a write second data signal to the first bit line, and writing the second data to the first storage device, and / or applying a start voltage to the second word line, turning on the second transistor, providing a write second data signal to the second bit line, and writing the second data to the second storage device;

[0076] Step S310: During the read state: applying a turn-on voltage to the first word line, turning on the first transistor, and reading data stored in the first storage device via the first bit line, and / or applying a turn-on voltage to the second word line, turning on the second transistor, and reading data stored in the second storage device via the second bit line.

[0077] In some embodiments, the present application further provides a data processing method for processing data on the storage array described in any of the above embodiments; the data processing method comprises at least one of the following steps:

[0078] Step S100: During the erase / reset state: providing a write first data signal to the common write source line of the selected storage area, and connecting the first common bit line and the second common bit line to the ground terminal, so that the parasitic PN junction in the substrate of the first transistor and the substrate of the second transistor in the selected storage area is opened, and the first data is written to the first storage device and the second storage device in the selected storage area;

[0079] Step S200: During the write state: applying a start voltage to the first common word line of the selected storage area, turning on the first transistor of the selected storage area, providing a write second data signal to the first common bit line of the selected storage area, and writing the second data to the first storage device of the selected storage area; and / or, applying a start voltage to the second common word line of the selected storage area, turning on the second transistor of the selected storage area, providing a write second data signal to the second common bit line of the selected storage area, and writing the second data to the second storage device of the selected storage area;

[0080] Step S300: During the read state: applying a turn-on voltage to the first common word line of the selected storage area, turning on the first transistor of the selected storage area, and reading the data stored in the first storage device via the first common bit line of the selected storage area; and / or, applying a turn-on voltage to the second common word line of the selected storage area, turning on the second transistor of the selected storage area, and reading the data stored in the second storage device via the second common bit line of the selected storage area.

[0081] The above data processing method completes part of the write operation of the resistive memory cell through an independent substrate-leading transistor parasitic PN junction, thereby reducing the area of ​​the transistor, and reduces the area waste caused by the transistor spacing by adopting a cell design in which transistors are connected in series, thereby effectively improving the storage density of the memory array.

[0082] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0083] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnet resistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0084] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0085] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A storage unit, characterized in that: include: A first transistor is configured such that: a first terminal is used to be electrically connected to a first bit line via a first storage device, a second terminal is used to be electrically connected to a source line, and a control terminal is used to be electrically connected to a first word line; The second transistor is configured as follows: the first end is used to be electrically connected to the second bit line via the second storage device, the second end is electrically connected to the first end of the first transistor, the control end is used to be electrically connected to the second word line, and the substrate is electrically connected to the substrate of the first transistor and is used to be electrically connected to the write source line.

2. The storage unit according to claim 1, characterized in that The first storage device and the second storage device each have at least two changeable storage states.

3. The storage unit according to claim 2, characterized in that The first memory device is selected from a resistive memory, a phase change memory and a combination thereof; and / or The second memory device is selected from a resistive memory, a phase change memory and a combination thereof.

4. The storage unit according to claim 1, characterized in that The first transistor and the second transistor are both metal-oxide semiconductor field effect transistors.

5. The storage unit according to any one of claims 1 to 4, characterized in that: is configured as: During the erase / reset state: providing a write first data signal to the write source line, and connecting the first bit line and the second bit line to the ground terminal, so that the parasitic PN junction in the substrate of the first transistor and the substrate of the second transistor is opened, and writing the first data to the first storage device and the second storage device; During a write state: applying a start voltage to the first word line to turn on the first transistor, providing a write second data signal to the first bit line, and writing second data to the first storage device; and / or An on voltage is applied to the second word line to turn on the second transistor, a write second data signal is provided to the second bit line, and second data is written to the second storage device.

6. The storage unit according to any one of claims 1 to 4, characterized in that: is configured as: During a read state: applying a turn-on voltage to the first word line to turn on the first transistor, and reading data stored in the first memory device via the first bit line; and / or An on voltage is applied to the second word line to turn on the second transistor, and data stored in the second storage device is read through the second bit line.

7. A storage array, characterized in that: comprising a plurality of storage areas arranged in rows and columns; The storage area comprises a plurality of storage units according to any one of claims 1 to 6; The memory cells of the memory area are configured as follows: the substrates are all electrically connected to the same common write source line, the first bit lines of the memory cells in the same row are all connected to the same first common bit line, the second bit lines of the memory cells in the same row are all connected to the same second common bit line, the first bit lines of the memory cells in different rows are all connected to different first common bit lines, and the second bit lines of the memory cells in different rows are all connected to different second common bit lines; and The control ends of the first transistors of the same column of memory cells are all connected to the same first common word line, and the control ends of the first transistors of different columns of memory cells are all connected to different first common word lines; the control ends of the second transistors of the same column of memory cells are all connected to the same second common word line, and the control ends of the second transistors of different columns of memory cells are all connected to different second common word lines; Memory cells in different memory areas are connected to different common write source lines.

8. An electronic device, characterized in that: include: The storage unit according to any one of claims 1 to 6; or The storage array as claimed in claim 7.

9. A data processing method, characterized in that: Used to process data on the storage unit according to any one of claims 1 to 6; the data processing method comprises at least one of the following steps: During the erase / reset state: providing a write first data signal to the write source line, and connecting the first bit line and the second bit line to the ground terminal, so that the parasitic PN junction in the substrate of the first transistor and the substrate of the second transistor is opened, and writing the first data to the first storage device and the second storage device; During the write state: applying a start voltage to the first word line, turning on the first transistor, providing a write second data signal to the first bit line, and writing second data to the first storage device, and / or applying a start voltage to the second word line, turning on the second transistor, providing a write second data signal to the second bit line, and writing second data to the second storage device; During the read state: applying an enable voltage to the first word line, turning on the first transistor, and reading data stored in the first storage device via the first bit line, and / or applying an enable voltage to the second word line, turning on the second transistor, and reading data stored in the second storage device via the second bit line.

10. A data processing method, characterized in that: Used to process data on the storage array according to claim 7; the data processing method comprises at least one of the following steps: During the erase / reset state: providing a write first data signal to a common write source line of a selected storage area, and connecting the first common bit line and the second common bit line to the ground terminal, so that the parasitic PN junction in the substrate of the first transistor and the substrate of the second transistor of the selected storage area is opened, and the first data is written to the first storage device and the second storage device of the selected storage area; During the write state: applying a start voltage to the first common word line of the selected storage area, turning on the first transistor of the selected storage area, providing a write second data signal to the first common bit line of the selected storage area, and writing second data to the first storage device of the selected storage area; and / or applying a start voltage to the second common word line of the selected storage area, turning on the second transistor of the selected storage area, providing a write second data signal to the second common bit line of the selected storage area, and writing second data to the second storage device of the selected storage area; During the read state: applying a turn-on voltage to the first common word line of the selected storage area, turning on the first transistor of the selected storage area, and reading the data stored in the first storage device via the first common bit line of the selected storage area; and / or applying a turn-on voltage to the second common word line of the selected storage area, turning on the second transistor of the selected storage area, and reading the data stored in the second storage device via the second common bit line of the selected storage area.

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