An integrated circuit fuse trim array test apparatus and method

Abstract

The application relates to the technical field of integrated circuit testing, and particularly discloses an integrated circuit fuse trimming array testing device and a testing method, the testing device comprising a testing machine and a probe station, a DUT board is arranged on the testing machine, a probe card and a wafer to be tested are arranged on the probe station, the DUT board is connected with the probe card through a wire, the probe card is connected with the wafer to be tested through a probe, and the probe card comprises a fuse trimming array; wherein the testing machine leads corresponding testing resources to the DUT board according to trimming requirements of the wafer to be tested, and the DUT board leads the corresponding testing resources to the probe card, so that the fuse trimming array can simultaneously trim and test multiple chips in the wafer to be tested according to the corresponding testing resources. The integrated circuit fuse trimming array testing device provided by the application can reduce the design difficulty of a PCB board, improve work efficiency, and reduce the operation cost of a company.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit testing technology, and more particularly, to an integrated circuit fuse trimming array testing device and an integrated circuit fuse trimming array testing method. BACKGROUND

[0002] When a power management type integrated circuit chip is manufactured, a chip design company provides a chip testing company with a chip manual, and adjusts multiple parameters of the chip, and the adjustment is achieved by burning out target fuses.

[0003] According to the chip manual of the design company, there are many fuse bits (at present, the maximum number of fuse bits of a single chip has reached 30), and most of the development is performed in parallel. The factors of many fuse bits and parallel testing of multiple sites increase the difficulty of PCB design, but the circuits of the fuse trimming part are similar, and currently, two methods are generally used, that is, a certain voltage is directly applied to the fuse pad by using the power supply of the test system to burn out the fuse, or the fuse is burned out by charging a capacitor first and then discharging the capacitor. Therefore, the fuse trimming array is designed by summarizing the principle of fuse trimming and the periphery.

[0004] In the traditional fuse trimming technology, special DUT boards, probe cards and other hardware are designed according to specific chip specifications, and the fuse trimming module is designed on the DUT board. The disadvantage of this method is that a special DUT board, probe card and other hardware need to be designed for each chip, which leads to complicated PCB drawing and easy errors. SUMMARY

[0005] The present application aims to at least solve one of the technical problems existing in the prior art, and provides an integrated circuit fuse trimming array testing device and method to solve the problems of complicated, difficult and error-prone PCB drawing in the related art.

[0006] As a first aspect of the present application, an integrated circuit fuse trimming array testing device is provided, which comprises a test machine and a probe station, the test machine is provided with a DUT board, the probe station is provided with a probe card and a wafer to be tested, the DUT board is connected with the probe card through a wire, the probe card is connected with the wafer to be tested through a probe, and the probe card comprises a fuse trimming array.

[0007] The test machine introduces corresponding test resources to the DUT board according to the trimming requirements of the wafer to be tested, the DUT board introduces the corresponding test resources to the probe card, so that the fuse trimming array can simultaneously trim and test multiple chips in the wafer to be tested according to the corresponding test resources.

[0008] Further, the fuse trimming array comprises a relay and a plurality of first switches ksite1-ksiten, each of the first switches being connected to a chip in the DUT wafer through a plurality of second switches k1-kn, and the tester controls the relay so that the relay can control the plurality of first switches to select a chip in the DUT wafer for trimming test or a plurality of chips for simultaneous trimming test.

[0009] Each of the first switches is connected to a plurality of second switches k1-kn, each of the second switches is connected to a piece of fuse, and the plurality of pieces of fuse connected to the first switch are connected to the fuse pad of a chip through a probe. When the fuse trimming array performs trimming test on each chip in the DUT wafer, the relay controls the plurality of second switches k1-kn connected to each first switch to select a piece of fuse or a plurality of pieces of fuse to be blown, thereby realizing trimming test on the chip connected to the first switch.

[0010] Further, the fuse trimming array performs trimming test on the chip in the DUT wafer by blowing the fuse in the power supply, the capacitor or the MOS tube.

[0011] Further, the DUT board is plugged into the tester through a connector to draw out the test resources of the tester, the test resources being used for pressure, current and test feedback. The fuse trimming array is plugged into the probe card through a connector. The flat cable is connected to the DUT board and the probe card through connectors, so that the test resources on the DUT board are connected to the fuse trimming array on the probe card.

[0012] Further, the DUT board and the fuse trimming array are universal, and the probe card is customized according to the specific information of the chip in the DUT wafer.

[0013] Further, the chip in the DUT wafer is a power management analog integrated circuit chip, and the tester performs trimming test on a plurality of parameters of the chip by blowing the fuse according to the chip specification file.

[0014] Further, the probe card further comprises other test peripheral circuits for testing other parameters of the chip in the DUT wafer.

[0015] As another aspect of the present application, an integrated circuit fuse trimming array test method is provided, which is realized by the integrated circuit fuse trimming array test device described above. The integrated circuit fuse trimming array test method comprises the following steps:

[0016] The corresponding test resource is led out to the DUT board by the tester according to the adjustment requirement of the wafer to be tested;

[0017] The corresponding test resource is led out to the probe card by the DUT board;

[0018] When the wafer to be tested needs to be tested, the test resource on the fuse adjustment array is directly called, the target segment fuse on the fuse adjustment array is burned out, and the multiple chips in the wafer to be tested are simultaneously adjusted and tested.

[0019] The integrated circuit fuse adjustment array test device provided by the application has the following advantages: the circuit of the fuse adjustment part is solidified by the way of directly burning the fuse by the power supply of the tester, the fuse adjustment array is designed to be universal, at the same time, the universal DUT board for chip testing is designed, the special probe card is designed according to the chip specification manual, the single-chip multi-segment fuse adjustment test is realized, and the number of test sites reaches the multi-site simultaneous adjustment test. The design difficulty of the PCB board is reduced, the work efficiency is improved, and the operation cost of the company is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings are used to provide a further understanding of the application, and constitute a part of the specification, and are used to explain the application together with the specific embodiments below, but do not constitute a limitation on the application.

[0021] Figure 1 The structure diagram of the integrated circuit fuse adjustment array test device of the embodiment of the application.

[0022] Figure 2 The principle diagram of the fuse adjustment array of the embodiment of the application.

[0023] Figure 3 The circuit diagram of the fuse adjustment array of the embodiment of the application.

[0024] Figure 4 The structure diagram of the wafer to be tested of the embodiment of the application.

[0025] Figure 5 The fuse pad schematic diagram of the wafer chip inside the embodiment of the application. DETAILED DESCRIPTION

[0026] For further illustrating the technical means and effects taken by the present application to achieve the predetermined inventive objectives, the specific implementation, structure, features and effects of the integrated circuit fuse trimming array testing device according to the present application are described in detail below in combination with the drawings and preferred embodiments. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present application.

[0027] It should be noted that the terms "first", "second", and the like in the description and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0028] In the present embodiment, an integrated circuit fuse trimming array testing device is provided, Figure 1 The structural diagram of the integrated circuit fuse trimming array testing device according to the embodiment of the present application is shown in Figure 1 The integrated circuit fuse trimming array testing device comprises a tester and a probe station, the tester is provided with a DUT board, the probe station is provided with a probe card and a wafer to be tested, as shown in Figure 4 The wafer to be tested comprises a plurality of chips, Figure 4 Each block is a chip; the DUT board is connected with the probe card through a cable, the probe card is connected with the wafer to be tested through a probe, and the probe card comprises a fuse trimming array.

[0029] The tester introduces corresponding test resources to the DUT board according to the trimming requirements of the wafer to be tested, the DUT board introduces the corresponding test resources to the probe card, so that the fuse trimming array can simultaneously trim and test the plurality of chips in the wafer to be tested according to the corresponding test resources.

[0030] Preferably, as Figure 2As shown, the fuse trimming array includes a relay and a plurality of first switches ksite1-ksiten, each of the first switches being connected to a chip in the wafer to be tested through a plurality of second switches k1-kn, and the tester controls the relay so that the relay can control the plurality of first switches to select a chip in the wafer to be tested for trimming test or a plurality of chips for trimming test at the same time; wherein each of the first switches is connected to a plurality of second switches k1-kn, each of the second switches is connected to a piece of fuse, and the plurality of pieces of fuse connected to each of the first switches are connected to a fuse pad of a chip through a probe (for example Figure 5 As shown, T0-T17 are fuse pads), when the fuse trimming array performs trimming test on each chip in the wafer to be tested, the relay controls the plurality of second switches k1-kn connected to each of the first switches to select a piece of fuse or a plurality of pieces of fuse to be burned out, thereby realizing trimming test on the chip connected to the first switch.

[0031] For example, as shown in Figure 3 As shown, a fuse trimming array (two fuse trimming arrays) can support two sites (i.e. two chips for parallel test), and more sites for parallel test can be realized by increasing the number of fuse trimming arrays. Figure 3 In the middle, T0a-T24a correspond to 25 pieces of fuse of one site, and T0b-T24b correspond to 25 pieces of fuse of another site, 25 pieces of fuse in one fuse trimming array are connected to a fuse pad of a chip, which can directly support trimming of 25 pieces of fuse and support expansion function, and can realize trimming test of more than 25 pieces of fuse of a single site. In addition, the relay multiplexing mode is used in one fuse trimming array, that is, switch K0B and switch K0C are actually two parts of a double-pole double-throw relay, and other switches are the same.

[0032] It should be noted that some relays are used independently for a single site and are not multiplexed.

[0033] It should be noted that the resources of some testers can also be multiplexed, which can not only be used in the fuse trimming array, but also be used for test of other projects.

[0034] Specifically, the fuse trimming array performs trimming test on the chip in the wafer to be tested by burning out the fuse through power supply, burning out the fuse through capacitor or burning out the fuse through MOS tube.

[0035] Preferably, the DUT board is plugged on the tester through connectors to lead out the test resources of the tester for voltage, current and test feedback; the fuse trimming array is plugged on the probe card through connectors; the flat cables are connected to the DUT board and the probe card through connectors, so that the test resources on the DUT board are connected to the fuse trimming array on the probe card.

[0036] Specifically, the DUT board and the fuse trimming array are universal, and the probe card is customized according to the specific information of the chips of the wafer to be tested.

[0037] Specifically, the chip type in the wafer to be tested is a power management type analog integrated circuit chip, and the tester adjusts and tests various parameters of the chip by burning out fuses according to a chip specification file.

[0038] Specifically, the probe card further comprises other test peripheral circuits for testing other parameters of the chips in the wafer to be tested.

[0039] Specifically, the tester comprises STS8200, etc. The STS8200, etc. test system is a hardware device specially used for testing power management type analog integrated circuit chips.

[0040] It should be noted that the fuse trimming array can support multi-site testing and multi-segment fuse testing for each site.

[0041] It should be noted that the fuse trimming array can be designed in various types and can be combined for application to fuses of different products.

[0042] It should be noted that the DUT board and the fuse trimming array can reduce the time for designing a special PCB for testing various types and small batches of wafers.

[0043] The integrated circuit fuse trimming array test device provided by the application can directly supply fuses with power from a tester, solidify the circuit of the fuse trimming part, and design a universal fuse trimming array. At the same time, a universal DUT board for testing chips is designed. When a chip CP of a wafer to be tested is tested, the CP (chip probe) test is a wafer test, a relay switch on the fuse trimming array is directly controlled by the tester to call test resources on the fuse trimming array, a target fuse is burned out, a special probe card is designed according to a chip specification manual, single-chip multi-segment fuse trimming test is realized, and the number of test sites reaches multi-site trimming test. The device can avoid repeated design of a fuse burning module, reduce the design difficulty of a PCB, improve work efficiency, and reduce the operating cost of a company.

[0044] As another embodiment of the present application, an integrated circuit fuse trimming array test method is provided, which is tested by the integrated circuit fuse trimming array test device described above, and the integrated circuit fuse trimming array test method comprises:

[0045] The corresponding test resource is led out to the DUT board by the tester according to the trimming requirement of the wafer to be tested;

[0046] The corresponding test resource is led out to the probe card by the DUT board;

[0047] When the wafer to be tested needs to be tested, the tester controls the relay to select the fuse trimming path on the fuse trimming array, directly calls the test resource on the fuse trimming array, and burns the target segment fuse on the fuse trimming array to realize the trimming test of multiple chips in the wafer to be tested at the same time.

[0048] The integrated circuit fuse trimming array test method provided by the present application can effectively shorten the drawing time of the PCB board during the CP test design, reduce the difficulty of the PCB board design, facilitate the inspection of possible problems in the PCB drawing, and effectively reduce the error rate of the PCB drawing.

[0049] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as above, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the above disclosed technical content without departing from the scope of the present application, and any simple modification, equivalent change and modification of the above embodiment according to the technical essence of the present application still belong to the scope of the present application.

Claims

1. An integrated circuit fuse trim array test apparatus, comprising: The integrated circuit fuse trimming array test device comprises a test machine and a probe station, the test machine is provided with a DUT board, the probe station is provided with a probe card and a wafer to be tested, the DUT board is connected with the probe card through a cable, the probe card is connected with the wafer to be tested through a probe, and the probe card comprises a fuse trimming array; The test machine introduces corresponding test resources to the DUT board according to the trimming requirements of the wafer to be tested, the DUT board introduces the corresponding test resources to the probe card, and the fuse trimming array can simultaneously trim and test multiple chips in the wafer to be tested according to the corresponding test resources. The fuse trimming array comprises a relay and multiple first switches ksite1-ksiten, each first switch is connected with a chip in the wafer to be tested through multiple second switches k1-kn, and the test machine controls the relay, so that the relay can control the multiple first switches to select a chip in the wafer to be tested for trimming test or multiple chips for trimming test at the same time. Each first switch is connected with multiple second switches k1-kn, each second switch is connected with a piece of fuse, and multiple pieces of fuse connected with each first switch are connected to a fuse pad of a chip through a probe. When the fuse trimming array performs trimming test on each chip in the wafer to be tested, the relay controls multiple second switches k1-kn connected with each first switch to select a piece of fuse or multiple pieces of fuse connected with the first switch, so as to realize trimming test on the chip connected with the first switch.

2. An integrated circuit fuse trim array test apparatus as recited in claim 1, wherein, The fuse trimming array performs trimming test on the chip in the wafer to be tested by burning out the fuse, the capacitor or the MOS tube.

3. The integrated circuit fuse trim array test apparatus of claim 1, wherein, The DUT board is inserted into the test machine through a connector to introduce the test resources of the test machine, the test resources are used for pressurization, current supply and test feedback, the fuse trimming array is inserted into the probe card through a connector, and the cable is connected with the DUT board and the probe card through connectors respectively, so that the test resources on the DUT board are connected with the fuse trimming array on the probe card.

4. The integrated circuit fuse trim array test apparatus of claim 1, wherein, The DUT board and the fuse trimming array are universal, and the probe card is customized according to the specific information of the chip in the wafer to be tested.

5. The integrated circuit fuse trim array test apparatus of claim 1, wherein, The chip in the wafer to be tested is a power management analog integrated circuit chip, and the test machine performs trimming test on multiple parameters of the chip by burning out the fuse according to the chip specification file.

6. The integrated circuit fuse trim array test apparatus of claim 1, wherein, The probe card further comprises other test peripheral circuits, and the other test peripheral circuits are used for testing other parameters of the chip in the wafer to be tested.

7. A method of testing an integrated circuit fuse trim array by the integrated circuit fuse trim array testing apparatus according to any one of claims 1 to 6, characterized by, The integrated circuit fuse trimming array test method comprises the following steps: introducing corresponding test resources to the DUT board through the test machine according to the trimming requirements of the wafer to be tested; introducing the corresponding test resources to the probe card through the DUT board; When the to-be-tested wafer needs to be tested, a test resource on the fuse trimming array is directly called, and a target segment fuse on the fuse trimming array is burned out to realize simultaneous trimming test on multiple chips in the to-be-tested wafer.

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