IGBT device with PMOS structure

Abstract

The present invention discloses an IGBT device with a PMOS structure, comprising a collector, a P+ collector region, a buffer layer and a drift region arranged in sequence from bottom to top, wherein a first floating region, a PMOS region, a second floating region and an NMOS region are formed in sequence in the drift region, wherein a PMOS structure is arranged in the PMOS region, and an NMOS structure is arranged in the NMOS region. The IGBT device with a PMOS structure of the present invention can reduce the EMI noise of the device without causing degradation of the Vcesat parameter.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to an IGBT device with a PMOS structure. Background Art

[0002] refer to Figure 1 As shown, Figure 1 This is an IGBT device structure with a floating p-base region in the prior art, and is an IGBT device proposed based on the need to reduce Vcesat (voltage drop). However, the introduction of the floating p-base region also causes the floating p-base region's potential to rise when the device is turned on due to the injection of holes from the back side, generating a displacement current from the floating p-base region to the G gate A. When the displacement current is large enough, the di / dt of the device will be mainly affected by the rate of change of the floating p-base region's potential and increase, resulting in the device generating a large EMI noise.

[0003] In order to solve the influence of the floating p-base region on the gate, a new structure capable of extracting holes at the floating p-base region during the start-up phase is proposed in the prior art - an IGBT device structure with a hole path, see Figure 2 As shown. When the IGBT device structure with hole path is turned on, due to the reverse bias voltage between the emitter and the N drift region, a large number of holes gather near the virtual gate B, forming an inverted P-type layer. Therefore, the holes in the floating p-base region can enter the emitter through the inverted P-type layer, forming a hole flow path, as shown in Figure 2 As shown by the arrow in . The existence of the hole path in the IGBT device structure reduces the holes stored in the floating p-base region and weakens the charging of the gate A by the displacement current in the floating p-base region. Therefore, the IGBT device structure with a hole path can suppress the EMI noise of the device.

[0004] However, although the proposed IGBT device structure with hole paths can extract holes from the floating P base region during the turn-on phase and reduce EMI noise, a large number of holes are extracted from the emitter during the turn-on phase, and the number of carriers in the N drift region is reduced, that is, the number of carriers participating in the conductivity modulation effect is also reduced, and the Vcesat of the device is therefore increased, resulting in an increase in the static loss of the device.

[0005] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0006] The object of the present invention is to provide an IGBT device with a PMOS structure, which can reduce the EMI noise of the device without causing degradation of the Vcesat parameter.

[0007] In order to achieve the above-mentioned purpose, a specific embodiment of the present invention provides an IGBT device with a PMOS structure, including a collector, a P+ collector region, a buffer layer and a drift region arranged in sequence from bottom to top, and a first floating region, a PMOS region, a second floating region and an NMOS region are formed in sequence in the drift region laterally, wherein a PMOS structure is arranged in the PMOS region, and an NMOS structure is arranged in the NMOS region.

[0008] In one or more embodiments of the present invention, the PMOS structure includes a first virtual gate and a second virtual gate arranged laterally, and a first spacer P-type region, a spacer N-type region and a second spacer P-type region are arranged in sequence from top to bottom between the first virtual gate and the second virtual gate.

[0009] In one or more embodiments of the present invention, the depths of the first virtual gate and the second virtual gate are both greater than the overlapping depths of the first spacer P-type region, the spacer N-type region, and the second spacer P-type region.

[0010] In one or more embodiments of the present invention, the depths of the first virtual gate and the second virtual gate are both greater than the depths of the first floating region and the second floating region.

[0011] In one or more embodiments of the present invention, the depth of the first floating region is equal to the depth of the second floating region.

[0012] In one or more embodiments of the present invention, a depth of the first spacer P-type region is equal to a depth of the first floating region or the second floating region.

[0013] In one or more embodiments of the present invention, the NMOS structure includes a laterally arranged gate, an N+ emitter region and a P+ emitter region, and a P base region and a carrier storage layer are formed below the N+ emitter region and the P+ emitter region.

[0014] In one or more embodiments of the present invention, the depth of the gate is greater than the superposition depth of the N+ emitter region, the P base region and the carrier storage layer.

[0015] In one or more embodiments of the present invention, a depth of the gate is greater than a depth of the second floating region.

[0016] In one or more embodiments of the present invention, both the first floating region and the second floating region are of P type, and both the buffer layer and the drift region are of N type.

[0017] In one or more embodiments of the present invention, an emitter is formed on a surface of the drift region facing away from the buffer layer.

[0018] Compared with the prior art, the IGBT device with a PMOS structure of the present invention reduces the EMI noise of the device while not causing degradation of the Vcesat parameter.

[0019] In the IGBT device with a PMOS structure of the present invention, during the start-up phase when the device is switched from off to on, Vce decreases, but is still maintained at a relatively high level, and the potential difference between the drift region and the virtual gate can fully open the PMOS structure, and holes flow out of the emitter without hindrance, thereby reducing the charging of the gate by the first floating region and the second floating region, and reducing EMI noise. When the device is in a stable on state, the potential difference between the drift region and the virtual gate is small, insufficient to open the PMOS structure, and holes are blocked near the second spaced P-type region of the PMOS structure, and can continue to participate in conductivity modulation, so Vcesat is not degraded due to the existence of the hole path.

[0020] It is understandable that since EMI noise is mainly generated in the start-up phase when the device switches from off to on, and not in the stable on phase of the device, when the device is on, the blocking of the hole path will not affect the improvement of EMI noise by the structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 It is a schematic diagram of an IGBT device structure with a floating p-base region in the prior art;

[0023] Figure 2 It is a schematic diagram of an IGBT device structure with a floating p-base region and a hole path in the prior art;

[0024] Figure 3 A schematic diagram of the structure of an IGBT device with a PMOS structure in one embodiment of the present invention;

[0025] Figure 4 A diagram of the hole path of an IGBT device having a PMOS structure in a turn-on stage according to an embodiment of the present invention;

[0026] Figure 5 FIG. 1 is a diagram illustrating a hole path of an IGBT device having a PMOS structure in a conduction phase according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0028] As mentioned in the background technology, Figure 1 The IGBT device structure with floating p-base shown is an IGBT device proposed based on the need to reduce Vcesat (voltage drop). However, the introduction of floating p-base also causes the floating p-base potential to rise when the device is turned on due to the injection of holes from the back side, generating a displacement current from the floating p-base to the G gate A. When the displacement current is large enough, the di / dt of the device will be mainly affected by the change rate of the floating p-base potential and increase, resulting in a large EMI noise generated by the device.

[0029] In order to solve the influence of the floating p-base region on the gate, a new structure capable of extracting holes at the floating p-base region during the start-up phase is proposed in the prior art - an IGBT device structure with a hole path, see Figure 2 As shown. When the IGBT device structure with hole path is turned on, due to the reverse bias voltage between the emitter and the N drift region, a large number of holes gather near the virtual gate B, forming an inverted P-type layer. Therefore, the holes in the floating p-base region can enter the emitter through the inverted P-type layer, forming a hole flow path, as shown in Figure 2 As shown by the arrow in . The existence of the hole path in the IGBT device structure reduces the holes stored in the floating p-base region and weakens the charging of the gate A by the displacement current in the floating p-base region. Therefore, the IGBT device structure with a hole path can suppress the EMI noise of the device.

[0030] However, although the proposed IGBT device structure with hole paths can extract holes from the floating P base region during the turn-on phase and reduce EMI noise, a large number of holes are extracted from the emitter during the turn-on phase, and the number of carriers in the N drift region is reduced, that is, the number of carriers participating in the conductivity modulation effect is also reduced, and the Vcesat of the device is therefore increased, resulting in an increase in the static loss of the device.

[0031] In order to solve the above technical problems, the present application proposes an IGBT device with a PMOS structure. Through the setting of the PMOS structure, a hole path area is formed together with the first floating area and the second floating area. In the PMOS structure, in the device startup stage, an inversion layer of holes is formed near the virtual gate, and the first floating area, the second floating area and the PMOS structure form a flow path for holes, which reduces the charging of the gate by the displacement current of the first floating area and the second floating area, so that the device has less noise. When the device is in a stable on state, the potential difference between the N drift region and the virtual gate is small, which is not enough to turn on the PMOS structure. The holes are blocked near the second interval P-type region of the PMOS structure and can continue to participate in conductivity modulation. Therefore, Vcesat is not degraded due to the existence of the hole path.

[0032] like Figure 3 As shown, an IGBT device with a PMOS structure in an embodiment of the present invention includes a collector 10, a P+ collector region 20, a buffer layer 30, a drift region 40, and an emitter 50 arranged in sequence from bottom to top. A first floating region 41, a PMOS region 42, a second floating region 43, and an NMOS region 44 are formed in sequence in the drift region 40. Among them, a PMOS structure is arranged in the PMOS region 42. An NMOS structure is arranged in the NMOS region 44.

[0033] The first floating region 41 and the second floating region 43 are both of P type. The buffer layer 30 and the drift region 40 are both of N type. The depth of the first floating region 41 is equal to the depth of the second floating region 43.

[0034] In one embodiment of the present application, the PMOS structure includes a first virtual gate 421 and a second virtual gate 422 which are arranged laterally, and a first spacer P-type region 423, a spacer N-type region 424 and a second spacer P-type region 425 which are located between the first virtual gate 421 and the second virtual gate 422 and are arranged in sequence from top to bottom.

[0035] The depths of the first virtual gate 421 and the second virtual gate 422 are both greater than the superposition depth of the first spacer P-type region 423, the spacer N-type region 424, and the second spacer P-type region 425. The depths of the first virtual gate 421 and the second virtual gate 422 are both greater than the depths of the first floating region 41 and the second floating region 43. The depth of the first spacer P-type region 423 is equal to the depth of the first floating region 41 or the second floating region 43.

[0036] In one embodiment of the present application, the NMOS structure includes a laterally arranged gate 441, an N+ emitter region 442 and a P+ emitter region 443, and a P base region 444 and a carrier storage layer 445 are formed below the N+ emitter region 442 and the P+ emitter region 443.

[0037] The depth of the gate 441 is greater than the superposition depth of the N+ emitter region 442, the P base region 444 and the carrier storage layer 445. The depth of the gate 441 is greater than the depth of the second floating region 43. The superposition depth of the N+ emitter region 442, the P base region 444 and the carrier storage layer 445 is greater than the depth of the second floating region 43. Preferably, the superposition depth of the N+ emitter region 442 and the P base region 444 is equal to the depth of the second floating region 43.

[0038] In the above technical solution, reference Figure 4 As shown, in the start-up phase when the device switches from off to on, Vce decreases but remains at a relatively high level. The potential difference between the drift region 40 and the virtual gate (421 / 422) can fully turn on the PMOS structure, and holes flow out of the emitter 50 without hindrance, thereby reducing the charging of the gate 441 by the first floating region 41 and the second floating region 43 and reducing EMI noise.

[0039] In the above technical solution, reference Figure 5 As shown, when the device is in a stable on-state, the potential difference between the drift region 40 and the virtual gate (421 / 422) is small, which is not enough to turn on the PMOS structure. The holes are blocked near the second spacing P-type region 425 of the PMOS structure and can continue to participate in conductivity modulation. Therefore, Vcesat is not degraded due to the existence of the hole path.

[0040] It is understandable that since EMI noise is mainly generated in the start-up phase when the device switches from off to on, and not in the stable on phase of the device, when the device is on, the blocking of the hole path will not affect the improvement of EMI noise by the structure.

[0041] Compared with the prior art, the IGBT device with a PMOS structure of the present invention reduces the EMI noise of the device while not causing degradation of the Vcesat parameter.

[0042] In the IGBT device with a PMOS structure of the present invention, during the start-up phase when the device is switched from off to on, Vce decreases, but is still maintained at a relatively high level, and the potential difference between the drift region and the virtual gate can fully open the PMOS structure, and holes flow out of the emitter without hindrance, thereby reducing the charging of the gate by the first floating region and the second floating region, and reducing EMI noise. When the device is in a stable on state, the potential difference between the drift region and the virtual gate is small, insufficient to open the PMOS structure, and holes are blocked near the second spaced P-type region of the PMOS structure, and can continue to participate in conductivity modulation, so Vcesat is not degraded due to the existence of the hole path.

[0043] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0044] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. An IGBT device with a PMOS structure, characterized in that: The device comprises a collector, a P+ collector region, a buffer layer and a drift region arranged in sequence from bottom to top, wherein a first floating region, a PMOS region, a second floating region and an NMOS region are formed in sequence in the drift region, wherein a PMOS structure is arranged in the PMOS region, and an NMOS structure is arranged in the NMOS region; The PMOS structure comprises a first virtual gate and a second virtual gate arranged laterally, wherein a first spacer P-type region, a spacer N-type region and a second spacer P-type region are sequentially arranged between the first virtual gate and the second virtual gate from top to bottom; The depths of the first virtual gate and the second virtual gate are both greater than the overlapping depths of the first spacer P-type region, the spacer N-type region and the second spacer P-type region; The depths of the first virtual gate and the second virtual gate are both greater than the depths of the first floating region and the second floating region; The NMOS structure includes a gate, an N+ emitter region and a P+ emitter region which are arranged laterally, and a P base region and a carrier storage layer are formed below the N+ emitter region and the P+ emitter region.

2. The IGBT device with a PMOS structure according to claim 1, characterized in that: The depth of the first floating area is equal to the depth of the second floating area; and / or, A depth of the first spacer P-type region is equal to a depth of the first floating region or the second floating region.

3. The IGBT device with a PMOS structure according to claim 1, characterized in that: The depth of the gate is greater than the overlapping depth of the N+ emitter region, the P base region and the carrier storage layer.

4. The IGBT device with a PMOS structure according to claim 1, characterized in that: The depth of the gate is greater than the depth of the second floating region.

5. The IGBT device with a PMOS structure according to claim 1, characterized in that: The first floating region and the second floating region are both of P type, and the buffer layer and the drift region are both of N type.

6. The IGBT device with a PMOS structure according to claim 1, characterized in that: An emitter is formed on a surface of the drift region facing away from the buffer layer.

Images