LED driver electromagnetic interference mitigation

Abstract

The present disclosure relates to an LED driver electromagnetic interference mitigation. An apparatus includes a digital ramp generator comprising a delay line including one or more delay elements and an oscillator, wherein the digital ramp generator is configured to generate a code based on respective outputs of the one or more delay elements; a digital-to-analog converter coupled to the digital ramp generator, wherein the digital-to-analog converter is configured to generate a reference signal, wherein the reference signal is generated based at least in part on the code; and a driver coupled to the digital-to-analog converter, the driver configured to generate a drive current based at least in part on the reference signal.

Description

[0001] Copyright Notice

[0002] This patent document contains a portion of copyrighted material. The copyright holder does not object to anyone reproducing the patent document or patent disclosure appearing in the Patent and Trademark Office's patent documents or records, but otherwise reserves all copyright rights. Technical Field

[0003] This disclosure generally relates to methods, systems, and apparatus for improving the performance and reliability of circuits including driver circuitry. Background Technology

[0004] In typical optical sensing systems, light-emitting diode (LED) or laser drivers are used to drive external LEDs or laser diodes (e.g., vertical-cavity surface-emitting lasers (VCSELs)). Fast current edge transitions in LED or laser drivers can cause electromagnetic interference (EMI), which can disrupt the operation of photoelectric sensing amplifiers, data acquisition, and other circuitry in the optical sensing system.

[0005] Therefore, methods, systems, and devices for mitigating EMI from LED drivers are provided. Summary of the Invention

[0006] In one aspect, this disclosure relates to an apparatus comprising: a digital ramp generator including a delay line comprising a plurality of delay elements and an oscillator, wherein the plurality of delay elements are configured to time with a clock signal generated by the oscillator, wherein a first delay element of the plurality of delay elements is configured to receive a control signal as input, wherein the oscillator is enabled by the control signal, wherein the digital ramp generator is configured to generate a code based on corresponding outputs of the plurality of delay elements; a digital-to-analog converter (DAC) coupled to the digital ramp generator, wherein the DAC is configured to generate a reference signal at least partially based on the code; and a driver coupled to the DAC, the driver being configured to generate a drive current at least partially based on the reference signal.

[0007] In another aspect, this disclosure relates to a circuit comprising: a plurality of delay elements, each of the plurality of delay elements being timed via a clock signal, wherein a first delay element of the plurality of delay elements is configured to receive a control signal as an input, and wherein a second delay element of the plurality of delay elements is configured to output a delayed control signal, the control signal including a first rising edge, the delayed control signal including a second rising edge, the second rising edge being later than the first rising edge; an oscillator configured to generate the clock signal, wherein the oscillator is configured to generate the clock signal in response to an enable signal; an XOR gate configured to output the enable signal, wherein a first input of the XOR gate is coupled to the control signal, and a second input of the XOR gate is coupled to the delayed control signal, wherein the enable signal is generated by an XOR of the first and second inputs; and a selector coupled to the plurality of delay elements, the selector being configured to provide a code based on the output of the plurality of delay elements.

[0008] In other aspects, this disclosure relates to a system comprising: a controller configured to generate a control signal; and circuitry coupled to the controller, the circuitry including: a plurality of delay elements, each of the plurality of delay elements being timed via a clock signal, wherein a first delay element of the plurality of delay elements is configured to receive the control signal as an input, and wherein a second delay element of the plurality of delay elements is configured to output a delayed control signal, the control signal including a first rising edge, the delayed control signal including a second rising edge later than the first rising edge; an oscillator configured to generate the clock signal, wherein the oscillator is configured to generate the clock signal in response to an enable signal; a selector coupled to the plurality of delay elements, the selector being configured to generate a code based on the outputs of the plurality of delay elements; a digital-to-analog converter (DAC) coupled to the selector, wherein the DAC is configured to generate a reference signal at least partially based on the code; a driver coupled to the circuitry, the driver being configured to generate a drive current at least partially based on the reference signal; and a light-emitting diode coupled to the driver, the light-emitting diode being configured to generate an optical signal based on the drive current. Attached Figure Description

[0009] A further understanding of the nature and advantages of particular embodiments can be achieved by referring to the remainder of the specification and the accompanying drawings, wherein the same element symbols are used to refer to similar components. In some cases, sublabels are associated with element symbols to indicate one of a plurality of similar components. When reference is made to an element symbol without specifying an existing sublabel, it is intended to refer to all such plurality of similar components.

[0010] Figure 1 This is a schematic block diagram of a system for EMI mitigation in LED and laser drivers according to various embodiments;

[0011] Figure 2 This is a schematic diagram of the slewing control architecture according to various embodiments;

[0012] Figure 3 This is a timing diagram illustrating the various signals in the slewing control architecture according to various embodiments;

[0013] Figure 4 These are schematic diagrams of oscillator circuits according to various embodiments; and

[0014] Figure 5 This is a flowchart of a method for implementing slewing rate control according to various embodiments. Detailed Implementation

[0015] Various embodiments illustrate systems, methods, and apparatus for EMI mitigation in LED and laser drivers.

[0016] In some embodiments, an apparatus for EMI mitigation in LED and laser drivers is provided. An apparatus includes: a digital ramp generator including a delay line comprising a plurality of delay elements and an oscillator, wherein the digital ramp generator is configured to generate a code based on corresponding outputs of the plurality of delay elements; a digital-to-analog converter coupled to the digital ramp generator, wherein the digital-to-analog converter is configured to generate a reference signal, wherein the reference signal is generated at least partially based on the code; and a driver coupled to the digital-to-analog converter, the driver being configured to generate a drive current at least partially based on the reference signal.

[0017] In other embodiments, a circuit for EMI mitigation in LED and laser drivers is provided. The circuit includes a plurality of delay elements, each of which is timed via a clock signal. A first delay element is configured to receive a control signal as an input, and a second delay element is configured to output a delayed control signal, the control signal including a first rising edge and the delayed control signal including a second rising edge later than the first rising edge. The circuit further includes: an oscillator configured to generate the clock signal, wherein the oscillator is configured to generate the clock signal in response to an enable signal; and an XOR gate configured to output the enable signal, wherein a first input of the XOR gate is coupled to the control signal, and a second input of the XOR gate is coupled to the delayed control signal, wherein the enable signal is generated by an XOR of the first and second inputs. The circuit further includes a selector coupled to the plurality of delay elements, the selector being configured to provide a code based on the output of the plurality of delay elements.

[0018] In other embodiments, a system for EMI mitigation in LED and laser drivers is provided. The system includes: a controller configured to generate a control signal; and circuitry coupled to the controller. The circuitry includes a plurality of delay elements, each of the plurality of delay elements being timed via a clock signal, wherein a first delay element of the plurality of delay elements is configured to receive the control signal as an input, and wherein a second delay element of the plurality of delay elements is configured to output a delayed control signal, the control signal including a first rising edge, and the delayed control signal including a second rising edge later than the first rising edge. The circuitry further includes: an oscillator configured to generate the clock signal, wherein the oscillator is configured to generate the clock signal in response to an enable signal; and a selector coupled to the plurality of delay elements, the selector being configured to generate a code based on the outputs of the plurality of delay elements. The circuitry further includes a digital-to-analog converter (DAC) coupled to the selector, wherein the DAC is configured to generate a reference signal at least partially based on the code. The system may further include: a driver coupled to the circuit, the driver being configured to generate a drive current at least partially based on the reference signal; and a light-emitting diode coupled to the driver, the light-emitting diode being configured to generate an optical signal based on the drive current.

[0019] In the following description, numerous details are set forth for illustrative purposes to provide a thorough understanding of the described embodiments. However, it will be apparent to those skilled in the art that other embodiments may be practiced without some of these details. Several embodiments are described herein, and while various features are attributed to different embodiments, it should be understood that features described with respect to one embodiment may also be incorporated into other embodiments. However, for the same reason, no single feature or features of any of the described embodiments should be considered essential to every embodiment of the invention, as such features may be omitted in other embodiments of the invention.

[0020] When an element is referred to herein as “connected” or “coupled” to another element, it should be understood that the element may be directly connected to the other element, or that there may be intermediate elements between the elements. Conversely, when an element is referred to as “directly connected” or “directly coupled” to another element, it should be understood that there are no intermediate elements in a “direct” connection between the elements. However, the presence of a direct connection does not preclude other connections in which intermediate elements may be present.

[0021] Furthermore, for ease of description, the methods and processes described herein may be described in a specific order. However, it should be understood that, unless the context otherwise requires, intermediate processes may occur before and / or after any part of the described process, and various further processes may be reordered, added, and / or omitted according to various embodiments.

[0022] Unless otherwise stated, all figures used herein to express quantities, dimensions, etc., should be understood to be modified by the term “about” in all instances. In this application, the use of the singular includes the plural unless otherwise specified, and the use of the terms “and” and “or” means “and / or” unless otherwise specified. Furthermore, the terms “including” and “having” and other forms (e.g., “includes,” “is included,” and “has / have / had”) should be considered non-exclusive. Additionally, terms such as “element” or “component” cover elements and components comprising one unit as well as elements and components comprising more than one unit, unless otherwise specified.

[0023] As used herein, the phrase “at least one of” preceding a series of items and the terms “and” or “or” separating any items modify the entire list, not each member of the list (i.e., each item). The phrase “at least one of…” does not require selection of at least one of each of the listed items; rather, the phrase allows for the meaning of at least one of any of the items and / or at least one of any combination of items. By example, the phrases “at least one of A, B, and C” or “at least one of A, B, or C” each refer to only A, only B, or only C; and / or any combination of A, B, and C. This is explicitly stated in cases where the intention is to select “at least one of each of A, B, and C” or alternatively “at least one of A, at least one of B, and at least one of C”.

[0024] Previous methods for mitigating EMI from LED or laser drivers have included slew rate control schemes based on free-running clocks and slew rate control based on delay lines. When using an internal free-running clock, the externally generated pulse control signal (TX_PU) is asynchronous with the internal free-running clock. Therefore, variability is introduced into the phase and pulse width of the transmitted (TX) output current, which further reduces the signal-to-noise ratio (SNR) performance. Furthermore, the internal free-running clock can also cause electromagnetic compatibility issues and noise coupling problems to the output current. Regarding delay line-based slew rate control, analog delay elements often occupy a large area with a large number of components. In addition, delay elements are sensitive to power supply noise, and large capacitors are used to reduce the impact of noise.

[0025] Therefore, a slew rate control architecture is described below, which utilizes a digital delay line and a relaxed oscillator design comprising multiple digital delay elements (e.g., flip-flops). The slew rate control architecture correlates the phase of a clock signal from the oscillator with TX_PU (e.g., a pulse control signal). Specifically, a clock signal is generated in response to an assertion of the TX_PU signal (e.g., a logic level indicating that the signal is active or otherwise enabled, such as logic high). Thus, in various instances, active, asserted, and enabled are used interchangeably. Similarly, inactive, "not asserted," and disabled are used interchangeably. Furthermore, by utilizing digital flip-flops instead of analog delay elements, the footprint of the slew rate control architecture is reduced.

[0026] Figure 1 This is a schematic block diagram of a system 100 for EMI mitigation of LED and laser drivers according to various embodiments. System 100 includes a controller 105, slew rate control logic 110, data acquisition logic 115, an LED / laser driver 120, an LED / VCSEL 125, a photodiode 130, and a photosensing amplifier 135. It should be noted that the various components of system 100... Figure 1 The illustrations are schematic, and modifications to various components and other arrangements of the system 100 are possible according to various embodiments.

[0027] In various embodiments, controller 105 may include slewing rate control logic 110 and data acquisition logic 115. In various instances, controller 105 may be implemented in hardware, software, and / or a combination of hardware and software. Specifically, controller 105, slewing rate control logic 110, and / or data acquisition logic 115 may include, but are not limited to, software (including firmware), circuitry (including logic circuitry), custom integrated circuits (ICs), system-on-a-chip (SoCs), or programmable logic (e.g., field-programmable gate arrays (FPGAs)) implementations. In other instances, slewing rate control logic 110 and / or data acquisition logic 115 may be implemented as part of the firmware of controller 105. In other arrangements, it should be understood that some logic (e.g., slewing rate control logic 110) may be implemented as part of other components. For example, in some embodiments, slewing rate control logic 110 may be implemented as part of LED / laser driver 120.

[0028] In various embodiments, controller 105 may be configured to generate a pulse control or TX_PU signal. Controller 105 may cause an LED / laser driver 120 drive current pulse (ITX) (e.g., drive current) to pass through LED / VCSEL 125 via the TX_PU signal. Therefore, ITX may be a drive current configured to drive LED / VCSEL 125. The drive current is the current supplied by the driver to power or otherwise activate LED / VCSEL 125. Therefore, in various embodiments, TX_PU is a signal asserted by controller 105 (e.g., set to a logic level indicating that the signal is active or otherwise enabled, such as logic high) to enable LED / laser driver 120 (e.g., to cause LED / laser driver to generate ITX). As previously described, the slew rate of ITX may be controlled to mitigate EMI generated by LED / laser driver 120. Slew rate refers to the rate at which the level of an output signal (e.g., the drive current of ITX or other output signals) increases or decreases.

[0029] In various instances, the LED / laser driver 120 may include circuitry or an IC configured to power the LED / VCSEL 125. For example, the LED / laser driver 120 may include various types of line drivers, such as constant current or constant voltage drivers. Therefore, the LED / laser driver 120 may be configured to provide voltage and / or current-regulated output signals to power the LED / VCSEL 125. In some instances, the LED / laser driver 120 may be an LED driver configured to power an LED, a laser driver configured to power a laser (e.g., a VCSEL), or an LED / laser driver configured to power either an LED or a laser. Therefore, in some instances, the laser driver may be a type of LED driver.

[0030] In various instances, the LED / VCSEL 125 can be configured to generate optical signals based on the output of the LED / laser driver 120. Specifically, the LED / VCSEL 125 can generate optical signals based on an ITX. The optical signals can be transmitted across an optical channel and received by a photodiode 130. In some instances, the optical signals can be reflected from a surface, and the reflection of the optical signals can be received by the photodiode 130. The photodiode 130 can be configured to receive the optical signals and convert them into current (e.g., photodiode current (IPD)). The IPD can be amplified via a photosensing amplifier 135 and provided to data acquisition logic 115. In various instances, the data acquisition logic 115 can be configured to extract data from the IPD and / or convert the IPD into a data signal. For example, the data acquisition logic 115 can be configured to sample the amplified signal from the photosensing amplifier 135 and generate a digital signal based on the sampled optical signal (e.g., representing the optical signal). In some instances, the slewing rate control logic 110 can be further configured to adjust the slewing rate of the ITX based on the received signal.

[0031] In various embodiments, the slew rate of the ITX can be controlled via slew rate control logic 110. Specifically, a digitally programmable slew rate control scheme can be implemented via slew rate control logic 110. In various embodiments, the slew rate control scheme can be implemented via a digital ramp generator. In some instances, the digital ramp generator may include a delay line, an oscillator, a selector, and / or an oscillator control circuitry. For example, the digital ramp generator generates a continuously rising or falling output signal. It can be used to generate various waveforms, including sawtooth waves, triangle waves, and square waves. The rate of change of the output signal (e.g., the slope of the ramp) can be controlled by adjusting the time delay between consecutive output steps. The delay line includes a series of multiple delay elements and can be used to control the output of a current-mode digital-to-analog converter (DAC) (e.g., to generate timing for the output of a current ramp). The output of the DAC may be a reference signal from which the LED / laser driver 120 generates the ITX. Therefore, a digital ramp generator can be configured to control the slew rate of a reference signal and also control the drive current (e.g., ITX) output by a driver.

[0032] In various embodiments, a delay element includes circuitry or components configured to cause a delay in a signal (e.g., a clock signal). A delay line may be a series of interconnected delay elements. Delay elements may include, but are not limited to, digital delay elements, programmable delay elements, flip-flops (e.g., D-type flip-flops), latches, or other types of delay elements. Suitable delay elements may include various types of delay elements capable of being timed (e.g., having an output controlled by a clock signal). Thus, timing refers to controlling the output of a delay element (e.g., a flip-flop) via a clock input. Therefore, the output can be enabled by a clock signal (e.g., a rising edge of the clock signal causes the input D of a D-type flip-flop to be output). The following discusses… Figure 2 The operation of the slewing rate control architecture is described in more detail.

[0033] Figure 2 This is a schematic diagram of the rotary control architecture 200. Architecture 200 includes a TX_PU input 205, multiple delay elements 210a to 210n (collectively referred to as "delay lines 210" or "delay elements 210"), a selector 215, a current-mode DAC (IDAC) 220, a driver 225, an LED 230, an XOR gate 235, and an oscillator 240. It should be noted that the various components of architecture 200... Figure 2 The illustrations are schematic, and modifications to various components and other arrangements of architecture 200 are possible according to various embodiments.

[0034] In various instances, architecture 200 is a circuit architecture for slewing rate control circuitry. In operation, this architecture may include a series of multiple delay elements 210a to 210n configured to receive a pulse control signal TX_PU. The outputs of the delay elements are coupled to a selector 215, which is configured to output a digital code to an IDAC 220. For example, the digital code includes a series of bits indicating the current output level of the IDAC 220, corresponding to the outputs of the delay elements (e.g., trigger circuitry used as a ripple counter). The IDAC 220 may then generate a reference signal having a slewing rate as controlled by architecture 200. The reference signal is provided to a driver 225, which may then generate a pulsed current (e.g., a drive current) ITX from the reference signal.

[0035] In the examples below, it should be understood that whether a signal is asserted or disabled is not limited to a specific logic level, and the association between asserted signals and logic high is for illustrative purposes only and to illustrate the relationship between signals in the slewing control architecture 200.

[0036] In various embodiments, TX_PU may be a control signal asserted to enable (e.g., activate) LED 230. Therefore, as used herein, assertion means that the signal is set to a logic level (e.g., logic high or logic low) associated with the signal being active (e.g., enabled). In some instances, TX_PU may be asserted by setting it from a logic low state to a logic high state. When TX_PU is asserted, a plurality of delay elements 210a to 210n may sequentially output a delayed TX_PU signal referred to as “tx_pu_dly”. Specifically, TX_PU may be received at the first delay element 210a of the plurality of delay elements 210a to 210n. Each of the delay elements 210a to 210n may be controlled (e.g., enabled) via a clock signal from oscillator 240. In various instances, multiple delay elements 210a to 210n may be digital delay elements (e.g., delay flip-flops) that can change the state of their output signal (Q) to the input state (D) (e.g., the state of the input signal) on the rising edge of the clock signal (CLK) at the clock input. Thus, when TX_PU is asserted (e.g., logic high), the first delay element 210a can toggle its output Q to logic high on the first rising edge of the clock signal CLK. The output of the first delay element 210a may be coupled to the input of selector 215 and the input D of the second delay element 210b. On a subsequent rising edge of CLK, the second flip-flop 210b can change its output Q to logic high. For example, the duration of the clock signal is consistent (e.g., the duration of the first clock signal is constant relative to the duration of the second clock signal). Therefore, in each clock cycle of CLK (e.g., at each consecutive rising edge), a subsequent delay element can toggle its output to logic high corresponding to the assertion of TX_PU. Thus, the nth delay element can change its output Q to logic high at the nth rising edge of CLK. Therefore, the total delay of tx_pu_dly is approximately equal to the number of elements n multiplied by the period of the CLK clock cycle (e.g., the frequency of 1 / CLK), without considering propagation and processing delays and other factors affecting signal delay. For example, n delay elements together are used as a counter, whose count is based on the number of clock cycles corresponding to the enabled (e.g., logic high) state of the TX_PU signal. When TX_PU is no longer asserted (e.g., logic low), the output at each of delay elements 210a to 210n can similarly change to logic low sequentially in response to successive rising edges of CLK (e.g., successive clock cycles of CLK).

[0037] Oscillator 240 can be activated when the oscillator enable signal (osc_en) is enabled (e.g., asserted). In various instances, osc_en is the output of XOR gate 235. XOR gate 235 can take TX_PU and tx_pu_dly (e.g., the output of the nth delay element 210n) as its inputs. Therefore, osc_en can be asserted when the states of TX_PU and tx_pu_dly are not the same (e.g., the output of XOR gate 235 is logic high). For example, osc_en can be asserted when TX_PU is logic high and tx_pu_dly is logic low. In other words, the state of osc_en can be given by: osc_en = TX_PU tx_pu_dly. In some embodiments, the XOR gate can be implemented using other logic gates, provided that the oscillator is enabled only when TX_PU and tx_pu_dly do not match.

[0038] As the states of multiple delay elements 210a to 210n change from low to high, osc_en can be deactivated (e.g., set to logic low) when both TX_PU and tx_pu_dly are in the same state (e.g., the output of the nth delay element changes to logic high). When TX_PU is then deactivated (e.g., no longer asserted) and set to logic low, tx_pu_dly and TX_PU can again be in different states (e.g., tx_pu_dly remains logic high, while TX_PU is logic low). Therefore, osc_en can be enabled (e.g., asserted) when TX_PU and tx_pu_dly are not in a mismatched state. When the output of the nth delay element changes to logic low, both tx_pu_dly and TX_PU can be in a logic low state, and osc_en can be deactivated (e.g., set to logic low). It should be understood that in other instances, an assertion signal can be associated with a logic low state, and a deactivation signal can be associated with a logic high state.

[0039] In various instances, oscillator 240 may be a relaxation oscillator configured to have a stable output frequency from the first cycle with zero startup delay. In other embodiments, oscillator 240 may include a clock source exhibiting low phase noise, low jitter, and insensitivity to power supply variations (e.g., power supply voltage). For example, other suitable oscillators 240 may include, but are not limited to, crystal oscillators.

[0040] In various instances, oscillator 240 can be configured to enter a standby state when osc_en is disabled. In standby mode, oscillator 240 can set its internal nodes to initial voltages (e.g., Vp and Vn), and the oscillator's comparator can be configured to operate in a mode with the correct DC operating point. Comparator bias control can be further used to reduce current in standby mode. The following section discusses... Figure 4 The architecture and operation of oscillator 240 are described in more detail.

[0041] The outputs of multiple delay elements 210a to 210n can be output in parallel to selector 215, which encodes the parallel outputs into serialized digital codes. As used herein, selector 215 is an electronic component (e.g., a multiplexer, or one or more multiplexers) configured to select among one or more inputs to produce an output (e.g., forwarding the selected input as an output). In some instances, selector 215 may include a multiplexer (or one or more multiplexers) configured to map the outputs of delay elements (e.g., the outputs of multiple delay elements 210a to 210n) to one or more IDAC inputs (e.g., digital codes). For example, in some embodiments, each delay element output may correspond to a corresponding bit of the digital code. In this example, ITX (or a reference signal generated by the IDAC) may have an increase / decrease in the number of discrete steps equal to the number of delay elements (e.g., digital code bits). In other embodiments, a single delay element output may correspond to multiple bits of the digital code. In this way, the IDX and / or reference signals generated by the IDAC can be configured to have a faster rotation rate and a smaller number of steps. In some other instances, selector 215 may include a serializer configured to take parallel inputs (e.g., delayed element outputs) and produce serialized outputs (e.g., digital codes).

[0042] The IDAC 220 can be a current-mode DAC configured to output current based on digitally coded values. Therefore, in some instances, the IDAC 220 may contain a thermometer-coded DAC.

[0043] In various embodiments, when TX_PU is asserted, the output of the digital code may be a first value during the first clock cycle of CLK (e.g., at the first rising edge of CLK). For example, when using four delay elements, the delay elements may output 1, 0, 0, 0 in parallel during the first clock cycle (e.g., the first delay element 210a outputs logic high "1", the second delay element 210b outputs logic low "0", the third delay element 210c outputs 0, and the fourth delay element 210d outputs 0). Then, selector 215 may generate the digital code 0001 based on the output of delay element 210. During the second clock cycle (e.g., at the second rising edge of CLK), delay element 210 may output 1, 1, 0, 0. Then, selector 215 may generate the digital code 0011 based on the output of the delay elements. This may continue into subsequent clock cycles until TX_PU and tx_pu_dly enter the same state (e.g., both are logic high) and oscillator 240 becomes deactivated.

[0044] At IDAC 220, each digital code corresponds to a specific output current. Therefore, at the first digital code 0001, a first output current can be output by IDAC. At the second digital code 0011, a second output current can be output. In some instances, a larger digital code corresponds to a larger output current. In this way, the digital code can increment with each clock cycle, causing IDAC 220 to generate a digital ramp signal. When osc_en is disabled, the current level output by IDAC 220 can be maintained. When TX_PU is disabled, osc_en can be asserted again, thus activating oscillator 240.

[0045] Similar to a ramp-up operation, delay elements 210a to 210d can be ramped down sequentially. Therefore, when TX_PU is disabled, during the first rising edge of CLK (e.g., the first clock cycle), the output of the delay element can be 0, 1, 1, 1; during the second clock cycle, it can be 0, 0, 1, 1; during the third clock cycle, it can be 0, 0, 0, 1; and during the fourth clock cycle, it can be 0, 0, 0, 0. The corresponding output at each clock cycle can be serialized via selector 215 and output to IDAC 220 to generate a digital ramp signal, where the output of IDAC 220 is ramped down.

[0046] Therefore, in various embodiments, the slew rate of the reference signal, and consequently the ITX, is controlled via multiple delay elements 210a to 210n and the clock frequency of CLK (e.g., the oscillation frequency of oscillator 240). Specifically, the number of delay elements may correspond to the number of steps (e.g., digital codes) by which the IDAC 220 can generate a corresponding output current level. Thus, the number of steps may correspond to the number of steps in the ramp of the reference signal. Therefore, the number of steps in the ramp can be controlled by adding or removing delay elements. Furthermore, when more steps (e.g., delay elements) are present, the ramp signal can increase more slowly (e.g., more clock cycles are required to reach the final output current level).

[0047] Furthermore, the clock frequency of CLK determines the rate at which new digital codes are output to the IDAC 220. In other words, a higher clock frequency means less time is spent on the corresponding digital code (e.g., output current level), and the ramp (e.g., output current level) will increase (or decrease) more quickly. Conversely, a slower clock frequency results in a slower ramp increase (or decrease).

[0048] In this way, the slew rate of the reference signal and thus the ITX can be controlled by the total number of delay elements and / or the clock frequency (e.g., the oscillation frequency).

[0049] In various embodiments, the output of IDAC 220 may be a reference signal from which driver 225 generates ITX. Driver 225 may be an LED driver and / or a laser driver as previously described. In some instances, driver 225 may be configured to drive the reference signal at a constant current and / or voltage. Thus, ITX may be a reference signal provided by driver 225 to LED 230 at a constant power (e.g., current). Similarly, as previously described, LED 230 may comprise a laser diode, such as a VCSEL.

[0050] Figure 3 This is a timing diagram 300 illustrating various signals in a slewing control architecture according to various embodiments. As previously discussed... Figure 2As described, the various signals of architecture 200 are illustrated relative to each other. In the illustrated example, TX_PU 305 is asserted at the first time (t1). At the second time (t2), TX_PU_DLY 310 is asserted after a delay of n delay elements, which is 4 delay elements in this example. As shown in the timing diagram, at t1 (ideally, excluding propagation, processing, and other delays), osc_en 315 is asserted simultaneously with TX_PU 305. Then, CLK 320 can be activated, where a first falling edge occurs at t1.1, a first rising edge occurs at the start of t1.2, and a second rising edge occurs at t1.3. In various instances, the first falling edge of the clock signal follows TX_PU. Specifically, starting the oscillator from standby can reduce (or in some cases minimize) startup delay and mitigate delay uncertainty. Therefore, in some instances, the delay between a TX_PU assertion and the first rising edge of the CLK320 may have a duration consistent with or sustained between consecutive (e.g., subsequent) TX_PU assertions. Similarly, when TX_PU is deactivated (e.g., no longer asserted), the delay between the falling edge of TX_PU and subsequent “first rising edge” of the CLK320 (e.g., after it has been asserted again) may similarly have a duration consistent with the TX_PU assertion, and when TX_PU is subsequently deactivated.

[0051] At each rising edge of the CLK 320, a new digital code can be output to the IDAC, and then to the LED / laser driver to generate the ITX 325. Thus, at t1, the digital code could be 0000, corresponding to a 0 current level. At t1.1, a first digital code corresponding to a first output current can be generated. In some instances, the first digital code could be 0001, corresponding to a first output current lower than the second output current. This is demonstrated in the ITX 325 where the output current ramps up from a baseline or 0 current level to the first output current. At t1.2, a second digital code corresponding to the second output current, such as 0011, can be generated. The second output current can have a current level greater than the first output current, thus causing an increase in the output current of the ITX 325. At t1.3, a third digital code corresponding to a third output current greater than the second output current can be generated. In this way, a ramp (e.g., a digital ramp) can be generated in the ITX 325.

[0052] When TX_PU_DLY 310 is asserted simultaneously with TX_PU305 at time t2, osc_en 315 can be disabled. When TX_PU is disabled, osc_en 315 can be enabled (e.g., asserted) at time t3. This allows CLK 320 to become active again, with a first falling edge at time t3.1, a first rising edge at time t3.2, and a second rising edge at time t3.3. Similar to ramp-up operation, ITX 325 can ramp down based on the digital code generated in descending order. For example, at the beginning of t3.1 (e.g., around the time TX_PU switches from high to low), the digital code can be reduced, reduced again at the first rising edge of t3.2, and so on at the second and third rising edges. In this way, the output current corresponding to the respective digital code can be reduced. In some embodiments, the output current during ramp-down operation (e.g., when TX_PU is deactivated) may correspond to the same output current level during ramp-up operation (e.g., when TX_PU is asserted). For example, the output current at the digital code generated at the third rising edge of t1.3 may correspond to the same output current at the digital code generated at the first rising edge of t3.1 (e.g., digital code 0111 may correspond to the same level of output current as digital code 1110), and so on for each corresponding ramp level. In other instances, each digital code may correspond to a different corresponding output current level.

[0053] Figure 4 This is a schematic diagram of an oscillator circuit 400 according to various embodiments. The oscillator circuit 400 includes a first resistor 405, a second resistor 410, a third resistor 415, a comparator 420, an OR gate 425, a fourth resistor 430, a switch 435, a capacitor 440, and a fifth resistor 445. It should be noted that the various components of the oscillator circuit 400... Figure 4 The diagram is schematic, and modifications to various components and other arrangements of the circuit 400 are possible according to various embodiments.

[0054] As previously described, the oscillator circuit 400 can be designed as a relaxation oscillator. The voltage applied to the non-inverting input of the comparator (Vp) can be controlled such that the applied voltage (V) is a supply voltage that depends on the state of the comparator output voltage (Vo). DD The voltage applied is 1 / 3 or 2 / 3 of the input voltage. The resistances of the first resistor 405 and the second resistor 410 can be set accordingly. The initial value of the non-inverting input (Vn) can be set such that 1 / 3V is applied. DD The voltage. Specifically, the OR gate 425 forces Vo high when osc_en is deasserted (enb=1) and sets Vp to 2 / 3 of Vdd.

[0055] When osc_en is asserted, switch 435 can be turned off (e.g., disconnected), and capacitor 440 can begin charging, thereby increasing Vn to 2 / 3V of Vp. DD Level. Once the two inputs become equal, the comparator's output switches its output Vo to 0, and causes capacitor 440 to slowly discharge through resistor 445, causing Vp to drop by 1 / 3V. DD This causes Vn to decrease slowly as capacitor 440 discharges. Once Vn drops to 1 / 3V... DD Comparator 420 can then output high again (for example, Vo is set to output logic high). Therefore, Vp can be set to 2 / 3V again. DD Furthermore, Vn increases slowly as capacitor 440 is charged. In this way, an oscillation frequency (f) determined based on the capacitance of capacitor 440 and the resistance of the fifth resistor 445 can be generated. osc The clock signal of f. Specifically, f osc It can be given as: Therefore, for the relaxation oscillator circuit 400, the oscillation frequency is related to V. DD Irrelevant (e.g., for V) DD (Insensitive to changes or noise).

[0056] When osc_en is disabled, the oscillator circuit 400 can enter a standby state, in which switch 435 can be closed (e.g., connected), thereby discharging capacitor 440 (e.g., via fourth resistor 430), and input nodes Vp and Vn are reset to their appropriate initial values ​​(e.g., 2 / 3 V each). DD and 1 / 3 V DD In some instances, switchable auxiliary resistor ladder and comparator bias control (not shown) can be further used to reduce standby current. In this way, oscillator 400 can be driven by TX_PU and synchronized with the assertion and deactivation of TX_PU (e.g., when TX_PU is set from logic high to logic low).

[0057] Figure 5 This is a flowchart of a method 500 for implementing slewing rate control. Method 500 includes providing a control signal in block 505. As previously described, a pulse control signal TX_PU can be asserted to activate and / or generate an optical signal via an LED or VCSEL. In various instances, the control signal (e.g., TX_PU) can be received by the input of a delay element of a delay line. The delay line can contain multiple delay elements. TX_PU can be further provided to an oscillator and / or an oscillator control circuitry (e.g., an XOR gate) to enable the oscillator, as previously described.

[0058] In block 510, method 500 can continue by generating a clock signal. As previously described, the clock signal can be configured to time multiple delay elements of the delay line. As previously described, the clock signal can be generated by an oscillator. In various embodiments, an oscillator enable signal osc_en is generated based on TX_PU. Specifically, an XOR gate can be configured to receive TX_PU and TX_PU_DLY as its inputs. TX_PU_DLY can be the delay control signal TX_PU output from the last delay element of the delay line. Therefore, when TX_PU and TX_PU_DLY are not at the same logic level, the oscillator can be enabled and a clock signal can be generated.

[0059] In block 515, the method continues by enabling multiple delay elements based on a clock signal. As previously described, the multiple delay elements of the delay line can be timed by a clock signal generated by an oscillator. When timed by the clock signal, the delay elements can be enabled on the rising edge of the clock signal. Specifically, when enabled by the clock signal, the output of the delay element can be changed (or maintained) to match the input signal. For example, in some embodiments, the delay element can be a digital flip-flop. Thus, the output of the flip-flop can be changed to match the input of the flip-flop (e.g., a D input) on the rising edge of the clock signal. When the signal at the input of the flip-flop is changed, the previous output is maintained until the next rising edge of the clock signal. Thus, the output can be changed to match the input on the subsequent rising edge of the clock signal. In this way, TX_PU can be delayed by the delay line based on the total number of delay elements and the clock frequency of the clock signal.

[0060] In block 520, method 500 continues by generating code based on the respective outputs of multiple delay elements. As previously described, in some instances, the output of each of the multiple delay elements can be provided to a selector in parallel. The selector can be configured to receive the parallel outputs of the respective multiple delay elements and generate serial code as output. As the outputs of the multiple delay elements change with each clock cycle, the selector can be configured to generate new code based on the changed or updated output of the current clock cycle. In this way, one or more codes can be generated and updated based on the outputs of multiple delay elements.

[0061] In block 525, method 500 continues by generating a reference signal based on a code. As previously described, the code generated by the selector can be provided to the DAC. The DAC can be a current-mode DAC (e.g., an IDAC) configured to output current based on a digital code. Specifically, the IDAC can be configured to generate a reference signal having an output current level corresponding to the respective code. For example, a first code can correspond to a first current level less than a second current level. A second code can correspond to a second current level less than a third current level, and so on. Thus, in various instances, the reference signal is a ramp signal (e.g., a digital ramp signal) that increases in discrete step size and is generated via the IDAC based on the generated code. The ramp slew rate can be determined based on the total number of delay elements and / or the frequency of the clock signal.

[0062] At block 530, method 500 further includes generating a drive current based on a reference signal. As previously described, the reference signal may be provided to an LED and / or laser driver to generate a drive current configured to drive the LED and / or VCSEL. In some instances, the drive current may be generated by the driver based on the reference signal. In other instances, the drive current may be a reference signal provided to the LED and / or VCSEL, whose voltage and / or current are regulated by the LED and / or laser driver (e.g., constant voltage and / or constant current). As an example, the slew rate (both ramp-up and ramp-down) of the drive current corresponds to the reference signal. Depending on the implementation, the magnitude of the drive current may be proportional to and many times greater than the magnitude of the reference signal.

[0063] While some features and aspects have been described with respect to embodiments, those skilled in the art will recognize that many modifications are possible. For example, the methods and processes described herein can be implemented using hardware components, custom integrated circuits (ICs), programming logic, and / or any combination thereof. Furthermore, while the various methods and processes described herein may be described with respect to specific structural and / or functional components for ease of description, the methods provided by the various embodiments are not limited to any particular structural and / or functional architecture, but can be implemented in any suitable hardware configuration. Similarly, while some functionality is attributed to one or more system components, unless the context otherwise specifies, this functionality may be distributed across a variety of other system components according to several embodiments.

[0064] Furthermore, although the procedures of the methods and processes described herein are presented in a specific order for ease of description, various procedures may be reordered, added, and / or omitted according to various embodiments unless the context otherwise requires. Moreover, procedures described with respect to a method or process may be incorporated into other described methods or processes; similarly, system components described with respect to a particular architecture and / or a system may be organized in an alternative architecture and / or incorporated into other described systems. Therefore, although various embodiments with or without certain features are described for ease of description and illustration of aspects of those embodiments, various components and / or features described herein with respect to particular embodiments may be replaced, added, and / or removed from other described embodiments unless the context otherwise requires. Therefore, although several embodiments have been described above, it will be understood that the invention is intended to cover all modifications and equivalents within the scope of the appended claims.

Claims

1. An apparatus comprising: A digital ramp generator includes a delay line comprising a plurality of delay elements and an oscillator, wherein the plurality of delay elements are configured to time with a clock signal generated by the oscillator, wherein a first delay element of the plurality of delay elements is configured to receive a control signal as input, wherein the oscillator is enabled by the control signal, and wherein the digital ramp generator is configured to generate codes based on the respective outputs of the plurality of delay elements. A digital-to-analog converter (DAC) coupled to the digital ramp generator, wherein the DAC is configured to generate a reference signal, the reference signal being generated at least in part based on the code; and A driver coupled to the DAC, the driver being configured to generate a drive current based at least in part on the reference signal; The oscillator includes a capacitor, and the oscillation frequency of the oscillator is independent of the power supply voltage and is determined at least in part based on the capacitance of the capacitor.

2. The device according to claim 1, wherein the oscillator is a relaxation oscillator.

3. The device of claim 2, wherein the first delay between the first rising edge of the clock signal and the rising edge of the control signal has a first duration, wherein the first delay coincides with a second delay between the falling edge of the control signal and a subsequent first rising edge of the clock signal enabled after the falling edge of the control signal.

4. The device according to claim 1, wherein the plurality of delay elements are digital delay elements.

5. The device of claim 4, wherein the digital delay element comprises a digital trigger.

6. The apparatus of claim 1, wherein the digital ramp generator is configured to control the slew rate of the reference signal, wherein the slew rate of the reference signal is determined at least in part based on the total number of delay elements of the plurality of delay elements.

7. The apparatus of claim 1, wherein the digital ramp generator is configured to control the slew rate of the reference signal, wherein the slew rate of the reference signal is determined at least in part based on the frequency of the clock signal.

8. A circuit comprising: A plurality of delay elements, each of the plurality of delay elements being timed via a clock signal, wherein a first delay element of the plurality of delay elements is configured to receive a control signal as input, and wherein a second delay element of the plurality of delay elements is configured to output a delayed control signal, the control signal including a first rising edge, the delayed control signal including a second rising edge, the second rising edge being later than the first rising edge; An oscillator configured to generate the clock signal, wherein the oscillator is configured to generate the clock signal in response to an enable signal; An XOR gate configured to output the enable signal, wherein a first input of the XOR gate is coupled to the control signal and a second input of the XOR gate is coupled to the delayed control signal, wherein the enable signal is generated by XORing the first and second inputs; and A selector coupled to the plurality of delay elements, the selector being configured to provide code based on the output of the plurality of delay elements.

9. The circuit of claim 8, further comprising a digital-to-analog converter (DAC), wherein the DAC is coupled to the selector and configured to generate a reference signal, wherein the current of the reference signal is determined at least in part based on the code.

10. The circuit of claim 9, further comprising a driver, wherein the driver is coupled to the DAC and configured to generate a drive current at least in part based on the reference signal.

11. The circuit of claim 10, wherein the slew rate of the reference signal is determined at least in part based on the total number of delay elements of the plurality of delay elements and the frequency of the clock signal.

12. The circuit of claim 8, wherein the oscillator is a relaxation oscillator.

13. The circuit of claim 12, wherein the first delay between the first rising edge of the clock signal and the rising edge of the control signal has a first duration, wherein the first delay coincides with a second delay between the falling edge of the control signal and a subsequent first rising edge of the clock signal enabled after the falling edge of the control signal.

14. The circuit of claim 12, wherein the oscillator includes a capacitor, the oscillation frequency of the oscillator is independent of the power supply voltage and is determined at least in part based on the capacitance of the capacitor, wherein the frequency of the clock signal is determined based on the oscillation frequency.

15. The circuit of claim 8, wherein the plurality of delay elements comprises digital delay elements.

16. The circuit of claim 15, wherein the digital delay element comprises a trigger.

17. A system comprising: A controller configured to generate control signals; A circuit coupled to the controller, the circuit comprising: A plurality of delay elements, each of the plurality of delay elements being timed via a clock signal, wherein a first delay element of the plurality of delay elements is configured to receive the control signal as an input, and wherein a second delay element of the plurality of delay elements is configured to output a delayed control signal, the control signal including a first rising edge, the delayed control signal including a second rising edge, the second rising edge being later than the first rising edge; An oscillator configured to generate the clock signal, wherein the oscillator is configured to generate the clock signal in response to an enable signal; A selector coupled to the plurality of delay elements, the selector being configured to generate code based on the output of the plurality of delay elements; A digital-to-analog converter (DAC) coupled to the selector, wherein the DAC is configured to generate a reference signal at least in part based on the code; A driver coupled to the circuit, the driver being configured to generate a drive current at least partially based on the reference signal; and A light-emitting diode coupled to the driver, the light-emitting diode being configured to generate an optical signal based on the drive current.

18. The system of claim 17, wherein the circuitry is configured to control the slew rate of the reference signal, wherein the slew rate of the reference signal is determined at least in part based on the total number of delay elements and the frequency of the clock signal.

19. The system of claim 17, wherein the oscillator is further configured to be enabled at least in part based on an enable signal, wherein the enable signal is generated as a function of the control signal and a delayed control signal, wherein the delayed control signal is output by the last delayed element of the plurality of delayed elements, and wherein the function is an XOR; and wherein the oscillator is configured to enter a standby state when the enable signal is disabled.

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