Memory management method, electronic device and storage medium

Abstract

The present application relates to the field of memory technology, and in particular to a memory management method, an electronic device, and a storage medium. The method can judge the used capacity of each rank in the memory when an electronic device containing multiple ranks (e.g., dual ranks, quad ranks, etc.) of memory is in a specific state (e.g., screen-off state, standby state, low-power state). After the judgment result is that the transfer condition is met, the data in at least one rank among the multiple ranks is transferred to the remaining ranks, and then the access to the ranks without data storage is stopped, thereby reducing the total power required for the entire memory and the number of memory chip refreshes.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a memory management method, electronic device and storage medium. Background Art

[0002] In existing electronic devices, synchronous dynamic random access memory (SDRAM) is usually used as memory to store the code and data required for the operation of data processing systems such as central processing units (CPUs). SDRAM has a large capacity and high read and write speed, which can better meet the memory requirements of data processing systems. However, since SDRAM uses capacitors for storage, in order to ensure that data is not lost, continuous power supply and refresh are required during operation, which in turn generates a large amount of power consumption, which leads to an increase in the power consumption of the entire data processing system. Summary of the invention

[0003] The embodiments of the present application provide a memory management method, an electronic device, and a storage medium, which can solve the problem of high power consumption when the memory in electronic devices such as mobile phones is running.

[0004] In a first aspect, an embodiment of the present application provides a memory management method, which is applied to an electronic device, wherein the electronic device includes a memory, and the memory includes multiple memory columns; and the method includes: obtaining the used capacity of each memory column in the multiple memory columns; determining whether the memory meets a transfer condition based on the used capacity and a usage threshold of each memory column; if it is determined that the memory meets the transfer condition, transferring data stored in a first memory column in the multiple memory columns to a second memory column in the multiple memory columns, and restricting access to the first memory column.

[0005] Among them, memory refers to double data rate synchronous dynamic random access memory, abbreviated as DDR, and memory column refers to multiple memory chips / particles connected to the same chip select signal (chip select), abbreviated as rank.

[0006] It can be understood that DDR is usually composed of at least one rank. The more ranks there are in DDR, the greater the power consumption of DDR. Based on this, in the memory management method of the embodiment of the present application, when the DDR contains multiple ranks, the electronic device determines whether the DDR meets the transfer condition based on the size relationship between the used capacity of each rank and the usage threshold. When it is determined that the transfer condition is met, the data in at least one rank (first memory column) of the multiple ranks is transferred to the remaining ranks (second memory column), and then the power supply of the rank (first memory column) without data storage is turned off to stop access to the rank (first memory column) without data storage. In this way, data transfer is performed when the DDR meets the transfer condition, which can reduce the number of ranks used for data storage in the DDR, thereby reducing the power consumed by the DDR, and reducing the number of refreshes of the memory chip in the DDR, which can ultimately reduce the power consumption of the DDR and alleviate the heating of the electronic device.

[0007] In addition, when the DDR does not meet the transfer condition, the electronic device can start timing, and when the timing meets the preset time, it is judged again based on the use threshold whether the used capacity of each rank meets the transfer condition. Alternatively, when the DDR does not meet the transfer condition, the electronic device can also detect the battery power. When it is detected that the battery power is less than the first power, or each time the battery power is detected to be reduced by the second power, it is judged again based on the use threshold whether the used capacity of each rank meets the transfer condition. Among them, the preset time can be set according to the actual application situation, and can be several minutes, several seconds, several milliseconds, etc., for example. The first power can be any power value that characterizes that the electronic device is in a low power state, such as 30%, 20%, 10%, etc., which is not limited in this application. The second power can be 3%, 5%, 10% or other arbitrary values, which is not limited in this application. In this way, the electronic device continues to detect the time or battery power when the DDR does not meet the transfer condition, which can ensure that data transfer can be performed in time when the DDR meets the transfer condition.

[0008] In some implementations of the first aspect above, the usage threshold includes a first usage threshold, and the transfer condition includes that the sum of the used capacities of the memory ranks is less than the first usage threshold.

[0009] It can be understood that when determining whether the DDR meets the transfer condition based on the size relationship between the used capacity of each rank and the usage threshold, it is possible to judge whether the sum of the used capacity of each rank is less than the first usage threshold, and then determine whether the DDR meets the transfer condition based on the judgment result. If it is determined that the sum of the used capacity of each rank is less than the first usage threshold, it is determined that the DDR meets the transfer condition, and after the transfer is completed, the DDR can complete the data storage task with fewer ranks. If it is determined that the used capacity of each rank is greater than or equal to the first usage threshold, it means that the current data processing volume is large, and all ranks in the DDR are required to store data, and the number of ranks cannot be reduced. Among them, the first usage threshold can be set in advance according to the number of ranks in the actual DDR and the memory capacity of each rank. The number of the first usage threshold can be one or more, determined according to the actual number of ranks in the DDR.

[0010] In this way, when the used capacity of each rank is judged to be small, the number of ranks is reduced, and the data storage task can be completed with less or even a single rank of memory capacity, which can reduce unnecessary power consumption.

[0011] In some implementations of the first aspect above, when the memory capacities of the memory columns are the same, the first usage threshold includes a preset proportion of the memory capacities of a first number of memory columns, and the first number is any value less than the total number of memory columns.

[0012] It is understandable that, in the case where the memory capacity of each rank is the same, the first usage threshold may be a preset proportion of the memory capacity of the first number of ranks, wherein the preset proportion may be any value between 0 and 100%, and this application does not limit this.

[0013] Taking DDR including two ranks as an example, the memory capacity of the two ranks is the same, and the first usage threshold may include a preset proportion of the memory capacity of a single rank (for example, 80%). At this time, the first number is 1; accordingly, the transfer condition may include that the sum of the used capacity of the two ranks is less than 80% of the memory capacity of a single rank.

[0014] Taking DDR as an example, which includes four ranks and the memory capacity of the four ranks is the same, the first usage threshold may include a preset proportion of the memory capacity of a single rank (for example, 80%), 80% of the sum of the memory capacity of two ranks, and 80% of the sum of the memory capacity of three ranks. At this time, the first number is 1, 2, and 3; accordingly, the transfer condition may include three sub-conditions: the sum of the used capacity of the four ranks is less than 80% of the memory capacity of a single rank, the sum of the used capacity of the four ranks is less than 80% of the sum of the memory capacity of two ranks, and the sum of the used capacity of the four ranks is less than 80% of the sum of the memory capacity of three ranks; if at least one of the above three sub-conditions is met, it can be considered that DDR meets the transfer condition.

[0015] The benefit of setting a preset ratio is that it can ensure data security. Specifically, the data is transferred when the used capacity of each rank reaches the preset ratio of the memory capacity, so that even if all the data in one rank is transferred to another rank, the amount of data in the other rank will not be too large, avoiding the transfer when the memory capacity reaches 100%, which may cause the other rank to automatically delete part of the data due to the excessive amount of stored data, resulting in data loss.

[0016] In the case where the memory capacities of the memory columns are not exactly the same, the first usage threshold may be a preset proportion of the memory capacity of any rank in at least two ranks, where any rank may include a combination of one rank or multiple ranks. It is understood that the memory capacities of the ranks are not exactly the same, which means that the memory capacities of at least two ranks are different.

[0017] In some implementations of the first aspect above, when the memory capacities of the memory columns are not exactly the same, the first usage threshold includes a preset proportion of the first second number of larger memory capacities in the multiple memory columns, and the second number is an arbitrary value less than the total number of memory columns in the multiple memory columns.

[0018] It is understandable that, in the case where the memory capacities of the ranks are not completely the same, the first usage threshold may be a preset proportion of the memory capacities of the first second number of the ranks with the largest memory capacities, wherein the preset proportion may be any value between 0 and 100%.

[0019] Taking DDR including two ranks as an example, the memory capacities of the two ranks are different, then the first usage threshold can be a preset proportion (for example, 80%) of the larger memory capacity of the two ranks, at this time, the second number is 1; accordingly, the transfer condition can include that the sum of the used capacities of the two ranks is less than 80% of the larger memory capacity.

[0020] Taking DDR including four ranks as an example, the memory capacities of the four ranks are not exactly the same. The first usage threshold may include a preset proportion of the maximum memory capacity (for example, 80%), 80% of the sum of the two larger memory capacities, and 80% of the sum of the three larger memory capacities. At this time, the second number is 1, 2, and 3; accordingly, the transfer condition may include three sub-conditions: the sum of the used capacity of the four ranks is less than 80% of the maximum memory capacity, the sum of the used capacity of the four ranks is less than 80% of the sum of the two larger memory capacities, and the sum of the used capacity of the four ranks is 80% of the sum of the three larger memory capacities; as long as at least one of the above three sub-conditions is met, DDR can be considered to meet the transfer condition.

[0021] In this way, since the first usage threshold is the preset proportion of the first second number of larger memory capacities in multiple ranks, that is, the first usage threshold is relatively large, the sum of the used capacity of each rank can more easily meet the transfer conditions, thereby ensuring that DDR can transfer data in a timely manner and minimize DDR power consumption.

[0022] In addition, in some implementations of the first aspect, the first usage threshold may be a fixed value or a dynamically changing value. For example, the first usage threshold may dynamically change according to the actual power, and the smaller the actual power, the larger the first usage threshold.

[0023] In some implementations of the first aspect above, the usage threshold includes a second usage threshold, and the transfer condition includes that the used capacity of each memory column is less than the second usage threshold.

[0024] It can be understood that when determining whether the DDR meets the transfer condition based on the size relationship between the used capacity of each rank and the usage threshold, it is possible to judge whether the used capacity of each rank is less than the second usage threshold, and then determine whether the DDR meets the transfer condition based on the judgment result. If it is determined that the used capacity of each rank is less than the second usage threshold, it is determined that the DDR meets the transfer condition, and after the transfer is completed, the DDR can complete the data processing task with fewer ranks. If it is determined that the used capacity of each rank is greater than or equal to the second usage threshold, it means that the current data processing volume is large and all ranks in the DDR are required to store it, and the number of ranks cannot be reduced. Among them, the second usage threshold can be set according to the number of ranks in the actual DDR and the memory capacity of each rank.

[0025] In some implementations of the first aspect, when the memory capacities of the memory columns are the same, the second usage threshold includes a third number of sub-thresholds, and the range of the sub-thresholds is a preset percentage of the memory capacity of a single memory column. Wherein, N is the total number of memory ranks in the plurality of memory ranks, and the third number is any value less than the total number of memory ranks in the plurality of memory ranks.

[0026] It can be understood that, for the case where the memory capacity of each rank is the same, the second usage threshold may include a third number of sub-thresholds, and the range of the sub-thresholds is a preset percentage of the memory capacity of a single rank. Here, the preset ratio may be any value between 0 and 100%.

[0027] Taking DDR including two ranks as an example, the memory capacity of the two ranks is the same, and the second usage threshold may include 1 sub-threshold, and the range of the sub-threshold is 1 / 2 of the preset proportion of the memory capacity of a single rank (for example, 80%). At this time, the third number is 1; accordingly, the transfer condition may include that the sum of the used capacity of the two ranks is less than 40% (80%*0.5) of the memory capacity of a single rank.

[0028] Taking DDR including four ranks as an example, the memory capacity of the four ranks is the same, and the second usage threshold may include two sub-thresholds, and the range of the sub-threshold is a preset proportion (for example, 80%) of the memory capacity of a single rank. For example, the two sub-thresholds may be 20% (80%*0.25) and 40% (80%*0.5) of the memory capacity of a single rank; at this time, the third number is 2; accordingly, the transfer conditions may include: the used capacity of the four ranks is less than 20% or 40% of the memory capacity of a single rank, respectively.

[0029] It can be understood that when the used capacity of each rank is less than any sub-threshold of the third number of sub-thresholds, the DDR is considered to meet the transfer condition. Among them, each rank can be less than a different sub-threshold.

[0030] In addition, in the case where the memory capacities of the ranks are not exactly the same, the second usage threshold may be a preset percentage of the memory capacity of any rank among the multiple ranks. Here, any rank may include a combination of one rank or multiple ranks. Specifically, the second usage threshold may be a preset percentage of the maximum memory capacity.

[0031] Thus, when the second usage threshold is the preset proportion of the mid-rank or the maximum memory capacity, When the second usage threshold is a single rank or a preset percentage of the maximum memory capacity, it can be guaranteed that at least one rank of data can be fully transferred to the rank with the largest memory capacity. When N-1 ranks are used, the data of N-1 ranks can be stored in one rank, thus minimizing the memory power consumption.

[0032] In some implementations of the first aspect above, the preset proportion is 80%.

[0033] It is understandable that 80% is a value derived from experience in actual applications. In different applications, the preset ratio may be larger or smaller than 80%. For example, when the preset ratio is 85% or 75%, the integrity and security of the data in the DDR can be ensured.

[0034] In some implementations of the first aspect above, after the DDR completes data transfer, the first memory column is in a closed state. If the electronic device detects new data to be stored, it can reopen the first memory column to save the new data to be stored; or, the electronic device can also determine whether to reopen the first memory column based on a judgment of the remaining capacity of the DDR and the battery power; or, the electronic device can also separate the hot and cold data stored in the DDR, delete the unpopular data in the stored data, and then save the new data to be stored. In this way, the storage demand for new data is met without reopening the first memory column, thereby avoiding increasing the power consumption of the DDR.

[0035] In addition, if the data transfer of DDR is triggered by force, for example, the data transfer of DDR is triggered based on the response to user operations, then even if the electronic device detects new data to be stored, the electronic device can directly discard the new data to be stored without saving it, so as to give priority to user operations and ensure user experience.

[0036] In some implementations of the first aspect above, the memory includes two memory ranks, and the memory management method further includes: randomly using one of the two memory ranks as the first memory rank and the other memory rank as the second memory rank.

[0037] It can be understood that if the electronic device determines that the DDR meets the transfer conditions, it can transfer the data in at least one rank (first memory column) to the remaining ranks (second memory columns). Here, the first memory column refers to the memory column that sends the transfer data, and the second memory column refers to the memory column that receives the transfer data. Taking the example of DDR including two ranks, the electronic device can randomly use any one of the two ranks as the first memory column and the other rank as the second memory column, and then transfer the data in the any one rank to the other rank.

[0038] In this way, data transfer can be completed quickly and easily using a random method.

[0039] In some implementations of the first aspect above, the memory includes two memory columns, and the memory management method also includes: according to the size relationship of the used capacity of each memory column, the memory column with the smaller used capacity of the two memory columns is used as the first memory column, and the memory column with the larger used capacity of the two memory columns is used as the second memory column.

[0040] It can be understood that the electronic device can transfer the data in the rank with less used capacity to the remaining ranks according to the size of the used capacity of each rank. Taking DDR including two ranks as an example, the electronic device can use the rank with smaller used capacity of the two ranks as the first memory column, and the rank with larger used capacity of the two memory columns as the second memory column, and then transfer the data in the first memory column to the second memory column. In this way, the amount of data to be transferred can be reduced, reducing the risk of data transfer.

[0041] In some implementations of the first aspect above, the memory includes more than two memory ranks, and the memory management method further includes: determining the second memory rank based on the sum of used capacities of the memory ranks and based on a size relationship between memory capacities of the memory ranks.

[0042] It can be understood that in the case where DDR contains multiple ranks, when transferring data, the electronic device can decide which rank to use as the first memory column and which rank to use as the second memory column based on the sum of the used capacity of each rank and the size relationship between the memory capacity of each rank.

[0043] In some implementations of the first aspect above, the memory includes four memory columns, and the size relationship between the memory capacity of each memory column includes the memory capacity of each memory column in the four memory columns arranged in order from small to large; the second memory column is determined based on the sum of the used capacity of each memory column and based on the size relationship between the memory capacity of each memory column, including: if the sum of the used capacity of each memory column is less than the memory capacity of the first memory column in the sorting, then one memory column is selected from the four memory columns as the second memory column; or, if the sum of the used capacity of each memory column is greater than or equal to the memory capacity of the first memory column in the sorting, and is less than the sum of the memory capacity of the first two memory columns in the sorting, then two memory columns are selected from the four memory columns as the second memory column; or, if the sum of the used capacity of each memory column is greater than or equal to the sum of the memory capacity of the first two memory columns in the sorting, and is less than the sum of the memory capacity of the first three memory columns, then three memory columns are selected from the four memory columns as the second memory column.

[0044] It can be understood that, taking DDR including four ranks as an example, the electronic device can sort the memory capacity of each rank from small to large, and then compare the sum of the used capacity of each rank with the memory capacity of the first rank, the sum of the memory capacity of the first two ranks, and the sum of the memory capacity of the first three ranks. If the sum of the used capacity of each rank is less than the memory capacity of the first rank, it means that the current amount of data is small and a single rank can complete the data storage task. Then, one rank is selected from the four ranks as the second memory column, and the other three ranks can all be used as the first memory column. In this way, DDR only uses a single rank to work, which can minimize the power consumption of DDR. If the sum of the used capacity of each rank is greater than or equal to the memory capacity of the first rank, and less than the sum of the memory capacity of the first two ranks, then two memory columns are selected from the four ranks as the second memory columns, and the other two ranks are selected as the first memory columns, that is, the data in the two ranks are transferred to the other two ranks. Alternatively, if the sum of the used capacities of each rank is greater than or equal to the sum of the memory capacities of the top two ranks, and is less than the sum of the memory capacities of the top three ranks, then three ranks are selected from the four ranks as the second memory column, and the other rank is selected as the first memory column, that is, only the data in one rank is transferred; in this way, while ensuring that the DDR memory capacity can meet the data storage requirements, DDR can work with two or three ranks to reduce DDR power consumption.

[0045] In some implementations of the first aspect above, obtaining the used capacity of each memory column in a plurality of memory columns includes: detecting that the electronic device is in a transfer state, and obtaining the used capacity of each memory column in the plurality of memory columns; wherein the transfer state includes at least one of a screen-off state, a low-power state, and a standby state.

[0046] It is understandable that when an electronic device is in a specific state such as the screen-off state, standby state, or low-power state, there are generally fewer data processing tasks and the amount of data required to be stored is smaller, which can usually be satisfied by less or even a single rank of memory capacity. Therefore, the electronic device can detect whether it is in a transfer state, and when it detects that it is in a transfer state, it can obtain the used capacity of each rank, and then judge the used capacity of each rank. In this way, the electronic device can timely reduce the number of ranks used for data storage in the DDR when the demand for memory capacity is small, so as to reduce the power consumption of the entire machine.

[0047] It can be understood that in addition to the above-mentioned screen-off state, standby state, and low-battery state, if the electronic device is in a state with low demand for memory capacity and an urgent need to save power consumption, the electronic device can be considered to be in a transfer state.

[0048] In some implementations of the first aspect above, the memory management method further includes: detecting a first instruction instructing data transfer to the memory, transferring data stored in a first memory column among the multiple memory columns to a second memory column among the multiple memory columns, and restricting access to the first memory column.

[0049] It is understandable that the electronic device may also forcefully trigger the data transfer process in certain specific circumstances. For example, the electronic device may respond to a first instruction triggered by a user and force data transfer, that is, directly transfer the data in the first memory column to the second memory column without determining whether the transfer condition is met. The first instruction includes but is not limited to a first voice instruction, a first touch instruction, or an instruction triggered by the user through other operation methods, and the specific form may be flexibly adjusted according to actual applications.

[0050] In some implementations of the first aspect above, the memory management method also includes: detecting that the battery power of the electronic device is lower than a power threshold, transferring data stored in a first memory column among the multiple memory columns to a second memory column among the multiple memory columns, and restricting access to the first memory column.

[0051] As mentioned above, the electronic device can also force triggering the data transfer process in some specific circumstances. Here, the electronic device can detect the battery power in real time, and when it detects that it is lower than the power threshold, it forces data transfer, that is, directly transfer the data in the first memory column to the second memory column without judging whether the transfer condition is met. Among them, the power threshold can be any power value that characterizes that the electronic device is in a low power state, such as 30%, 20%, 10%, etc., which is not limited in this application. In this way, in a low power state, by forcing data transfer, the DDR power consumption can be reduced to increase the battery life of the electronic device.

[0052] In a second aspect, an embodiment of the present application provides an electronic device, comprising: one or more processors; one or more memories; one or more memories storing one or more programs, and when one or more programs are executed by one or more processors, the electronic device executes the memory management method of the first aspect mentioned above.

[0053] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, on which instructions are stored. When the instructions are executed on a computer, the computer executes the memory management method of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1A This is a schematic diagram of the structure of the first DDR provided in the embodiment of the present application;

[0055] Figure 1B is a schematic diagram of the structure of a second DDR provided in an embodiment of the present application;

[0056] Figure 1C It is a schematic diagram of a working mode of a single-rank memory provided in an embodiment of the present application;

[0057] Figure 1D It is a schematic diagram of a working mode of a dual-rank memory provided in an embodiment of the present application;

[0058] Figure 2 It is a schematic diagram of the hardware structure of a mobile phone provided in an embodiment of the present application;

[0059] Figure 3 It is a flowchart of a memory management method provided in an embodiment of the present application;

[0060] Figure 4 is a schematic diagram of the structure of the third DDR provided in the embodiment of the present application;

[0061] Figure 5 This is the first specific embodiment of the memory management method provided in the embodiments of the present application;

[0062] Figure 6 This is a second specific embodiment of the memory management method provided in the embodiments of the present application;

[0063] Figure 7 This is a third specific embodiment of the memory management method provided in the embodiments of the present application;

[0064] Figure 8 This is the fourth specific embodiment of the memory management method provided in the embodiments of the present application;

[0065] Fig. 9 This is a schematic diagram of a display page in an electronic device provided in an embodiment of the present application;

[0066] Fig.10 It is a block diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0067] The illustrative embodiments of the present application include, but are not limited to, a memory management method, an electronic device, and a storage medium. The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0068] In order to more clearly understand the solution of the present application, the relevant field terms involved in the present application are first explained.

[0069] Random access memory (RAM): RAM can be used as internal memory for exchanging data directly with the CPU, and can also be called main memory (memory). It can be read and written at any time, and the speed is very fast. It is usually used as a temporary data storage medium for operating systems or other running programs. RAM can be divided into static random access memory and dynamic random access memory (DRAM). DRAM further includes SDRAM and double data rate synchronous dynamic random access memory (DDRSDRAM).

[0070] Among them, DRAM can only keep data for a short time. DRAM uses capacitors to store data. Since capacitors will gradually leak electricity, they must be refreshed at regular intervals. Refreshing means recharging the capacitors that store 1 regularly to replenish the leaked charge. It is also expressed that refreshing means periodically performing read and write operations on the capacitors. If the storage unit is not refreshed, the stored information will be lost.

[0071] SDRAM can keep the clock frequency the same as the system clock of the CPU front-end bus. In each clock cycle, the CPU will send a clock signal, and the SDRAM will respond to the rising or falling edge of the clock signal to read or write data.

[0072] DDR SDRAM: hereinafter referred to as DDR. Compared with SDRAM, SDRAM can only transmit data once in one clock cycle, while DDR can transmit data twice in one clock cycle, once on the rising edge and once on the falling edge, so that double data rate can be achieved without increasing the clock frequency.

[0073] In terms of physical structure, DDR consists of several memory chips / particles (such as DRAM chips) soldered on a circuit board. Among them, multiple memory chips / particles connected to the same chip select signal belong to the same memory rank. Rank is also commonly known as physical bank (P-Bank). At present, DDR can have single-rank DDR, dual-rank DDR, quad-rank DDR, etc., depending on the number of ranks.

[0074] The bit width of a single rank is equal to the sum of the bit widths of all memory chips in the rank. In addition, the bit width of a single rank must be consistent with the bit width of the CPU so that the CPU can access each rank independently. When the CPU accesses each rank, it can access all memory chips in the rank at the same time.

[0075] Taking a 64-bit CPU as an example, in order to fully utilize the processing performance of the CPU, the bit width of the data / control bus between the CPU and DDR is also 64 bits, that is, the CPU can send or read 64 bits of data to or from the DDR in one clock cycle. Correspondingly, the bit width of each rank should also be 64 bits. If the bit width of a single memory chip is less than 64 bits, for example, the bit width of a single memory chip is only 4 bits, 8 bits, 16 bits or 32 bits at present, it is necessary to connect multiple memory chips in parallel to form a data set with a bit width of 64 bits, forming a rank to exchange data with the CPU. For example, for a 16-bit memory chip, four 16-bit memory chips need to be connected in parallel to meet the work of a 64-bit CPU (16 bits × 4 = 64 bits). These four memory chips connected in parallel are called a rank.

[0076] To ensure communication with the CPU, each DDR contains at least one rank, and each rank contains multiple memory chips. Figure 1A and Figure 1B Two DDR structures are provided as examples, both of which take 64 bits per rank as an example. Figure 1A shows a single-rank memory, Figure 1A Each memory chip is 8 bits, and 8 memory chips (chip0, chip1, chip2...chip7) are connected in parallel on the circuit board to form a rank, and the bit width of the rank is 8*8 bits, 64 bits. Figure 1B A dual-rank memory is shown. Specifically, Figure 1BThe DDR shown is composed of 8 16-bit memory chips, among which the upper 4 memory chips (i.e., chip8, chip9, chip10, chip11) are connected in parallel to form rank0, and the lower 4 memory chips (i.e., chip12, chip13, chip14, chip15) are connected in parallel to form rank1. Here, the bit width of rank0 and rank1 are both 4*16bit, i.e., 64bit. The bit width of the entire DDR is the sum of the bit widths of rank0 and rank1, i.e., 128bit. However, since the data channel between DDR and CPU is currently only 64 bits wide, the CPU can only access one rank in the dual ranks at a time, such as the CPU can only access the above rank0 or rank1 at a time.

[0077] Combine the following Figure 1C and Figure 1D The working modes of the above two memory types, single-rank memory and dual-rank memory, are described respectively. Figure 1C As shown, a single-rank memory includes only one rank A, and only one chip select signal (signal CS_a) is needed to control rank A. When the CPU sends a chip select signal CS_a, it indicates that rank A is selected, and then the CPU can access the full nominal capacity of the memory through the data / control bus. Here, the full nominal capacity of the memory is the memory capacity of rank A. Figure 1D As shown, dual-rank memory requires two chip select signals (signal CS_a and signal CS_b) to control the two ranks (rank A and rank B) respectively. When the chip select signal sent by the CPU is signal CS_a, it means that rank A is selected. At this time, the memory capacity of rank A can be used, and the CPU can access rank A; when the chip select signal sent by the CPU is signal CS_b, it means that rank B is selected. At this time, the memory capacity of rank B can be used, and the CPU can access rank B; that is, the CPU can only access the memory capacity of rank A or the memory capacity of rank B through the data / control bus at a time. Here, the sum of the memory capacity of rank A and rank B is equal to the total nominal capacity of the memory. At present, in order to ensure a certain memory capacity, electronic devices such as mobile phones and tablets often use the following Figure 1B Dual-rank memory in .

[0078] As mentioned above, electronic devices mostly use DDR as memory to store the code and data required for CPU operation, and most of the current memory uses dual rank. Although dual rank can increase the nominal capacity of memory in electronic devices, it will increase the number of memory chips, or the bit width of a single memory chip will increase. The increase in the number of memory chips will directly lead to an increase in power supply and an increase in the number of refreshes. The increase in the bit width of a single memory chip will also lead to an increase in the number of refresh bits, which will increase memory power consumption and aggravate the heating of electronic devices. Taking mobile phones as an example, the power consumption of dual-rank memory when running is relatively large in the entire machine, about 10%-20%. Therefore, it is urgent to reduce the power consumption of memory when running in electronic devices such as mobile phones.

[0079] Based on this, an embodiment of the present application provides a memory management method. This method determines the used capacity of each rank in the memory when an electronic device containing multiple ranks (e.g., dual ranks, quad ranks, etc.) of memory is in a specific state (e.g., screen-off state, standby state, low-power state). After the judgment result is that the transfer condition is met, the data in at least one rank among the multiple ranks is transferred to the remaining ranks, and then the access to the ranks without data storage is stopped, thereby reducing the total power supply required for the entire memory and the number of memory chip refreshes.

[0080] It is understood that in some embodiments, the transfer condition may be that the sum of the used capacities of the ranks in the memory is less than the first usage threshold, or that the used capacities of at least N ranks in the memory are less than the second usage threshold. The transfer condition may also be a combination of one or more of the above situations.

[0081] Among them, the first usage threshold and the second usage threshold need to be determined based on the memory capacity of each rank, which will be explained in detail below and will not be repeated here.

[0082] Take an electronic device containing dual-rank memory as an example. When the electronic device enters a specific state such as the screen-off state, the standby state, the low-power state, etc., the used capacity of the first rank and the second rank in the dual rank is detected, and the used capacity of the first rank and the second rank is judged. After the judgment result satisfies the first transfer condition that the sum of the used capacity of the first rank and the used capacity of the second rank is less than the first usage threshold, and / or the second transfer condition that the used capacity of the first rank and the used capacity of the second rank are both less than the second usage threshold, the data in the first rank can be transferred to the second rank, or the data in the second rank can be transferred to the first rank. Exemplarily, assuming that the memory capacity of the first rank and the memory capacity of the second rank are the same, and both are 8GB, then the first usage threshold and the second usage threshold can be 8GB*0.8, that is, 6.4GB. Taking the transfer of data from the first rank to the second rank as an example, after the data transfer is completed, stop access to the first rank and disconnect the power supply of the first rank. In this way, dual-rank memory can work in the working mode of single-rank memory. In scenarios where the demand for memory capacity is not large and the amount of data processed is small, that is, low bandwidth, the number of ranks is reduced, the number of memory chips used is reduced, and the total power supply required for the entire memory and the number of memory chip refreshes are reduced, which can significantly reduce the power consumption of the memory.

[0083] It is understood that, in addition to the above-mentioned electronic device being able to automatically transfer data based on the judgment result of the used capacity of each rank in a specific state, the electronic device can also transfer data in at least one of the multiple ranks in response to the first instruction triggered by the user in any state. That is, in some embodiments, the transfer condition can also be the detection of the first instruction instructing to transfer data to the memory.

[0084] Before describing the memory management method of the embodiment of the present application in detail, the electronic device mentioned in the embodiment of the present application is first introduced. It can be understood that the electronic device in the embodiment of the present application can be a mobile phone, a computer, a virtual reality (VR) device, a tablet computer, a wearable device, an augmented reality (AR) device, a laptop computer and other electronic devices. The form of the electronic device in the embodiment of the present application is not specifically limited.

[0085] Taking the electronic device being a mobile phone as an example, the hardware structure diagram of the mobile phone 10 capable of implementing the method of the present application is introduced below.

[0086] like Figure 2As shown, the mobile phone 10 may include a processor 110, a power module 140, a memory 180, a mobile communication module 130, a wireless communication module 120, a sensor module 190, an audio module 150, a camera 170, an interface module 160, a button 101 and a display screen 102, etc.

[0087] It is to be understood that the structure illustrated in the embodiment of the present invention does not constitute a specific limitation on the mobile phone 10. In other embodiments of the present application, the mobile phone 10 may include more or fewer components than shown in the figure, or combine some components, or separate some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0088] The processor 110 may include one or more processing units, for example, a processing module or processing circuit including a CPU, a graphics processing unit (GPU), a digital signal processor (DSP), a microprocessor (MCU), an artificial intelligence (AI) processor, or a programmable logic device (field programmable gate array, FPGA). Among them, different processing units may be independent devices or integrated into one or more processors. A storage unit may be provided in the processor 110 for storing instructions and data. In some embodiments of the present application, the processor 110 may be used to execute the memory management method mentioned in the present application. The storage unit may store relevant instructions for executing the memory management method mentioned in the present application. The memory 180 may be a dual-rank memory, a quad-rank memory, or other multi-rank memory.

[0089] The power module 140 may include a power supply, a power management component, etc. The power supply may be a battery. The power management component is used to manage the charging of the power supply and the power supply to other modules. The mobile communication module 130 may include, but is not limited to, an antenna, a power amplifier, a filter, a low noise amplifier (LNA), etc. The mobile communication module 130 may provide a solution for wireless communications including 2G / 3G / 4G / 5G applied to the mobile phone 10. In some embodiments, the mobile communication module 130 and the wireless communication module 120 of the mobile phone 10 may also be located in the same module. The display screen 102 is used to display a human-computer interaction interface, images, videos, etc. The audio module 150 is used to convert digital audio information into an analog audio signal output, or to convert an analog audio input into a digital audio signal. The audio module 150 can also be used to encode and decode audio signals. The camera 170 is used to capture static images or videos.

[0090] It should be noted that the hardware functional components of the above-mentioned mobile phone 10 can be changed according to user needs. It can be understood that the specific embodiment introduced above is only a specific implementation method of the electronic device. Other ways to implement the embodiments of the present application are also within the scope of protection of the present application and will not be repeated here.

[0091] Figure 3 is a flow chart of a memory management method provided in an embodiment of the present application. The memory management method can be executed by a processor in an electronic device, and the memory of the electronic device includes at least two ranks. Figure 3 As shown, the memory management method may include:

[0092] S301: The processor detects the used capacity of each rank in at least two ranks.

[0093] It can be understood that the memory of the electronic device contains at least two ranks, and the processor needs to detect the used capacity of each rank. The used capacity of each rank can be the memory size currently used by each rank, or it can be the proportion of memory currently used by each rank.

[0094] In some embodiments, as described above, the processor can automatically detect the used capacity of each rank when the electronic device is in a specific state such as the screen-off state, standby state, or low-power state, and then determine the used capacity of each rank. Among them, in the screen-off state and standby state, the user will not use the electronic device, and the amount of data that the electronic device needs to process is small, or there is basically no data that needs to be processed, that is, the processor has a small demand for memory capacity, which is usually met by a small amount or even a single rank of memory capacity. Extra ranks will only increase unnecessary memory power consumption. In a low-power state, electronic devices need to reduce the power consumption of the entire device to increase the battery life of the electronic device.

[0095] It can be understood that in addition to the above-mentioned screen-off state, standby state, and low-battery state, in other situations where the demand for memory capacity is small and there is an urgent need to save power, the processor can automatically detect the used capacity of each rank to perform subsequent judgments.

[0096] In some embodiments, the processor may also execute S301 when a second instruction triggered by a user is detected. The second instruction is used to instruct the processor to detect the used capacity of each rank in at least two ranks. The second instruction includes but is not limited to a second voice instruction, a second touch instruction, or an instruction triggered by the user through other operation methods. That is, in some embodiments, the transfer condition of the present application may also include detecting a second instruction instructing to detect the used capacity of each rank in the memory.

[0097] 302: The processor determines whether the used capacity of each rank in at least two ranks meets the transfer condition, and determines whether the transfer condition is met. If the transfer condition is met, execute S303; otherwise, end the process.

[0098] In an embodiment of the present application, there are multiple ways for the processor to judge the used capacity of each rank. For example, it can judge whether the sum of the used capacities of each rank is less than a first usage threshold, or it can judge whether the used capacity of each rank is less than a second usage threshold separately.

[0099] The first usage threshold and the second usage threshold are determined according to the memory capacity of each rank and the number of ranks.

[0100] In some embodiments, if the memory capacity of each rank is the same, the memory capacity of a single rank can be 8GB, 12GB, 16GB, etc. The first usage threshold can be a preset proportion of the memory capacity of a preset number (first number) of ranks. The preset proportion can be any value between 0 and 100%, and can be specifically 80%. In this way, the transfer is performed when 80% of the memory capacity is reached, so that even after all the data in one rank is transferred to another rank, the amount of data in the other rank will not be too large, avoiding the transfer when 100% of the memory capacity is reached. This may cause another rank to automatically delete part of the data due to excessive storage of data, resulting in data loss. Therefore, setting a preset proportion can ensure data security. The preset number is an arbitrary number that is less than the number of ranks in the memory. The second usage threshold can be a preset proportion of the memory capacity of a preset number (third number) of ranks. The preset percentage is described above and will not be described here. N represents the number of ranks in the memory. When the second usage threshold is the preset percentage of the single-rank memory capacity, When the second usage threshold is the preset proportion of the single-rank memory capacity, it can be guaranteed that at least one rank of data can be transferred to other ranks, reducing memory power consumption. When N-1 ranks are used, the data of N-1 ranks can be stored in one rank, thus minimizing the memory power consumption.

[0101] It can be understood that the higher the first usage threshold and the second usage threshold, the easier it is to meet the transfer condition. Based on the experience of actual applications, in a dual-rank memory, the first usage threshold can be 80% of the memory capacity of a single rank. In this way, data security can be guaranteed, and the memory capacity can meet the needs of data processing. At the same time, memory power consumption is not wasted when the used capacity of the dual rank is low.

[0102] In some embodiments, if the memory capacity of each rank is different, the first usage threshold may be a preset proportion of the memory capacity of any rank among at least two ranks. Specifically, the first usage threshold may be a preset proportion of the first second number of larger memory capacities among at least two ranks. The first usage threshold may be a fixed value or a dynamically changing value. For example, the first usage threshold may change dynamically according to the actual power. The smaller the actual power, the larger the first usage threshold. The second usage threshold may be a preset proportion of the memory capacity of any rank among at least two ranks. Specifically, the second usage threshold may be a preset ratio of the maximum memory capacity in at least two ranks. When the second usage threshold is the preset percentage of the maximum memory capacity When the second usage threshold is the preset percentage of the maximum memory capacity, it can be guaranteed that at least one rank of data can be fully transferred to the rank with the largest memory capacity. When the data of N-1 ranks are stored in one rank, the memory power consumption can be minimized. The second usage threshold can be a fixed value or a dynamically changing value. For example, the second usage threshold can also change dynamically according to the actual power. The smaller the actual power, the larger the second usage threshold.

[0103] The following will introduce several different judgment methods and the transfer conditions corresponding to each judgment method, which will not be elaborated here.

[0104] In some embodiments, if the transfer condition is not met, the processor may re-execute S301 after a period of time after the process ends. For example, the processor may start timing when S302 is judged as no, and when the timing meets the preset duration, the used capacity of each rank is detected again to determine whether the used capacity of each rank meets the transfer condition. In this way, considering that when the electronic device has just entered a specific state such as the screen-off state, standby state, low-power state, etc., some data processing processes are still in progress, and the used capacity may still be large, and the transfer condition is not met. It takes a while to release the memory capacity. Therefore, the processor can count when it is judged that the transfer condition is not met for the first time or several times in a row, and judge again whether the transfer condition is met when the preset duration is reached. Among them, the preset duration can be set according to the actual application situation. For example, it can be a few minutes, a few seconds, a few milliseconds, etc., and this application does not limit this.

[0105] In some embodiments, if the transfer condition is not met, the processor can also detect the battery power of the electronic device in real time. When the processor detects that the battery power is less than the first power, S301 is re-executed. The first power can be any power value that represents a low power state, such as 30%, 20%, 10%, etc., which is not limited in this application. Alternatively, every time the processor detects that the battery power is reduced to a second power, S301 is re-executed. The second power can be 3%, 5%, 10% or any other value, which is not limited in this application.

[0106] S303: The processor controls the memory to transfer data so that data in at least one rank is transferred to the remaining ranks, and stops access to ranks without data storage.

[0107] In an embodiment of the present application, after the processor determines that the transfer condition is met based on the judgment of the used capacity of each rank, it can control the memory to transfer data so that the data in at least one rank is transferred to the remaining ranks. Here, there are multiple transfer methods. For example, the processor can control the memory to randomly transfer data in any rank to the remaining ranks, or transfer data in the rank with less used capacity to the remaining ranks. The transfer method will be explained in detail below and will not be repeated here.

[0108] It can be understood that stopping access to the rank without data storage, that is, disconnecting the power supply of the rank without data storage, does not require regular refresh of the memory chips in the rank, which reduces the total power required for the entire memory, thereby saving energy such as Figure 2 The power of the battery in the power module 140 shown increases the battery life of the electronic device.

[0109] In addition, as described above, the electronic device can also transfer data in at least one rank among multiple ranks in response to a first instruction triggered by the user in any state. The first instruction is used to instruct the processor to control the memory to transfer data, so that the data in at least one rank is transferred to the remaining ranks, and the access to the ranks without data storage is stopped. That is, when the processor detects the first instruction triggered by the user, it can directly execute S303 without executing the above S301 and S302. The first instruction may include but is not limited to a first voice instruction, a first touch instruction, or an instruction triggered by the user through other operation methods.

[0110] In some embodiments, after the processor controls the memory to transfer data, at least one rank in the memory is in a closed state. If the processor detects new data to be stored, the rank can be reopened to save the new data to be stored. Alternatively, the processor can also determine whether to reopen the rank based on the relationship between the amount of data to be stored and the remaining capacity of the memory. The remaining capacity of the memory is the sum of the remaining capacities of all ranks in the open state. Alternatively, the processor can also determine whether to reopen the rank based on a judgment of the battery power. When reopening the rank, one or more ranks that are in the closed state can be opened.

[0111] For example, when the processor detects new data to be stored, if the remaining capacity of the memory is less than or equal to the amount of data to be stored, the number of ranks to be opened is determined based on the amount of data to be stored; if the remaining capacity of the memory is greater than the amount of data to be stored, the ranks are not opened.

[0112] For another example, when the processor detects new data to be stored, if the battery power is less than the first power, the rank is not turned on; if it is greater than or equal to the first power, the number of ranks to be turned on is determined based on the amount of data to be stored.

[0113] In some embodiments, when the processor detects new data to be stored, it can also separate the stored data in the memory into hot and cold data, delete the unpopular data in the stored data, and release the memory capacity occupied by the unpopular data to save the new data to be stored. In this way, the storage requirements of the new data are met without reopening the first memory column, thereby avoiding increasing the DDR power consumption.

[0114] Specifically, when the processor performs cold and hot separation on the stored data, it can classify the stored data based on indicators such as data usage frequency, storage time, value, and business needs, and classify data with low usage frequency, long storage time, low value, or low business demand as cold data. It should be noted that this application does not limit the specific cold and hot separation method. In actual applications, other data classification methods can also be used to determine the data to be deleted.

[0115] In some embodiments, when the electronic device responds to a first instruction triggered by a user, controls the memory to transfer data, and makes at least one rank in a closed state, even if the electronic device detects new data to be stored, the rank is not reopened, and the data to be stored is directly discarded. In this way, user operations are prioritized to ensure user experience.

[0116] Figure 4 Schematic diagram of the structure of DDR in an electronic device provided in an embodiment of the present application. Figure 4 As shown, the DDR includes 12 memory chips (chip 1, chip 2, chip 3...chip 12), wherein chip 1 to chip 4 are connected to the same chip select signal (chip select 0 and CS0 shown in the figure), and chip 5 to chip 12 are connected to the same chip select signal (chip select 1 and CS1 shown in the figure). It can be understood that the DDR includes two ranks, namely the first rank includes chip 1 to chip 4, and the second rank includes chip 5 to chip 12. Among them, the memory capacity of each chip in chip 1 to chip 4 is 16GB, and the bit width is 16bit, therefore, the bit width of the first rank is 4*16bit, i.e. 64bit. The memory capacity of each chip in chip 5 to chip 12 is 16GB, and the bit width is 8bit, therefore, the bit width of the second rank is 8*8bit, i.e. 64bit.

[0117] Chips of different ranks can also be divided into different memory channels, and different memory channels can be addressed and read and write data by the processor separately. Figure 4As shown, chip 1, chip 5 and chip 6 belong to the same memory channel A, chip 2, chip 7 and chip 8 belong to the same memory channel B, chip 3, chip 9 and chip 10 belong to the same memory channel C, and chip 4, chip 11 and chip 12 belong to the same memory channel D. It can be understood that when the CPU selects CS0, chip 1 corresponding to CS0_A, chip 2 corresponding to CS0_B, chip 3 corresponding to CS0_C, and chip 4 corresponding to CS0_D, that is, the chips connected to chip select 0 in memory channel A to memory channel D can be accessed at the same time. When the CPU selects CS1, chip 5 and chip 6 corresponding to CS1_A, chip 7 and chip 8 corresponding to CS1_B, chip 9 and chip 10 corresponding to CS1_C, and chip 11 and chip 12 corresponding to CS1_D, that is, the chips connected to chip select 1 in memory channel A to memory channel D can be accessed at the same time.

[0118] In addition, DDR also includes other control signals such as reset signal and control signal. Figure 4 The RESET_N signal in is used to control the reset of chip 1 to chip 12. The ZQ_A_C signal is used to control the calibration of each chip in memory channel A and memory channel C, and the ZQ_B_D signal is used to control the calibration of each chip in memory channel B and memory channel D. CK_T_X and CK_C_X are the differential clock signals of each memory channel X (X is A / B / C / D). WCK[1:0]_T_X and WCK[1:0]_C_X are the write clock signals of each memory channel X. CA[6:0]_X is the signal of each memory channel for providing instruction and address input. The DQ signal is the data signal of each chip, the RDQS signal is the synchronization signal corresponding to the read operation of each chip, and the DMI signal is the data mask inversion signal of each chip. The specific functions of the above-mentioned various signals can be referred to the relevant information of DDR, and this application will not provide detailed descriptions of each signal.

[0119] The following describes a specific embodiment of the memory management method of the present application.

[0120] Figure 5 This is a specific embodiment of the memory management method provided in the embodiment of the present application. Taking the application of dual-rank memory as an example, the memory management method in this embodiment may specifically include:

[0121] S501: The processor detects the used capacity of the first rank and the used capacity of the second rank.

[0122] Here, S501 can refer to the above description of S301. The processor can automatically detect the used capacity of the first rank and the used capacity of the second rank when the electronic device is in specific states such as screen off state, standby state, low power state, etc., and can also respond to the second instruction in any state to detect the used capacity of the first rank and the used capacity of the second rank.

[0123] S502: The processor determines whether the sum of the used capacity of the first rank and the used capacity of the second rank is less than the first usage threshold. If the sum of the used capacity of the first rank and the used capacity of the second rank is less than the first usage threshold, execute S503; otherwise, end the process.

[0124] It can be understood that the transfer condition here is that the sum of the used capacity of the first rank and the used capacity of the second rank is less than the first usage threshold.

[0125] Regarding the setting of the first usage threshold, in some embodiments, when the memory capacity of the first rank and the second rank is the same, the first usage threshold can be 80% of the memory capacity of a single rank. Here, 80% is only a possible example, as described above, it can be any percentage between 0 and 100%. For example, if the memory capacity of a single rank is 8GB, 12GB, 16GB, etc., then the first usage threshold can be 6.4GB, 9.6GB, 12.8GB, etc.

[0126] In some embodiments, when the memory capacity of the first rank and the second rank are different, the first usage threshold can be 80% of the larger memory capacity. Here, 80% is only a possible example, as described above, it can be any percentage between 0 and 100%. Exemplarily, the memory capacity of the first rank is 64GB, and the memory capacity of the second rank is 128GB. Then, the first usage threshold can be 128*0.8, that is, 102.4GB.

[0127] In some embodiments, the first usage threshold can change dynamically, for example, the first usage threshold increases as the actual power of the electronic device decreases. For example, as the actual power decreases, the first usage threshold can increase linearly or nonlinearly. Taking the memory capacity of each rank as the same, and the memory capacity of a single rank as 16GB as an example, at the first moment, the initial value of the first usage threshold can be 0GB, and the actual power is 100%; at the second moment, the actual power becomes 80%, and accordingly, the first usage threshold becomes 3GB; at the nth moment, the actual power becomes 20%, and accordingly, the first usage threshold becomes 12.8GB; in this way, the judgment conditions are tightened and the probability of data transfer is increased, so that the loss caused by memory can be saved in a timely manner as the power of the electronic device gradually decreases.

[0128] In some embodiments, if the sum of the used capacity of the first rank and the used capacity of the second rank is greater than or equal to the first usage threshold, the process is terminated. After a period of time after the process is terminated, or when it is detected that the battery power is lower than the first power, or each time the battery power is detected to be lower than the second power, the processor can re-execute S501.

[0129] Specifically, the processor may start timing when it determines that the sum of the used capacity of the first rank and the used capacity of the second rank is greater than or equal to the first usage threshold. When the timing meets the preset duration, the processor again detects the used capacity of the first rank and the used capacity of the second rank, and determines whether the sum of the used capacity of the first rank and the used capacity of the second rank is less than the first usage threshold, that is, the above steps S501 and S502 are executed in a loop until it is determined that the sum of the used capacity of the first rank and the used capacity of the second rank is less than the first usage threshold.

[0130] S503: The processor controls the memory to transfer data, so that the data in the first rank is transferred to the second rank, or the data in the second rank is transferred to the first rank, and stops access to the rank without data storage.

[0131] In some embodiments, when the memory capacities of the first rank and the second rank are the same, the data in the first rank can be transferred to the second rank and then the access to the first rank can be stopped; the data in the second rank can also be transferred to the first rank and then the access to the second rank can be stopped. That is, the data in one rank is randomly transferred to another rank. Alternatively, according to the used capacity of the first rank and the used capacity of the second rank, the data in the rank with smaller used capacity is transferred to another rank.

[0132] In some embodiments, when the memory capacities of the first rank and the second rank are different, the data transfer method between the first rank and the second rank is determined based on the sum of the used capacities of the first rank and the second rank and the size relationship between the memory capacity of the first rank and the memory capacity of the second rank.

[0133] Specifically, if the sum of the used capacity of the first rank and the second rank is less than or equal to the smaller memory capacity of the first rank and the second rank, the data in any rank can be randomly transferred to another rank; if the sum of the used capacity of the first rank and the second rank is greater than the smaller memory capacity, the data in the rank corresponding to the smaller memory capacity is directly transferred to another rank, and access to the rank corresponding to the smaller memory capacity is stopped.

[0134] For example, if the memory capacity of the first rank is 64GB and the memory capacity of the second rank is 128GB, if the sum of the used capacity of the first rank and the second rank (for example, 60GB) is less than or equal to 64GB, the data in the first rank can be transferred to the second rank, and then the access to the first rank can be stopped, or the data in the second rank can be transferred to the first rank, and then the access to the second rank can be stopped; if the sum of the used capacity of the first rank and the second rank (for example, 80GB) is greater than 64GB, the data in the first rank can be directly transferred to the second rank, and then the access to the first rank can be stopped.

[0135] It can be understood that since it has been determined that the first rank and the second rank meet the transfer conditions, for example, the sum of the used capacity of the first rank and the used capacity of the second rank is less than the first usage threshold, therefore, when performing data transfer, the sum of the used capacity of the first rank and the second rank can be directly compared with the memory capacity of the first rank and the memory capacity of the second rank, without having to compare with the preset proportion of the memory capacity of the first rank (for example, 80%) and the preset proportion of the memory capacity of the second rank. In this way, the judgment process can be simplified, the amount of data calculation in the data transfer process can be reduced, and the transfer of memory data can be accelerated.

[0136] The above-mentioned embodiment of the memory management method applied to dual-rank memory is also applicable to quad-rank memory or other multi-rank memory. Taking quad-rank memory as an example, the memory management method of the present application may include the following: Figure 6 The following steps are shown:

[0137] S601: The processor detects the used capacity of each rank in the first rank, the second rank, the third rank and the fourth rank.

[0138] Here, S601 can refer to the above description of S501 and S301, which will not be repeated here.

[0139] S602: The processor determines whether the sum of the used capacity of each rank is less than the first usage threshold. If the sum of the used capacity of each rank is less than the first usage threshold, execute S603; otherwise, end the process.

[0140] It can be understood that the transfer condition here is that the sum of the used capacity of each rank in the first rank, the second rank, the third rank and the fourth rank is less than the first usage threshold.

[0141] Regarding the setting of the first usage threshold, in some embodiments, when the memory capacity of each rank in the first rank, the second rank, the third rank, and the fourth rank is the same, the first usage threshold may include at least one sub-threshold of 80% of the memory capacity of a single rank, 80% of the memory capacity of two ranks, and 80% of the memory capacity of three ranks. Here, 80% is only a possible example, as described above, it can be any percentage between 0 and 100%. Exemplarily, if the memory capacity of a single rank is 8GB, taking the example that the first usage threshold includes three sub-thresholds, the three sub-thresholds can specifically be 6.4GB, 12.8GB, and 19.2GB.

[0142] Taking the example that the first usage threshold includes three sub-thresholds, correspondingly, the above transfer condition can be that the sum of the used capacity of each rank is less than any one of the three sub-thresholds. The three sub-thresholds are the maximum sub-threshold, the middle sub-threshold and the minimum sub-threshold. That is, the transfer condition includes three sub-conditions, and the three sub-conditions are that the sum of the used capacity of each rank is less than the minimum sub-threshold, the sum of the used capacity of each rank is greater than or equal to the minimum sub-threshold and less than the middle sub-threshold, and the sum of the used capacity of each rank is greater than or equal to the middle sub-threshold and less than the maximum sub-threshold.

[0143] It can be understood that in a multi-rank memory, if the memory capacity of each rank is the same, the first usage threshold may include at least one of N-1 sub-thresholds, where N represents the number of ranks. The N-1 sub-thresholds are 80% of the memory capacity of a single rank, 80% of the memory capacity of two ranks, and so on. 80% of the memory capacity of N-1 ranks. Here, 80% is only a possible example, as mentioned above, it can be any percentage between 0 and 100%.

[0144] In some embodiments, when the memory capacity of each rank in the first rank, the second rank, the third rank and the fourth rank is not exactly the same, the first usage threshold may include at least one sub-threshold of 80% of the maximum memory capacity, 80% of the sum of the two larger memory capacities, and 80% of the sum of the three larger memory capacities. Here, 80% is only a possible example, as described above, it can be any percentage between 0 and 100%. For example, if the memory capacity of the first rank is 8GB, the memory capacity of the second rank is 12GB, the memory capacity of the third rank is 16GB, and the memory capacity of the fourth rank is 24GB, taking the first usage threshold including three sub-thresholds as an example, the three sub-thresholds can specifically be 0.8*24GB, 0.8*16GB, and 0.8*12GB.

[0145] Taking the example that the first usage threshold includes three sub-thresholds, correspondingly, the above transfer condition can be that the sum of the used capacity of each rank is less than any one of the three sub-thresholds. The three sub-thresholds are the maximum sub-threshold, the middle sub-threshold and the minimum sub-threshold. That is, the transfer condition includes three sub-conditions, and the three sub-conditions are that the sum of the used capacity of each rank is less than the minimum sub-threshold, the sum of the used capacity of each rank is greater than or equal to the minimum sub-threshold and less than the middle sub-threshold, and the sum of the used capacity of each rank is greater than or equal to the middle sub-threshold and less than the maximum sub-threshold.

[0146] It can be understood that in a multi-rank memory, if the memory capacity of each rank is not exactly the same, the first usage threshold may include at least one of the N-1 sub-thresholds, where N represents the number of ranks. The N-1 sub-thresholds are, respectively, 80% of the maximum memory capacity, 80% of the sum of the two larger memory capacities, 80% of the sum of the three larger memory capacities... 80% of the sum of the N-1 larger memory capacities. It should be noted that the N-1 sub-thresholds can be 80% of the memory capacity of any rank. For example, the N-1 sub-thresholds can also include at least one sub-threshold of 80% of the minimum memory capacity, 80% of the sum of the two smaller memory capacities, and 80% of the sum of the three smaller memory capacities. Here, 80% is only a possible example. As mentioned above, it can be any percentage between 0 and 100%.

[0147] In some embodiments, if the sum of the used capacity of each rank in the first rank, the second rank, the third rank, and the fourth rank is greater than or equal to the first usage threshold, the process is terminated. After a period of time after the process is terminated, or when it is detected that the battery power is lower than the first power level, or each time it is detected that the battery power is lower than the second power level, the processor can re-execute S601.

[0148] S603: The processor controls the memory to transfer data so that data in ranks other than the target rank is transferred to the target rank, and stops access to ranks without data storage.

[0149] Among them, the memory capacity of the target rank needs to meet the used capacity of each rank. The target rank described in this application is also the second memory column described in this application.

[0150] In some embodiments, when the memory capacity of each rank in the first rank, the second rank, the third rank and the fourth rank is the same, the target rank and the data transfer method between the ranks are determined based on the sum of the used capacity of each rank and the memory capacity of a single rank.

[0151] Specifically, if the sum of the used capacities of each rank is less than the memory capacity of a single rank, a rank is randomly selected as the target rank, the data in the remaining three ranks are transferred to the target rank, and access to the three ranks without data storage is stopped. Assuming the memory capacity of a single rank is 8GB, if the sum of the used capacities of each rank is less than 8GB, a rank is randomly selected as the target rank, the data in the remaining three ranks are transferred to the target rank, and access to the three ranks without data storage is stopped.

[0152] If the sum of the used capacity of each rank is greater than or equal to the memory capacity of a single rank and less than the memory capacity of two ranks, for example, the sum of the used capacity of each rank (for example, 10GB) is greater than or equal to 8GB and less than 16GB, then two random ranks are used as target ranks, the data in the remaining two ranks are transferred to the target ranks, and access to the two ranks without data storage is stopped.

[0153] If the sum of the used capacity of each rank is greater than or equal to the memory capacity of two ranks and less than the memory capacity of three ranks, for example, the sum of the used capacity of each rank (for example, 20GB) is greater than or equal to 16GB and less than 24GB, then three random ranks are used as target ranks, the data in the remaining rank is transferred to the target rank, and access to a rank with no data storage is stopped.

[0154] It can be understood that since it has been determined that the first rank, the second rank, the third rank and the fourth rank meet the transfer conditions, for example, the sum of the used capacity of each rank in the first rank, the second rank, the third rank and the fourth rank is less than the first usage threshold, therefore, when performing data transfer, the sum of the used capacity of each rank can be directly compared with the memory capacity of a single rank, the memory capacity of two ranks, and the memory capacity of three ranks, without having to compare with the preset proportion of the memory capacity of a single rank (for example, 80%), the preset proportion of the memory capacity of two ranks, and the preset proportion of the memory capacity of three ranks. In this way, the complexity of the comparison process can be reduced, the amount of data calculation in the data transfer process can be reduced, and the transfer of memory data can be accelerated.

[0155] In some embodiments, when the memory capacity of each rank in the first rank, the second rank, the third rank and the fourth rank is not exactly the same, the target rank and the data transfer method between the ranks are determined based on the sum of the used capacity of each rank and the memory capacity of each rank.

[0156] Specifically, the memory capacity of each rank is sorted from small to large, and then the sum of the used capacity of each rank is compared with the memory capacity of the first rank, the sum of the memory capacity of the first two rank, and the sum of the memory capacity of the first three rank, and the target rank is determined based on the comparison results.

[0157] Specifically, if the sum of the used capacities of all ranks is less than the memory capacity of the first ranked rank, a rank is randomly selected as the target rank, the data in the remaining three ranks are transferred to the target rank, and access to the three ranks without data storage is stopped. For example, the memory capacities of the first rank, second rank, third rank, and fourth rank are 8GB, 12GB, 16GB, and 24GB, respectively. If the sum of the used capacities of all ranks is less than 8G, a rank is randomly selected as the target rank, the data in the remaining three ranks are transferred to the target rank, and access to the three ranks without data storage is stopped.

[0158] If the sum of the used capacity of each rank is greater than or equal to the memory capacity of the first rank in the ranking, and less than the sum of the memory capacity of the first two ranks, for example, the sum of the used capacity of each rank (for example, 16GB) is greater than or equal to 8GB, and less than 20B, then two ranks are randomly selected as target ranks, the data in the remaining two ranks are transferred to the target ranks, and access to the two ranks without data storage is stopped.

[0159] If the sum of the used capacity of each rank is greater than or equal to the sum of the memory capacity of the first two ranks and less than the sum of the memory capacity of the first three ranks, for example, the sum of the used capacity of each rank (for example, 24GB) is greater than or equal to 20GB and less than 36GB, then three random ranks are used as target ranks, the data in the remaining rank is transferred to the target rank, and access to a rank with no data storage is stopped.

[0160] It can be understood that since it has been determined that the first rank, the second rank, the third rank and the fourth rank meet the transfer conditions, for example, the sum of the used capacity of each rank in the first rank, the second rank, the third rank and the fourth rank is less than the first usage threshold, therefore, when performing data transfer, the sum of the used capacity of each rank can be directly compared with the memory capacity of the first rank, the sum of the memory capacity of the first two ranks, and the sum of the memory capacity of the first three ranks, without having to compare with the preset proportion of the memory capacity of the first rank (for example, 80%), the preset proportion of the memory capacity of the first two ranks, and the preset proportion of the memory capacity in the top three ranks. In this way, the complexity of the comparison process can be reduced, the amount of data calculation in the data transfer process can be reduced, and the transfer of memory data can be accelerated.

[0161] It should be noted that the above embodiment adopts a random selection method when selecting the target rank. In other embodiments, the rank with a larger used capacity can be preferentially selected as the target rank to reduce the amount of data transfer. The above data transfer method applied to four-rank memory is also applicable to other multi-rank memories, and this application will not elaborate on it.

[0162] Figure 7 This is another specific embodiment of the memory management method provided in the embodiment of the present application. Taking the application of dual-rank memory as an example, the memory management method in this embodiment may specifically include:

[0163] S701: The processor detects the used capacity of the first rank and the used capacity of the second rank.

[0164] Here, S701 refers to the above description of S301 and S501, which will not be repeated here.

[0165] S702: The processor determines whether the used capacity of the first rank and the used capacity of the second rank are both less than the second usage threshold. If the used capacity of the first rank and the used capacity of the second rank are both less than the second usage threshold, execute S703; otherwise, end the process.

[0166] It can be understood that the transfer condition here is that the used capacity of the first rank and the used capacity of the second rank are respectively less than the second usage threshold.

[0167] Regarding the setting of the second usage threshold, in some embodiments, when the memory capacity of the first rank and the second rank are the same, the second usage threshold can be 80% of the memory capacity of a single rank. To ensure that the data of two ranks can be stored in one of the ranks, while ensuring the security of the data after transfer. Here, 80% is only a possible example. As mentioned above, it can be any percentage between 0 and 100%. For example, if the memory capacity of a single rank is 8GB, 12GB, 16GB, etc., then the second usage threshold can be 3.2GB, 4.8GB, 6.4GB, etc.

[0168] In some embodiments, when the memory capacities of the first rank and the second rank are different, the second usage threshold may be 80% of the larger memory capacity. Here, 80% is just a possible example. As mentioned above, it can be any percentage between 0 and 100%. For example, the memory capacity of the first rank is 64GB, and the memory capacity of the second rank is 128GB. Then, the second usage threshold can be 128*0.5*0.8, that is, 51.2GB.

[0169] In some embodiments, the second usage threshold may change dynamically. For example, the second usage threshold may change with the actual power of the electronic device. For details, please refer to the above embodiment in which the first usage threshold changes with the actual power, which will not be repeated here.

[0170] In some embodiments, if the used capacity of the first rank and the used capacity of the second rank are respectively greater than or equal to the second usage threshold, the process ends. After a period of time after the process ends, if the electronic device is still in a specific state such as the screen off state, standby state, low power, etc., the processor can re-execute S701. That is, the processor can repeatedly execute steps S701 and S702 according to a cycle.

[0171] Specifically, the processor may start timing when it determines that the used capacity of the first rank and the used capacity of the second rank are respectively greater than or equal to the second usage threshold. When the timing meets the preset duration, the processor again detects the used capacity of the first rank and the used capacity of the second rank, and determines whether the used capacity of the first rank and the used capacity of the second rank are respectively less than the second usage threshold, that is, the above steps S701 and S702 are executed in a loop until it is determined that the used capacity of the first rank and the used capacity of the second rank are respectively less than the second usage threshold.

[0172] S703: The processor controls the memory to transfer data, so that the data in the first rank is transferred to the second rank, or the data in the second rank is transferred to the first rank, and stops access to the rank without data storage.

[0173] Specifically, S703 may refer to the embodiment of S503 above, which will not be described in detail here.

[0174] The above-mentioned embodiment of the memory management method applied to the dual-rank memory of the present application is also applicable to the quad-rank memory or other multi-rank memory. Taking the quad-rank memory as an example, the memory management method of the present application may include the following: Figure 8 The following steps are shown:

[0175] S801: The processor detects the used capacity of each rank in the first rank, the second rank, the third rank and the fourth rank.

[0176] Here, S801 can refer to the above description of S501 and S301, which will not be repeated here.

[0177] S802: The processor determines whether the used capacity of each rank is less than the second usage threshold. If the used capacity of each rank is less than the second usage threshold, execute S803; otherwise, end the process.

[0178] Regarding the setting of the second usage threshold, in some embodiments, when the memory capacity of each rank in the first rank, the second rank, the third rank, and the fourth rank is the same, the second usage threshold may include 80% of the memory capacity of a single rank. Here, 80% is only a possible example. As mentioned above, it can be any percentage between 0 and 100%. For example, if the memory capacity of a single rank is 8GB, the second usage threshold may include other sub-thresholds such as 8*0.8*(2 / 3)≈4.3GB and 1.6GB(8*0.8*0.25).

[0179] Taking the second usage threshold including three sub-thresholds as an example, correspondingly, the above transfer condition can be understood as that the used capacity of each rank is less than any one of the three sub-thresholds. Each rank can be less than a different sub-threshold.

[0180] In some embodiments, when the memory capacities of the first rank, the second rank, the third rank, and the fourth rank are not exactly the same, the second usage threshold may be 80% of the maximum memory capacity. Here, 80% is only a possible example, as mentioned above, it can be any percentage between 0 and 100%. For example, if the memory capacity of the first rank is 8GB, the memory capacity of the second rank is 12GB, the memory capacity of the third rank is 16GB, and the memory capacity of the fourth rank is 16GB, the second usage threshold can be 3.2GB (16*0.8*0.25), 6.4GB (16*0.8*0.5), or other sub-thresholds.

[0181] In addition, in some embodiments, the second usage threshold may also be 80% of the memory capacity of any of the first rank, the second rank, the third rank, and the fourth rank. This application does not limit this.

[0182] In some embodiments, if the used capacity in the first rank, the second rank, the third rank, and the fourth rank is greater than or equal to the second usage threshold, the process is terminated. After a period of time after the process is terminated, or when it is detected that the battery power is lower than the first power, or each time the battery power is detected to be lower than the second power, the processor can re-execute S801.

[0183] S803: The processor controls the memory to transfer data so that data in ranks other than the target rank is transferred to the target rank, and stops access to ranks without data storage.

[0184] Specifically, S803 may refer to the embodiment of S603 above, which will not be described in detail here.

[0185] As described above, the electronic device can also transfer data in at least one of the multiple ranks in response to a first instruction triggered by a user in any state, that is, transfer data stored in a first memory column among the multiple memory columns to a second memory column among the multiple memory columns, and restrict access to the first memory column.

[0186] In some embodiments, the first instruction may be a first touch instruction. Fig. 9 An embodiment of transferring data in at least one rank among multiple ranks in response to a first touch instruction is introduced.

[0187] In addition, in some embodiments, the processor may also transfer data in at least one of the multiple ranks when detecting that the battery power of the electronic device is lower than the power threshold, that is, transfer data stored in a first memory column among the multiple memory columns to a second memory column among the multiple memory columns, and restrict access to the first memory column.

[0188] Fig. 9It is a schematic diagram of a display page 90 in an electronic device provided in an embodiment of the present application. In the display page 90, some auxiliary functions of the electronic device (auxiliary function 1, auxiliary function 2...) are displayed. The user can jump to the page by clicking on the options of each auxiliary function, and then set each auxiliary function. At the same time, the display page 90 also provides an option 901 for low-power single-rank mode and a corresponding control 901a in the option. The user can trigger the generation of a first touch instruction by clicking on the control 901a, so that when the processor detects that the first touch instruction indicates to turn on the low-power single-rank mode, it directly controls the memory to enter the low-power single-rank mode, without judging the used capacity of each rank, and transferring the data in all ranks to one rank to realize the low-power single-rank mode. In this low-power single-rank mode, the memory uses this rank to interact with the processor for data. It can be understood that when the processor detects that the first touch instruction indicates to turn on the low-power single-rank mode, there is no need to execute S301~S303, S501~S503, S601~S603, S701~S703 and S801~S803 in the embodiment. The processor can execute S301~S303, S501~S503, S601~S603, S701~S703 or S801~S803 when it detects that the first touch instruction indicates to turn off the low-power single-rank mode.

[0189] Fig.10 This is a block diagram of an electronic device 100 provided in an embodiment of the present application. The electronic device 100 may include two processors (processor 1 and processor 2) and a memory including four ranks (rank 1 to rank 4). Each rank has an independent clock signal and data processing function. Each processor can control the working mode of the four-rank memory through the bus, such as shutting down a rank through the Power Down instruction, and controlling the rank to perform a self-refresh operation through the SelfRefresh instruction. It can also determine through the bus which physical direct line to send the chip select signal, and then control the corresponding memory interface to wake up the corresponding rank to enter the working state.

[0190] Compared with the solution in the related art for reducing DDR power consumption, which is mainly through limiting the operating frequency or operating voltage of the memory, which may affect the data response speed of the memory or cause the memory to lose data, the memory management method of the embodiment of the present application controls the working mode of DDR when the electronic device is in a specific state, such as switching the dual-rank working mode to the single-rank working mode. By reducing the number of ranks used, the memory power consumption can be reduced without affecting the write and read operations of the memory. It is suitable for all electronic devices with large-capacity DDR containing multiple ranks.

[0191] The various embodiments disclosed in this application may be implemented in hardware, software, firmware, or a combination of these implementation methods. The embodiments of this application may be implemented as a computer program or program code executed on a programmable system, the programmable system comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0192] Program code can be applied to input instructions to perform the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor such as, for example, a DSP, a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0193] Program code can be implemented with high-level programming language or object-oriented programming language to communicate with the processing system. When necessary, program code can also be implemented with assembly language or machine language. In fact, the mechanism described in this application is not limited to the scope of any specific programming language. In either case, the language can be a compiled language or an interpreted language.

[0194] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, instructions may be distributed over a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine (e.g., computer) readable form, including, but not limited to, floppy disks, optical disks, optical disks, read-only memories (CD-ROMs), magneto-optical disks, read-only memories (ROMs), RAM, erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or a tangible machine-readable memory for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in electrical, optical, acoustic, or other forms of propagation signals. Therefore, machine-readable media include any type of machine-readable media suitable for storing or transmitting electronic instructions or information in a machine (e.g., computer) readable form.

[0195] In the accompanying drawings, some structural or method features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be required. Instead, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of structural or method features in a particular figure does not mean that such features are required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0196] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation method of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce units / modules that are not closely related to solving the technical problems proposed by the present application, which does not mean that there are no other units / modules in the above-mentioned device embodiments.

[0197] It should be noted that, in the examples and description of the present application, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the statement "comprise one" do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

[0198] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the present application.

Claims

1. A memory management method, applied to an electronic device, characterized in that: The electronic device includes a memory, the memory including a plurality of memory ranks; and The method comprises: Get the used capacity of each memory column in multiple memory columns; Determining whether the memory meets a transfer condition based on the used capacity and the use threshold of each memory column; If it is determined that the memory satisfies the transfer condition, data stored in a first memory column among the multiple memory columns is transferred to a second memory column among the multiple memory columns, and access to the first memory column is restricted; The usage threshold includes a second usage threshold, and the transfer condition includes that the used capacity of each memory column is less than the second usage threshold; Furthermore, in the case where the memory capacities of the memory ranks are the same, the second usage threshold includes a third number of sub-thresholds, and the range of the sub-thresholds is a preset percentage of the memory capacity of a single memory rank. Wherein, N is the total number of memory ranks in the plurality of memory ranks, and the third number is any value smaller than the total number of memory ranks in the plurality of memory ranks.

2. The memory management method according to claim 1, characterized in that: The usage threshold includes a first usage threshold, and the transfer condition includes that a sum of used capacities of the memory ranks is less than the first usage threshold.

3. The memory management method according to claim 2, characterized in that: In the case where the memory capacities of the memory ranks are the same, the first usage threshold includes a preset proportion of the memory capacities of a first number of memory ranks, where the first number is any value less than the total number of memory ranks.

4. The memory management method according to claim 2, characterized in that: When the memory capacities of the memory columns are not exactly the same, the first usage threshold includes a preset proportion of the first second number of larger memory capacities among the multiple memory columns, and the second number is any value less than the total number of memory columns among the multiple memory columns.

5. The memory management method according to any one of claims 1 to 4, characterized in that: The preset proportion is 80%.

6. The memory management method according to claim 1 or 2, characterized in that: The memory includes two memory ranks, and the method further includes: One of the two memory ranks is randomly selected as the first memory rank, and the other memory rank is randomly selected as the second memory rank.

7. The memory management method according to claim 1 or 2, characterized in that: The memory includes two memory ranks, and the method further includes: According to the size relationship of the used capacities of the memory ranks, the memory rank with the smaller used capacity of the two memory ranks is used as the first memory rank, and the memory rank with the larger used capacity of the two memory ranks is used as the second memory rank.

8. The memory management method according to claim 1, characterized in that: The memory includes more than two memory ranks, and the method further includes: The second memory rank is determined based on the sum of used capacities of the memory ranks and based on a size relationship between memory capacities of the memory ranks.

9. The memory management method according to claim 8, characterized in that: The memory includes four memory columns, and the size relationship between the memory capacities of the memory columns includes the memory capacities of the memory columns of the four memory columns arranged in ascending order; The determining the second memory rank based on the sum of the used capacities of the memory ranks and based on the size relationship between the memory capacities of the memory ranks comprises: If the sum of the used capacities of the memory ranks is less than the capacity of the memory ranked first, selecting a memory rank from the four memory ranks as the second memory rank; Or, if the sum of the used capacities of the memory columns is greater than or equal to the memory capacity of the first memory column in the sorting, and less than the sum of the memory capacities of the first two memory columns in the sorting, two memory columns are selected from the four memory columns as the second memory columns; Or; if the sum of the used capacities of the memory columns is greater than or equal to the sum of the memory capacities of the top two memory columns in the sorting, and less than the sum of the memory capacities of the top three memory columns, three memory columns are selected from the four memory columns as the second memory columns.

10. The memory management method according to claim 1, characterized in that: The obtaining of the used capacity of each memory column in the plurality of memory columns comprises: detecting that the electronic device is in a transfer state, and obtaining a used capacity of each memory column in a plurality of memory columns; The transfer state includes at least one of a screen-off state, a low-battery state, and a standby state.

11. The memory management method according to claim 1, characterized in that: The method further comprises: A first instruction instructing to transfer data to the memory is detected, data stored in a first memory rank among the plurality of memory ranks is transferred to a second memory rank among the plurality of memory ranks, and access to the first memory rank is restricted.

12. The memory management method according to claim 1, characterized in that: The method further comprises: It is detected that the battery power of the electronic device is lower than a power threshold, data stored in a first memory column among the multiple memory columns is transferred to a second memory column among the multiple memory columns, and access to the first memory column is restricted.

13. An electronic device, characterized in that: include: one or more processors; One or more memories; the one or more memories store one or more programs, and when the one or more programs are executed by the one or more processors, the electronic device executes the memory management method described in any one of claims 1 to 12.

14. A computer-readable storage medium, characterized in that: The storage medium stores instructions, which, when executed on a computer, enable the computer to execute the memory management method according to any one of claims 1 to 12.

Images