A high-speed data transmission apparatus and method

Abstract

The application provides a high-speed data transmission device and method. The device comprises a single-chip microcomputer module, an FPGA master station, an FPGA slave station and an analog-to-digital conversion module connected in sequence, and the input end of the FPGA slave station is connected with at least one analog-to-digital conversion module. The analog-to-digital conversion module is used for converting an external analog signal into a digital signal and then transmitting the digital signal to the FPGA slave station. The FPGA slave station is used for receiving the digital signal according to a first time sequence, generating first FIFO data and transmitting the first FIFO data to the FPGA master station. The FPGA master station is used for sending a clock signal to a plurality of FPGA slave stations, determining the data transmission sequence of the FPGA slave stations, receiving the first FIFO data transmitted by the plurality of FPGA slave stations in parallel according to a second time sequence, generating second FIFO data and transmitting the second FIFO data to the single-chip microcomputer module, and the second time sequence is the same as the first time sequence. The single-chip microcomputer module is used for receiving the second FIFO data according to a third time sequence and obtaining a processing result corresponding to the second FIFO data. The device is used for fast and reliable data transmission.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of array communication technology, in particular to a high-speed data transmission device and method. BACKGROUND

[0002] With the development of science and technology and the progress of industrial production, the demand for large-scale data acquisition and processing is increasing. Especially in the fields of medical treatment, scientific research, industrial monitoring, etc., a large amount of channel data needs to be collected for analysis and processing to improve production efficiency or achieve accurate diagnosis and other purposes.

[0003] The traditional data transmission mode has bandwidth limitation, which limits the data transmission rate. During the data transmission process, the processor for processing data can only read data sequentially one by one, and the transmission time will be prolonged with the increase of data volume, which greatly affects the data transmission rate. SUMMARY

[0004] Therefore, the present application provides a high-speed data transmission device and method to quickly and reliably transmit data.

[0005] Specifically, the present application is realized by the following technical solutions:

[0006] The first aspect of the present application provides a high-speed data transmission device, which comprises a single-chip microcomputer module, an FPGA master station, an FPGA slave station and an analog-to-digital conversion module connected in sequence, the number of the FPGA slave stations is N times the number of the FPGA master stations, N is a positive integer, N>1, and the input end of the FPGA slave station is connected with at least one analog-to-digital conversion module, wherein:

[0007] The analog-to-digital conversion module is used to convert an external analog signal into a digital signal and then transmit the digital signal to the FPGA slave station;

[0008] The FPGA slave station is used to receive the digital signal according to a first time sequence, generate first FIFO data and transmit the first FIFO data to the FPGA master station;

[0009] The FPGA master station is used to send a clock signal to a plurality of FPGA slave stations, determine the data transmission sequence of the FPGA slave stations, receive the first FIFO data transmitted by a plurality of FPGA slave stations in parallel according to a second time sequence, generate second FIFO data and transmit the second FIFO data to the single-chip microcomputer module, and the second time sequence is the same as the first time sequence;

[0010] The single-chip microcomputer module is used to receive the second FIFO data in parallel according to a third time sequence and obtain the processing result corresponding to the second FIFO data.

[0011] The second aspect of the application provides a high-speed data transmission method, the method is applied to the high-speed data transmission device, the device comprises a single-chip microcomputer module, an FPGA master station, an FPGA slave station and an analog-digital conversion module connected in sequence, the number of the FPGA slave station is N times of the number of the FPGA master station, N is a positive integer, N>1, the input end of the FPGA slave station is connected with at least one analog-digital conversion module, wherein:

[0012] The analog-digital conversion module converts an external analog signal into a digital signal and transmits the digital signal to the FPGA slave station;

[0013] The FPGA slave station receives the digital signal according to a first time sequence, generates first FIFO data and transmits the first FIFO data to the FPGA master station;

[0014] The FPGA master station sends a clock signal to a plurality of FPGA slave stations, determines the data transmission sequence of the FPGA slave stations, and receives the first FIFO data transmitted by the plurality of FPGA slave stations in parallel according to a second time sequence, generates second FIFO data and transmits the second FIFO data to the single-chip microcomputer module, and the second time sequence is the same as the first time sequence;

[0015] The single-chip microcomputer module receives the second FIFO data according to a third time sequence and obtains a processing result corresponding to the second FIFO data.

[0016] The high-speed data transmission device and method provided by the application receives digital signals sent by a plurality of analog-to-digital conversion modules through a plurality of FPGA slave stations, then receives first FIFO data generated after processing by the plurality of FPGA slave stations through the FPGA master station and processes the first FIFO data, and then sends second FIFO data obtained to a single-chip microcomputer module for processing. In this way, the plurality of FPGA slave stations receive signals, the amount of received data can be freely controlled according to the number of analog-to-digital converters, and a large amount of first FIFO data can be received simultaneously by the FPGA master station without reducing the transmission time. Therefore, all data of the FPGA slave stations can be received in parallel, and data transmission can be quickly and reliably completed. Specifically, the plurality of FPGA slave stations are directly connected to the analog-to-digital converters, and can quickly obtain analog-to-digital conversion results of any order of magnitude. The FPGA master station and the FPGA slave stations maintain a parallel communication mode, and can receive all analog-to-digital conversion results simultaneously under the clock period of the FPGA master station, thereby achieving simultaneous and rapid transmission of massive data. Further, the FPGA master station sends all received data to the single-chip microcomputer through parallel communication under another clock period through data adaptation. Since the FPGA master station has received all analog-to-digital conversion results, the single-chip microcomputer can receive all analog-to-digital conversion results, and the normal operation of the analog-to-digital converters is not affected. Since the FPGA master station adapts and packages the data, the communication capability can be maximized, and stable data transmission can be ensured. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 A schematic diagram of a high-speed data transmission device according to an example embodiment of the application;

[0018] Figure 2 A data reading schematic diagram according to an example embodiment of the application;

[0019] Figure 3 A second FIFO data reading sequence diagram according to an example embodiment of the application;

[0020] Figure 4 A flowchart of a high-speed data transmission method according to an example embodiment of the application;

[0021] Figure 5 A schematic diagram of a high-speed data transmission device according to an example embodiment of the application. DETAILED DESCRIPTION

[0022] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The description of the exemplary embodiments is intended to apply to any exemplary embodiment, unless specifically noted. The following description is not meant to limit the application to any one or more particular embodiments, but to provide examples and teaching to enable others skilled in the art to make and use the application.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0024] It is to be understood that the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It is to be understood that the term "and / or" as used herein encompasses all possible combinations of particular items listed apart from disjunctively worded limitations of various claims. It is further understood that the terms "comprise" (and any form of comprise, e.g., comprised of, comprises, and comprising), "have" (and any form of have, e.g., has and having), "include" (and any form of include, e.g., includes and including), and "contain" (and any form contain, e.g., contains and containing) are open-ended linking verbs of inclusion. As a result, a system that "comprises", "has", "includes" or "contains" one or more elements possesses those one or more elements, but is not limited to possessing only those one or more elements. Likewise, a

[0025] The application provides a high-speed data transmission device and method to solve fast, reliable data transmission.

[0026] The application provides a high-speed data transmission device, equipment and method, which receives digital signals sent by a plurality of analog-to-digital conversion modules through a plurality of FPGA slave stations, then receives first FIFO data generated after processing by the plurality of FPGA slave stations through a FPGA master station and processes the first FIFO data, and then sends second FIFO data obtained to a single-chip microcomputer module for processing. In this way, the signal is received through the plurality of FPGA slave stations, and the amount of received data can be freely controlled according to the number of analog-to-digital converters, and a large amount of first FIFO data can be received simultaneously through the FPGA master station without reducing the transmission time. As a result, all FPGA slave station data can be received in parallel, and data transmission can be completed quickly and reliably.

[0027] The following specific embodiments are given to introduce the technical solutions of the application in detail.

[0028] Figure 1 An example of a high-speed data transmission device is shown in the schematic diagram of an example embodiment. Please refer to Figure 1The device provided by the embodiment can include a single-chip microcomputer module, an FPGA master station, FPGA slave stations and an analog-to-digital conversion module connected in sequence, the number of the FPGA slave stations is N times of the number of the FPGA master stations, N is a positive integer, N>1, and the input end of the FPGA slave station is connected with at least one analog-to-digital conversion module, wherein:

[0029] The analog-to-digital conversion module is configured to convert an external analog signal into a digital signal and transmit the digital signal to the FPGA slave station.

[0030] The FPGA slave station is configured to receive the digital signal according to a first time sequence, generate first FIFO data and transmit the first FIFO data to the FPGA master station.

[0031] The FPGA master station is configured to send a clock signal to a plurality of FPGA slave stations, determine a data transmission sequence of the FPGA slave stations, receive the first FIFO data transmitted by the plurality of FPGA slave stations in parallel according to a second time sequence, generate second FIFO data and transmit the second FIFO data to the single-chip microcomputer module, and the second time sequence is the same as the first time sequence.

[0032] The single-chip microcomputer module is configured to receive the second FIFO data in parallel according to a third time sequence and obtain a processing result corresponding to the second FIFO data.

[0033] Specifically, the analog-to-digital conversion module is configured to receive an external analog signal and generate a corresponding digital signal after processing by the analog-to-digital conversion module. It should be noted that the analog signal can be from an external sensor, a collection device or other analog signal source, and the generated digital signal after processing by the analog-to-digital conversion module is convenient for subsequent processing.

[0034] Further, at least one analog-to-digital conversion module is connected to each FPGA slave station, and the specific number of analog-to-digital conversion modules connected to the FPGA slave station is determined according to actual needs, which is not limited in the embodiment. For example, in an embodiment, more than 1000 analog-to-digital conversion channels can be expanded according to the amount of analog data to be processed.

[0035] Further, after the FPGA slave station receives the digital signal of the analog-to-digital conversion module, the corresponding first FIFO data is generated according to the first-in first-out rule. It should be noted that the high-speed data transmission device has at least two FPGA slave stations, and the specific number of FPGA slave stations is determined according to actual needs, which is not limited in the embodiment. For example, in an embodiment, more than 10 FPGA slave stations can be expanded according to the amount of analog data to be processed, each FPGA slave station is expanded with more than 100 analog-to-digital conversion channels, and more than 1000 analog-to-digital conversion channels are expanded on the FPGA master station.

[0036] In a specific implementation, the first FIFO data can be generated by using a conventional FIFO data generation method or by using an IP core method. For example, in an embodiment, the FIFO slave station includes a plurality of IP cores, and the IP cores process the digital signal data and output corresponding first FIFO data.

[0037] It should be noted that the IP core is a reusable hardware design module, and an IP core that has been packaged by a manufacturer can be used in the FPGA slave station of the embodiment.

[0038] Further, after the FPGA slave station generates the first FIFO data, the FPGA master station receives the first FIFO data from the FPGA slave station in parallel. Since the FPGA master station can receive the first FIFO data in parallel, when the number of FPGA slave stations is large, the data transmission can also be completed quickly. Meanwhile, the FPGA master station transmits the complete data to the single-chip microcomputer in parallel according to the communication condition, which can guarantee the integrity and quality of data transmission and prevent data from being missed or repeatedly transmitted.

[0039] The FPGA slave station is configured to receive the digital signal according to a first timing, generate first FIFO data, and transmit the first FIFO data to the FPGA master station. The FPGA master station is configured to send a clock signal to a plurality of FPGA slave stations, determine a data transmission order of the FPGA slave stations, and receive the first FIFO data transmitted by the plurality of FPGA slave stations in parallel according to a second timing.

[0040] Specifically, the first timing is the timing at which the analog-to-digital converter obtains a data conversion result, and the second timing is the timing at which the FPGA master station receives data from the FPGA slave station. The first timing is the same as the second timing. As soon as the analog-to-digital converter obtains the data conversion result, the FPGA master station simultaneously obtains the results of all the analog-to-digital converters in parallel, which ensures that the FPGA master station can accurately obtain all the data and avoids data omission or repetition, thereby ensuring the accuracy of the data.

[0041] Further, the FPGA master station sends a clock signal to a plurality of FPGA slave stations, and determines the first timing by using the clock signal. In the first timing, the FPGA slave station receives the digital signal.

[0042] Optionally, the clock signal is a preset frequency division, and the FPGA slave station is further configured to, when the first preset frequency of the preset frequency division is reached, decrease the value of a slave station counter by one and start receiving the digital signal. The slave station counter identifies the starting position at which the FPGA slave station reads the digital signal.

[0043] The FPGA master station is further configured to decrease the value of a master station counter by one and start receiving the first FIFO data when the second preset frequency of the preset frequency division is reached.

[0044] In a specific implementation, the clock signal is preset frequency division, and a specific frequency division frequency is set according to actual needs, which is not limited in this embodiment.

[0045] The order of the transmission signals of the FPGA slave station and the FPGA master station is described below by taking 8 frequency division of the clock signal as an example.

[0046] Specifically, the first preset frequency and the second preset frequency are different frequencies in the clock signal. For example, when the clock signal is divided into 8 frequency division, the first preset frequency can be set to 1-2 frequency, and the second preset frequency can be set to 3-8 frequency.

[0047] Further, Figure 2 A data reading schematic diagram of an exemplary embodiment is shown. Please refer to Figure 2 When the clock signal is divided into 8 frequency division, in combination with the above example, the clock signal is low in the first preset frequency (1-2 frequency), at this time, the FPGA slave station receives the digital signal of the analog-to-digital conversion module, and the FPGA master station sends the second FIFO data to the single-chip microcomputer module. In the second preset frequency (3-8 frequency), the clock signal is high, at this time, the FPGA master station receives the first FIFO data of all FPGA slave stations in parallel.

[0048] Further, when the FPGA slave station reads data, the starting position of the digital signal reading can be identified by the slave station counter of the FPGA slave station, and then the digital signal is read at the starting position. It should be noted that the correctness and synchronization of data transmission can be ensured by the slave station counter, since the slave station counter is a decreasing counter, the value of the slave station counter is decreased by 1 when the first preset frequency arrives.

[0049] Further, when the FPGA master station reads data, the starting position of the first FIFO data reading can be identified by the master station counter of the FPGA master station, and then the first FIFO data is read at the starting position. It should be noted that the correctness and synchronization of data transmission can be ensured by the master station counter, since the master station counter is a decreasing counter, the value of the master station counter is decreased by 1 when the second preset frequency arrives.

[0050] The high-speed data transmission device provided by the embodiment realizes that the FPGA slave station receives corresponding data after the analog-digital converter obtains the conversion result, on the one hand, through the same timing working mechanism, the FPGA master station receives the data of all the FPGA slave stations in parallel, so that the FPGA master station can obtain the results of all the analog-digital converters completely, avoids the omission of the results of any analog-digital converter, and improves the accuracy and integrity of the data; on the other hand, through the role of the counter in the data interaction process, when a single analog-digital converter is read, the read data is continuous and uninterrupted, which guarantees the accuracy and integrity of the data at the data level.

[0051] As an optional embodiment, before the FPGA master station reads the data, the FPGA master station is further configured to match the maximum parallel communication amount based on the parallel communication attribute of the FPGA master station and the data sending attribute of the FPGA slave station, determine the parallel communication number based on the maximum parallel communication amount, and determine the communication order of all the FPGA slave stations based on the parallel communication number and the actual number of the FPGA slave stations. Specifically, the parallel communication attribute is the maximum data amount that can be transmitted by the master station in parallel communication, the data sending attribute is the maximum data amount sent by the FPGA slave station at a time or the average data amount sent by the FPGA slave station at a time in a first historical time period, the maximum parallel communication amount refers to the maximum number of FPGA slave stations that can be received by the FPGA master station at a time, if the number of the FPGA slave stations is more than the maximum parallel communication amount, the maximum parallel communication amount is taken as the parallel communication number at a time, otherwise, the number of the FPGA slave stations is taken as the parallel communication number at a time, the communication groups are determined according to the measured data conversion speeds of the FPGA slave stations, each communication group includes the same number of FPGA slave stations as the parallel communication number, the communication order of each communication group is determined according to the average measured data conversion speeds of the FPGA slave stations, so as to determine the communication order of all the slave stations, and the data of the FPGA slave stations in each communication group is read according to the communication order. The device provided by the application can read the data of all the slave stations in parallel on the one hand; on the other hand, in order to guarantee the stability of data reading and improve the robustness of the device, the device can automatically identify the number of the slave stations, and for the case of a large number of slave stations, the transmission capacity between the master station and the slave stations is automatically identified, and a data transmission scheme is adaptively generated, so that the device collapse caused by the expansion of the slave stations due to application requirements is avoided.

[0052] Optionally, the FPGA master station further comprises a plurality of IP cores, wherein:

[0053] The FPGA master station is further configured to calculate the number of IP cores according to the number of FPGA slave stations, and instantiate a plurality of IP cores; each instantiated IP core corresponds to one FPGA slave station; that is, a first number of IP cores are instantiated according to the number of FPGA slave stations, wherein the first number is greater than or equal to the number of FPGA slave stations, and a corresponding relationship between the instantiated IP cores and the FPGA slave stations is established, wherein one FPGA slave station corresponds to one IP core, and the FPGA slave stations corresponding to different IP cores are different.

[0054] The FPGA master station is further configured to store the first FIFO data received from the FPGA slave stations into the corresponding instantiated IP cores, and remove the data storage address between the communication protocol of the FPGA master station and the FPGA slave stations.

[0055] The FPGA master station is further configured to generate second FIFO data according to the first FIFO data in the plurality of instantiated IP cores, and transmit the second FIFO data to the single-chip microcomputer module.

[0056] Specifically, a plurality of IP cores can be used in the FPGA master station, and the addresses of the first FIFO data are recorded by the IP cores. It should be noted that the specific number of IP cores in the FPGA master station is determined according to actual needs, which is not limited in the embodiment. For example, in an embodiment, the FPGA master station is connected with 10 FPGA slave stations, and the FPGA master station has 10 IP cores.

[0057] In a specific implementation, a suitable IP core is selected as a usable IP core in the FPGA master station to realize the function of transmitting FIFO data. Further, the FPGA master station instantiates the IP core, and then configures the instantiated IP core. It should be noted that each instantiated IP core corresponds to one FPGA slave station, and when the first FIFO data of the FPGA slave station is received, the first FIFO data is stored in the corresponding IP core. For example, in an embodiment, the FPGA slave station 11 corresponds to the instantiated IP core IP core 101, and after receiving the first FIFO data FIFO11 of the FPGA slave station 11, the first FIFO data FIFO11 is stored in the IP core 101.

[0058] Further, the FPGA master station generates second FIFO data based on the data in the IP core, and then transmits the second FIFO data to the single-chip microcomputer module. The single-chip microcomputer directly reads data from each instantiated IP core corresponding to the data in the FPGA master station according to the reading order of the FIFO data.

[0059] The high-speed data transmission device provided by the embodiment stores the first FIFO data of the corresponding FPGA slave station through the plurality of IP cores in the FPGA master station, so that the address of the data in the communication protocol can be deleted since the address signal of the data can be determined through the IP core, the protocol content is simplified, and the efficiency and reliability of the data transmission are improved.

[0060] Further, the FPGA master station generates the second FIFO data that can be processed by the single-chip microcomputer module after obtaining the first FIFO data, and transmits the second FIFO data to the single-chip microcomputer module, so as to complete the processing of the data through the single-chip microcomputer module. The size of the second FIFO data matches the communication attribute of the single-chip microcomputer module, and the size of the second FIFO data is not completely the same as the size of any first FIFO data. Since each FPGA slave station obtained by the master station has corresponding FIFO data, the number of the first FIFO data corresponds to the number of the FPGA slave stations, further, in order to maximize the parallel communication capability of the single-chip microcomputer and the FPGA master station, the data is processed and repackaged to generate the second FIFO data, and the size of the second FIFO data is to better realize the maximum data transmission amount at a time, and there is no corresponding relationship with the FPGA slave station, that is, according to the size of the communication capability, the second FIFO data can only include one first FIFO data, can include a plurality of first FIFO data, or can include part of the first FIFO data.

[0061] Further, the generating the second FIFO data at least comprises: determining the transmission order of each first FIFO data based on the attribute of each first FIFO data; calculating the maximum data amount of parallel communication based on the real-time communication attribute of the single-chip microcomputer and the FPGA master station; determining a plurality of transmission groups with a sequence order based on the maximum data amount of parallel communication and the corresponding description theme of each first FIFO data, so as to obtain a plurality of second FIFO data, the sorting of all transmission groups matches the transmission order of each first FIFO data, and the data transmission of one transmission group is completed each time of communication; and transmitting the first FIFO data in each transmission group in parallel according to the sequence order. Specifically, the determining the transmission order of each first FIFO data based on the attribute of each first FIFO data comprises: obtaining the corresponding description object and timestamp of each first FIFO data, determining the initial transmission order of the first FIFO data based on the association degree between the description object and the task executed by the single-chip microcomputer module, calculating the delay time based on the timestamp and the real-time communication time, and adjusting the initial transmission order based on the delay time, so as to determine the transmission order of each first FIFO data. Specifically, the delay time is calculated based on the difference between the timestamp and the real-time communication time, and the transmission order of the first FIFO data with the delay time greater than the transmission threshold is advanced by a preset number of bits. Preferably, the transmission threshold of different description objects is not completely the same, and the transmission threshold of the description object with a high association degree with the task executed by the single-chip microcomputer module is smaller than the transmission threshold of the description object with a low association degree.

[0062] The method provided by the application can calculate the real-time second FIFO data according to the real-time communication ability during parallel communication, considering the influence of the environment and the real-time change of the communication ability, realizes the adaptive matching of data transmission and real-time communication, maximizes the stability of data transmission and maximizes the utilization of data communication ability. Further, compared with the sorting according to the sequence of the timestamp in the prior art, the application fully considers the urgency of the task executed by the single-chip microcomputer module to each data, adjusts the data transmission order, and fine-tunes the order according to the sequence of the timestamp, so as to ensure that the important data is transmitted first on one hand, and the data with long delay time is transmitted as soon as possible on the other hand, thereby improving the efficiency of the single-chip microcomputer in executing the task through the important data acquisition mode, and ensuring the real-time performance of data transmission through fine-tuning.

[0063] Optionally, when the second FIFO data in the FPGA master station is a plurality of second FIFO data, the method comprises:

[0064] The single-chip microcomputer module is further configured to receive the plurality of second FIFO data in parallel, wherein the single-chip microcomputer module marks the last data of the second FIFO data currently being received as characteristic data.

[0065] The single-chip microcomputer module receives next second FIFO data from the feature data, and marks the end data of the next second FIFO data as new feature data.

[0066] Specifically, the single-chip microcomputer module sends a read pulse signal to the FPGA master station, and requests reading of the second FIFO data based on the read pulse signal. It should be noted that the read pulse signal is generated continuously, and therefore the process of reading the second FIFO data is also a continuous process.

[0067] Further, the second FIFO data in the FPGA master station is generated based on the first FIFO data transmitted by the FPGA slave station. Since the FPGA slave station continuously sends multiple first FIFO data, the second FIFO data in the FPGA master station also exists in multiple pieces.

[0068] Further, the feature data is the end data of any second FIFO data. In specific implementation, the end data of the second FIFO data being transmitted can be marked as feature data by marking.

[0069] Figure 3 A second FIFO data reading sequence diagram of an exemplary embodiment of the present application is shown. Please refer to Figure 3 When the single-chip microcomputer module reads the second FIFO data, it reads multiple second FIFO data in sequence, and in this embodiment, two second FIFO data are taken as an example. The second FIFO data being read is FIFO1, and at this time, the "0003h" data is the end data, which is marked as feature data.

[0070] Further, before reading the feature data "0003h", i.e. after reading the data "7059h", the second second FIFO data, i.e. FIFO2, is started to be received.

[0071] It should be noted that the first data of the second FIFO data is invalid data, and therefore needs to be deleted after reading. Please continue to refer to Figure 3 After reading the feature data "0003h" and the first data "0000h" of FIFO2, "0000h" is deleted, and only the data "0003h" is recorded. At the same time, the end data of the FIFO2 data is marked as feature data.

[0072] Please continue to refer to Figure 3In the embodiment, in combination with the above example, the timing of data reading can also be controlled by different second FIFO data corresponding read enable signals, and the read enable and data switching can be realized by using the IP core asynchronous second FIFO data number rdusedw signal and the read empty flag rdempty signal. For example, in combination with the above example, the read enable signal of FIFO1 data is set to 0 after the data reading is completed, and the read enable signal of FIFO2 data is set to 1 in advance, so that the first invalid data 0000 in the FIFO2 data is read out and discarded first, thereby realizing seamless connection of two second FIFO data, and the data reading method between other second FIFO data is the same.

[0073] It should be noted that the master station FPGA notifies the slave station of the start and end of communication by changing the pulse width of the clock signal SCL at the start and end.

[0074] The high-speed data transmission device provided in the embodiment can realize connection reading between adjacent two second FIFO data without data loss by reading the next second FIFO data in advance by one bit, and the single-chip microcomputer module will not miss or read extra data when reading due to the invalid data of the first second FIFO data, thereby improving the reliability and efficiency of data transmission.

[0075] Optionally, the high-speed data transmission device further comprises a buffering device, an input end of the buffering device is connected with a clock signal output end of the FPGA master station, and an output end of the buffering device is connected with a clock signal input end of the FPGA slave station.

[0076] The buffering device is installed between the FPGA master station and the FPGA slave station, and is used for providing buffering for the clock signal sent by the FPGA master station.

[0077] Specifically, the clock signal sent by the FPGA master station can be provided to the FPGA slave station through the buffering device. It should be noted that the specific model of the buffering device can be determined according to actual needs, and the embodiment does not limit this.

[0078] Further, the buffering device can enhance the clock signal sent by the FPGA master station to amplify the pin driving capability of the FPGA master station.

[0079] The high-speed data transmission device provided in the embodiment can improve the driving capability of the clock signal output by the FPGA master station through the buffering device between the FPGA master station and the FPGA slave station, thereby ensuring the reliability of the high-speed data transmission device.

[0080] Optionally, the high-speed data transmission device further comprises a clock signal generating device, wherein:

[0081] The clock signal generation device is configured to generate an initial clock signal and divide the initial clock signal according to the preset frequency to obtain the divided clock signal.

[0082] The clock signal generation device is further configured to input the clock signal into the high-speed data transmission device.

[0083] Specifically, the clock generation device is configured to generate an initial clock signal, which is an undivided signal, and can generate a corresponding initial clock signal according to actual needs. In a specific implementation, a power-compliant clock signal generator can be used to generate the initial clock signal.

[0084] Further, the initial clock signal can be divided to obtain the clock signal, and the preset frequency is determined according to actual needs. In this embodiment, no limitation is imposed thereon. For example, in combination with the above example, the preset frequency can be set to 8, and the initial clock signal is divided into an 8-divided clock signal.

[0085] Further, the clock generation device inputs the clock signal into the high-speed data transmission device to complete the function of the same frequency.

[0086] The high-speed data transmission device provided in this embodiment generates a clock signal through the clock generation device, so that the clock signal is input into the high-speed data transmission device after processing, and the function of the same frequency can be completed through the clock signal.

[0087] Figure 4 A flowchart of a high-speed data transmission method provided in an exemplary embodiment of the present application is shown in FIG. 4. Figure 4 Corresponding to the foregoing embodiment of the high-speed data transmission device, the present application further provides an embodiment of a high-speed data transmission method.

[0088] The method is applied to the high-speed data transmission device, which includes single-chip microcomputer modules, FPGA master stations, FPGA slave stations and analog-to-digital conversion modules connected in sequence, the number of the FPGA slave stations is N times the number of the FPGA master stations, N is a positive integer, N>1, the input end of the FPGA slave station is connected with at least one analog-to-digital conversion module, and the method includes the following steps.

[0089] S401, the analog-to-digital conversion module converts an external analog signal into a digital signal and transmits the digital signal to the FPGA slave station.

[0090] S402, the FPGA slave station receives the digital signal according to a first time sequence, generates first FIFO data and transmits the first FIFO data to the FPGA master station.

[0091] S403, the FPGA master station sends a clock signal to a plurality of FPGA slave stations, determines a data transmission order of the FPGA slave stations, and receives the first FIFO data transmitted by the plurality of FPGA slave stations in parallel according to a second time sequence, generates second FIFO data and transmits the second FIFO data to the single-chip microcomputer module, wherein the second time sequence is the same as the first time sequence.

[0092] S404, the single-chip microcomputer module receives the second FIFO data in parallel according to a third time sequence, and obtains a processing result corresponding to the second FIFO data.

[0093] The method provided in the embodiment can be used in the high-speed data transmission device in the above-described embodiments, and the specific implementation principle and implementation process are similar, which will not be described here.

[0094] Figure 5 A schematic diagram of a high-speed data transmission device according to an exemplary embodiment of the present application is shown in FIG. 1. Figure 5 The high-speed data transmission device includes the high-speed data transmission device according to any one of the first aspect of the present application, and the specific implementation principle and implementation process of the high-speed data transmission device are similar, which will not be described here.

[0095] The above merely provides the preferred embodiments of the present application, but should not be used to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A high-speed data transmission device, characterized in that, The device comprises, in sequence, a microcontroller module, an FPGA master station, an FPGA slave station, and an analog-to-digital converter module. The number of FPGA slave stations is N times the number of FPGA master stations, where N is a positive integer and N>1. At least one of the analog-to-digital converter modules is connected to the input terminal of each FPGA slave station. The analog-to-digital converter module is used to convert external analog signals into digital signals and then transmit the digital signals to the FPGA slave station. The FPGA slave station is used to receive the digital signal according to the first timing sequence, generate the first FIFO data and transmit it to the FPGA master station. The FPGA master station is used to send clock signals to multiple FPGA slave stations to determine the data transmission order of the FPGA slave stations, and to receive the first FIFO data transmitted by multiple FPGA slave stations in parallel according to the second timing sequence, generate second FIFO data and transmit it to the microcontroller module. The second timing sequence is the same as the first timing sequence. The microcontroller module is used to receive the second FIFO data in parallel according to the third timing sequence and obtain the processing result corresponding to the second FIFO data. The clock signal is a preset frequency division; The FPGA slave station is further configured to decrement the value of the slave station counter by one when the first preset frequency of the preset frequency division is reached, and to start receiving the digital signal; wherein, the slave station counter indicates the starting position of the FPGA slave station reading the digital signal; The FPGA master station is further configured to decrement the value of the master station counter by one and start receiving the first FIFO data when the second preset frequency of the preset frequency division is reached; wherein, the master station counter identifies the starting position of the FPGA master station reading the first FIFO data.

2. The high-speed data transmission device according to claim 1, characterized in that, The FPGA master station also includes multiple IP cores, among which: The FPGA master station is also used to calculate the number of IP cores based on the number of FPGA slave stations, and instantiate multiple IP cores; wherein each instantiated IP core corresponds to one FPGA slave station; The FPGA master station is also used to store the first FIFO data received from the FPGA slave station into the corresponding instantiated IP core, and to remove the data storage address between the communication protocols of the FPGA master station and the FPGA slave station. The FPGA master station is also used to generate second FIFO data based on the first FIFO data in the multiple instantiated IP cores and transmit it to the microcontroller module.

3. The high-speed data transmission device according to claim 1, characterized in that, When there are multiple second FIFO data in the FPGA master station, they include: The microcontroller module is also used to receive multiple second FIFO data in parallel, wherein the microcontroller module marks the last data of the currently received second FIFO data as feature data; The microcontroller module receives the next second FIFO data starting from the feature data, and marks the last data of the next second FIFO data as the new feature data.

4. The high-speed data transmission device according to claim 1, characterized in that, The high-speed data transmission device further includes a buffer device. The input terminal of the buffer device is connected to the clock signal output terminal of the FPGA master station, and the output terminal of the buffer device is connected to the clock signal input terminal of the FPGA slave station. The buffer device is installed between the FPGA master station and the FPGA slave station to provide buffering for the clock signal sent by the FPGA master station.

5. The high-speed data transmission device according to any one of claims 1-4, characterized in that, The high-speed data transmission device further includes a clock signal generator, wherein: The clock signal generating device is used to generate an initial clock signal and divide the initial clock signal according to a preset frequency to obtain the divided clock signal. The clock signal generator is also used to input the clock signal into the high-speed data transmission device.

6. The high-speed data transmission device according to claim 1, characterized in that, Before the FPGA master station receives the first FIFO data transmitted by multiple FPGA slave stations in parallel according to the second timing sequence, The FPGA master station is also used to match the maximum parallel communication volume based on the parallel communication attributes of the FPGA master station and the data transmission attributes of the FPGA slave station, and to determine the number of parallel communications based on the maximum parallel communication volume. The number of parallel communications is used to represent the number of FPGA slave stations that are allowed to work in parallel. The communication order of all FPGA slaves is determined based on the number of parallel communications and the actual number of FPGA slaves.

7. The high-speed data transmission device according to claim 1, characterized in that, Generating the second FIFO data includes at least: The transmission order of each first FIFO data is determined based on the attributes of each first FIFO data. Calculate the maximum data volume of parallel communication based on the real-time communication attributes of the microcontroller and FPGA master station; Based on the maximum data volume of the parallel communication and the description topic corresponding to each first FIFO data, multiple transmission packets with a sequential order are determined to obtain multiple second FIFO data. The order of all transmission packets matches the transmission order of each first FIFO data, and the data transmission of one transmission packet is completed in each communication. The first FIFO data in each transmission packet is transmitted in parallel according to the aforementioned sequence.

8. The high-speed data transmission device according to claim 7, characterized in that, The process of determining the transmission order of each first FIFO data based on its attributes includes: Obtain the description object and timestamp corresponding to each first FIFO data. The initial transmission order of the first FIFO data is determined based on the degree of association between the described object and the task executed by the microcontroller module. The delay time is calculated based on the timestamp and real-time communication time, and the initial transmission order is adjusted based on the delay time to determine the transmission order of each first FIFO data.

9. A high-speed data transmission method, characterized in that, The method is applied to the high-speed data transmission device according to any one of claims 1-8, the device comprising, in sequence: a microcontroller module, an FPGA master station, an FPGA slave station, and an analog-to-digital converter module, wherein the number of FPGA slave stations is N times the number of FPGA master stations, where N is a positive integer and N>1, and at least one of the analog-to-digital converter modules is connected to the input terminal of each FPGA slave station, the method comprising: The analog-to-digital converter module converts external analog signals into digital signals and then transmits the digital signals to the FPGA slave station. The FPGA slave station receives the digital signal according to the first timing sequence, generates the first FIFO data, and transmits it to the FPGA master station. The FPGA master station sends clock signals to multiple FPGA slave stations to determine the data transmission order of the FPGA slave stations, and receives the first FIFO data transmitted by multiple FPGA slave stations in parallel according to the second timing sequence, generates second FIFO data and transmits it to the microcontroller module. The second timing sequence is the same as the first timing sequence. The microcontroller module receives the second FIFO data in parallel according to the third timing sequence and obtains the processing result corresponding to the second FIFO data. The clock signal is a preset frequency division; When the FPGA slave reaches the first preset frequency of the preset frequency division, it decrements the value of the slave counter by one and begins receiving the digital signal; wherein, the slave counter indicates the starting position of the FPGA slave reading the digital signal; When the FPGA master station reaches the second preset frequency of the preset frequency division, it decrements the value of the master station counter by one and begins receiving the first FIFO data; wherein, the master station counter indicates the starting position of the FPGA master station reading the first FIFO data.

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