Protection circuit, method and display device

Abstract

Embodiments of the present application relate to a kind of protection circuit, method and display device, circuit includes: timing control module, first transistor, comparison module, compensation module, drive module and or gate;The output of timing control module is connected with the first end of first transistor and the first input of comparison module;The second end of first transistor is connected with the output of or gate and control signal output end, the third end of first transistor is connected to the second input of comparison module;The output of comparison module is connected to the input of compensation module;The output of compensation module is connected to the input of drive module;The signal that timing control module outputs is detected by voltage comparator, the signal that is disturbed is compensated by compensation module, whereby, it can realize the technical effect of solving display panel display not full, display abnormal black screen and other undesirable phenomenon.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the display technical field, and in particular to a protection circuit, method and display device. BACKGROUND

[0002] In the current TV panel architecture, it is usually composed of a mainboard (SOC), a TCON board (timing controller), a data driving module (Driver IC) and a panel. The communication between the modules is achieved by a protocol to complete the transmission of data. For the ISP interface protocol commonly used in TV, the communication between the TCON board and the Driver IC is achieved by the handshake connection of the LOCK signal generated by the TCON. After the handshake is successful, the display communication is entered to transmit the ISP signal. In fact, when the LOCK signal output by the TCON is at a high level, it indicates that the handshake between the TCON board and the Driver IC is successful to establish a connection, and the TCON can transmit signals through the ISP data transmission to normally display a picture.

[0003] In the actual hardware circuit, after the handshake between the LOCK signal generated by the TCON and the Driver IC is successful, the ISP signal transmission is performed. The timing control signal may be unstable in probability, that is, the LOCK generated by the TCON may be unstable due to external interference, resulting in the loss of locking between the TCON board and the panel, the disconnection of signal transmission and the black screen or display defects or incomplete display of the picture.

[0004] In the current TV panel, when the Driver IC receives abnormal front-end data, the LOCK signal is pulled down to disconnect the handshake connection to protect the panel and the rear-end circuit from being damaged. The LOCK connection communication signal output by the TCON board is easily disturbed by the external environment. For example, when the layout engineer designs, the LOCK signal and the jumping voltage signal are placed close to each other due to insufficient layout space. The LOCK signal is pulled and stretched due to the load, resulting in unstable level and handshake failure, causing data loss. In an abnormal environment, the abnormality caused by the characteristics of the circuit components results in the loss of the LOCK signal and abnormal data transmission, causing the picture to be black and display defects. SUMMARY

[0005] In view of this, to solve the technical problem that the timing controller causes unstable display picture due to unstable signal, embodiments of the present application provide a protection circuit, method and display device.

[0006] In a first aspect, the embodiments of the present application provide a protection circuit, comprising:

[0007] a timing control module, a first transistor, a comparison module, a compensation module, a driving module and an OR gate.

[0008] The output end of the timing control module is connected with the first end of the first transistor and the first input end of the comparison module;

[0009] The second end of the first transistor is connected with the output end of the OR gate and the control signal output end, and the third end of the first transistor is connected to the second input end of the comparison module;

[0010] The output end of the comparison module is connected to the input end of the compensation module;

[0011] The output end of the compensation module is connected to the input end of the driving module;

[0012] The first input end of the OR gate is connected to the first output end of the driving module, the second input end is connected to the second output end of the driving module, the third input end is connected to the third output end of the driving module, and the fourth input end is connected to the fourth output end of the driving module.

[0013] In a possible implementation, the first transistor is in a conductive state under the action of a control signal, the timing control module outputs a timing signal to the comparison module and the first transistor, the first transistor inputs the timing signal to the comparison module, inputs the timing signal to the compensation module through the comparison module for signal compensation, and inputs the compensated compensation signal to the driving module, the driving module generates its own driving signal on the basis of the compensation signal, so that the driving module performs driving control on the display panel by using the driving signal;

[0014] When the driving signal is abnormal, an abnormal driving signal is input to the OR gate, and after logical processing of the OR gate, the first transistor is controlled to be in a disconnected state, so that the timing control module cannot transmit the timing signal to the driving module.

[0015] In a possible implementation, the comparison module comprises a comparator, a first resistor, a second transistor and a first variable resistor;

[0016] The positive input end of the comparator is connected to the output end of the timing control module as the first input end of the comparison module, the negative input end is connected to one end of the first resistor and one end of the first variable resistor, and the output end is connected to the second end of the second transistor;

[0017] The first end of the second transistor is connected to the third end of the first transistor as the second input end of the comparison module, and the third end is connected to the input end of the compensation module as the output end of the comparison module;

[0018] The other end of the first resistor is connected to a first ground end;

[0019] Another end of the first variable resistor is connected to a first power supply output end.

[0020] In a possible implementation, the compensation module comprises an amplifier, a second resistor, a third resistor, a fourth resistor and a second variable resistor.

[0021] One end of the second resistor is connected to an output end of the comparison module as an input end of the compensation module, and the other end is connected to a positive input end of the amplifier.

[0022] A negative input end of the amplifier is connected to one end of the third resistor and one end of the second variable resistor, and an output end of the amplifier is connected to one end of the fourth resistor.

[0023] The other end of the third resistor is connected to a second ground end.

[0024] The other end of the second variable resistor is connected to the other end of the fourth resistor as an output end of the compensation module and an input end of the driving module.

[0025] In a possible implementation, the driving module is configured to drive the display panel to display.

[0026] The driving module comprises a plurality of driving units.

[0027] An input end of each driving unit is connected to the output end of the compensation module as the input end of the driving module, a first output end of the driving unit is connected to an input end of the OR gate, and a second output end of the driving unit is connected to the display panel.

[0028] In a second aspect, an embodiment of the present application provides a protection method, comprising:

[0029] When detecting an interference signal output by the timing control module, determining a switching state of the first transistor;

[0030] Determining an output signal of the comparison module based on the interference signal;

[0031] Determining a compensation coefficient of the compensation module according to the output signal;

[0032] The driving module performs a driving operation on the display panel by using the compensation coefficient.

[0033] In a possible implementation, the determining of the switching state of the first transistor comprises:

[0034] When the driving module is in a normal operation mode, a first low-level signal output by the OR gate is acquired, and a second low-level signal output by the control signal output end is acquired;

[0035] based on the first low-level signal and the second low-level signal, control the first transistor to keep in the conductive state;

[0036] or,

[0037] when the driving module is in the abnormal operation mode, acquire a first high-level signal output by the or gate, and acquire a third low-level signal output by the control signal output terminal;

[0038] based on the first high-level signal and the third low-level signal, control the first transistor to keep in the non-conductive state.

[0039] In one possible implementation, the determining the output signal of the comparison module based on the interference signal comprises:

[0040] when the first transistor is in the conductive state, control the comparator to output a fourth low-level signal based on the interference signal;

[0041] control the second transistor to keep in the conductive state based on the fourth low-level signal;

[0042] determine a first target signal based on the second transistor;

[0043] when the first transistor is in the non-conductive state, control the comparator to output a fifth low-level signal based on the interference signal;

[0044] control the second transistor to keep in the conductive state based on the fifth low-level signal;

[0045] determine a second target signal based on the second transistor.

[0046] In one possible implementation, the determining the compensation coefficient of the compensation module based on the output signal comprises:

[0047] when the output signal is the first target signal, determine a target compensation coefficient based on the second variable resistor and the amplifier;

[0048] when the output signal is the second target signal, determine the compensation coefficient as zero;

[0049] the driving module performs a driving operation on the display panel by using the compensation coefficient, comprising:

[0050] when the compensation coefficient is the target compensation coefficient, determine a target compensation signal output by the compensation module;

[0051] perform a driving operation on an external display panel based on the target compensation signal;

[0052] When the compensation coefficient is zero, the driving module stops driving the display panel based on the compensation coefficient.

[0053] In a third aspect, the embodiments of the present application provide a display device, comprising: a housing, a display panel and a protection circuit as described in the first aspect arranged in the housing.

[0054] The protection circuit provided by the embodiments of the present application comprises a timing control module, a first transistor, a comparison module, a compensation module, a driving module and an OR gate. An output end of the timing control module is connected with a first end of the first transistor and a first input end of the comparison module. A second end of the first transistor is connected with an output end and a control signal output end of the OR gate, and a third end is connected with a second input end of the comparison module. An output end of the comparison module is connected with an input end of the compensation module. An output end of the compensation module is connected with an input end of the driving module. A first input end of the OR gate is connected with a first output end of the driving module, a second input end is connected with a second output end of the driving module, a third input end is connected with a third output end of the driving module, and a fourth input end is connected with a fourth output end of the driving module. The signal output by the timing control module is detected by the voltage comparator, and the disturbed signal is compensated by the compensation module. The technical effect of solving the incomplete display, abnormal display and black screen of the panel can be achieved by the present scheme. BRIEF DESCRIPTION OF DRAWINGS

[0055] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0056] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, for those skilled in the art, other drawings can also be obtained without creative labor.

[0057] One or more embodiments are illustrated by way of example in the drawings that are for illustrative purposes only, and are not construed to limit the embodiments, and elements having the same reference numerals in the drawings represent similar elements, unless otherwise specified, and the drawings do not constitute a proportional limitation.

[0058] Figure 1 A structural schematic diagram of a protection circuit provided by the embodiments of the present application is shown in the figure.

[0059] Figure 2 A structural schematic diagram of another protection circuit provided by the embodiments of the present application is shown in the figure.

[0060] Figure 3 A flowchart of a protection method provided by an embodiment of the present application is shown in the figure.

[0061] Figure 4 A flowchart of another protection method provided by an embodiment of the present application is shown in the figure.

[0062] Figure 5 A structure diagram of a display device based on a protection circuit provided by an embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0063] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in connection with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the protection scope of the present application.

[0064] The terms “include” and “have” in the embodiments of the present application are used to represent an open-ended inclusion, and refer to that in addition to the listed elements / components / etc., there can be other elements / components / etc.; the terms “first” and “second” etc. are only used as labels, and are not a limitation on the number of their objects. In addition, different elements and regions in the drawings are only schematically shown, and thus the present application is not limited to the sizes or distances shown in the drawings.

[0065] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in connection with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the protection scope of the present application.

[0066] Figure 1 A structure diagram of a protection circuit provided by an embodiment of the present application is shown in the figure. The protection circuit is applied in a protection process of a device. According to the figure, the protection circuit specifically includes: Figure 1 A structure diagram of a protection circuit provided by an embodiment of the present application is shown in the figure. The protection circuit is applied in a protection process of a device. According to the figure, the protection circuit specifically includes:

[0067] The timing control module 11, the first transistor T1, the comparison module 12, the compensation module 13, the driving module 14 and the OR gate 15.

[0068] The output end of the timing control module 11 is connected with the first end of the first transistor T1 and the first input end of the comparison module 12.

[0069] The second end of the first transistor T1 is connected with the output end of the OR gate 15 and the control signal output end S1, and the third end of the first transistor is connected to the second input end of the comparison module 12.

[0070] The output end of the comparison module 12 is connected to the input end of the compensation module 13.

[0071] The output end of the compensation module 13 is connected to the input end of the driving module 14 .

[0072] The first input terminal of the OR gate 15 is connected to the first output terminal of the driving module 14 , the second input terminal is connected to the second output terminal of the driving module 14 , the third input terminal is connected to the third output terminal of the driving module 14 , and the fourth input terminal is connected to the fourth output terminal of the driving module 14 .

[0073] The first transistor mentioned here can be understood as a thin film transistor, such as a triode, a MOS transistor, or an IGBT. A P-type thin film transistor is used here. The first terminal of the first transistor here is the source of the P-type thin film transistor, the second terminal is the gate of the P-type thin film transistor, and the third terminal is the drain of the P-type thin film transistor.

[0074] according to Figure 1 In the provided structure, the first transistor T1 is turned on by a low-level control signal, and the timing control module 11 outputs a timing signal to the comparison module 12 and the first transistor T1. The timing signal is then input into the comparison module 12 via the first transistor T1. The comparison module 12 then inputs the timing signal into the compensation module 13 for signal compensation. The compensated signal is then input into the driver module 14. The driver module 14 generates its own drive signal based on the compensation signal, so that the driver module 14 uses the drive signal to drive the display panel. This prevents external interference on the timing signal output by the timing control module, which could affect the timing signal and the driver module's ability to drive and control external devices, thereby achieving stable output.

[0075] When the driving signal is abnormal, the abnormal driving signal is input to the OR gate 15. After logical processing by the OR gate 15, the first transistor is controlled to be in the off state, so that the timing control module 11 cannot transmit the timing signal to the driving module 14. This further avoids the phenomenon that the timing control module continues to output the timing signal due to the abnormality of the driving module, resulting in unstable signals driving external devices, and provides a basis for further synchronous drive control.

[0076] Furthermore, the timing control module outputs a LOCK timing signal, assisting the driver module in driving the display panel. The compensation module amplifies and compensates the signal, reducing the impact of external interference signals on the input signal. The comparison module compares the output signals of the timing control module to determine whether the LOCK timing signal currently output by the timing control module is normal.

[0077] The protection circuit provided in the embodiment of the application comprises a timing control module, a first transistor, a comparison module, a compensation module, a driving module and an OR gate; an output end of the timing control module is connected with a first end of the first transistor and a first input end of the comparison module; a second end of the first transistor is connected with an output end of the OR gate and a control signal output end, and a third end of the first transistor is connected with a second input end of the comparison module; an output end of the comparison module is connected with an input end of the compensation module; an output end of the compensation module is connected with an input end of the driving module; a first input end of the OR gate is connected with a first output end of the driving module, a second input end is connected with a second output end of the driving module, a third input end is connected with a third output end of the driving module, and a fourth input end is connected with a fourth output end of the driving module. The signal output by the timing control module is detected by the voltage comparator, and the disturbed signal is compensated by the compensation module. According to the scheme, the technical effect of solving the problems of incomplete display, abnormal display and black screen of the panel can be achieved.

[0078] Figure 2 Another structure diagram of a protection circuit provided in the embodiment of the application is shown in the figure. Figure 2 The embodiment is introduced on the basis of the above embodiment. Figure 2 According to the figure provided in the embodiment, the protection circuit specifically comprises:

[0079] a timing control module 11, a first transistor T1, a comparison module 12, a compensation module 13, a driving module 14 and an OR gate 15.

[0080] According to the figure provided in the embodiment, the comparison module 12 in the protection circuit comprises a comparator Q1, a first resistor R4, a second transistor T2 and a first variable resistor R5. Figure 2 The positive input end of the comparator Q1 is connected with the output end of the timing control module 11 as the first input end of the comparison module 12, the reverse input end is connected with one end of the first resistor R4 and one end of the first variable resistor R5, and the output end is connected with the second end of the second transistor T2.

[0081] The first end of the second transistor T2 is connected with the third end of the first transistor T1 as the second input end of the comparison module 12, and the third end is connected with the input end of the compensation module 13 as the output end of the comparison module 12.

[0082] The other end of the first resistor R4 is connected with the first ground end.

[0083] The other end of the first variable resistor R5 is connected with the first power supply output end Vcc.

[0084]

[0085] ​The second transistor can be a thin film transistor, such as a triode, a MOS tube, or an IGBT. In this embodiment, a P-type thin film transistor is used. The first end of the second transistor is the source of the P-type thin film transistor, the second end is the gate of the P-type thin film transistor, and the third end is the drain of the P-type thin film transistor. The first variable resistor can increase the reference voltage, adjust the reference voltage in real time, and be suitable for various timing control types and driving types.

[0086] According to Figure 2 In the provided diagram, the control signal output end S1 always outputs a low level. When the driving module 13 is working normally, the or gate 15 outputs a low level signal, and the first transistor T1 is kept in a conducting state under the action of the low level signal. When the timing control module 11 (hereinafter referred to as TCON module) receives an external interference output interference LOCK timing signal, the comparator Q1 compares with the first variable resistor R5, and outputs a low level. The second transistor T2 is turned on under the action of the low level, so that the interference LOCK timing signal output through the first transistor T1 is input to the compensation module through the first transistor T2. The compensation module amplifies and processes the interference LOCK timing signal, achieves compensation, and outputs a stable anti-interference LOCK timing signal. The stable LOCK timing signal acts on the driving module 14, so that the driving module 14 starts the driving program and further drives the external device, realizing the normal starting process. When the driving module 14 is abnormally running, in order to avoid the phenomenon that the external device cannot be stably output due to the continuous output of the LOCK timing signal by the timing control module, when the driving module 14 is abnormally running, the corresponding abnormal signal is output as a high level after logical processing by the or gate 15, the first transistor T1 is controlled to be disconnected, and the output of the LOCK timing signal is blocked, so as to avoid the phenomenon that the data transmission is abnormal due to the loss of the LOCK timing signal, resulting in a black screen and poor display.

[0087] According to Figure 2 In the provided diagram, the compensation module 13 in the protection circuit includes an amplifier Q2, a second resistor R1, a third resistor R2, a fourth resistor R7, and a second variable resistor R6.

[0088] One end of the second resistor R1 is connected to the output end of the comparison module 12 as the input end of the compensation module 13, and the other end is connected to the positive input end of the amplifier Q2.

[0089] The reverse input end of the amplifier Q2 is connected to one end of the third resistor R2 and one end of the second variable resistor R6, and the output end of the amplifier Q2 is connected to one end of the fourth resistor R7.

[0090] The other end of the third resistor R2 is connected to the second ground end.

[0091] The other end of the second variable resistor R6 is connected with the other end of the fourth resistor R7 as an output end of the compensation module 13 and an input end of the driving module 14.

[0092] The second resistor R1 and the fourth resistor R7 play a role of current limiting. The second variable resistor R6 can increase the amplification factor, adjust the compensation in real time, and be applicable to various timing control types and driving types.

[0093] According to Figure 2 In the provided diagram, the control signal output end S1 always keeps low level output. When the driving module 13 works normally, the low level signal is output by the logical control of the OR gate 15, and the first transistor T1 keeps in the conducting state under the action of the low level signal. When the timing control module 11 (hereinafter referred to as TCON module) receives the interference LOCK timing signal output by external interference, the interference LOCK timing signal is input into the amplifier Q2 after being turned on by the comparison module. The resistance value of the second variable resistor R6 is adjusted to achieve the purpose of adjusting the output amplification factor. The interference LOCK timing signal is amplified and compensated by the amplifier Q2, and a stable timing signal is output. The stable timing signal acts on the driving module 14, and then starts the display of the external device, and realizes normal opening. When the driving module 14 drives abnormally, the corresponding abnormal signal is output by the logical processing of the OR gate 15, and the first transistor T1 is controlled to be turned off, so as to block the output of the LOCK timing signal, avoid the picture black screen and display defects caused by the loss of LOCK timing signal and abnormal data transmission.

[0094] According to Figure 2 In the provided diagram, the driving module 14 in the protection circuit is used for driving the display panel TV to display.

[0095] The driving module 14 includes a plurality of driving units (for example, D1, D2, D3, D4, …).

[0096] The input end of each driving unit is connected to the output end of the compensation module 13 as the input end of the driving module, the first output end of the driving unit is connected to the input end of the OR gate 15, and the second output end of the driving unit is connected to the display panel TV.

[0097] In a possible example scenario, according to Figure 2 The provided diagram is used for realizing the protection control of the display picture. The specific process is as follows:

[0098] The first stage: the control signal output end S1 always outputs low level, the P-type thin film transistor T1 (i.e. the first transistor) is turned on, when the timing control module-TCON board is correctly connected with the display panel TV, the timing control module normally outputs the LOCK timing signal, when the LOCK timing signal is disturbed by the external voltage, the LOCK timing level is lower than the reference voltage of the comparator Q1, a low level voltage is output through the comparator Q1, the P-type thin film transistor T2 (i.e. the second transistor) is opened, and the LOCK timing voltage which is pulled low is compensated.

[0099] The second stage: the LOCK timing voltage which is pulled low enters the positive amplifier Q2 through the current limiting resistor R1, the voltage amplification multiple of the amplifier Q2 is N=1+R6 / R2, the appropriate amplification multiple ratio is obtained by comparing the LOCK timing voltage which is pulled low with the reference voltage and is adjusted through the second variable resistor R6, the LOCK timing signal which is disturbed is stably output to the driving module-Driver IC of the subsequent stage, and the normal communication with the display panel TV is maintained.

[0100] The third stage: when the front-end data is abnormal or the subunit in the driving unit-Driver IC receives the data abnormally, the driving unit-Driver IC outputs high level, the logic circuit of the or gate 15 also outputs a high level to the control signal output end S1, since the control signal output end S1 continuously outputs low level and the high level given by the or gate 15 circuit is superimposed, the P-type thin film transistor T1 is closed, the LOCK timing signal is cut off, and the output data signal protects the rear-end circuit. Thus, the technical effect of solving the panel display incompleteness, display abnormal black screen and other bad phenomena can be achieved.

[0101] Figure 3 A flowchart of a protection method provided for the embodiments of the application is shown. According to the flowchart, the protection method specifically includes the following steps. Figure 3 According to the diagram, the protection method specifically includes the following steps.

[0102] S301, when detecting that the timing control module outputs the interference signal, the switching state of the first transistor is determined.

[0103] The application is applied to the protection circuit. By increasing the timing level detection circuit and the compensation circuit, the timing level can be stably output without being disturbed by the outside, the variable resistor of the reference voltage is increased to adjust the reference voltage in real time, which can be suitable for the selection of various timing control models and various driving chips; the compensation module increases the current limiting resistor protection to avoid the large current impact. When the data of the driving module is abnormal, the feedback branch of the driving module and the or gate logic circuit are used to ensure that the timing signal connection is cut off as long as the driving module receives the abnormal data.

[0104] Further, during the operation of the circuit, an unstable interference signal is detected from the output of the timing control module, in order to protect the external device, first, the switching state of the first transistor connected with the timing control module provides a precondition for reducing the influence of the interference signal on the display device in the next step.

[0105] S302, determining the output signal of the comparison module based on the interference signal.

[0106] Further, since the comparison module is connected with the first transistor and the timing control module, when the timing control module outputs a timing signal with interference, the comparison module compares the reference voltage signal inside the comparison module with the interference signal to determine the size of the output signal, which provides a reference basis for the next step of compensating the signal or blocking the interference signal.

[0107] S303, determining the compensation coefficient of the compensation module according to the output signal.

[0108] The compensation coefficient mentioned here can be understood as the amplification coefficient of the interference signal by the compensation module in the normal operation state of the driving module.

[0109] Further, according to whether the driving module is normally operated, the compensation module compensates the input interference signal, and the compensation coefficient corresponding to the interference signal is obtained by calculating the required compensation multiple, which provides reference data for the next step of outputting a stable timing signal.

[0110] S304, the driving module performs a driving operation on the display panel using the compensation coefficient.

[0111] Further, the compensation coefficient of the interference signal is calculated by the compensation module, the stable timing signal after compensation is output by the compensation processing of the compensation module, and the stable timing signal is input into the driving module to start the driving operation of the driving module on the external device, realizing the device starting processing based on the combination of the stable timing signal and the driving signal, so as to realize the technical effect of solving the incomplete display, abnormal display black screen and other bad phenomena of the display panel.

[0112] The embodiment of the application provides a protection method, when detecting that the timing control module outputs an interference signal, determining the switching state of the first transistor; determining the output signal of the comparison module based on the interference signal; determining the compensation coefficient of the compensation module according to the output signal; and the driving module performs a driving operation on the display panel using the compensation coefficient. The voltage comparison module and the compensation module amplify and compensate the interference signal output by the timing control module, to provide a stable timing signal for the driving module, and solve the incomplete display, abnormal display black screen and other bad phenomena of the display panel caused by unstable timing signal.

[0113] Figure 4 Another protection method provided by the embodiment of the application is shown in the flowchart. Figure 4 is introduced on the basis of the above embodiment. According to Figure 4 The protection method further includes the following steps according to the provided diagram:

[0114] S401, when detecting that the timing control module outputs an interference signal, determining the switching state of the first transistor.

[0115] The present application is applied to the display device. When the timing signal receives external interference, the comparison module and the compensation module compare and compensate the interference signal, and then output a stable timing signal. The stable timing signal and the driving module jointly act on the display panel to realize the stable lighting of the display panel. The technical effect of solving the display panel display not full, display abnormal black screen and other bad phenomenon caused by unstable timing signal.

[0116] Further, during the operation of the circuit, it is detected that the timing control module outputs an unstable interference signal. In order to protect the external device, first, the switching state of the first transistor connected with the timing control module is determined to provide a prerequisite for reducing the influence of the interference signal on the display device in the next step.

[0117] S402, when the driving module is in normal operation mode, obtaining a first low-level signal output by the or gate, and obtaining a second low-level signal output by the control signal output end.

[0118] S403, based on the first low-level signal and the second low-level signal, controlling the first transistor to keep the conduction state.

[0119] Further, according to the working state of the driving module, the switching state of the first transistor is determined. When the driving module is normally operated, the driving unit outputs a low-level signal, and multiple low-level signals act on the or gate. The multiple low-level signals are processed by logic or, and still output a low-level signal. Since the first transistor is a P-type thin film transistor, according to the principle of low-level conduction, the first transistor keeps the conduction state based on the first low-level signal and the second low-level signal.

[0120] S404, when the driving module is in abnormal operation mode, obtaining a first high-level signal output by the or gate, and obtaining a third low-level signal output by the control signal output end.

[0121] S405, based on the first high-level signal and the third low-level signal, controlling the first transistor to keep the off state.

[0122] Further, the switching state of the first transistor is determined according to the working state of the driving module. When the driving module is abnormally running, one or more high-level signals are output by the multiple driving units, the one or more high-level signals act on the OR gate, the multiple high-level signals are subjected to logical OR processing, and a high-level signal is output. Since the first transistor is a P-type thin film transistor, according to the low-level conduction principle, the first transistor remains in the off state based on the first low-level signal and the first high-level signal.

[0123] S406, when the first transistor is in the on state, the fourth low-level signal is output by the comparator based on the interference signal.

[0124] S407, the second transistor is controlled to remain in the on state based on the fourth low-level signal.

[0125] S408, the first target signal is determined based on the second transistor.

[0126] Further, when the first transistor is in the on state, the interference signal is compared with the reference signal, and a low-level signal is output by the comparator after comparison. Since the second transistor is a P-type thin film transistor, according to the low-level conduction principle, the second transistor is turned on after the comparator outputs the low-level signal, and the interference signal is output as the first target signal through the connection between the first transistor and the second transistor, which improves the reference data for the next step of compensating the first target signal.

[0127] S409, when the first transistor is in the off state, the fifth low-level signal is output by the comparator based on the interference signal.

[0128] S410, the second transistor is controlled to remain in the on state based on the fifth low-level signal.

[0129] S411, the second target signal is determined based on the second transistor.

[0130] Further, when the first transistor is in the off state, the interference signal is compared with the reference signal, and a low-level signal is output by the comparator after comparison. Since the second transistor is a P-type thin film transistor, according to the low-level conduction principle, the second transistor is turned on after the comparator outputs the low-level signal. Since the first transistor is in the off state, the interference signal cannot be input to the second transistor, and the signal output by the second transistor at this time is taken as the second target signal.

[0131] S412, when the output signal is the first target signal, the target compensation coefficient is determined based on the second variable resistor and the amplifier.

[0132] S413, when the output signal is the second target signal, the compensation coefficient is determined to be zero.

[0133] Further, when the first target signal is output through the second transistor, the timing signal carrying interference is input into the amplifier, and the target compensation coefficient N is obtained through the adjustment of the first variable resistor according to the amplification formula: N = 1 + R6 / R2. When the first transistor is disconnected due to abnormal operation of the driving module, the second target signal output through the second transistor is empty, that is, there is no timing signal that needs to be compensated by the amplifier, and the compensation coefficient corresponding to this condition is set to 0, that is, the timing signal is not processed.

[0134] S414, when the compensation coefficient is the target compensation coefficient, determining a target compensation signal output by the compensation module.

[0135] S415, performing a driving operation on the external display panel based on the target compensation signal.

[0136] S416, when the compensation coefficient is 0, stopping the driving operation on the display panel based on the driving module.

[0137] Further, when the target compensation coefficient N is obtained, the stable timing signal is obtained after signal compensation, and the stable timing signal is input into the driving module as the target compensation signal. After the driving module receives the target compensation signal, the driving display on the display panel is started, so that the purpose of maintaining normal display under the influence of external interference is achieved. When the compensation coefficient is 0, it indicates that the current driving module is abnormal. In order to protect the display panel from being affected, the first transistor is disconnected to achieve the purpose of disconnecting the timing signal. After this processing, the driving module cannot receive the timing signal, thereby blocking the influence of abnormal signals on the display panel, and solving the bad phenomenon of incomplete display, abnormal display and black screen of the display panel caused by unstable timing signal.

[0138] The embodiment of the application provides another protection method. First, the conduction state of the first transistor is determined by judging whether the driving module is abnormal. When the driving module is normal, a low-level signal is output through the OR gate, and a low level is combined with the low-level output by the control signal output end to control the first transistor to maintain the conduction state. The interference signal output by the timing control module is compared with the basic signal through the comparator to output the first target signal with interference. The compensation coefficient is determined through the adjustment of the second variable resistor and the amplification of the amplifier. Then, the target compensation signal is output, and the driving module can normally drive the display panel to display under the action of the target compensation signal. When the driving module is abnormal, a high level is output through the OR gate to directly control the first transistor to be disconnected, block the compensation of the interference signal and the input to the driving module, so that the driving module cannot receive the timing signal, thereby blocking the influence of abnormal signals on the display panel, and solving the bad phenomenon of incomplete display, abnormal display and black screen of the display panel caused by unstable timing signal.

[0139] Figure 5 A structural schematic diagram of a display device 10000 is provided for an embodiment of the present application. Figure 5 According to the provided diagram, the display device includes a housing, a display panel 1000 and a protection circuit 100 as described in the Figure 1-2 above provided in the housing.

[0140] The above detailed description merely describes the specific implementation of the present application, and is not used to limit the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific implementation of the present application, and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A protection circuit, characterized in that: include: A timing control module, a first transistor, a comparison module, a compensation module, a driving module and an OR gate; The output terminal of the timing control module is connected to the first terminal of the first transistor and the first input terminal of the comparison module; The second end of the first transistor is connected to the output end of the OR gate and the control signal output end, and the third end of the first transistor is connected to the second input end of the comparison module; The output terminal of the comparison module is connected to the input terminal of the compensation module; The output end of the compensation module is connected to the input end of the driving module; The first input terminal of the OR gate is connected to the first output terminal of the driving module, the second input terminal is connected to the second output terminal of the driving module, the third input terminal is connected to the third output terminal of the driving module, and the fourth input terminal is connected to the fourth output terminal of the driving module.

2. The circuit according to claim 1, wherein: The first transistor is in a conducting state under the action of a control signal, the timing control module outputs a timing signal to the comparison module and the first transistor, the first transistor inputs the timing signal into the comparison module, and the comparison module inputs the timing signal into the compensation module for signal compensation, and the compensated signal is input into the driving module, and the driving module generates its own driving signal based on the compensation signal, so that the driving module uses the driving signal to perform driving control on the display panel; When the driving signal is abnormal, the abnormal driving signal is input to the OR gate, and after logic processing by the OR gate, the first transistor is controlled to be in an off state, so that the timing control module cannot transmit the timing signal to the driving module.

3. The circuit according to claim 1, wherein: The comparison module includes: a comparator, a first resistor, a second transistor and a first variable resistor; The positive input terminal of the comparator is connected to the output terminal of the timing control module as the first input terminal of the comparison module, the negative input terminal is connected to one end of the first resistor and one end of the first variable resistor, and the output terminal is connected to the second end of the second transistor; The first terminal of the second transistor is connected to the third terminal of the first transistor as the second input terminal of the comparison module, and the third terminal is connected to the input terminal of the compensation module as the output terminal of the comparison module; The other end of the first resistor is connected to a first ground terminal; The other end of the first variable resistor is connected to the first power output end.

4. The circuit according to claim 1, wherein: The compensation module includes: an amplifier, a second resistor, a third resistor, a fourth resistor and a second variable resistor; One end of the second resistor is connected to the output end of the comparison module as the input end of the compensation module, and the other end is connected to the positive input end of the amplifier; The inverting input terminal of the amplifier is connected to one end of the third resistor and one end of the second variable resistor, and the output terminal of the amplifier is connected to one end of the fourth resistor; The other end of the third resistor is connected to the second ground terminal; The other end of the second variable resistor and the other end of the fourth resistor are connected as the output end of the compensation module and the input end of the driving module.

5. The circuit according to claim 1, wherein: The driving module is used to drive the display panel to display; The driving module includes a plurality of driving units; The input end of each driving unit is connected to the output end of the compensation module as the input end of the driving module, the first output end of the driving unit is connected to the input end of the OR gate, and the second output end of the driving unit is connected to the display panel.

6. A protection method, characterized in that: The protection method is applied to the protection circuit according to any one of claims 1 to 5, and the protection method includes: When it is detected that the timing control module outputs an interference signal, determining the switching state of the first transistor; determining an output signal of a comparison module based on the interference signal; determining a compensation coefficient of a compensation module according to the output signal; The driving module performs a driving operation on the display panel using the compensation coefficient.

7. The method according to claim 6, characterized in that The determining the switching state of the first transistor includes: When the driving module is in a normal operating mode, obtaining a first low-level signal output by the OR gate, and obtaining a second low-level signal output by the control signal output terminal; Based on the first low-level signal and the second low-level signal, controlling the first transistor to remain in an on state; or, When the driving module is in an abnormal operation mode, obtaining a first high-level signal output by the OR gate, and obtaining a third low-level signal output by the control signal output terminal; Based on the first high-level signal and the third low-level signal, the first transistor is controlled to remain in an off state.

8. The method according to claim 7, characterized in that The determining the output signal of the comparison module based on the interference signal includes: When the first transistor is in an on state, controlling the comparator to output a fourth low-level signal based on the interference signal; controlling the second transistor to remain in a turned-on state based on the fourth low-level signal; determining a first target signal based on the second transistor; When the first transistor is in an off state, controlling the comparator to output a fifth low-level signal based on the interference signal; controlling the second transistor to remain in a turned-on state based on the fifth low-level signal; A second target signal is determined based on the second transistor.

9. The method according to claim 8, characterized in that The determining of the compensation coefficient of the compensation module according to the output signal includes: When the output signal is a first target signal, determining a target compensation coefficient based on a second variable resistor and an amplifier; When the output signal is the second target signal, determining the compensation coefficient to be zero; The driving module performs a driving operation on the display panel using the compensation coefficient, including: When the compensation coefficient is a target compensation coefficient, determining a target compensation signal output by the compensation module; performing a driving operation on an external display panel based on the target compensation signal; When the compensation coefficient is zero, the driving operation of the display panel is stopped based on the driving module.

10. A display device, characterized in that: include: The housing comprises a display panel and a protection circuit as claimed in claims 1 to 5.

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