Apparatus, memory device and electronic system

Abstract

This application relates to devices, memory devices, and electronic systems. A device includes a stacked structure including tiers each comprising: a memory level including memory elements; a control logic level vertically adjacent to and in electrical communication with the memory level and including a control logic device configured to implement a portion of control operations of the memory level; and an additional control logic level vertically adjacent to and in electrical communication with the memory level and including an additional control logic device configured to implement an additional portion of the control operations of the memory level. A memory device, a method of operating a device, and an electronic system are also described.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the invention patent application with application date of April 18, 2019, application number 201980029595.4, and invention name “Device, Memory Device and Electronic System”.

[0003] Priority Declaration

[0004] This application is a national phase entry of international patent application PCT / US2019 / 028067, filed on April 18, 2019, which designates the People's Republic of China and was published in English as international patent publication WO2019 / 212753 A1 on November 7, 2019, which claims the benefit under Article 8 of the Patent Cooperation Treaty of U.S. patent application No. 15 / 966,197, entitled "Semiconductor Devices, and Related Memory Devices, Electronic Systems, and Methods of Operating Semiconductor Devices," filed on April 30, 2018. Technical Field

[0005] Embodiments of the present invention relate to the field of semiconductor device design and fabrication. More specifically, embodiments of the present invention relate to semiconductor devices including a stacked structure comprising a memory level operatively associated with a control logic level and an additional control logic level, and to related memory devices, electronic systems, and methods. Background Art

[0006] Semiconductor device designers generally desire to increase the level of integration or feature density within semiconductor devices by reducing the size of individual features and by reducing the separation distance between adjacent features. In addition, semiconductor device designers generally desire designs that are not only compact but also provide performance advantages and simplified design architectures.

[0007] One example of a semiconductor device is a memory device. Memory devices are typically provided as internal integrated circuits in computers or other electronic devices. There are many different types of memory, including but not limited to random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), flash memory, and variable resistance memory. Non-limiting examples of variable resistance memory include resistive random access memory (ReRAM), conductive bridging random access memory (CBRAM), magnetic random access memory (MRAM), phase change material (PCM) memory, phase change random access memory (PCRAM), spin torque transfer random access memory (STTRAM), oxygen vacancy-based memory, and programmable conductor memory.

[0008] A typical memory cell of a memory device includes an access device (e.g., a transistor) and a memory storage structure (e.g., a capacitor). Modern applications of semiconductor devices may employ a significant number of memory cells arranged into a memory array showing rows and columns of memory cells. The memory cells may be electrically accessed via digit lines (e.g., bit lines) and word lines (e.g., access lines) arranged along the rows and columns of memory cells in the memory array. The memory array may be two-dimensional (2D) to show a single stack of memory cells (e.g., a single layer, a single level), or three-dimensional (3D) to show multiple stacks of memory cells (e.g., multiple levels, multiple layers).

[0009] Control logic devices within the base control logic structure of the memory array of an underlying memory device have been used to control the operations (e.g., access operations, read operations, write operations) of the memory cells of the memory device. The assembly of control logic devices electrically communicating with the memory cells of the memory array can be provided by means of routing and interconnect structures. However, as the number of stacks of 3D memory arrays increases, the assembly of control logic devices electrically connecting the memory cells of different stacks of the 3D memory array to the control logic devices within the base control logic structure can create size and spacing complexities associated with the increased amount and size of routing and interconnect structures required to facilitate the electrical connections. Furthermore, the number, size, and arrangement of the different control logic devices employed within the base control logic structure can also undesirably hinder reductions in the size of the memory device, increases in the storage density of the memory device, and / or reductions in manufacturing costs.

[0010] Therefore, it would be desirable to have improved semiconductor devices, control logic assemblies, and control logic devices, as well as methods of forming semiconductor devices, control logic assemblies, and control logic devices that facilitate higher packaging density. Summary of the Invention

[0011] In some embodiments, a device includes a stacked structure, the stacked structure including stacks, each of the stacks including: a memory level including memory elements; a control logic level vertically adjacent to and electrically connected to the memory level and including a control logic device, the control logic device being configured to implement a portion of the control operation of the memory level; and an additional control logic level vertically adjacent to and electrically connected to the memory level and including an additional control logic device, the additional control logic device being configured to implement an additional portion of the control operation of the memory level.

[0012] In an additional embodiment, a method of operating a device includes controlling functions of a stacked structure including a memory level using one or more control logic levels in electrical communication with the memory level. Additionally, controlling different functions of the stacked structure using one or more additional control logic levels in electrical communication with the memory level. Furthermore, controlling different functions of the stacked structure using a base control logic structure in electrical communication with the one or more control logic levels and the one or more additional control logic levels of the stacked structure.

[0013] In another embodiment, a memory device includes a base control logic structure, a stacked structure above the base control logic structure, a first interconnect structure, and a second interconnect structure. The stacked structures each include: a first control logic level above the base control logic structure; a first memory level above and electrically coupled to the first control logic level; a first additional control logic level above and electrically coupled to the first memory level; a second memory level above and electrically coupled to the first additional control logic level; and a second control logic level above and electrically coupled to the second memory level. The first interconnect structure extends from the base control logic structure to the first and second control logic levels of each of the stacked structures. The second interconnect structure extends from the base control logic structure to the first additional control logic level of each of the stacked structures.

[0014] In still other embodiments, an electronic system includes an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device. The memory device includes a stacked structure comprising tiers. Each tier in the stack includes a memory level, a control logic level vertically adjacent to the memory level and including a control logic device configured to implement a portion of control operations for the memory level, and an additional control logic level vertically adjacent to the memory level and including an additional control logic device configured to implement an additional portion of the control operations for the memory level. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A and 1B is a simplified side elevation view of a semiconductor device according to an embodiment of the present invention ( Figure 1A ) and floor plan ( Figure 1B ).

[0016] Figure 2 According to an embodiment of the present invention Figure 1A is a block diagram of a first shared control logic level of a semiconductor device shown in .

[0017] Figure 3 According to an embodiment of the present invention Figure 1A . A block diagram of another shared control logic hierarchy of a semiconductor device is shown in FIG.

[0018] Figure 4A and 4B is a simplified side elevation view of a semiconductor device according to an additional embodiment of the present invention ( Figure 4A ) and floor plan ( Figure 4B ).

[0019] Figure 5 is a schematic block diagram illustrating an electronic system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The present invention describes a semiconductor device including a stacked structure comprising a stack operatively associated with a control logic level and an additional control logic level, as well as a memory device, an electronic system, and a method of operating a semiconductor device. In some embodiments, the semiconductor device includes a stacked structure comprising a plurality of stacks (e.g., layers), each stack individually comprising a memory level vertically positioned between a control logic level and an additional control logic level. The control logic level and the additional control logic level can be configured and operable to control operations of different memory levels, such as different columns and rows of an array of memory elements in a memory level. Thus, the control logic devices and circuits included in the control logic level can be at least partially different from the control logic devices and circuits included in the additional control logic level. The control logic level and / or the additional control logic level can also be shared between a memory level and one or more additional memory levels vertically adjacent to the memory level. For example, a control logic level can be shared between a memory level and an additional memory level that is vertically adjacent to the memory level, such that the control logic level implements the same control operations (e.g., column-based operations) within the memory level and the additional memory level. As another example, an additional control logic level can be shared between a memory level and another memory level that is vertically adjacent to the memory level, such that the control logic level implements the same control operations (e.g., row-based operations) within the memory level and the additional memory level. The control logic devices included in the control logic level and the additional control logic levels associated with at least one tier of the stacked structure can include at least one device including transistors (e.g., vertical transistors, horizontal transistors, fin field-effect transistors (FinFETs)) that are laterally (e.g., horizontally) displaced (e.g., spaced apart, separated) from each other, and / or can include at least one device including transistors (e.g., vertical transistors, horizontal transistors) that are longitudinally (e.g., vertically) displaced from each other. Furthermore, the control logic level and the additional control logic levels associated with each tier of the stacked structure can be electrically connected to a base control logic structure of the semiconductor device. The base control logic structure may include control logic devices and circuits that are different from those included in the control logic level and additional control logic levels of the stacked structure. The additional control logic devices and circuits included in the base control logic structure work together with the control logic devices and circuits included in the control logic level and additional control logic levels associated with each of the tiers of the stacked structure to facilitate desired operations (e.g., access operations, read operations, write operations) of the semiconductor device. The devices, structures, assemblies, and methods of the present invention can facilitate increased efficiency, performance, simplicity, and durability in semiconductor devices that rely on high packaging density, such as 3D memory devices.

[0021] The following description provides specific details such as material type, material thickness, and processing conditions in order to provide a thorough description of embodiments of the present invention. However, those skilled in the art will understand that embodiments of the present invention may be practiced without adopting these specific details. In fact, embodiments of the present invention may be practiced in conjunction with conventional manufacturing techniques employed by the industry. In addition, the description provided below does not form a complete process flow for manufacturing semiconductor devices (e.g., memory devices). The semiconductor device structure described below does not form a complete semiconductor device. Only those process actions and structures necessary to understand the embodiments of the present invention are described in detail below. Additional actions for forming a complete semiconductor device from the semiconductor device structure may be performed by conventional manufacturing techniques. Also note that any figures accompanying this application are for illustrative purposes only and are therefore not drawn to scale. In addition, common elements between the figures may retain the same numerical designations.

[0022] As used herein, the term "configured" refers to the size, shape, material composition, material distribution, orientation, and arrangement of one or more of at least one structure and at least one device to facilitate operation of one or more of the structure and device in a predetermined manner.

[0023] As used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0024] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0025] As used herein, the terms "longitudinal," "vertical," "lateral," and "horizontal" refer to a principal plane of a substrate (e.g., a substrate material, a substrate structure, a substrate configuration, etc.) in or on which one or more structures and / or features are formed and which is not necessarily defined by the Earth's gravitational field. A "lateral" or "horizontal" direction is a direction substantially parallel to the principal plane of the substrate, while a "longitudinal" or "vertical" direction is a direction substantially perpendicular to the principal plane of the substrate. A principal plane of a substrate is defined by a surface of the substrate having a relatively large area compared to other surfaces of the substrate.

[0026] As used herein, "vertically adjacent" or "longitudinally adjacent" features (e.g., structures, layers, stacks, devices) means and includes features that are located in closest vertical proximity (e.g., vertically closest) to each other. Additionally, as used herein, "horizontally adjacent" or "laterally adjacent" features (e.g., structures, layers, stacks, devices) means and includes features that are located in closest horizontal proximity (e.g., horizontally closest) to each other.

[0027] As used herein, for ease of description, spatially relative terms (e.g., "below," "beneath," "lower," "bottom," "above," "upper," "top," "front," "back," "left," "right," etc.) may be used to describe the relationship of one element or feature to another (further) element or feature, as illustrated in the figures. Unless otherwise specified, spatially relative terms are intended to encompass different orientations of material in addition to the orientation depicted in the figures. For example, if the material in the figures were inverted, an element described as being "below," "beneath," "beneath," or "on the bottom" of another element or feature would be oriented "above" or "on top" of the other element or feature. Thus, the term "below" may encompass both orientations of above and below, as would be apparent to one skilled in the art, depending on the context in which the term is used. The material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped, etc.) and the spatially relative descriptors used herein interpreted accordingly.

[0028] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and encompasses the degree to which the given parameter, property, or condition is satisfied with varying degrees (e.g., within an acceptable tolerance) as would be understood by one skilled in the art. By way of example, depending on the particular parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be at least 90.0% satisfied, at least 95.0% satisfied, at least 99.0% satisfied, at least 99.9% satisfied, or even 100.0% satisfied.

[0029] As used herein, "about" or "approximately" with respect to a numerical value of a particular parameter is inclusive of the stated numerical value and the degree of variation from the numerical value that one skilled in the art would understand is within an acceptable tolerance for the particular parameter. For example, "about" or "approximately" with respect to a numerical value may include additional numerical values ​​within a range from 90.0% to 110.0% of the numerical value, such as within a range from 95.0% to 105.0% of the numerical value, within a range from 97.5% to 102.5% of the numerical value, within a range from 99.0% to 101.0% of the numerical value, within a range from 99.5% to 100.5% of the numerical value, or within a range from 99.9% to 100.1% of the numerical value.

[0030] As used herein, the term "NMOS" transistor refers to and includes so-called metal oxide transistors having an N-type channel region. The gate of an NMOS transistor may comprise a conductive metal, another conductive material (e.g., polysilicon), or a combination thereof. As used herein, the term "PMOS" transistor refers to and includes so-called metal oxide transistors having a P-type channel region. The gate of a PMOS transistor may comprise a conductive metal, another conductive material (e.g., polysilicon), or a combination thereof. Thus, the gate structures of such transistors may comprise conductive materials that are not necessarily metals.

[0031] Figure 1A A simplified side elevation view of a semiconductor device 100 (eg, a 3D memory device) is shown in accordance with an embodiment of the present invention. Figure 1A , the semiconductor device 100 includes a base control logic structure 102 and a stacked structure 104 overlying the base control logic structure 102. As described in further detail below, the stacked structure 104 includes a plurality of stacks, for example, stacks 106A-106C (e.g., layers) including a memory level 108, a control logic level 110 (e.g., a thin film transistor (TFT) control logic level), and an additional control logic level 112 (e.g., an additional TFT control logic level). Each of the stacks 106A-106C may include one of the memory levels 108 positioned vertically (e.g., longitudinally) between one of the control logic levels 110 and one of the additional control logic levels 112. The control logic levels 110 and the additional control logic levels 112 may present different configurations from one another (e.g., different control logic devices, different assemblies of control logic devices), and may be configured and operated to perform different control functions for the semiconductor device 100 from one another, also as described in further detail below. Figure 1A As shown in FIG, one or more of the control logic levels 110 can be shared by vertically adjacent memory levels 108 of the stacked structure 104 structure, so that various control operations (e.g., control operations for columns of memory elements) for two (2) vertically adjacent memory levels 108 can be implemented by a single (e.g., only one) control logic level 110 vertically therebetween. Figure 1A , one or more of the additional control logic levels 112 may be shared by vertically adjacent memory levels 108 of the stacked structure 104 structure, such that various control operations for two (2) vertically adjacent memory levels 108 (e.g., control operations for a row of memory elements) may be implemented by a single (e.g., only one) additional control logic level 112 vertically therebetween. The base control logic structure 102 of the semiconductor device 100 may be in electrical communication with one or more (e.g., each) of the stacked structures 104 by way of an interconnect structure 114 extending between the base control logic structure 102 and each of the control logic level 110 and the additional control logic levels 112 of the stacked structure 104. Additionally, the memory levels 108 of the stacked structure 104 may be in electrical communication with the control logic level 110 and the additional control logic levels 112 vertically adjacent thereto by way of an additional interconnect structure 116.

[0032] The base control logic structure 102 may include devices and circuits for controlling various operations of the stacked structure 104. The devices and circuits included in the base control logic structure 102 may be selected relative to the devices and circuits included in the control logic level 110 and the additional control logic level 112 of the stacked structure 104. The devices and circuits included in the base control logic structure 102 may be different from the devices and circuits included in the control logic level 110 and the additional control logic level 112 of the stacked structure 104 and may be used and shared by different tiers 106 of the stacked structure 104 to facilitate desired operation of the stacked structure 104. By way of non-limiting example, the base control logic structure 102 may include one or more (e.g., each) of the following: a charge pump (e.g., V CCP Charge pump, V NEGWL charge pump, DVC2 charge pump), delay-locked loop (DLL) circuit (e.g., ring oscillator), drain supply voltage (V dd ) regulators and various chip / stack control circuits. The devices and circuits included in the base control logic structure 102 may employ different conventional control logic devices (e.g., different conventional CMOS devices, such as conventional CMOS inverters, conventional CMOS NAND gates, conventional CMOS pass-through gates), which are not described in detail herein. Furthermore, as described in further detail below, at least some of the devices and circuits included in the control logic level 110 and the additional control logic level 112 of the stacked structure 104 may also be shared by different (e.g., vertically adjacent) stacks 106 of the stacked structure 104 and may be dedicated to implementing and controlling various operations (e.g., memory level operations) of the stacks 106 (e.g., vertically adjacent stacks 106) associated therewith but not included in the functionality of the devices and circuits included in the base control logic structure 102.

[0033] like Figure 1AAs shown in FIG, the interconnect structure 114 of the semiconductor device 100 may include a first interconnect structure 114A and a second interconnect structure 114B. The first interconnect structure 114A may extend and electrically couple between the base control logic structure 102 and the control logic levels 110 (e.g., the first control logic level 110A and the second control logic level 110B) of the stacked structure 104. The second interconnect structure 114B may extend and electrically couple between the base control logic structure 102 and the additional control logic levels 112 (e.g., the first additional control logic level 112A and the second additional control logic level 112B) of the stacked structure 104. At least some (e.g., each) of the first interconnect structures 114A may be disposed in a different lateral region (e.g., a different lateral area) across the semiconductor device 100 than at least some (e.g., each) of the second interconnect structures 114B. For example, the first interconnect structure 114A may be disposed in a first socket region near (e.g., adjacent to) a first lateral boundary of the stacked structure 104; and for example, the second interconnect structure 114B may be disposed in a second, different socket region near (e.g., adjacent to) a second, different lateral boundary of the stacked structure 104.

[0034] By way of non-limiting example, Figure 1B exhibit Figure 1A The plan view of the semiconductor device 100 shown in FIG. 1 includes a substrate control logic structure 102 ( Figure 1A ) is connected to the control logic level 110 ( Figure 1A ) and additional control logic level 112 ( Figure 1A ) in different socket areas. Figure 1B As shown in FIG. 1 , the first socket region 118 can be positioned proximate to (e.g., adjacent to) and extend in substantially the same lateral direction (e.g., X direction) as the first lateral boundary 117 of the stacked structure 104, and the second socket region 120 can be positioned proximate to (e.g., adjacent to) and extend in substantially the same lateral direction (e.g., Y direction) as the second lateral boundary 119 of the stacked structure 104. For example, the first socket region 118 can laterally accommodate the control logic structure 102 ( Figure 1A ) extends to the control logic level 110 ( Figure 1A ) of the first interconnect structure 114A ( Figure 1A ); and for example, the second socket area 120 may laterally accommodate the control logic structure 102 ( Figure 1A ) extends to an additional control logic level 112 of the stack structure 104 ( Figure 1A ) of the second interconnect structure 114B ( Figure 1A In additional embodiments, the first socket region 118 may laterally accommodate the slave substrate control logic structure 102 ( Figure 1A) extends to an additional control logic level 112 of the stack structure 104 ( Figure 1A ) of the second interconnect structure 114B ( Figure 1A ); and the second socket area 120 may laterally accommodate the control logic structure 102 from the substrate ( Figure 1A ) extends to the control logic level 110 ( Figure 1A ) of the first interconnect structure 114A ( Figure 1A ).

[0035] Return Reference Figure 1A , the stacked structure 104 may include any desired number of stacked layers 106. For clarity and ease of understanding of the drawings and related descriptions, Figure 1AThe stacked structure 104 is shown as including three (3) stacks 106. A first stack 106A of the stacked structure 104 may include a first memory level 108A, a first control logic level 110A, and a first additional control logic level 112A. The first memory level 108A of the first stack 106A may be electrically coupled to and vertically interposed between the first control logic level 110A and the first additional control logic level 112A. A second stack 106B of the stacked structure 104 may vertically overlie the first stack 106A of the stacked structure 104 and may include a first additional control logic level 112A, a second memory level 108B, and a second additional control logic level 112B. The first additional control logic level 112A may be shared by the first memory level 108A of the first stack 106A and the second memory level 108B of the second stack 106B. The second memory level 108B of the second stack 106B can be electrically coupled to and vertically interposed between the first additional control logic level 112A and the second control logic level 110B. The third stack 106C of the stacked structure 104 can vertically overlie the second stack 106B of the stacked structure 104 and can include the second control logic level 110B, the third memory level 108C, and the second additional control logic level 112B. The second control logic level 110B can be shared by the second memory level 108B of the second stack 106B and the third memory level 108C of the third stack 106C. The third memory level 108C of the third stack 106C can be electrically coupled to and vertically interposed between the second control logic level 110B and the second additional control logic level 112B. In additional embodiments, the stacked structure 104 includes a different number of stacks 106. For example, the stacked structure 104 may include greater than three (3) stacks 106 (e.g., greater than or equal to four (4) stacks 106, greater than or equal to eight (8) stacks 106, greater than or equal to sixteen (16) stacks 106, greater than or equal to thirty-two (32) stacks 106, greater than or equal to sixty-four (64) stacks 106) or may include less than three (3) stacks 106 (e.g., two (2) stacks 106).

[0036] The memory levels 108 (e.g., first memory level 108A, second memory level 108B, third memory level 108C) of the stack 106 (e.g., first memory level 106A, second memory level 106B, third memory level 106C) of the stack structure 104 can each individually include an array of memory elements and an array of access devices. For a given memory level 108 (e.g., first memory level 108A, second memory level 108B, or third memory level 108C), the access devices of the access device array can underlie (or overlie) and be in electrical communication with the memory elements of the memory element array. The access devices and the memory elements of the given memory level 108 together can form a memory cell for each of the stack 106 of the stack structure 104.

[0037] For example, the memory element array of each of memory levels 108 may include rows of memory elements extending in a first lateral direction and columns of memory elements extending in a second lateral direction, the second lateral direction being perpendicular to the first lateral direction. In additional embodiments, the array may include a different arrangement of memory elements, such as a hexagonal close-packed arrangement of memory elements. The memory elements of the memory element array may include RAM elements, ROM elements, DRAM elements, SDRAM elements, flash memory elements, variable resistance memory elements, or another type of memory element. In some embodiments, the memory elements include DRAM elements. In additional embodiments, the memory elements include variable resistance memory elements. Non-limiting examples of variable resistance memory elements include ReRAM elements, conductive bridging RAM elements, MRAM elements, PCM memory elements, PCRAM elements, STTRAM elements, oxygen vacancy-based memory elements, and programmable conductor memory elements.

[0038] For example, the number and lateral positioning of access devices in the access device array of each of the memory levels 108 may correspond to the number and lateral positioning of memory elements in the memory element array of a given memory level. For example, the access devices may each individually include: a channel region between a pair of source / drain regions; and a gate configured to electrically connect the source / drain regions to each other through the channel region. The access devices may include planar access devices (e.g., planar TFT access devices; planar diode devices, such as planar two-terminal diode devices; planar threshold switching devices) or vertical access devices (e.g., vertical TFT access devices; vertical diode devices, such as vertical two-terminal diode devices; vertical threshold switching devices). Planar access devices can be distinguished from vertical access devices based on the direction of current flow between their source and drain regions. The current flow between the source region and the drain region of the vertical access device is primarily substantially orthogonal (e.g., perpendicular) to the major (e.g., main) surface of the underlying substrate or base (e.g., base control logic structure 102), and the current flow between the source region and the drain region of the planar access device is primarily parallel to the major surface of the underlying substrate or base.

[0039] The control logic levels 110 may include TFT control logic levels that each individually include one or more field effect transistors, each including a film that functions as a semiconductor material, a dielectric material, and metal contacts. The control logic levels 110 (e.g., the first control logic level 110A, the second control logic level 110B) employed by the layers 106 (e.g., the first layer 106A, the second layer 106B, and the third layer 106C) of the stacked structure 104 may include devices and circuits for controlling various operations of the memory levels 108 (e.g., the first memory level 108A, the second memory level 108B, and the third memory level 108C) of the stack 106, which are not encompassed (e.g., implemented, implemented, or covered) by the devices and circuits of the base control logic structure 102 and the additional control logic levels 112. As non-limiting examples, the control logic levels 110 may each individually include devices and circuits for controlling column operations of an array (e.g., a memory element array, an access device array) of the memory level 108 with which it is operatively associated, such as one or more (e.g., each) of the following: decoders (e.g., a local stacked decoder, a column decoder), sense amplifiers (e.g., an equalization (EQ) amplifier, an isolation (ISO) amplifier, an NMOS sense amplifier (NSA), a PMOS sense amplifier (PSA)), repair circuits (e.g., a column repair circuit), I / O devices (e.g., a local I / O device), memory test devices, array multiplexers (MUXs), and error checking and correction (ECC) devices. As another non-limiting example, the control logic levels 110 may each individually include devices and circuits for controlling row operations of an array (e.g., a memory element array, an access device array) of the memory level 108 with which it is operatively associated, such as one or more (e.g., each) of the following: a decoder (e.g., a local stack decoder, a row decoder), a driver (e.g., a word line (WL) driver), a repair circuit (e.g., a row repair circuit), a memory test device, a MUX, an ECC device, and a self-refresh / wear leveling device. As described in further detail below, the devices and circuits included in the control logic level 110 may employ control devices such as TFT complementary metal oxide semiconductor (CMOS) devices, including one or more of laterally shifted transistors (e.g., laterally shifted NMOS and PMOS transistors) and vertically shifted transistors (e.g., vertically shifted NMOS and PMOS transistors).

[0040] The devices and circuits of a given control logic level 110 may be used to implement and control operations only within a single (e.g., only one) stack 106 of the stacked structure 104 (e.g., may not be shared between two or more of the stacks 106), or may be used to implement and control operations within multiple (e.g., more than one) stacks 106 of the stacked structure 104 (e.g., may be shared between two or more of the stacks 106). For example, Figure 1A As shown in FIG, a first control logic level 110A may control only operations within the first tier 106A of the stacked structure 104 (e.g., column operations for an array within the first memory level 108A), and a second control logic level 110B may control operations within each of the second tier 106B and the third tier 106C of the stacked structure 104 (e.g., column operations for an array within each of the second memory level 108B and the third memory level 108C). Furthermore, each of the control logic levels 110 of the stacked structure 104 (e.g., the first control logic level 110A, the second control logic level 110B) may exhibit substantially the same configuration (e.g., substantially the same components and arrangement of components), or at least one of the control logic levels 110 of the stacked structure 104 may exhibit a different configuration (e.g., different components and / or different arrangement of components) than at least one other of the control logic levels 110.

[0041] The additional control logic levels 112 may include additional TFT control logic levels each individually including one or more field effect transistors including films of active semiconductor material, dielectric material, and metal contacts. The additional control logic levels 112 (e.g., first additional control logic level 112A, second additional control logic level 112B) employed by the layers 106 (e.g., first layer 106A, second layer 106B, third layer 106C) of the stacked structure 104 may include devices and circuits for controlling various operations of the memory levels 108 (e.g., first memory level 108A, second memory level 108B, third memory level 108C) of the stack 106 that are not encompassed (e.g., implemented, implemented, or covered) by the devices and circuits of the base control logic structure 102 and the control logic level 110. As non-limiting examples, the additional control logic levels 112 may each individually include devices and circuits for controlling row operations of the array (e.g., memory element array, access device array) of the memory level 108 with which it is operatively associated, such as one or more (e.g., each) of the following: decoders (e.g., local stack decoders, row decoders), drivers (e.g., WL drivers), repair circuits (e.g., row repair circuits), memory test devices, MUXs, ECC devices, and self-refresh / wear-leveling devices. As another non-limiting example, the additional control logic levels 112 may each individually include devices and circuits for controlling column operations of the array (e.g., memory element array, access device array) of the memory level 108 with which it is operatively associated, such as one or more (e.g., each) of the following: decoders (e.g., local stack decoders, column decoders), sense amplifiers (e.g., EQ amplifiers, ISO amplifiers, NSAs, PSAs), repair circuits (e.g., column repair circuits), I / O devices (e.g., local I / O devices), memory test devices, MUXs, and ECC devices. As described in further detail below, the devices and circuits included in the additional control logic levels 112 may employ control devices such as TFT CMOS devices, including one or more of laterally shifted transistors (e.g., laterally shifted NMOS and PMOS transistors) and vertically shifted transistors (e.g., vertically shifted NMOS and PMOS transistors).

[0042] The devices and circuits of a given additional control logic level 112 may be used only to implement and control operations within a single (e.g., only one) stack 106 of the stacked structure 104 (e.g., may not be shared between two or more of the stacks 106), or may be used to implement and control operations within multiple (e.g., more than one) stacks 106 of the stacked structure 104 (e.g., may be shared between two or more of the stacks 106). For example, Figure 1A, a first additional level of control logic 112A may control operations within each of the first and second stacks 106A, 106B of the stacked structure 104 (e.g., row operations for the arrays of each of the first and second memory levels 108A, 108B), and a second additional level of control logic 112B may only control operations within the third stack 106C of the stacked structure 104 (e.g., row operations for the arrays within the third memory level 108C). Furthermore, each of the additional levels of control logic 112 of the stacked structure 104 (e.g., the first additional level of control logic 112A, the second additional level of control logic 112B) may exhibit substantially the same configuration (e.g., substantially the same components and arrangement of components), or at least one of the additional levels of control logic 112 of the stacked structure 104 may exhibit a different configuration (e.g., different components and / or different arrangement of components) than at least one other of the additional levels of control logic 112.

[0043] The entire control operation for the memory levels 108 (e.g., first memory level 108A, second memory level 108B, third memory level 108C) of the stacks 106 (e.g., first stack 106A, second stack 106B, third stack 106C) of the stacked structure 104 can be implemented through the combination of the differential control operations and control devices of the base control logic structure 102, the control logic level 110, and the additional control logic level 112. In other words, no one (e.g., none) of the base control logic structure 102, the control logic level 110, and the additional control logic level 112 can exclusively (e.g., by itself) facilitate (e.g., provide, implement) all control operations for a given memory level 108, but rather the combination of the base control logic structure 102, the given control logic level 110, and the given additional control logic level 112 can facilitate all control operations for a given memory level 108. By way of non-limiting example, the combination of the base control logic structure 102, the first control logic level 110A, and the first additional control logic level 112A may facilitate full control of the first memory level 108A of the first stack 106A of the stack structure 104; the combination of the base control logic structure 102, the first additional control logic level 112A, and the second control logic level 110B may facilitate full control of the second memory level 108B of the second stack 106B of the stack structure 104; and the combination of the base control logic structure 102, the second control logic level 110B, and the second additional control logic level 112B may facilitate full control of the third memory level 108C of the third stack 106C of the stack structure 104.

[0044] Figure 2 It is for Figure 1AThe stacked structure 104 ( Figure 1A ) of the laminate 106 ( Figure 1A ) is a block diagram of a configuration of a control logic level 210 used in one or more of ). The configuration of the control logic level 210 may correspond to Figure 1A Alternatively, the configuration of the control logic level 210 may correspond to the configuration of one or more (eg, each) of the control logic levels 110 (eg, the first control logic level 110A, the second control logic level 110B) shown in FIG. Figure 1A The configuration of one or more (e.g., each) of the additional control logic levels 112 (e.g., first additional control logic level 112A, second additional control logic level 112B) shown in FIG. The control logic level 210 may include various control logic devices and circuits that are originally included in circuits outside the stack (e.g., circuits that do not exist within the control logic level 210), such as base control logic structures (e.g., Figure 1A For example, the circuits within the base control logic structure 102 shown in FIG. Figure 2 As shown in FIG, the assembly of control logic devices and circuits present within the control logic level 210 may include one or more (e.g., each) of the following: a local overlay decoder 222, a MUX 224 (in Figure 2 2, a first MUX 224A and a second MUX 224B are illustrated in FIG, a column decoder 226, a sense amplifier 228, a local I / O device 230, a column repair device 232, a memory test device 234, and an ECC device 236. The assembly of control logic devices and circuits present within the control logic level 210 can be interconnected with circuits located outside the control logic level 210, such as at Figure 1A The stack-out devices 238 (e.g., controllers, hosts, global I / O devices) are operatively associated with (e.g., electrically connected to) the base control logic structure 102 shown in FIG. The stack-out devices 238 can send various signals (e.g., stack enable signals 240, column address signals 242, global clock signals 243) to the control logic level 210; and can also receive various signals (e.g., global data signals 244) from the control logic level 210. Although Figure 2 A specific configuration of the control logic hierarchy 210 is depicted, but those skilled in the art will appreciate that different control logic assembly configurations (including different control logic devices and circuits and / or different arrangements of control logic devices and circuits) are known in the art that may be adapted for use in embodiments of the present invention. Figure 2 Just one non-limiting example of the control logic hierarchy 210 is illustrated.

[0045] like Figure 2, located outside the additional control logic level 210 (e.g., Figure 1A 24 and / or the second MUX 224) of the control logic level 210. As described in further detail below, when activated, the MUXs 224 may be individually configured and operated to select one of several input signals and then forward the selected input into a single line.

[0046] A first MUX 224A (e.g., a column MUX) of the control logic level 210 may be in electrical communication with a local stack decoder 222 and a column decoder 226 of the control logic level 210. The first MUX 224A may be activated by a signal from the local stack decoder 222 and may be configured and operable to selectively forward at least one column address signal 242 from an off-stack device 238 to the column decoder 226. The column decoder 226 may be configured and operable to select a stack (e.g., a stack that shares) the control logic level 210 based on a column address select signal received thereby. Figure 1A 106A, the second stack 106B, and the third stack 106C shown in FIG. 106B .

[0047] The column repair device 232 of the control logic level 210 can be in electrical communication with the column decoder 226 and can be configured and operable to restore a memory level (eg, Figure 1A 8C) is replaced with a spare, non-defective column of memory elements in the memory element array of the memory level. The column repair device 232 can convert a column address signal 242 directed to the column decoder 226 (e.g., from the first MUX 224A) for identifying the defective column of memory elements into another column address signal for identifying the spare, non-defective column of memory elements. For example, the column of defective memory elements can be determined using the memory test device 234 of the control logic level 210, as described in further detail below.

[0048] The ECC device 236 of the control logic level 210 may be configured and operated to generate an ECC code (also referred to as a "check bit"). The ECC code may correspond to a particular data value and may be stored along with the data value in a memory level operatively associated with the control logic level 210 (e.g., Figure 1A 108C). When a data value is read back from the memory element, another ECC code is generated and compared to the previously generated ECC code to access the memory element. If non-zero, the difference between the previously generated ECC code and the newly generated ECC code indicates that an error has occurred. If an error condition is detected, the ECC device 236 can then be used to correct the erroneous data.

[0049] The memory test device 234 of the control logic level 210 may be configured and operated to identify a memory level (eg, Figure 1A 8C) of the memory element array. Memory testing device 234 may attempt to access and write test data to memory elements at different column addresses within the memory element array. Memory testing device 234 may then attempt to read data stored at the memory elements and compare the read data with expected test data at the memory elements. If the read data differs from the expected test data, memory testing device 234 may identify the memory elements as defective. The defective memory elements (e.g., columns of defective memory elements) identified by memory testing device 234 may then be acted upon and / or circumvented by other components of control logic hierarchy 210 (e.g., column repair device 232).

[0050] Continue to refer Figure 2 , the local I / O device 230 of the control logic level 210 may be configured and operated to receive data from a digit line selected by the column decoder 226 during a read operation, and to output data to a digit line selected by the column decoder 226 during a write operation. Figure 2 , local I / O device 230 may include a sense amplifier 228 configured and operative to receive a digit line input from a digit line selected by column decoder 226 during a read operation and generate a digital data value. During a write operation, local I / O device 230 may program data into memory elements of a memory level operatively associated with control logic level 210 by placing appropriate voltages on the digit line selected by column decoder 226. For binary operations, one voltage level is typically placed on the digit line to represent a binary "1" and another voltage level represents a binary "0."

[0051] A second MUX 224B of the control logic level 210 can be in electrical communication with the local I / O device 230 and the local layer decoder 222. The second MUX 224B can be enabled by a signal received from the local layer decoder 222, and can be configured and operated to receive digital data values generated by the local I / O device 230 and to generate therefrom a global data signal 244. The global data signal 244 can be forwarded to one or more off-layer devices 238 (e.g., a controller).

[0052] According to embodiments of the disclosure, one or more of the components of the control logic level 210 (e.g., one or more of the local layer decoder 222, the MUXs 224 (the first MUX 224A and / or the second MUX 224B), the column decoder 226, the sense amplifier 228, the local I / O device 230, the column repair device 232, the ECC device 236, the memory test device 234) can employ one or more control logic devices, such as one or more TFT CMOS devices. Non-limiting examples of different control logic devices that can be included in one or more of the components of the control logic level 210 include one or more of an inverter (e.g., a CMOS inverter, such as a balanced CMOS inverter), a pass- through gate (e.g., a CMOS pass-through gate, such as a balanced CMOS pass-through gate), a ring oscillator, and a NAND gate (e.g., a two-input NAND gate, such as a balanced two-input NAND gate). If present, the TFT CMOS devices can include horizontally adjacent transistors (e.g., horizontally adjacent NMOS and PMOS transistors) and / or can include vertically adjacent transistors (e.g., vertically adjacent NMOS and PMOS transistors). The horizontally adjacent transistors (if any) can comprise vertical transistors (e.g., vertical NMOS transistors, vertical PMOS transistors) that exhibit a channel extending vertically between vertically displaced source and drain regions, or can comprise horizontal transistors (e.g., horizontal NMOS transistors, horizontal PMOS transistors) that exhibit a channel extending horizontally between horizontally displaced source and drain regions. The vertically adjacent transistors (if any) can comprise vertical transistors (e.g., vertical NMOS transistors, vertical PMOS transistors) that exhibit a channel extending vertically between vertically displaced source and drain regions, or can comprise horizontal transistors (e.g., horizontal NMOS transistors, horizontal PMOS transistors) that exhibit a channel extending horizontally between horizontally displaced source and drain regions. Thus, reference is made to the foregoing for further details regarding TFT CMOS devices. Figure 1AOne or more components of at least one of the control logic levels 110 (e.g., first control logic level 110A, second control logic level 110B) employed in one or more of the stacks 106 (e.g., first stack 106A, second stack 106B, third stack 106C) of the stacked structure 104 of the described semiconductor device 100 may include one or more TFT CMOS devices, wherein the one or more TFT CMOS devices include at least one NMOS transistor (e.g., vertical NMOS transistor, horizontal NMOS transistor, NMOS fin field-effect transistor (FinFET)) adjacent to (e.g., horizontally adjacent, vertically adjacent to) at least one PMOS transistor (e.g., vertical PMOS transistor, horizontal PMOS transistor, PMOS FinFET).

[0053] Figure 3 It is for Figure 1A The stacked structure 104 ( Figure 1A ) of the laminate 106 ( Figure 1A ) is a block diagram of a configuration of an additional control logic level 312 used in one or more of ). The configuration of the additional control logic level 312 may correspond to Figure 1A Alternatively, the configuration of one or more (eg, each) of the additional control logic levels 112 (eg, first additional control logic level 112A, second additional control logic level 112B) shown in FIG. 312 may correspond to the configuration of the additional control logic level 312. Figure 1A The configuration of one or more (e.g., each) of the control logic levels 110 (e.g., the first control logic level 110A, the second control logic level 110B) shown in FIG. The additional control logic level 312 includes Figure 1A 100 and / or structures (e.g., base control logic structure 102). Thus, the additional control logic level 312 presents various control logic devices and circuits in other levels (e.g., control logic level 110) and / or structures (e.g., base control logic structure 102) of the semiconductor device 100 shown in FIG. Figure 2 The control logic level 210 is described in different configurations. For example, Figure 3 As shown in FIG, the assembly of control logic devices and circuits present within the additional control logic level 312 may include one or more (e.g., each) of the following: a local stack decoder 346, a MUX 348, a row decoder 350, a word line (WL) driver 352, a row repair device 354, a memory test device 356, and a self-refresh / wear leveling device 358. The assembly of control logic devices and circuits present within the additional control logic level 312 may be coupled to a plurality of control logic devices located at the local stack decoder 346, a MUX 348, a row decoder 350, a word line (WL) driver 352, a row repair device 354, a memory test device 356, and a self-refresh / wear leveling device 358. Figure 1A312 (e.g., within the base control logic structure 102). The off-stack device 238 may send various signals, such as a stack enable signal 360, a row address signal 362, and a global clock signal 364, to the additional control logic level 312. Although Figure 3 A specific configuration of additional control logic level 312 is depicted, but those skilled in the art will appreciate that different control logic assembly configurations (including different control logic devices and circuits and / or different arrangements of control logic devices and circuits) are known in the art that may be adapted for use in embodiments of the present invention. Figure 3 Just one non-limiting example of additional control logic levels 312 is illustrated.

[0054] like Figure 3 , located outside the additional control logic level 312 (e.g., Figure 1A One or more of the out-of-stack devices 238 (shown in the base control logic structure 102 shown in FIG. 1 ) may be configured and operated to carry signals (e.g., stack enable signal 360, row address signal 362) to different devices of the additional control logic level 312. For example, the out-of-stack device 238 may send the stack enable signal 360 to the local stack decoder 346, which may decode the stack enable signal 360 and activate the MUX 348 of the additional control logic level 312.

[0055] The MUX 348 (e.g., row MUX) of the additional control logic level 312 may be in electrical communication with the local stack decoder 346 and the row decoder 350 of the additional control logic level 312. The MUX 348 may be activated by a signal from the local stack decoder 346 and may be configured and operative to selectively forward at least one row address signal 362 from the off-stack device 238 to the row decoder 350. The row decoder 350 may be configured and operative to select a stack 106 (e.g., row decoder 350) to employ based on the row address signal 362 received thereby. Figure 1A 106A, the second stack 106B, and the third stack 106C shown in FIG.

[0056] Continue to refer Figure 3 , the row repair device 354 of the additional control logic level 312 can be in electrical communication with the row decoder 350 and can be configured and operable to restore the memory level (e.g., Figure 1A8C) is replaced with a spare, non-defective row of memory elements of the memory element array of the memory level. The row repair device 354 can convert a row address signal 362 directed to the row decoder 350 (e.g., from the MUX 348) for identifying the defective row of memory elements into another row address signal for identifying the spare, non-defective row of memory elements. For example, the defective row of memory elements can be determined using the memory test device 356 of the additional control logic level 312, as described in further detail below.

[0057] The WL driver 352 of the additional control logic level 312 can be in electrical communication with the row decoder 350 and can be configured and operated to activate a stack (e.g., Figure 1A 106C) of the first stack 106A, the second stack 106B, and the third stack 106C shown in FIG. Memory levels operatively associated with the additional control logic level 312 (e.g., the first and second stacks 106A, 106B, and 106C) may be accessed by way of access devices of the memory level for reading or programming by using voltages placed on the word lines using WL drivers 352. Figure 1A Memory elements of one of the memory levels 108A, 108B, 108C shown in FIG.

[0058] The self-refresh / wear leveling device 358 of the additional control logic level 312 can be in electrical communication with the row decoder 350 and can be configured and operable to store data stored in a memory level (e.g., Figure 1A 108C) is shown in the memory level 108A, 108B, 108C shown in FIG. During a self-refresh / wear leveling operation, the self-refresh / wear leveling device 358 may be activated in response to an external command signal and may generate different row address signals that may be forwarded to the row decoder 350. The row decoder 350 may then select a stack of additional control logic levels 312 (e.g., Figure 1A 106C). The row decoder 350 may then communicate with the WL driver 352 to activate the selected word line, and the charge accumulated in the capacitor of the memory element operatively associated with the selected word line may then be amplified by the sense amplifier and then stored again in the capacitor.

[0059] The memory test device 356 of the additional control logic level 312 may be configured and operated to identify a memory level (eg, Figure 1A 8C) of the memory element array. Memory test device 356 may attempt to access and write test data to memory elements at different row addresses within the memory element array. Memory test device 356 may then attempt to read data stored at the memory elements and compare the read data with expected test data at the memory elements. If the read data differs from the expected test data, memory test device 356 may identify the memory elements as defective. The defective memory elements (e.g., rows of defective memory elements) identified by memory test device 356 may then be acted upon and / or circumvented by other components of additional control logic level 312 (e.g., row repair device 354).

[0060] According to an embodiment of the present invention, one or more of the components of the additional control logic level 312 (e.g., one or more of the local stack decoder 346, the MUX 348, the row decoder 350, the WL driver 352, the row repair device 354, the memory test device 356, and the self-refresh / wear-leveling device 358) may employ one or more control logic devices, such as TFT CMOS devices. Non-limiting examples of different control logic devices included in one or more components of the additional control logic level 312 include one or more of an inverter (e.g., a CMOS inverter, such as a balanced CMOS inverter), a pass-through gate (e.g., a CMOS pass-through gate, such as a balanced CMOS pass-through gate), a ring oscillator, and a NAND gate (e.g., a two-input NAND gate, such as a balanced two-input NAND gate). If present, the TFT CMOS device may include horizontally adjacent transistors (e.g., horizontally adjacent NMOS and PMOS transistors) and / or may include vertically adjacent transistors (e.g., vertically adjacent NMOS and PMOS transistors). The horizontally adjacent transistors, if any, may include vertical transistors (e.g., vertical NMOS transistors, vertical PMOS transistors) that present a channel extending vertically between a vertically shifted source region and a drain region, or may include horizontal transistors (e.g., horizontal NMOS transistors, horizontal PMOS transistors) that present a channel extending horizontally between a horizontally shifted source region and a drain region. The vertically adjacent transistors, if any, may include vertical transistors (e.g., vertical NMOS transistors, vertical PMOS transistors) that present a channel extending vertically between a vertically shifted source region and a drain region, or may include horizontal transistors (e.g., horizontal NMOS transistors, horizontal PMOS transistors) that present a channel extending horizontally between a horizontally shifted source region and a drain region. Therefore, the previous reference to Figure 1A One or more components of at least one of the additional control logic levels (e.g., first additional control logic level 112A, second additional control logic level 112B) employed in one or more of the stacks 106 (e.g., first stack 106A, second stack 106B, third stack 106C) of the stacked structure 104 of the described semiconductor device 100 may include one or more TFT CMOS devices, wherein the one or more TFT CMOS devices include at least one NMOS transistor (e.g., vertical NMOS transistor, horizontal NMOS transistor, NMOS FinFET) adjacent to (e.g., horizontally adjacent, vertically adjacent to) at least one PMOS transistor (e.g., vertical PMOS transistor, horizontal PMOS transistor, PMOS FinFET).

[0061] Therefore, according to an embodiment of the present invention, a semiconductor device includes a stacked structure, the stacked structure including a stack, each of the stacks including: a memory level, which includes memory elements; a control logic level, which is vertically adjacent to the memory level and electrically connected to it and includes a control logic device, the control logic device is configured to implement a portion of the control operation of the memory level; and an additional control logic level, which is vertically adjacent to the memory level and electrically connected to it and includes an additional control logic device, the additional control logic device is configured to implement an additional portion of the control operation of the memory level.

[0062] Furthermore, according to an additional embodiment of the present invention, a method of operating a semiconductor device includes controlling functions of a stacked structure including a memory level using one or more control logic levels in electrical communication with the memory level. Furthermore, controlling different functions of the stacked structure using one or more additional control logic levels in electrical communication with the memory level. Furthermore, controlling different functions of the stacked structure using a base control logic structure in electrical communication with the one or more control logic levels and the one or more additional control logic levels of the stacked structure.

[0063] Although Figure 1A The semiconductor device 100 is depicted as including a single stack structure 104, but the semiconductor device 100 may include a plurality (eg, more than one) of stack structures 104. By way of non-limiting example, Figure 4A A simplified side elevation view of a semiconductor device 400 (eg, a 3D memory device) is shown according to an additional embodiment of the present invention. Figure 4A As shown in FIG, the semiconductor device 400 includes a base control logic structure 402 and a plurality of stacked structures 404 overlying the base control logic structure 402. Throughout the remaining description and drawings, functionally similar features are referred to by like reference numerals incremented by 100. To avoid repetition, the following description is not provided herein. Figure 4A Rather, unless otherwise described below, it will be understood that features designated by features designated by an element number incremented by 100 of the element number of a previously described feature (regardless of whether the previously described feature was first described before or after the present paragraph) will be substantially similar to the previously described feature.

[0064] like Figure 4A As shown in FIG. 4 , the semiconductor device 400 may include a first stack structure 404A and a second stack structure 404B, the second stack structure 404B being laterally adjacent to the first stack structure 404A. Each of the stack structures 404 may be substantially similar to the previously described stack structures. Figure 1AFor example, each of the stacked structures 404 may include a stack 406 (e.g., a first stack 406A, a second stack 406B, a third stack 406C), the stack 406 including memory levels 408 (e.g., a first memory level 408A, a second memory level 408B, a third memory level 408C), a control logic level 410 (e.g., a first control logic level 410A, a second control logic level 410B), and an additional control logic level 412 (e.g., a first additional control logic level 412A, a second additional control logic level 412B). Each of the stacks 406 of each of the stacked structures 404 may include one of the memory levels 408 positioned vertically between one of the control logic levels 410 and one of the additional control logic levels 412, wherein the control logic levels 410 and the additional control logic levels 412 exhibit different configurations from one another (e.g., different control logic devices, different assemblies of control logic devices) and are configured and operated to perform different control operations from one another. For example, each of the control logic levels 410 of each of the stacked structures 404 may exhibit a configuration similar to that previously described with reference to FIG. Figure 2 and, for example, each of the additional control logic levels 412 of each of the stacked structures 404 may present a configuration similar to that described previously with reference to FIG. Figure 3 The configuration of the additional control logic level 312 is described. In addition, the base control logic structure 402 of the semiconductor device 400 can be electrically connected to the stack 406 of each of the stacked structures 404 by means of an interconnect structure 414 extending between the base control logic structure 402 and the control logic level 410 and the additional control logic level 412 of each of the stacked structures 404; and the memory level 408 of each of the stacked structures 404 can be electrically connected to the control logic level 410 and the additional control logic level 412 vertically adjacent thereto by means of an additional interconnect structure 416.

[0065] The semiconductor device 400 may include any desired number of stacked structures 404. Figure 4AThe semiconductor device 400 is shown as including two (2) stack structures 104. In additional embodiments, the semiconductor device 400 includes a different number of stack structures 404. For example, the semiconductor device 400 may include greater than or equal to four (4) stack structures 404, greater than or equal to eight (8) stack structures 404, greater than or equal to sixteen (16) stack structures 404, greater than or equal to thirty-two (32) stack structures 404, greater than or equal to sixty-four (64) stack structures 404, greater than or equal to one hundred and twenty-eight (128) stack structures 404, greater than or equal to two hundred and fifty-six (256) stack structures 404, greater than or equal to five hundred and twelve (512) stack structures 404, or greater than or equal to one thousand and twenty-four (1024) stack structures 404. Additionally, the semiconductor device 400 may include any desired distribution of stack structures 404. For example, the semiconductor device 400 may include rows of stacked structures 404 extending in a first lateral direction and columns of stacked structures 404 extending in a second lateral direction that is perpendicular to the first lateral direction.

[0066] like Figure 4A As shown in , the interconnect structure 414 of the semiconductor device 400 may include a first interconnect structure 414A and a second interconnect structure 414B. The first interconnect structure 414A may extend and electrically couple between the base control logic structure 402 and the control logic level 410 of each of the stacked structures 404. The second interconnect structure 414B may extend and electrically couple between the base control logic structure 402 and the additional control logic level 412 of each of the stacked structures 404. At least one of the first interconnect structures 414A (e.g., each) may be disposed across the semiconductor device 400 in a different lateral region (e.g., a different lateral zone) than one of the second interconnect structures 414B (e.g., each). For example, the first interconnect structure 414A may be disposed in at least one socket area located between at least two (2) laterally adjacent stacked structures 404 (e.g., the first stacked structure 404A and the second stacked structure 404B); and the second interconnect structure 414B may be disposed in at least one other socket area that is different from the socket area. By way of non-limiting example, Figure 4B exhibit Figure 4A The semiconductor device 400 shown in FIG. 4 includes a plan view of a semiconductor device 400 including a substrate control logic structure 402 ( Figure 4A ) is connected to the control logic level 410 ( Figure 4A ) and additional control logic level 412 ( Figure 4A ) in different socket areas. Figure 4B , the dotted line 401 corresponds to Figure 4A4. As shown in FIG. 4, a lateral region of the semiconductor device 400 is shown in FIG. 4 (eg, the lateral region of the semiconductor device 400 includes the first stacked structure 404A and the second stacked structure 404B). Figure 4B As shown in FIG, the first socket area 418 can extend in a first lateral direction (e.g., the X direction) and can be positioned between laterally adjacent stack structures 404 (e.g., between the first stack structure 404A and the third stack structure 404C adjacent to the first stack structure 404A in the Y direction; between the second stack structure 404B and the third stack structure 404C adjacent to the second stack structure 404B in the Y direction); and the second socket area 420 can extend in a second lateral direction (e.g., the Y direction) and can be positioned between additional laterally adjacent stack structures 404 (e.g., between the first stack structure 404A and the second stack structure 404B adjacent to the first stack structure 404A in the X direction; between the third stack structure 404C and the fourth stack structure 404D adjacent to the third stack structure 404C in the X direction). For example, the first socket area 418 can laterally accommodate the control logic structure 402 from the base ( Figure 4A ) extends to the control logic level 410 ( Figure 4A ) of the first interconnect structure 414A ( Figure 4A ); and for example, the second socket area 420 may laterally accommodate the control logic structure 402 from the substrate ( Figure 4A ) extends to an additional control logic level 412 of the stack structure 404 ( Figure 4A ) of the second interconnect structure 414B ( Figure 4A In additional embodiments, the first socket region 418 may be laterally contained within the base control logic structure 402 ( Figure 4A ) and the additional control logic level 412 ( Figure 4A ) extending between the second interconnect structure 414B ( Figure 4A ); and the second socket area 420 may be laterally contained in the base control logic structure 402 ( Figure 4A ) and the control logic level 410 ( Figure 4A ) extending between the first interconnect structure 414A ( Figure 4A ).

[0067] Return Reference Figure 4A, one or more of the interconnect structures 414 of the semiconductor device 400 may be shared (e.g., shared) by horizontally adjacent stack structures 404 (e.g., first stack structure 404A and second stack structure 404B) of the semiconductor device 400. At least some (e.g., all) of the corresponding (e.g., substantially similarly vertically positioned) control logic levels 410 of the horizontally adjacent stack structures 404 may share one or more of the first interconnect structures 414A, and / or at least some (e.g., all) of the corresponding additional control logic levels 412 of the laterally adjacent stack structures 404 may share one or more of the second interconnect structures 414B. By way of non-limiting example, as Figure 4A As shown in FIG, one or more of the first interconnect structures 414A may be shared by the first control logic level 410A of the first stacked structure 404A and the second stacked structure 404B, at least one other of the first interconnect structures 414A may be shared by the second control logic level 410B of the first stacked structure 404A and the second stacked structure 404B, at least one of the second interconnect structures 414B may be shared by the first additional control logic level 412A of the first stacked structure 404A and the second stacked structure 404B, and at least one other of the second interconnect structures 414B may be shared by the second additional control logic level 412B of the first stacked structure 404A and the second stacked structure 404B. If one or more interconnect structures 414 are shared by two horizontally adjacent stacked structures 404 (e.g., the first stacked structure 404A and the second stacked structure 404B) of the semiconductor device 400, one or more devices located outside the horizontally adjacent stacked structures 404 may be used to selectively activate one of the two horizontally adjacent stacked structures 404. For example, a device (e.g., a controller) within the base control logic structure 402 may send a stack enable signal to one or more decoders (e.g., one or more local stack decoders) of one of the first stack structure 404A and the second stack structure 404B, which may then decode the stack enable signal and selectively activate one of the first stack structure 404A and the second stack structure 404B relative to the other of the first stack structure 404A and the second stack structure 404B. In additional embodiments, the interconnect structure 414 of the semiconductor device 400 is not shared by horizontally adjacent stack structures 404 (e.g., the first stack structure 404A and the second stack structure 404B) of the semiconductor device 400.

[0068] Therefore, according to an embodiment of the present invention, a memory device includes a base control logic structure, a stacked structure above the base control logic structure, a first interconnect structure, and a second interconnect structure. Each of the stacked structures includes: a first control logic level above the base control logic structure; a first memory level above and electrically coupled to the first control logic level; a first additional control logic level above and electrically coupled to the first memory level; a second memory level above and electrically coupled to the first additional control logic level; and a second control logic level above and electrically coupled to the second memory level. The first interconnect structure extends from the base control logic structure to the first control logic level and the second control logic level of each of the stacked structures. The second interconnect structure extends from the base control logic structure to the first additional control logic level of each of the stacked structures.

[0069] According to embodiments of the present invention, semiconductor devices (e.g., semiconductor devices 100, 400) including semiconductor device structures (e.g., stacked structures 104, 404; substrate control logic structures 102, 402) may be used in embodiments of electronic systems of the present invention. For example, Figure 5 is a block diagram of an illustrative electronic system 503 according to an embodiment of the present invention. For example, electronic system 503 may include a computer or computer hardware component, a server or other network connection hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-capable tablet computer (e.g., or The electronic system 503 includes at least one memory device 505. For example, the memory device 505 can include embodiments of the semiconductor devices (e.g., semiconductor devices 100, 400) previously described herein, where different tiers (e.g., tiers 106, 406) of one or more stack structures (e.g., stack structures 104, 404) of the semiconductor devices each include a memory level (e.g., one of memory levels 108, 408), a control logic level (e.g., one of control logic levels 110, 410), and an additional control logic level (e.g., one of additional control logic levels 112, 412). One or more of the control logic levels and / or one or more of the additional control logic levels of a stack structure can be shared between vertically adjacent tiers of the stack structure. The electronic system 503 can further include at least one electronic signal processor device 507 (commonly referred to as a "microprocessor"). As appropriate, the electronic signal processor device 507 can include embodiments of the semiconductor devices (e.g., semiconductor devices 100, 400) previously described herein. The electronic system 503 can further include one or more input devices 509 for inputting information to the electronic system 503 by a user, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, buttons, or control panels. The electronic system 503 can further include one or more output devices 511 for outputting information (e.g., visual or audio output) to a user, such as, for example, a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device 509 and the output device 511 can comprise a single touch screen device that can be used to both input information to the electronic system 503 and output visual information to a user. The input device 509 and the output device 511 can be in electrical communication with one or more of the memory device 505 and the electronic signal processor device 507.

[0070] Thus, according to embodiments of the present disclosure, an electronic system includes an input device, an output device, a processor device operably coupled to the input device and the output device, and a semiconductor device operably coupled to the processor device. The semiconductor device includes a stack structure including tiers. Each of the tiers includes a memory level, a control logic level vertically adjacent to the memory level and including a control logic device configured to implement a portion of a control operation of the memory level, and an additional control logic level vertically adjacent to the memory level and including an additional control logic device configured to implement an additional portion of the control operation of the memory level.

[0071] Compared to conventional devices, conventional structures, and conventional assemblies, the devices, structures, assemblies, and methods of the present invention advantageously facilitate improved semiconductor device performance, reduced costs (e.g., manufacturing costs, material costs), increased component miniaturization, and greater packaging density. The devices, structures, assemblies, and methods of the present invention may also improve scalability, efficiency, and simplicity compared to conventional devices, conventional structures, and conventional assemblies. For example, relative to conventional semiconductor device configurations, the configuration of semiconductor devices (e.g., semiconductor devices 100, 400) of the present invention (including the configuration of their stacked structures, which present a stack of layers including a memory level, a control logic level, and an additional control logic level) may reduce the lateral size of their base control logic structures (e.g., base control logic structures 102, 402) to facilitate a relatively smaller stacked structure (e.g., stacked structures 104, 404) lateral size while maintaining or improving its efficiency. For example, the smaller stacked structure lateral size may facilitate a relatively higher signal-to-noise ratio and a relatively reduced raw bit error rate for memory read operations. Additionally, providing and sharing control operations of the memory levels (e.g., memory levels 108, 408) of the stacking structure (e.g., stacking structure 104, 404) of the present invention with the aid of the control logic levels (e.g., control logic levels 110, 410) and additional control logic levels (e.g., additional control logic levels 112, 412) of the present invention can provide increased performance and improved memory array, die, and / or socket area efficiency compared to conventional stacking structure configurations by promoting parallel and localized stacking and stacking structure operations.

[0072] Additional non-limiting example embodiments of the invention are described below.

[0073] Embodiment 1: A device comprising: a stacked structure, the stacked structure comprising a stack, each of the stacks comprising: a memory level comprising memory elements; a control logic level vertically adjacent to and electrically connected to the memory level and comprising a control logic device, the control logic device being configured to implement a portion of a control operation of the memory level; and an additional control logic level vertically adjacent to and electrically connected to the memory level and comprising an additional control logic device, the additional control logic device being configured to implement an additional portion of the control operation of the memory level.

[0074] Embodiment 2: The device of Embodiment 1, further comprising a base control logic structure in electrical communication with the stack structure and comprising other control logic devices configured to implement another portion of the control operations of the memory level.

[0075] Embodiment 3: The device according to embodiment 1 or embodiment 2 further includes: a first interconnect structure extending from and between the control logic level of the base control logic structure and each of the stacked layers of the stacked structure; and a second interconnect structure extending from and between the additional control logic level of the base control logic structure and each of the stacked layers of the stacked structure.

[0076] Embodiment 4: The apparatus of embodiment 3, wherein: the first interconnect structure is laterally contained within a first socket region positioned proximate a first lateral boundary of the stacked structure; and the second interconnect structure is laterally contained within a second, different socket region positioned proximate a second, different lateral boundary of the stacked structure.

[0077] Embodiment 5: The device of any one of embodiments 1-4, wherein the memory level is vertically interposed between the control logic level and the additional control logic level.

[0078] Embodiment 6: The device of any one of embodiments 1-5, wherein one or more of the control logic level and the additional control logic level are shared between vertically adjacent tiers of the stacked structure.

[0079] Embodiment 7: The device of any one of embodiments 1 to 6, wherein: the control logic level is configured to control column operations of an array of the memory elements within the memory level, the array comprising columns of the memory elements and rows of the memory elements; and the additional control logic level vertically overlies the control logic level and is configured to control row operations of the array of the memory elements within the memory level.

[0080] Embodiment 8: The device of Embodiment 7, wherein the control logic level includes a control device arrangement including one or more of: a column decoder, a sense amplifier, a local I / O device, and a column repair device.

[0081] Embodiment 9: The device of Embodiment 7, wherein the additional level of control logic comprises an additional control device arrangement comprising one or more of: a row decoder, a word line driver, and a row repair device.

[0082] Embodiment 10: The device of any one of embodiments 1 to 6, wherein: the control logic level is configured to control row operations of an array of the memory elements within the memory level, the array comprising columns of the memory elements and rows of the memory elements; and the additional control logic level vertically overlies the control logic level and is configured to control column operations of the array of the memory elements within the memory level.

[0083] Embodiment 11: The device of any one of embodiments 1-10, wherein the control logic level and the additional control logic level each comprise a TFT CMOS device.

[0084] Embodiment 12: The device of Embodiment 11, wherein one or more of the TFT CMOS devices comprises: a first transistor including an N-type channel region; and a second transistor horizontally adjacent to the first transistor and including a P-type channel region.

[0085] Embodiment 13: The device of Embodiment 11, wherein one or more of the TFT CMOS devices comprises: a first transistor including an N-type channel region; and a second transistor vertically adjacent to the first transistor and including a P-type channel region.

[0086] Embodiment 14: A memory device comprising: a base control logic structure; a stacked structure above the base control logic structure and each comprising: a first control logic level above the base control logic structure; a first memory level above the first control logic level and electrically coupled to the first control logic level; a first additional control logic level above the first memory level and electrically coupled to the first memory level; a second memory level above the first additional control logic level and electrically coupled to the first additional control logic level; and a second control logic level above the second memory level and electrically coupled to the second memory level; and a first interconnect structure extending from the base control logic structure to the first control logic level and the second control logic level of each of the stacked structures; and a second interconnect structure extending from the base control logic structure to the first additional control logic level of each of the stacked structures.

[0087] Embodiment 15: The memory device of Embodiment 14, wherein the first additional level of control logic is configured to partially control operation of each of the first and second memory levels.

[0088] Embodiment 16: The memory device of Embodiment 15, wherein the first additional level of control logic is configured to control row operations of an array of memory elements within the first and second memory levels.

[0089] Embodiment 17: The memory device of embodiment 16, wherein: the first control logic level is configured to control column operations of an array of memory elements within the first memory level; and the second control logic level is configured to control column operations of an array of additional memory elements within the second memory level.

[0090] Embodiment 18: A memory device according to any one of embodiments 14 to 17, wherein: each of the stacked structures further includes: a third memory level that is above the second control logic level and electrically coupled to the second control logic level; and a second additional control logic level that is above the third memory level and electrically coupled to the third memory level; and a portion of the second interconnect structure extends from the base control logic structure to the second additional control logic level of each of the stacked structures.

[0091] Embodiment 19: The memory device of Embodiment 18, wherein the second level of control logic is configured to partially control operation of each of the second and third memory levels.

[0092] Embodiment 20: The memory device of Embodiment 18, wherein the second level of control logic is configured to control column operations of arrays of memory elements within the second and third memory levels.

[0093] Embodiment 21: The memory device of any one of Embodiments 14 to 20, wherein the first control logic level, the first additional control logic level, and the second control logic level comprise TFT levels comprising TFT CMOS devices.

[0094] Embodiment 22: A memory device according to any one of embodiments 14 to 21, wherein at least a portion of the first interconnection structure is inserted between a first one of the stacked structures and a second one of the stacked structures, the second one of the stacked structures being horizontally adjacent to the first one of the stacked structures in a first direction; and at least a portion of the second interconnection structure is inserted between the first one of the stacked structures and a third one of the stacked structures, the third one of the stacked structures being horizontally adjacent to the first one of the stacked structures in a second direction perpendicular to the first direction.

[0095] Embodiment 23: A memory device according to any one of embodiments 14 to 22, wherein one or more of the first interconnect structures and one or more of the second interconnect structures are shared by a first of the stack structures and a second of the stack structures, the second of the stack structures being horizontally adjacent to the first of the stack structures.

[0096] Embodiment 24: A method of operating a device, the method comprising: using one or more control logic levels electrically connected to a memory level to control functions of a stacked structure including the memory level; using one or more additional control logic levels electrically connected to the memory level to control additional different functions of the stacked structure; and using a base control logic structure electrically connected to the one or more control logic levels of the stacked structure and the one or more additional control logic levels to control other different functions of the stacked structure.

[0097] Embodiment 25: An electronic system comprising: at least one input device; at least one output device; at least one processor device operably coupled to the input device and the output device; and at least one memory device operably coupled to the at least one processor device and comprising: a stacked structure comprising stacks, each of the stacks comprising: a memory level; a control logic level vertically adjacent to the memory level and comprising a control logic device, the control logic device being configured to implement a portion of a control operation of the memory level; and an additional control logic level vertically adjacent to the memory level and comprising an additional control logic device, the additional control logic device being configured to implement an additional portion of the control operation of the memory level.

[0098] While the present invention is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, the invention is not limited to the particular forms disclosed. Rather, the invention is intended to cover all modifications, equivalents, and alternatives coming within the scope of the appended claims and their legal equivalents.

Claims

1. A device comprising: A first stacking structure comprising: a first memory level comprising a first memory cell; a first control logic level below the first memory level and comprising a first control logic device, the first control logic device comprising a first thin film transistor, the first control logic device configured to implement a portion of control operations of the first memory level; a second control logic level above the first memory level and comprising a second control logic device, the second control logic device comprising a second thin film transistor, the second control logic device configured to implement an additional portion of the control operations of the first memory level; a second memory level comprising second memory cells above the second control logic level, the The second control logic device of the second control logic level is configured to implement a portion of the control operations of the second memory level; and A third control logic level above the second memory level includes a third control logic device including a third thin film transistor, the third control logic device configured to implement an additional portion of the control operations of the second memory level.

2. The device of claim 1, wherein the first control logic device and the second control logic device comprise complementary metal oxide semiconductor devices.

3. The apparatus according to claim 1, further comprising: A base control logic structure underlying the first stacked structure includes a third control logic device configured to implement another portion of the control operations of the first memory level.

4. A device comprising: A first stacking structure comprising: a first memory level comprising a first memory cell; a first control logic level below the first memory level and comprising a first control logic device including a first thin film transistor, the first control logic device configured to implement a portion of control operations of the first memory level; and a second control logic level above the first memory level and comprising a second control logic device including a second thin-film transistor, the second control logic device configured to implement an additional portion of the control operations of the first memory level; and a second stacking structure, which is adjacent to the first stacking structure in a first horizontal direction, the second stacking structure comprising: a second memory level comprising a second memory cell; a third control logic level below the second memory level and comprising a third control logic device including a third thin film transistor, the third control logic device configured to implement a portion of the control operations of the second memory level; and A fourth control logic level above the second memory level includes a fourth control logic device including a fourth thin film transistor, the fourth control logic device configured to implement an additional portion of the control operations of the second memory level.

5. The apparatus according to claim 4, further comprising: a third stacking structure, which is adjacent to the first stacking structure in a second horizontal direction orthogonal to the first horizontal direction, the third stacking structure comprising: a third memory level comprising a third memory cell; a fifth control logic level below the third memory level and comprising a fifth control logic device, the fifth control logic device comprising a fifth thin film transistor, the fifth control logic device configured to implement a portion of the control operations of the third memory level; and A sixth control logic level, above the third memory level, includes a sixth control logic device including a sixth thin-film transistor, the sixth control logic device configured to implement an additional portion of the control operations of the third memory level.

6. The apparatus according to claim 5, further comprising: a first interconnect structure horizontally disposed between the first stack structure and the second stack structure and electrically connected thereto; and The second interconnection structure is horizontally placed between the first stacking structure and the third stacking structure and is electrically connected thereto.

7. The apparatus according to claim 6, further comprising: a base control logic structure underlying the first, second, and third stacked structures, the base control logic structure being electrically connected to the first and second interconnect structures and comprising a seventh control logic device configured to implement additional control operations for the first, second, and third memory levels.

8. The apparatus according to claim 6, wherein: The first interconnect structure is in electrical communication with the first control logic level of the first stacked structure and the third control logic level of the second stacked structure; as well as The second interconnect structure is in electrical communication with the second control logic level of the first stack structure and the sixth control logic level of the third stack structure.

9. A memory device comprising: Stack structure, each stack structure independently includes: Control logic level; a memory level above and in electrical communication with the control logic level; an additional control logic level above and in electrical communication with the memory level; an interconnection structure interposed between two of the stacked structures adjacent to each other in the first horizontal direction and electrically connected thereto; and An additional interconnection structure is interposed between and electrically connected to the other two of the stacked structures adjacent to each other in a second horizontal direction perpendicular to the first horizontal direction.

10. The memory device of claim 9, wherein the interconnect structure is electrically coupled to the control logic level of each of the two of the stacked structures.

11. The memory device of claim 10, wherein the additional interconnect structure is electrically coupled to the additional control logic level of each of the other two of the stacked structures.

12. The memory device of claim 9, wherein each of the stacked structures further comprises: an additional memory level above and in electrical communication with the additional control logic level; and Other levels of control logic are above and in electrical communication with the additional levels of memory.

13. The memory device of claim 12, wherein: the interconnect structure electrically coupled to the control logic level and the other control logic level of each of the two of the stacked structures; and The additional interconnect structure is electrically coupled to the additional control logic level of each of the other two of the stacked structures.

14. The memory device of claim 9, further comprising a base control logic structure beneath the stacked structure.

15. The memory device of claim 14, wherein the base control logic structure, the control logic level of each of the stacked structures, and the additional control logic level of each of the stacked structures are configured to control operations in the stacked structures that are different from one another.

16. The memory device of claim 9, wherein: The control logic level includes control logic devices configured to control row operations of an array of memory cells of the memory level; and The additional level of control logic includes additional control logic devices configured to control column operations of the array of memory cells of the memory level.

17. An electronic system comprising: input device; output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and comprising: Stacked structures, each stacked structure comprising stacks, each of the stacks comprising: a memory hierarchy comprising memory elements; a control logic level vertically below and in electrical communication with the memory level and comprising control logic devices configured to implement a portion of the control operations of the memory level; and an additional control logic level vertically above and in electrical communication with the memory level and comprising additional control logic devices configured to implement an additional portion of the control operations for the memory level; an interconnection structure interposed between two of the stacked structures adjacent to each other in the first horizontal direction and electrically connected thereto; and An additional interconnection structure is interposed between and electrically connected to the other two of the stacked structures that are adjacent to each other in a second horizontal direction perpendicular to the first horizontal direction.

18. The electronic system of claim 17, wherein each of the memory levels of each of the stacks of each of the stacked structures comprises rows of memory cells extending in the first horizontal direction and columns of memory cells extending in a second horizontal direction orthogonal to the first horizontal direction.

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