A solar cell, a method for manufacturing the same, and a photovoltaic module

Abstract

The application provides a solar cell, a preparation method thereof and a photovoltaic module, and relates to the technical field of photovoltaics. The solar cell comprises a silicon substrate, an interface passivation layer located on the silicon substrate, and a doped semiconductor layer located on the side of the interface passivation layer away from the silicon substrate. The doped semiconductor layer comprises a first sublayer and a second sublayer which are sequentially stacked in a direction away from a tunnel oxide layer. The grain size of the second sublayer is smaller than the grain size of the first sublayer, and the thickness of the first sublayer is greater than the thickness of the second sublayer. The solar cell has less recombination and better surface passivation performance, can effectively improve the minority carrier lifetime, and has high production efficiency.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, in particular to a solar cell and a preparation method thereof, and a photovoltaic module. Background Art

[0002] The silicon substrate of the passivation contact solar cell is sequentially stacked with an interface passivation layer and a doped semiconductor layer. The solar cell has good passivation contact performance and therefore has a wide range of application scenarios.

[0003] Current passivated contact solar cells suffer from uneven carrier collection, high metal-semiconductor contact resistance, and poor surface passivation. Summary of the Invention

[0004] The present invention provides a solar cell, a preparation method thereof, and a photovoltaic module, aiming to solve the problems of uneven carrier collection, high metal-semiconductor contact resistance, and poor surface passivation performance in existing passivated contact solar cells while taking into account production capacity.

[0005] A first aspect of the present invention provides a solar cell comprising:

[0006] Silicon substrate;

[0007] an interface passivation layer, located on the silicon substrate;

[0008] A doped semiconductor layer is located on a side of the interface passivation layer away from the silicon substrate; wherein the doped semiconductor layer includes: a first sublayer and a second sublayer stacked in sequence in a direction away from the interface passivation layer; the grain size of the second sublayer is smaller than the grain size of the first sublayer, and the thickness of the first sublayer is greater than the thickness of the second sublayer.

[0009] In an embodiment of the present invention, the doped semiconductor layer includes: a first sublayer and a second sublayer stacked sequentially in a direction away from the interfacial passivation layer. Therefore, in the doped semiconductor layer, the second sublayer is the sublayer furthest away from the silicon substrate. The grain size of the second sublayer is smaller than the grain size of the first sublayer, and the grain size of the second sublayer of the doped semiconductor layer is smaller, that is, the nucleation rate of the second sublayer is slower, and therefore the second sublayer is denser and more uniform than the first sublayer. In other words, the surface of one side of the doped semiconductor layer is denser and more uniform, so the surface of the doped semiconductor layer has fewer dangling bonds, less recombination, and better surface passivation performance, which can effectively improve the minority carrier lifetime. In addition, the surface of the second sublayer is denser and more uniform, and the metal-semiconductor contact formed is more uniform, which reduces the contact resistance, is conducive to the uniformity of carrier collection, and improves the short-circuit current. The grain size of the first sublayer is the largest, that is, the nucleation rate of the first sublayer is the fastest. At the same time, the thickness of the first sublayer is the largest, that is, the deposition rate of the first sublayer, which occupies the majority of the doped semiconductor layer, is the fastest, thereby effectively shortening the preparation time of the doped semiconductor layer and improving production efficiency. In summary, this solar cell not only has less recombination and lower contact resistance, but also more uniform carrier collection and better surface passivation performance, which can effectively improve the minority carrier lifetime and has high production efficiency.

[0010] Optionally, the surface roughness of the second sub-layer is smaller than the surface roughness of the first sub-layer.

[0011] Optionally, the refractive index of the second sublayer is greater than the refractive index of the first sublayer.

[0012] Optional,

[0013] The thickness of the first sublayer is 200 nm to 320 nm; and / or,

[0014] The second sublayer has a thickness of 40 nm to 70 nm.

[0015] Optionally, the grain size of the first sub-layer is 45 nm to 55 nm; and / or,

[0016] The grain size of the second sub-layer is 30 nm to 40 nm.

[0017] Optionally, the average surface roughness of the first sublayer is 4.2 nm to 4.5 nm; and / or,

[0018] The average surface roughness of the second sub-layer is 3.7 nm to 3.9 nm.

[0019] Optionally, the refractive index of the first sublayer is 2.95 to 3.05; and / or,

[0020] The refractive index of the second sublayer is 3.15 to 3.25.

[0021] Optionally, the doped semiconductor layer further includes: a third sublayer located on a side of the first sublayer away from the second sublayer;

[0022] The grain size of the third sub-layer is smaller than that of the first sub-layer, and the thickness of the first sub-layer is greater than that of the third sub-layer.

[0023] Optionally, the surface roughness of the third sub-layer is smaller than the surface roughness of the first sub-layer; and / or,

[0024] The refractive index of the third sub-layer is greater than the refractive index of the first sub-layer.

[0025] Optionally, the thickness of the third sublayer is 40 nm to 80 nm; and / or,

[0026] The grain size of the third sub-layer is 30 nm to 40 nm.

[0027] Optionally, the average surface roughness of the third sublayer is 3.4 nm to 3.6 nm; and / or,

[0028] The refractive index of the third sublayer is 3.2 to 3.3.

[0029] Optionally, the thickness of the doped semiconductor layer is 250 nm to 400 nm.

[0030] Optionally, the doped semiconductor layer is an N-type doped semiconductor layer and / or a P-type doped semiconductor layer;

[0031] In the case where both the N-type doped semiconductor layer and the P-type doped semiconductor layer include: the first sublayer and the second sublayer, the smallest grain size in the P-type doped semiconductor layer is larger than the largest grain size in the N-type doped semiconductor layer; and / or,

[0032] The thickness of the P-type doped semiconductor layer is greater than that of the N-type doped semiconductor layer.

[0033] A second aspect of the present invention provides a photovoltaic assembly comprising: a plurality of any of the aforementioned solar cells.

[0034] A third aspect of the present invention provides a method for preparing a solar cell, comprising:

[0035] preparing an interface passivation layer on a silicon substrate;

[0036] A doped semiconductor layer is prepared on the side of the interface passivation layer facing away from the silicon substrate; the doped semiconductor layer includes: a first sublayer and a second sublayer stacked in sequence in a direction away from the interface passivation layer; the grain size of the second sublayer is smaller than the grain size of the first sublayer, and the thickness of the first sublayer is greater than the thickness of the second sublayer; during the preparation of both the first sublayer and the second sublayer, the process pressure and process time for preparing the first sublayer are both greater.

[0037] Optionally, the doped semiconductor layer further includes: a third sublayer located on a side of the first sublayer away from the second sublayer;

[0038] During the preparation of both the first sub-layer and the third sub-layer, the process pressure and process time for preparing the first sub-layer are both greater.

[0039] Optionally, forming a doped semiconductor layer on a side of the interface passivation layer facing away from the silicon substrate includes:

[0040] An intrinsic amorphous silicon layer is formed on a side of the interface passivation layer facing away from the silicon substrate; the intrinsic amorphous silicon layer comprises: a first intrinsic amorphous silicon sublayer and a second intrinsic amorphous silicon sublayer stacked in sequence in a direction away from the interface passivation layer; during the preparation of the first intrinsic amorphous silicon sublayer and the second intrinsic amorphous silicon sublayer, the process pressure and process time of the first intrinsic amorphous silicon sublayer are both greater;

[0041] The intrinsic amorphous silicon layer is doped to obtain a doped semiconductor layer.

[0042] Optionally, the intrinsic amorphous silicon layer further includes: a third intrinsic amorphous silicon sublayer, located on a side of the first intrinsic amorphous silicon sublayer away from the second intrinsic amorphous silicon sublayer;

[0043] During the preparation of both the first intrinsic amorphous silicon sub-layer and the third intrinsic amorphous silicon sub-layer, the process pressure and process time for preparing the first intrinsic amorphous silicon sub-layer are both greater.

[0044] Optionally, the process pressure for depositing the first intrinsic amorphous silicon sub-layer is: 180 mTorr to 220 mTorr;

[0045] The process pressure for depositing the second intrinsic amorphous silicon sub-layer is: 100 mTorr to 120 mTorr; and / or,

[0046] The process duration for depositing the first intrinsic amorphous silicon sublayer is: 55 minutes to 95 minutes;

[0047] The process time for depositing the second intrinsic amorphous silicon sublayer is 20 minutes to 37 minutes.

[0048] Optionally, the process pressure for depositing the third intrinsic amorphous silicon sub-layer is: 100 mTorr to 120 mTorr; and / or,

[0049] The process duration for depositing the third intrinsic amorphous silicon sublayer is 18 minutes to 42 minutes.

[0050] The above-mentioned solar cell preparation method, solar cell, and photovoltaic module have the same or similar beneficial effects, and will not be described in detail here to avoid repetition. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0052] Figure 1 A schematic structural diagram of a solar cell in an embodiment of the present invention is shown.

[0053] Description of the accompanying figures:

[0054] 1-silicon substrate, 2-interface passivation layer, 3-doped semiconductor layer, 31-first sublayer, 32-second sublayer, 33-third sublayer. DETAILED DESCRIPTION

[0055] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0056] The present invention provides a solar cell. Figure 1 FIG1 shows a schematic structural diagram of a solar cell according to an embodiment of the present invention. Figure 1 , the solar cell may include: a silicon substrate 1, an interface passivation layer 2, and the interface passivation layer 2 is located on the silicon substrate 1. A doped semiconductor layer 3 is located on the side of the interface passivation layer 2 away from the silicon substrate 1. The material of the interface passivation layer is silicon oxide or the like, and its specific material is not limited. The doped semiconductor layer 3 includes: a first sublayer 31 and a second sublayer 32 stacked in sequence in a direction away from the interface passivation layer 2. That is, in the doped semiconductor layer 3, the second sublayer 32 is the sublayer farthest away from the silicon substrate 1, so one surface of the doped semiconductor layer 3 is the surface of the second sublayer 32.

[0057] The grain size of the first sublayer 31 refers to the size of the grains in the first sublayer 31, which may be the maximum size of the grains in the first sublayer 31 in one of three mutually perpendicular directions. The grain size of the second sublayer 32 refers to the size of the grains in the second sublayer 32, which may be the maximum size of the grains in the second sublayer 32 in one of three mutually perpendicular directions.

[0058] The grain size of the second sublayer 32 is smaller than the grain size of the first sublayer 31, so the grain size of the second sublayer 32 of the doped semiconductor layer 3 is smaller, that is, the nucleation rate of the second sublayer 32 is slower, so the second sublayer 32 is denser and more uniform than the first sublayer 31, that is, the surface of the doped semiconductor layer 3 is denser and more uniform, so the surface of the doped semiconductor layer 3 has fewer dangling bonds, less recombination and better surface passivation performance, which can effectively improve the minority carrier lifetime; in addition, the surface of the second sublayer 32 is denser and more uniform, and the formed metal semiconductor contact is more uniform, which reduces the contact resistance, is beneficial to the uniformity of carrier collection, and improves the short-circuit current.

[0059] The grain size of the second sublayer 32 is smaller than that of the first sublayer 31. This means that the first sublayer 31, located in the middle of the doped semiconductor layer 3, has the fastest deposition rate. Of the first and second sublayers 31, 32, the first sublayer 31 has the greatest thickness. This means that the first sublayer 31, which occupies the majority of the doped semiconductor layer 3, has the fastest deposition rate. This effectively shortens the preparation time of the doped semiconductor layer 3, improving production efficiency and capacity.

[0060] In summary, in this application, the solar cell not only has low recombination and good surface passivation performance, but can effectively improve the minority carrier lifetime and achieve high production efficiency. It should be noted that this application does not limit the doping type of silicon substrate 1. For example, silicon substrate 1 can be a P-type silicon substrate or an N-type silicon substrate. Doped semiconductor layer 3 can be a doped polysilicon layer.

[0061] Optionally, the doped semiconductor layer 3 may be a P-type doped semiconductor layer and / or an N-type doped semiconductor layer, that is, at least one of the P-type doped semiconductor layer and the N-type doped semiconductor layer has the aforementioned first sublayer and second sublayer, and the doping type of the doped semiconductor layer 3 is flexible and diverse. The N-type doped semiconductor layer and the P-type doped semiconductor layer may both be located on the same side of the silicon substrate 1, for example, the solar cell may be a TBC (tunneling oxide passivated back contact) cell, or the N-type doped semiconductor layer and the P-type doped semiconductor layer may be located on different sides of the silicon substrate 1, for example, the solar cell may be a Topcon (tunneling oxide passivated contact) cell.

[0062] Optionally, when both the N-type doped semiconductor layer and the P-type doped semiconductor layer include: the aforementioned first sublayer and second sublayer, the minimum grain size in the P-type doped semiconductor layer is larger than the maximum grain size in the N-type doped semiconductor layer; and / or the thickness of the P-type doped semiconductor layer is larger than the thickness of the N-type doped semiconductor layer. Specifically, in the process of preparing a solar cell, the P-type doped semiconductor layer is usually prepared first, and then the N-type doped semiconductor layer is prepared. Therefore, the P-type doped semiconductor layer undergoes more high-temperature processes than the N-type doped semiconductor layer. Therefore, the P-type doped semiconductor layer has a larger grain size and / or a larger thickness. Therefore, the minimum grain size in the P-type doped semiconductor layer is larger than the maximum grain size in the N-type doped semiconductor layer; and / or the thickness of the P-type doped semiconductor layer is larger than the thickness of the N-type doped semiconductor layer.

[0063] The grain size of the sub-layer can be measured by instruments such as a field emission scanning electron microscope, and there is no limitation on the specific measuring instrument. The thickness of the sub-layer can be measured by a thickness measuring instrument such as an ellipsometer, and there is no limitation on the specific measuring tool. The direction of the thickness of the sub-layer is parallel to the direction in which the first sub-layer 31 and the second sub-layer 32 are stacked in sequence. The silicon substrate 1 may include: a light-facing side and a backlight side relative to each other, and the light-facing side refers to the side that mainly receives light during the normal operation of the solar cell. For example, referring to Figure 1 The interface passivation layer 2 and the doped semiconductor layer 3 may be located only on the light-facing side or only on the backlight side of the silicon substrate 1. Alternatively, the interface passivation layer 2 and the doped semiconductor layer 3 may be located on both the light-facing side and the backlight side of the silicon substrate 1.

[0064] Optionally, the doped semiconductor layer 3 further includes a third sublayer 33, located on the side of the first sublayer 31 away from the second sublayer 32. The third sublayer 33 is the sublayer closest to the silicon substrate 1, and therefore one surface of the doped semiconductor layer 3 is the surface of the third sublayer 33. The grain size of the third sublayer 33 refers to the size of the grains in the third sublayer 33, which can be the maximum size of the grains in the third sublayer 33 in one of three mutually perpendicular directions. If the grain size of the third sublayer 33 is smaller than the grain size of the first sublayer 31, the grain size of the third sublayer 33 of the doped semiconductor layer 3 is smaller, meaning that the nucleation rate of the third sublayer 33 is slower. Therefore, the third sublayer 33 is denser and more uniform than the first sublayer 31. In other words, the surface of the doped semiconductor layer 3 is denser and more uniform. Consequently, the surface of the doped semiconductor layer 3 has fewer dangling bonds, less recombination, and better surface passivation properties, effectively improving the minority carrier lifetime.

[0065] Optionally, the thickness of the third sublayer 33 is less than that of the first sublayer, and thus among the first sublayer 31, the second sublayer 32 and the third sublayer 33, the thickness of the first sublayer 31 is the largest. That is to say, in the doped semiconductor layer 3, the first sublayer 31 located in the middle and occupying its main size has the fastest deposition speed, thereby effectively shortening the preparation time of the doped semiconductor layer 3, improving production efficiency and increasing production capacity.

[0066] The surface roughness of a sublayer refers to the smoothness of the surface of the sublayer. Optionally, the surface roughness of the second sublayer 32 is less than the surface roughness of the first sublayer 31, which means that the surface roughness of the second sublayer 32 located outside the doped semiconductor layer 3 is smaller, and thus the density of the second sublayer 32 located outside the doped semiconductor layer 3 is more uniform. Therefore, the surface of the doped semiconductor layer 3 has fewer dangling bonds, less recombination, and better surface passivation performance, which can effectively improve the minority carrier lifetime; in addition, the surface of the second sublayer 32 is denser and more uniform, and the metal-semiconductor contact formed is more uniform, which reduces the contact resistance, is conducive to the uniformity of carrier collection, and improves the short-circuit current.

[0067] It should be noted that the surface roughness of the sub-layer can be measured by a surface roughness measuring instrument, such as a 3D profilometer, and the specific measuring instrument is not particularly limited.

[0068] Optionally, when the doped semiconductor layer includes a third sublayer, the surface roughness of the third sublayer 33 is smaller than the surface roughness of the first sublayer 31, that is, the surface roughness of the third sublayer 33 and the second sublayer 32 located on the outside of the doped semiconductor layer 3 are both smaller, and thus the density of the third sublayer 33 and the second sublayer 32 located on the outside of the doped semiconductor layer 3 is more uniform, so the surface of the doped semiconductor layer 3 has fewer dangling bonds, less recombination and better surface passivation performance, which can effectively improve the minority carrier lifetime.

[0069] Optionally, the refractive index of the second sublayer 32 is greater than the refractive index of the first sublayer 31. Generally, under the same material composition, the greater the refractive index, the denser and more uniform the material. Therefore, the second sublayer 32 is denser and more uniform, which means that the second sublayer 32 located on the outside of the doped semiconductor layer 3 is denser and more uniform. Therefore, the surface of the doped semiconductor layer 3 has fewer dangling bonds, less recombination, and better surface passivation performance, which can effectively improve the minority carrier lifetime. In addition, the surface of the second sublayer 32 is denser and more uniform, and the metal-semiconductor contact formed is more uniform, which reduces the contact resistance, is conducive to the uniformity of carrier collection, and improves the short-circuit current. The refractive index of the sublayer can be measured using an instrument such as a refractometer, and the specific measuring instrument is not limited. The aforementioned first sublayer 31 can be deposited separately on the side of the interface passivation layer 2 facing away from the silicon substrate 1, and then the refractive index of the first sublayer 31 can be measured using an instrument such as a refractometer. The second sub-layer 32 can be deposited separately on the side of the interface passivation layer 2 facing away from the silicon substrate 1, and then the refractive index of the second sub-layer 32 can be measured using an instrument such as a refractometer. Alternatively, the first sub-layer 31 can be deposited on the side of the interface passivation layer 2 facing away from the silicon substrate 1, and then the refractive index of the first sub-layer 31 can be measured using an instrument such as a refractometer. Subsequently, the second sub-layer 32 can be deposited on the side of the first sub-layer 31 facing away from the silicon substrate 1, and then the refractive index of the second sub-layer 32 can be measured using an instrument such as a refractometer. In this application, there is no specific limitation on the method for testing the refractive index of each sub-layer. It should be noted that directly measuring the refractive index of a sublayer deposited separately on the side of the interface passivation layer 2 facing away from the silicon substrate 1 may more accurately reflect the refractive index of the sublayer deposited by the corresponding process. However, since the refractive index of the sublayer is mainly determined by the density of the surface material, whether it is directly measuring the refractive index of a sublayer deposited separately on the side of the interface passivation layer 2 facing away from the silicon substrate 1, or measuring the refractive index of a sublayer after depositing it in sequence according to the preparation order, the difference in the refractive indices measured by the two is not much, and both are within the scope of protection of this application.

[0070] Optionally, when the doped semiconductor layer includes a third sublayer, the refractive index of the third sublayer 33 is greater than the refractive index of the first sublayer 31. Generally, given the same material composition, a higher refractive index indicates a denser and more uniform structure. Therefore, the third sublayer 33 is denser and more uniform, meaning that the third sublayer 33 located outside the doped semiconductor layer 3 is denser and more uniform. Consequently, the doped semiconductor layer 3 has fewer surface dangling bonds, less recombination, and better surface passivation, effectively improving the minority carrier lifetime. The third sublayer 33 can be deposited separately on the side of the interface passivation layer 2 facing away from the silicon substrate 1, and the refractive index of the third sublayer 33 can then be measured using a refractive index meter or other instrument. The first sublayer 31 can be deposited separately on the side of the interface passivation layer 2 facing away from the silicon substrate 1, and the refractive index of the first sublayer 31 can then be measured using a refractive index meter or other instrument. The second sublayer 32 can be deposited separately on the side of the interface passivation layer 2 facing away from the silicon substrate 1, and the refractive index of the second sublayer 32 can then be measured using a refractive index meter or other instrument. Alternatively, the third sub-layer 33 may be deposited on the side of the interface passivation layer 2 facing away from the silicon substrate 1, and the refractive index of the third sub-layer 33 may then be measured using a refractometer or other instrument. The first sub-layer 31 may then be deposited on the side of the third sub-layer 33 facing away from the silicon substrate 1, and the refractive index of the first sub-layer 31 may then be measured using a refractometer or other instrument. Subsequently, the second sub-layer 32 may be deposited on the side of the first sub-layer 31 facing away from the silicon substrate 1, and the refractive index of the second sub-layer 32 may then be measured using a refractometer or other instrument. In this application, the method for testing the refractive index of each sub-layer is not specifically limited. It should be noted that directly measuring the refractive index of a sublayer deposited separately on the side of the interface passivation layer 2 facing away from the silicon substrate 1 may more accurately reflect the refractive index of the sublayer deposited by the corresponding process. However, since the refractive index of the sublayer is mainly determined by the density of the surface material, whether it is directly measuring the refractive index of a sublayer deposited separately on the side of the interface passivation layer 2 facing away from the silicon substrate 1, or measuring the refractive index of a sublayer after depositing it in sequence according to the preparation order, the difference in the refractive indices measured by the two is not much, and both are within the scope of protection of this application.

[0071] Optionally, the thickness of the first sublayer 31 is 200 nm (nanometers) to 320 nm. The thickness of the first sublayer 31 is appropriate, not too thin, avoiding increasing the preparation time of the doped semiconductor layer 3, and not too thick, so that the second sublayer 32 located on the outside of the doped semiconductor layer 3 has a more appropriate thickness, so that the surface of the doped semiconductor layer 3 has fewer dangling bonds, less recombination and better surface passivation performance, which can effectively improve the minority carrier lifetime.

[0072] For example, the thickness of the first sublayer 31 can be 200nm, or 213nm, or 230nm, or 244.2nm, or 250nm, or 260nm, or 263.7nm, or 270nm, or 287nm, or 290nm, or 293.1nm, or 300nm, or 303nm, or 312nm, or 320nm.

[0073] Optionally, the thickness of the second sublayer 32 is 40 nm to 70 nm. The thickness of the second sublayer 32 is appropriate and not too thin. This allows the surface of the doped semiconductor layer 3 furthest from the silicon substrate 1 to have fewer dangling bonds, less recombination, and better surface passivation, effectively improving the minority carrier lifetime. In addition, the surface of the second sublayer 32 is denser and more uniform, resulting in a more uniform metal-semiconductor contact, reducing contact resistance, facilitating uniform carrier collection, and improving short-circuit current. It is also not too thick to increase the preparation time of the doped semiconductor layer 3. For example, the thickness of the second sublayer 32 can be 40 nm, 42 nm, 50 nm, 55 nm, 56 nm, 60 nm, 64.8 nm, or 70 nm.

[0074] Optionally, the thickness of the third sublayer 33 is 40 nm to 80 nm. The thickness of the third sublayer 33 is suitable and not too thin, so that the surface of the doped semiconductor layer 3 closest to the silicon substrate 1 has fewer dangling bonds, less recombination, and better surface passivation performance, which can effectively improve the minority carrier lifetime. It is also not too thick and does not increase the preparation time of the doped semiconductor layer 3. For example, the thickness of the third sublayer 33 can be 40 nm, or 43 nm, or 50 nm, or 55.2 nm, or 60 nm, or 67.3 nm, or 70 nm, or 74.1 nm, or 79 nm, or 80 nm.

[0075] Optionally, the grain size of the first sublayer 31 is 45nm to 55nm. The grain size of the first sublayer 31 is relatively appropriate, not too small, avoiding increasing the preparation time of the doped semiconductor layer 3, and not too large, so that the second sublayer 32 located on the outside of the doped semiconductor layer 3 has fewer surface dangling bonds, less recombination and better surface passivation performance, which can effectively improve the minority carrier lifetime.

[0076] For example, the grain size of the first sublayer 31 can be 45nm, or 45.3nm, or 46nm, or 46.2nm, or 47nm, or 47.7nm, or 47.2nm, or 48nm, or 48.5nm, or 49nm, or 50nm, or 50.7nm, or 52nm, or 53.3nm, or 54.2nm, or 55nm.

[0077] Optionally, the grain size of the second sublayer 32 is 30 nm to 40 nm. The grain size of the second sublayer 32 is relatively appropriate and not too large, so that the surface of the doped semiconductor layer 3 farthest from the silicon substrate 1 has fewer dangling bonds, less recombination, and better surface passivation performance, which can effectively improve the minority carrier lifetime. In addition, the surface of the second sublayer 32 is denser and more uniform, and the metal-semiconductor contact formed is more uniform, which reduces the contact resistance, is conducive to the uniformity of carrier collection, and improves the short-circuit current; it is also not too small, which does not increase the preparation time of the doped semiconductor layer 3. For example, the grain size of the second sublayer 32 can be 30 nm, or 32 nm, or 33.7 nm, or 34 nm, or 35 nm, or 35.4 nm, or 36 nm, or 37.8 nm, or 38.4 nm, or 40 nm.

[0078] Optionally, the grain size of the third sublayer 33 is 30nm to 40nm. The grain size of the third sublayer 33 is relatively appropriate, not too small, avoiding too slow deposition speed, not increasing the preparation time of the doped semiconductor layer 3, and not too large. The surface of the third sublayer 33 has fewer dangling bonds, less recombination and better surface passivation performance, which can effectively improve the minority carrier lifetime.

[0079] For example, the grain size of the third sub-layer 33 may be 30 nm, or 31 nm, or 31.4 nm, or 33.2 nm, or 35 nm, or 36.3 nm, or 37.2 nm, or 39 nm, or 40 nm.

[0080] Optionally, the average surface roughness of the first sublayer 31 (i.e., Ra, indicating the average height deviation of tiny undulations on the surface) is 4.2nm to 4.5nm. The average surface roughness of the first sublayer 31 is relatively appropriate, not too small, thereby avoiding increasing the preparation time of the doped semiconductor layer 3, and not too large, so that the surface of the second sublayer 32 located on the outside of the doped semiconductor layer 3 has fewer dangling bonds, less recombination, and better surface passivation performance, which can effectively improve the minority carrier lifetime; in addition, the surface of the second sublayer 32 is denser and more uniform, and the metal semiconductor contact formed is more uniform, thereby reducing the contact resistance, being beneficial to the uniformity of carrier collection, and improving the short-circuit current.

[0081] For example, the average surface roughness of the first sub-layer 31 may be 4.2 nm, or 4.23 nm, or 4.26 nm, or 4.3 nm, or 4.37 nm, or 4.4 nm, or 4.45 nm, or 4.47 nm, or 4.5 nm.

[0082] Optionally, the average surface roughness of the second sublayer 32 is 3.7nm to 3.9nm. The average surface roughness of the second sublayer 32 is appropriate and not too large, so that the surface of the doped semiconductor layer 3 farthest from the silicon substrate 1 has fewer dangling bonds, less recombination, and better surface passivation performance, which can effectively improve the minority carrier lifetime. It is also not too small and does not increase the preparation time of the doped semiconductor layer 3. In addition, the surface of the second sublayer 32 is denser and more uniform, and the metal-semiconductor contact formed is more uniform, reducing the contact resistance, which is beneficial to the uniformity of carrier collection and improving the short-circuit current. For example, the average surface roughness of the second sublayer 32 can be 3.7nm, or 3.72nm, or 3.77nm, or 3.8nm, or 3.84nm, or 3.87nm, or 3.9nm.

[0083] Optionally, the average surface roughness of the third sublayer 33 is 3.4nm to 3.6nm. The average surface roughness of the third sublayer 33 is appropriate, not too small, avoiding too slow deposition speed, not increasing the preparation time of the doped semiconductor layer 3, and not too large. The surface of the third sublayer 33 has fewer dangling bonds, less recombination and better surface passivation performance, which can effectively improve the minority carrier lifetime.

[0084] For example, the average surface roughness of the third sublayer 33 may be 3.4 nm, or 3.43 nm, or 3.42 nm, or 3.45 nm, or 3.5 nm, or 3.51 nm, or 3.54 nm, or 3.58 nm, or 3.6 nm.

[0085] Optionally, the refractive index of the first sublayer 31 is 2.95 to 3.05. The refractive index of the first sublayer 31 is relatively appropriate, not too large, thereby avoiding increasing the preparation time of the doped semiconductor layer 3, and not too small. This allows the second sublayer 32 located on the outside of the doped semiconductor layer 3 to have fewer surface dangling bonds, less recombination, and better surface passivation performance, which can effectively improve the minority carrier lifetime.

[0086] For example, the refractive index of the first sublayer 31 may be 2.95, or 2.96, or 2.97, or 2.98, or 2.99, or 3, or 3.01, or 3.02, or 3.03, or 3.04, or 3.05.

[0087] Optionally, the refractive index of the second sublayer 32 is 3.15 to 3.25. The refractive index of the second sublayer 32 is relatively appropriate and not too small, so that the surface of the doped semiconductor layer 3 farthest from the silicon substrate 1 has fewer dangling bonds, less recombination, and better surface passivation performance, which can effectively improve the minority carrier lifetime. It is also not too large and does not increase the preparation time of the doped semiconductor layer 3. In addition, the surface of the second sublayer 32 is denser and more uniform, and the metal-semiconductor contact formed is more uniform, which reduces the contact resistance, is conducive to the uniformity of carrier collection, and improves the short-circuit current. For example, the refractive index of the second sublayer 32 can be 3.15, or 3.16, or 3.17, or 3.18, or 3.19, or 3.2, or 3.21, or 3.22, or 3.23, or 3.24, or 3.25.

[0088] Optionally, the refractive index of the third sublayer 33 is 3.2 to 3.3. The refractive index of the third sublayer 33 is suitable, not too large, thereby preventing a slow deposition rate and increasing the preparation time of the doped semiconductor layer 3, and not too small. The surface of the third sublayer 33 has fewer dangling bonds, less recombination, and better surface passivation, which can effectively improve the minority carrier lifetime. The refractive index measurement method of each sublayer can be referred to the relevant description above, and to avoid repetition, it is not repeated here.

[0089] For example, the refractive index of the third sublayer 33 may be 3.2, or 3.23, or 3.24, or 3.25, or 3.26, or 3.27, or 3.28, or 3.29, or 3.3.

[0090] Optional, see Figure 1 The thickness h of the doped semiconductor layer 3 is 250 nm to 400 nm. The thickness of the doped semiconductor layer 3 is suitable, and its passivation performance and other properties are excellent without wasting material. For example, the thickness h of the doped semiconductor layer 3 can be 250 nm, or 263.7 nm, or 270 nm, or 290 nm, or 300 nm, or 307.7 nm, or 318.4 nm, or 320 nm, or 325 nm, or 335 nm, or 340 nm, or 350 nm, or 357 nm, or 360 nm, or 372.2 nm, or 380 nm, or 387.6 nm, or 400 nm.

[0091] The present invention further provides a photovoltaic module comprising any of the aforementioned solar cells. The photovoltaic module may further include an encapsulating film and other structures located outside the solar cell. Other structures of the photovoltaic module are not specifically limited. The photovoltaic module has the beneficial effects of any of the aforementioned solar cells and can be described in the aforementioned related descriptions. To avoid repetition, these descriptions are omitted here.

[0092] The present invention also provides a method for preparing a solar cell, which is used to prepare any of the aforementioned solar cells. The method may include the following steps.

[0093] Step 101: prepare an interface passivation layer on a silicon substrate.

[0094] The interface passivation layer 2 may be deposited by a method such as low pressure chemical vapor deposition (LPCVD), and the specific preparation method of the interface passivation layer 2 is not limited.

[0095] Step 102, preparing a doped semiconductor layer on the side of the interface passivation layer facing away from the silicon substrate; the doped semiconductor layer includes: a first sublayer and a second sublayer stacked in sequence in a direction away from the interface passivation layer; the grain size of the second sublayer is smaller than the grain size of the first sublayer, and the thickness of the first sublayer is greater than the thickness of the second sublayer; in the preparation process of both the first sublayer and the second sublayer, the process pressure and process time of preparing the first sublayer are both greater.

[0096] During the preparation of both the first and second sublayers, the first sublayer undergoes greater process pressure and duration. High process pressure results in faster nucleation and deposition rates, resulting in larger grain sizes and a longer process duration. Consequently, the grain size of the second sublayer is smaller than that of the first sublayer, and the thickness of the first sublayer is greater than that of the second sublayer. The doped semiconductor layer may also be prepared using methods such as LPCVD, which is not specifically limited.

[0097] Optionally, the aforementioned doped semiconductor layer also includes: a third sublayer 33, located on the side of the first sublayer 31 away from the second sublayer. During the preparation of both the first sublayer 31 and the third sublayer 33, the process pressure and process time for preparing the first sublayer are greater. The process pressure is high, the nucleation speed is fast, the deposition speed is fast, the size of the formed grains is large, and the process time is longer. Therefore, the grain size of the prepared third sublayer is smaller than the grain size of the first sublayer, and the thickness of the first sublayer is greater than the thickness of the third sublayer.

[0098] Optionally, step 102 may include steps 1021 and 1022. Step 1021: Form an intrinsic amorphous silicon layer on a side of the interface passivation layer facing away from the silicon substrate. The intrinsic amorphous silicon layer includes a first intrinsic amorphous silicon sublayer and a second intrinsic amorphous silicon sublayer stacked sequentially in a direction away from the interface passivation layer. During the preparation of the first intrinsic amorphous silicon sublayer and the second intrinsic amorphous silicon sublayer, the first intrinsic amorphous silicon sublayer has a greater process pressure and a longer process time. Step 1022: Dope the intrinsic amorphous silicon layer to obtain a doped semiconductor layer.

[0099] Specifically, the intrinsic amorphous silicon layer includes: a first intrinsic amorphous silicon sublayer and a second intrinsic amorphous silicon sublayer stacked in sequence in a direction away from the interface passivation layer; during the preparation of both the first intrinsic amorphous silicon sublayer and the second intrinsic amorphous silicon sublayer, the process pressure and process time for preparing the first intrinsic amorphous silicon sublayer are both greater. In the prepared intrinsic amorphous silicon layer, the second intrinsic amorphous silicon sublayer is farthest from the silicon substrate. During the preparation of both the first intrinsic amorphous silicon sublayer and the second intrinsic amorphous silicon sublayer, the process pressure and process time for preparing the first intrinsic amorphous silicon sublayer are both greater. The high process pressure leads to a fast nucleation rate, a fast deposition rate, a large grain size, and a longer process time. Therefore, the prepared first intrinsic amorphous silicon sublayer has a larger thickness and a larger grain size, while the second intrinsic amorphous silicon sublayer has a smaller thickness and grain size.

[0100] During the doping process, the first intrinsic amorphous silicon sublayer is converted into the first sublayer 31, and the second intrinsic amorphous silicon sublayer is converted into the second sublayer 32. Because the prepared first intrinsic amorphous silicon sublayer has a greater thickness and larger grain size, while the second intrinsic amorphous silicon sublayer has a smaller thickness and grain size, the doped first sublayer 31 has the greatest thickness and the largest grain size, while the second sublayer 32 has a smaller thickness and grain size. The doping here can be performed by diffusion or other methods, and this is not specifically limited.

[0101] Optionally, the intrinsic amorphous silicon layer may be deposited by low-pressure chemical vapor deposition, which can facilitate deposition under different process pressures.

[0102] Optionally, the intrinsic amorphous silicon layer also includes: a third intrinsic amorphous silicon sublayer, located on the side of the first intrinsic amorphous silicon sublayer away from the second intrinsic amorphous silicon sublayer. During the preparation of the first intrinsic amorphous silicon sublayer and the third intrinsic amorphous silicon sublayer, the process pressure and process time for preparing the first intrinsic amorphous silicon sublayer are greater. The process pressure is high, the nucleation speed is fast, the deposition speed is fast, the size of the formed grains is large, and the process time is longer. Therefore, the prepared first intrinsic amorphous silicon sublayer has a larger thickness and a larger grain size, and the thickness and grain size of the third intrinsic amorphous silicon sublayer are smaller. After the third intrinsic amorphous silicon sublayer is doped, the third sublayer is obtained.

[0103] Optionally, the process pressure for depositing the third intrinsic amorphous silicon sublayer is 100 mTor to 120 mTor. The process pressure for depositing the third intrinsic amorphous silicon sublayer is relatively suitable, and the grain size of the formed third sublayer 33 is relatively suitable, so that the surface of the doped semiconductor layer 3 closest to the silicon substrate 1 has fewer dangling bonds, less recombination, and better surface passivation performance, which can effectively improve the minority carrier lifetime. The process pressure is not too small and does not increase the preparation time of the doped semiconductor layer 3. For example, the process pressure for depositing the third intrinsic amorphous silicon sublayer can be 100 mTor, or 107.2 mTor, or 109 mTor, or 110 mTor, or 112.3 mTor, or 114.6 mTor, or 115 mTor, or 116.4 mTor, or 117 mTor, or 118.9 mTor, or 120 mTor.

[0104] Optionally, the process pressure for depositing the first intrinsic amorphous silicon sublayer is 180 mTor to 220 mTor. The process pressure for depositing the first intrinsic amorphous silicon sublayer is suitable, the grain size of the formed first sublayer is suitable, and the deposition speed is fast, which can reduce the preparation time of the doped semiconductor layer 3 and improve production efficiency. For example, the process pressure for depositing the first intrinsic amorphous silicon sublayer can be 180 mTor, or 183.2 mTor, or 190 mTor, or 197 mTor, or 192.3 mTor, or 194.6 mTor, or 200 mTor, or 206.4 mTor, or 207 mTor, or 210 mTor, or 211.2 mTor, or 213.7 mTor, or 2115 mTor, or 218.4 mTor, or 220 mTor.

[0105] Optionally, the process pressure for depositing the second intrinsic amorphous silicon sublayer is: 100 mTorr to 120 mTorr. The process pressure for depositing the second intrinsic amorphous silicon sublayer is relatively appropriate, and the grain size of the formed second sublayer 32 is relatively appropriate, so that the surface of the doped semiconductor layer 3 farthest from the silicon substrate 1 has fewer dangling bonds, less recombination and better surface passivation performance, which can effectively improve the minority carrier lifetime; in addition, the surface of the second sublayer 32 is more uniform, and the formed metal semiconductor contact is more uniform, which is beneficial to the uniformity of carrier collection and improves the short-circuit current; the process pressure is not too small and will not increase the preparation time of the doped semiconductor layer 3. For example, the process pressure for depositing the second intrinsic amorphous silicon sublayer may be 100 mTor, or 104.2 mTor, or 108.9 mTor, or 110 mTor, or 111.3 mTor, or 114.7 mTor, or 115 mTor, or 116.7 mTor, or 117 mTor, or 118.3 mTor, or 120 mTor.

[0106] Optionally, the process time for depositing the third intrinsic amorphous silicon sublayer is: 18 minutes (min) to 42 minutes. The process time for depositing the third intrinsic amorphous silicon sublayer is relatively appropriate, and the thickness of the formed third sublayer 33 is relatively appropriate. The surface of the doped semiconductor layer 3 closest to the silicon substrate 1 has fewer dangling bonds, fewer recombination bonds, and better surface passivation performance, which can effectively improve the minority carrier lifetime. The process time is not too short and does not increase the preparation time of the doped semiconductor layer 3. For example, the process time for depositing the third intrinsic amorphous silicon sublayer can be: 18 min, or 18.2 min, or 19 min, or 20 min, or 22.3 min, or 24.6 min, or 29 min, or 30 min, or 31.7 min, or 33.9 min, or 35 min, or 36.8 min, or 40 min, or 42 min.

[0107] Optionally, the process time for depositing the first intrinsic amorphous silicon sublayer is 55 minutes to 95 minutes. The process time for depositing the first intrinsic amorphous silicon sublayer is suitable, the thickness of the formed first sublayer is suitable, and the deposition speed is fast, which can reduce the preparation time of the doped semiconductor layer 3 and improve production efficiency. For example, the process time for depositing the first intrinsic amorphous silicon sublayer can be 55 minutes, or 56.2 minutes, or 59 minutes, or 60 minutes, or 62.3 minutes, or 74.6 minutes, or 79 minutes, or 80 minutes, or 81.7 minutes, or 83.9 minutes, or 85 minutes, or 86.8 minutes, or 90 minutes, or 95 minutes.

[0108] Optionally, the process time for depositing the second intrinsic amorphous silicon sublayer is: 20 minutes to 37 minutes. The process time for depositing the second intrinsic amorphous silicon sublayer is relatively appropriate, and the thickness of the formed second sublayer 32 is relatively appropriate, and the surface of the doped semiconductor layer 3 farthest from the silicon substrate 1 has fewer dangling bonds, less recombination, and better surface passivation performance, which can effectively improve the minority carrier lifetime; in addition, the surface of the second sublayer 32 is more uniform, and the metal semiconductor contact formed is more uniform, which is conducive to the uniformity of carrier collection and improves the short-circuit current; the process time is not too long and will not increase the preparation time of the doped semiconductor layer 3. For example, the process time for depositing the second intrinsic amorphous silicon sublayer can be: or 20 minutes, or 22.5 minutes, or 24.7 minutes, or 29 minutes, or 30 minutes, or 31.5 minutes, or 33.8 minutes, or 35 minutes, or 35.8 minutes, or 36 minutes, or 36.7 minutes, or 37 minutes.

[0109] In the present application, the solar cell, the method for preparing the solar cell, and the photovoltaic module have the same or similar beneficial effects, and reference can be made to the aforementioned related records. To avoid repetition, the relevant parts will not be repeated.

[0110] The present application is further explained below with reference to specific embodiments.

[0111] Example

[0112] The first step is to inject process nitrogen to purge and load the N-type or P-type silicon substrate, check for leaks, and observe the airtightness of the cavity.

[0113] In the second step, the temperature is first raised to 570°C to 630°C, and then oxygen is introduced to grow a 1nm to 2nm thick interface passivation layer, which can be a tunneling oxide layer. The oxygen flow rate is 20slm (Standard Liter per Minute) to 25slm, and the time for preparing the interface passivation layer is 10min to 20min.

[0114] The third step is to stabilize the pressure within a predetermined range under a nitrogen atmosphere.

[0115] Silane (SiH4) is introduced into the LPCVD furnace tube to deposit the intrinsic amorphous silicon sublayer. This is a three-step pressure-variable deposition process. The following details the three substeps of the intrinsic amorphous silicon sublayer deposition process.

[0116] In the first sub-step, the third intrinsic amorphous silicon sub-layer is deposited at low pressure. The process temperature is 570°C to 595°C, the silane flow rate is 110sccm (Standard Cubic Centimeter per Minute) to 400sccm, the process pressure is controlled at 100mTor to 120mTor, the process time is 18min to 42min, and the thickness of the third intrinsic amorphous silicon sub-layer is 40nm to 80nm.

[0117] In the second sub-step, the first intrinsic amorphous silicon sub-layer is deposited under high pressure. The process temperature is consistent with the temperature of the first sub-step, the silane flow rate is 110sccm to 400sccm, the process pressure is controlled at 180mTor to 220mTor, the process time is 55min to 95min, and the thickness of the first intrinsic amorphous silicon sub-layer is 200nm to 320nm.

[0118] In the third sub-step, the second intrinsic amorphous silicon sub-layer is deposited at low pressure. The process temperature is consistent with the temperature of the first sub-step, the silane flow rate is 110sccm to 400sccm, the process pressure is controlled at 100mTor to 120mTor, the process time is 20min to 37min, and the thickness of the second intrinsic amorphous silicon sub-layer is 40nm to 70nm. The third intrinsic amorphous silicon sub-layer, the first intrinsic amorphous silicon sub-layer and the second intrinsic amorphous silicon sub-layer stacked in sequence constitute an intrinsic amorphous silicon layer, and the total thickness of the intrinsic amorphous silicon layer is 250nm to 400nm. Turn off the silane flow, evacuate and purge, and then turn on the nitrogen gas to return the air pressure to an atmospheric pressure.

[0119] The fourth step is to diffuse phosphorus or boron into the formed intrinsic amorphous silicon layer to form a doped semiconductor layer. The doped semiconductor layer includes: a third sublayer, a first sublayer, and a second sublayer stacked in sequence; the third sublayer is adjacent to the interface passivation layer; the grain size of the third sublayer and the grain size of the second sublayer are both smaller than the grain size of the first sublayer, and the thickness of the first sublayer is the largest among the three sublayers. The partial structure diagram of the obtained solar cell is shown as follows: Figure 1 shown.

[0120] The fifth step is to prepare a passivation anti-reflection layer and an electrode on the doped semiconductor layer.

[0121] Comparative Example 1

[0122] The only difference between Comparative Example 1 and the embodiment is the third step. In the third step of Comparative Example 1, low-pressure deposition is used throughout, with a specific process pressure of 100 to 120 mTorr and a process time of 200 to 220 minutes. The remaining steps of Comparative Example 1 are the same as those of the embodiment.

[0123] Comparative Example 2

[0124] The only difference between Comparative Example 2 and the embodiment is the third step. In the third step of Comparative Example 2, high-pressure deposition is used throughout, with a specific process pressure of 180 to 220 mTorr and a process duration of 110 to 120 minutes. The remaining steps of Comparative Example 1 are identical to those of the embodiment.

[0125] Comparative Example 3

[0126] The only difference between Comparative Example 3 and the embodiment is the third step. The third step of Comparative Example 3 is divided into two sub-steps. In the first sub-step of Comparative Example 3, a layer of intrinsic amorphous silicon sub-layer is deposited at low pressure, and the process time is 10 minutes to 25 minutes. The remaining process parameters of the first sub-step of Comparative Example 3 are the same as the remaining process parameters of the first sub-step in the embodiment.

[0127] In the second sub-step of Comparative Example 3, a layer of intrinsic amorphous silicon sub-layer was deposited under high pressure, with a process time of 95 to 105 minutes. The remaining process parameters of the second sub-step of Comparative Example 3 were the same as those of the second sub-step of the embodiment. The total process time of the first and second sub-steps of Comparative Example 3 was 120 to 130 minutes. The remaining steps of Comparative Example 3 were the same as those of the embodiment.

[0128] Under the same environmental conditions, the solar cells formed in the embodiment and comparative examples 1 to 3 were tested. The test results are shown in the table below.

[0129] Table 2: Test results of solar cells formed in Example 1 and Comparative Examples 1 to 3

[0130] PL brightness Voc(mV) Minority carrier lifetime (μs) <![CDATA[J0(fA / cm 2 ) <!-- 11 -->]]> Example 28554 719.51 639 18.16 Comparative Example 1 29096 720.43 650 17.33 Comparative Example 2 14523 709.85 319 31.76 Comparative Example 3 21587 715.82 456 26.28

[0131] In the above table, PL brightness refers to the brightness of photoluminescence when the exposure time is 0.2s under 1Sun. Here, 1Sun refers to the simulation of double the sunlight intensity when testing solar cells. It is equivalent to giving the solar cell the energy of 1 sun, stimulating the internal electron transition of the solar cell, and then collecting the fluorescence signal to understand the passivation, defect conditions and other information of the solar cell. The larger the PL brightness value, the better the passivation effect. Voc refers to the open circuit voltage, and J0 refers to the saturation current density after passivation. It can be inferred from the above table that the passivation performance, open circuit voltage, minority carrier lifetime, and saturation current density after passivation of the embodiment and comparative examples 1 to 3 are ranked from best to worst as follows: comparative example 1> embodiment> comparative example 3> comparative example 2. That is, the solar cell performance of Comparative Example 1 is the best, but the preparation process time of the intrinsic amorphous silicon layer in Comparative Example 1 is 200min to 220min, which is the longest time and the lowest production efficiency. The solar cell performance of the embodiment is second, which is not much different from the solar cell performance of Comparative Example 1. However, the preparation process time of the intrinsic amorphous silicon layer in the embodiment is only 140min to 160min, which is 45min to 80min shorter than the preparation process time of the intrinsic amorphous silicon layer in Comparative Example 1, which can effectively improve production efficiency and effectively increase production capacity. In addition, J0 also proves that the recombination current of Comparative Examples 2 and 3 is extremely large, and the surface passivation performance of Comparative Examples 2 and 3 is poor, and the recombination is serious. Compared with Comparative Example 1, the difference between the embodiment and Comparative Example 1 is not obvious, indicating that the method of the present application can ensure good passivation performance and effectively shorten the deposition time.

[0132] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present application are not limited by the order of the actions described, because according to the embodiments of the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present application.

[0133] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0134] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better embodiment. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in each embodiment of the present invention.

[0135] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

Claims

1. A solar cell, characterized in that: include: Silicon substrate; an interface passivation layer, located on the silicon substrate; a doped semiconductor layer located on a side of the interface passivation layer facing away from the silicon substrate; wherein the doped semiconductor layer comprises: a first sublayer and a second sublayer stacked in sequence in a direction away from the interface passivation layer; The grain size of the second sub-layer is smaller than the grain size of the first sub-layer, and the thickness of the first sub-layer is greater than the thickness of the second sub-layer; The doped semiconductor layer further includes: a third sublayer located on a side of the first sublayer away from the second sublayer; The grain size of the third sub-layer is smaller than the grain size of the first sub-layer, and the thickness of the first sub-layer is greater than the thickness of the third sub-layer; The second sublayer is a sublayer of the doped semiconductor layer that is most distant from the silicon substrate.

2. The solar cell according to claim 1, wherein The surface roughness of the second sub-layer is smaller than the surface roughness of the first sub-layer.

3. The solar cell according to claim 1, wherein The refractive index of the second sub-layer is greater than the refractive index of the first sub-layer.

4. The solar cell according to any one of claims 1 to 3, characterized in that The thickness of the first sublayer is 200 nm to 320 nm; and / or, The second sublayer has a thickness of 40 nm to 70 nm.

5. The solar cell according to any one of claims 1 to 3, characterized in that: The grain size of the first sub-layer is 45 nm to 55 nm; and / or, The grain size of the second sub-layer is 30 nm to 40 nm.

6. The solar cell according to any one of claims 1 to 3, characterized in that: The average surface roughness of the first sub-layer is 4.2 nm to 4.5 nm; and / or, The average surface roughness of the second sub-layer is 3.7 nm to 3.9 nm.

7. The solar cell according to any one of claims 1 to 3, characterized in that: The refractive index of the first sub-layer is 2.95 to 3.05; and / or, The refractive index of the second sublayer is 3.15 to 3.

25.

8. The solar cell according to claim 1, wherein The surface roughness of the third sub-layer is less than the surface roughness of the first sub-layer; and / or, The refractive index of the third sub-layer is greater than the refractive index of the first sub-layer.

9. The solar cell according to claim 1, wherein The thickness of the third sublayer is 40 nm to 80 nm; and / or, The grain size of the third sub-layer is 30 nm to 40 nm.

10. The solar cell according to claim 8, wherein The average surface roughness of the third sub-layer is 3.4 nm to 3.6 nm; and / or, The refractive index of the third sublayer is 3.2 to 3.

3.

11. The solar cell according to any one of claims 1 to 3, characterized in that: The thickness of the doped semiconductor layer is 250 nm to 400 nm.

12. The solar cell according to any one of claims 1 to 3, characterized in that: The doped semiconductor layer is an N-type doped semiconductor layer and / or a P-type doped semiconductor layer; In the case where both the N-type doped semiconductor layer and the P-type doped semiconductor layer include: the first sublayer and the second sublayer, the smallest grain size in the P-type doped semiconductor layer is larger than the largest grain size in the N-type doped semiconductor layer; and / or, The thickness of the P-type doped semiconductor layer is greater than that of the N-type doped semiconductor layer.

13. A photovoltaic module, characterized in that: include: The solar cell according to any one of claims 1 to 12.

14. A method for preparing a solar cell, characterized in that: include: preparing an interface passivation layer on a silicon substrate; preparing a doped semiconductor layer on a side of the interface passivation layer facing away from the silicon substrate; The doped semiconductor layer includes: a first sublayer and a second sublayer stacked in sequence in a direction away from the interface passivation layer; the grain size of the second sublayer is smaller than the grain size of the first sublayer, and the thickness of the first sublayer is greater than the thickness of the second sublayer; during the preparation of the first sublayer and the second sublayer, the process pressure and process time for preparing the first sublayer are both greater; the doped semiconductor layer also includes: a third sublayer located on a side of the first sublayer away from the second sublayer; During the preparation of both the first sub-layer and the third sub-layer, the process pressure and process time for preparing the first sub-layer are both greater; The second sublayer is the sublayer of the doped semiconductor layer that is most distant from the silicon substrate.

15. The method for preparing a solar cell according to claim 14, wherein: A doped semiconductor layer is formed on the side of the interface passivation layer facing away from the silicon substrate, comprising: An intrinsic amorphous silicon layer is formed on a side of the interface passivation layer facing away from the silicon substrate; the intrinsic amorphous silicon layer comprises: a first intrinsic amorphous silicon sublayer and a second intrinsic amorphous silicon sublayer stacked in sequence in a direction away from the interface passivation layer; during the preparation of the first intrinsic amorphous silicon sublayer and the second intrinsic amorphous silicon sublayer, the process pressure and process time of the first intrinsic amorphous silicon sublayer are both greater; The intrinsic amorphous silicon layer is doped to obtain a doped semiconductor layer.

16. The method for preparing a solar cell according to claim 15, wherein: The intrinsic amorphous silicon layer further includes: a third intrinsic amorphous silicon sublayer, located on a side of the first intrinsic amorphous silicon sublayer away from the second intrinsic amorphous silicon sublayer; During the preparation of both the first intrinsic amorphous silicon sub-layer and the third intrinsic amorphous silicon sub-layer, the process pressure and process time for preparing the first intrinsic amorphous silicon sub-layer are both greater.

17. The method for preparing a solar cell according to claim 15, wherein: The process pressure for depositing the first intrinsic amorphous silicon sub-layer is 180 mTorr to 220 mTorr, and the process pressure for depositing the second intrinsic amorphous silicon sub-layer is 100 mTorr to 120 mTorr; and / or, The process duration for depositing the first intrinsic amorphous silicon sublayer is 55 minutes to 95 minutes, and the process duration for depositing the second intrinsic amorphous silicon sublayer is 20 minutes to 37 minutes.

18. The method for preparing a solar cell according to claim 16, wherein: The process pressure for depositing the third intrinsic amorphous silicon sub-layer is: 100 mTorr to 120 mTorr; and / or, The process duration for depositing the third intrinsic amorphous silicon sublayer is 18 minutes to 42 minutes.

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