A multi-channel HDLC de-framing scheduling method

Abstract

The present invention discloses a method for multi-channel HDLC de-framing and scheduling, including receiving unframed data and channel number information, pre-fetching the unframed data according to a waiting room model; continuously monitoring the pre-fetched data, printing frame status information at all times, and providing a bit offset; querying a bit offset table item according to the channel number, and outputting unprocessed HDLC frame data reorganized after the bit offset; using a pipeline model, concurrently removing 0 bits and filling processing on the unprocessed HDLC frame bit by bit to obtain processed HDLC frame data; and distributing the HDLC frame by channel according to the channel number and storing it in a cache, waiting for a subsequent call. The multi-channel HDLC de-framing and scheduling implementation method provided by the present invention uses a concurrent parsing method to efficiently process multi-channel data, which can improve the effective working data throughput of the system and reduce the resource consumption of the system.

Description

Technical Field

[0001] The invention relates to an advanced data link control technology in the communication field, and in particular to a multi-channel HDLC de-framing scheduling method. Background Art

[0002] High level Data Link Control (HDLC) is a bit-oriented data link layer protocol for transmitting data on a synchronous network. HDLC is widely used in the synchronous Point-to-Point Protocol (PPP) service to access the wide area network. It is very important to correctly extract the HDLC frame and complete the zero-bit padding processing at the receiving end.

[0003] In the transmission of HDLC frames, the frame delimiter byte is the binary number 01111110 (hexadecimal number is 0x7E), which indicates the start and end of an HDLC, and the frame delimiter is transmitted in idle time. When there are five consecutive "1"s in a data byte of an HDLC frame, a "0" bit will be inserted immediately after the bit "1". This method is called 0-bit padding, so there will not be more than five consecutive "1"s in the HDLC data frame. When receiving, the extra padding "0" bits need to be removed, that is, to remove the 0-bit padding. To correctly parse an HDLC frame, it is necessary to determine the start and end of the frame and remove the 0-bit padding.

[0004] In the traditional HDLC de-framing method, serial analysis is usually used, that is, 1 byte transmitted on the same channel is processed continuously each time. This method is easier to implement when de-framing, but when processing HDLC data of N channels in a system, N serial analysis modules need to be called, and the resources required by the system are consumed N times. Summary of the invention

[0005] The object of the present invention is to provide a multi-channel HDLC de-framing scheduling method.

[0006] To achieve the above object, the present invention is implemented according to the following technical solutions:

[0007] The present invention comprises the following steps:

[0008] S1: The data pre-fetch unit obtains the unframed data and channel number information, and pre-fetches the unframed data according to the waiting room model; wherein the data pre-fetch unit obtains the unframed data and channel number information transmitted by the previous module, the unframed data is transmitted in units of 1 byte, and the channel number is the corresponding channel of the unframed data to be parsed in the total N channels. The unframed data and channel number information are valid in the same clock cycle, indicating that the unframed data transmitted in the current cycle is the data of a certain channel M. According to the waiting room model, the data of N channels are polled, and the high 3 bytes of data are pre-fetched. The waiting room model is that N waiting rooms correspond to N memory spaces. When the data pre-fetch unit receives the unframed data, it first determines its channel number M and stores the unframed data in the corresponding memory space, and the data written each time is written in sequence. The system will poll N waiting rooms, and read out the 3 bytes of pre-fetched data stored earliest in the polled waiting room in the subsequent cycle, and release the 1 byte of memory space stored earliest.

[0009] S2: The data monitoring unit will monitor the pre-fetched data, and print the frame status information including the frame header, frame tail, frame validity and frame abnormality at all times, and provide the bit offset; the data monitoring unit will monitor the pre-fetched 3-byte data and print different frame status information labels. The data monitoring is to search for the number of consecutive "1"s in the pre-fetched 3-byte data content and judge the frame status. When more than 6 consecutive "1"s appear in the pre-fetched 3-byte data, it is judged as a frame abnormality state. When 6 consecutive "1"s appear in the 3-byte data, it is judged as a frame delimiter. When all the pre-fetched 3-byte data are judged to be frame delimiters, it is judged to be an idle state. When the pre-fetched 3-byte data is judged to be a frame delimiter, followed by a non-frame delimiter, it is judged to be a frame header state. When the pre-fetched 3-byte data is judged to be a non-frame delimiter, followed by a frame delimiter, it is judged to be a frame tail state. The state between the frame header and the frame tail is the frame valid state.

[0010] S3: The data extraction unit queries the bit offset table item and outputs the unprocessed HDLC frame data reassembled after the bit offset; the data extraction process of the data extraction unit is: 1. Establish an offset table item in the system to record the bit offsets of all N channels. 2. When the data monitoring unit determines that the frame header state appears in the pre-fetched data of the Mth channel, the bit offset is calculated according to the position of the frame delimiter (binary number 01111110) in the 3 bytes of the pre-fetched data and written into the offset table item of the corresponding channel M. 3. When the pre-fetched data of the Mth channel is in the valid frame state, the corresponding bit offset is read from the offset table item, and the pre-fetched data is bit-shifted to obtain valid unprocessed HDLC frame data. 4. Repeat the previous steps for other channels.

[0011] S4: The HDLC framing unit uses a pipeline model to concurrently remove zero-bit padding from unprocessed HDLC frames to obtain processed HDLC frame data; the HDLC framing unit's workflow is as follows: 1. Establish a framing information table entry in the system to record the data to be reassembled unrecon_data, the consecutive "1" count serial_one_cnt, and the bit validity indication bit_keep; 2. When the unit receives an unprocessed HDLC frame, it first reads out all framing signals from the framing signal table entry according to the channel number; 3. The unit uses a 9-stage pipeline to concurrently process data, pipelines 0 to 7 process data from bit 7 to bit 0 respectively, and pipeline 8 outputs the processed data; 4. 9 pipelines work simultaneously, and can process data from 8 channels at the same time, thereby improving the data processing bandwidth. Pipeline 0 to pipeline 7 only perform zero-filling processing on a single bit of data in each clock cycle, that is, pipeline 0 processes the data of bit 7, determines the number of consecutive "1s", updates and stores the current data to be reassembled, and when the bit valid indication is 8, it means that a complete byte has been reassembled, and the reassembled data is latched. Pipeline 1 to pipeline 7 are analogous in this way.

[0012] S5: The data distribution unit distributes the HDLC frames by channel according to the channel number and stores them in the cache, waiting for the subsequent module to call.

[0013] The beneficial effects of the present invention are:

[0014] The present invention is a multi-channel HDLC de-framing scheduling method. Compared with the prior art, the present invention is a concurrent pipeline parsing method that can use only one HDLC de-framing module to simultaneously process data parsing work of N channels, greatly reducing system resource consumption and improving the system's effective working data throughput. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a functional block diagram of the present invention;

[0016] Figure 2 is a functional block diagram of the concurrent pipeline processing of the present invention;

[0017] Figure 3 is a process flow chart of the method of the present invention;

[0018] Figure 4 It is a multiplexing schematic diagram of a specific embodiment of the present invention. DETAILED DESCRIPTION

[0019] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments. The illustrative embodiments and descriptions of the present invention are used to explain the present invention but are not intended to limit the present invention.

[0020] For simplicity, some technical features known to those skilled in the art are omitted in the following description. According to an embodiment of the present application, a multi-channel HDLC deframing and scheduling method is provided, which solves the problem of framing and deframing of multi-channel HDLC frames.

[0021] like Figure 1 and Figure 3 As shown, according to the present invention, the following steps are included:

[0022] S1, the data pre-fetching unit obtains the unframed data and the channel number information, and pre-fetches the unframed data according to the waiting hall model;

[0023] S2, the data monitoring unit will monitor the pre-fetched data, always print the frame status information including the frame header, frame tail, frame validity and frame abnormality, and provide the bit offset;

[0024] S3, the data extraction unit queries the bit offset table item and outputs the unprocessed HDLC frame data reassembled after the bit offset;

[0025] S4, the HDLC framing unit uses a pipeline model to concurrently remove zero-bit padding processing on the unprocessed HDLC frame to obtain processed HDLC frame data;

[0026] S5. The data distribution unit distributes the HDLC frames by channel according to the channel number and stores them in the cache, waiting for the subsequent module to call.

[0027] In the transmission of HDLC frames, the frame delimiter byte is the binary number 01111110, which indicates the start and end of an HDLC frame. When there are five consecutive "1"s in a data byte in an HDLC frame, a "0" bit will be inserted immediately after the bit "1". This method is called 0-bit padding. For HDLC deframing operations, when there are five consecutive "1"s in the data, the following "0" needs to be removed. This operation is called 0-bit padding. When there are six consecutive "1"s in the data, it indicates a frame delimiter. When there are more than six consecutive "1"s in the data, it indicates a transmission error.

[0028] like Figure 1 As shown, the specific method of step S1 includes the following sub-steps:

[0029] S1-1. The data pre-fetching unit divides the memory into corresponding N waiting halls according to the total N data channels, and the received data of the Mth channel will be temporarily stored in the memory of the corresponding Mth waiting hall.

[0030] S1-2, the data pre-fetch unit receives the unframed data and channel number transmitted by the previous module, and the unframed data and channel number are valid in the same clock cycle. The data pre-fetch unit first writes the unframed data byte sequence into the corresponding memory in the waiting hall model according to the channel number.

[0031] S1-3, the data pre-fetching unit polls the memory of N waiting room models, pre-fetches the earliest 3 bytes of data written in the memory each time, and releases the earliest 1 byte of memory space stored. The unframed data is written into the corresponding memory space in the order of data.

[0032] S1-4, the data pre-fetch unit outputs the pre-fetched 3 bytes of data and the channel number to the data monitoring unit at the same time.

[0033] like Figure 1 As shown, the specific method of step S2 includes the following sub-steps:

[0034] S2-1, the data monitoring unit will always monitor the pre-fetched 3 bytes of data content, and continuously determine the number of consecutive "1", and will label the data with different frame status. The frame status includes idle (IDLE), abnormal frame (ERR), frame start (SOP), frame end (EOP) and frame valid (DVAL).

[0035] S2-2: When more than 6 consecutive "1"s appear in the pre-fetched 3-byte data content, it is judged to be in ERR state.

[0036] S2-3, when six consecutive "1"s appear in the pre-fetched 3-byte data content, it is determined to be a frame delimiter. When all the 3-byte data content is determined to be a frame delimiter, it is determined to be an IDLE state.

[0037] S2-4: If the pre-fetched 3-byte data content is judged to be a frame delimiter followed by a non-frame delimiter, it is judged to be in SOP state.

[0038] S2-5. If the pre-fetched 3-byte data content is judged to be a non-frame delimiter followed by a frame delimiter, it is judged to be in the EOP state.

[0039] S2-6, the state between the SOP frame head state and the EOP frame tail state is the DVAL state. The data monitoring unit can output valid pre-fetch data only in the SOP, DVAL and EOP states.

[0040] S2-7. When the data monitoring unit determines that the pre-fetched data of the Mth channel is in the frame header state, the bit offset of the current channel data can be calculated according to the position of the frame delimiter in the first 2 bytes.

[0041] S2-8, the data monitoring unit simultaneously outputs the pre-fetched data, channel number, bit offset and frame status information to the subsequent data extraction unit.

[0042] like Figure 1 As shown, the specific method of step S3 includes the following sub-steps:

[0043] S3-1. The data extraction unit creates a table entry of a bit offset according to a total of N data channels. The table entry records the offset values ​​of the N channels, ie, the bit offsets.

[0044] S3-2, when receiving the SOP frame header status, the data extraction unit writes and updates the offset value into the table entry of the current channel M. After the first 2 bytes of pre-fetched data are bit-shifted, 1 byte of reorganized unframed data is obtained and transmitted to the subsequent unit.

[0045] S3-3. When receiving the DVAL frame valid state or the EOP frame tail state, read the bit offset of the current channel from the table entry, perform bit offset on the first 2 bytes of pre-fetched data, and obtain 1 byte of reorganized unframed data to transmit to the subsequent unit.

[0046] S3-4. The data extraction unit transmits the frame status information, channel number and reassembled data to the subsequent HDLC framing unit.

[0047] like Figure 1 As shown, the specific method of step S4 includes the following sub-steps:

[0048] S4-1. The HDLC framing unit establishes a framing information table entry according to a total of N data channels. The table entry records the framing information of the N channels. The framing information includes the data to be reassembled unrecon_data, the consecutive "1" count serial_one_cnt, and the bit valid value bit_keep.

[0049] S4-2, when the HDLC framing unit receives the SOP frame header status, it will initialize the data to be reassembled, the consecutive "1" count and the bit valid indication. When the DVAL frame valid status is received, the framing information will be read from the table entry of the corresponding channel. The framing unit performs concurrent pipeline zero-bit filling processing on the unframed data. At most 9 pipelines work simultaneously in each clock cycle, and each pipeline can process single-bit data.

[0050] S4-3: Single-bit zero-filling processing can be divided into two cases: the current bit is "1" or "0". The specific processing flow is as follows:

[0051] S4-3-1, if the currently processed data bit is "1": the "1" count value is increased by 1. If the valid bit of the data to be reassembled is not 8, "1" is shifted to the lowest bit of the data to be reassembled, and the bit effective value is increased by 1; if the valid bit of the data to be reassembled is 8, the byte is latched and waited for output, and the data to be reassembled and the bit effective value are set to zero.

[0052] S4-3-2, if the data bit currently being processed is "0": if the count value of consecutive "1" is not 5, it means that the bit "0" is normal data and does not need to be processed by removing the 0 bit. If the valid bit of the data to be reassembled is not 8, "0" is added to the lowest bit of the data to be reassembled, and the bit value is effectively increased by 1; if the valid bit of the data to be reassembled is 8, the byte is latched and waits for output, and the data to be reassembled and the bit effective value are set to zero. If the count value of consecutive "1" is 5, it means that the bit "0" is a filler number and needs to be processed by removing the 0 bit. At this time, the data to be reassembled remains unchanged, and the bit effective value also remains unchanged. Finally, the count value of consecutive "1" is cleared to zero.

[0053] like Figure 2 As shown, the specific method of the zero-bit filling operation of the N-channel concurrent pipeline in step S4 is as follows:

[0054] S4-4, the single-bit zero-removal bit filling process described in the above step S4-3 is U(i,j), where i represents the valid data of the i-th channel, and j represents the current j-th pipeline. The data processing operation of pipelines L0 to L7 is a single single-bit zero-removal bit filling process, that is, L0 processes the bit 7 data of the unframed data, L1 processes the bit 6 data of the unframed data, and so on, L7 processes the bit 0 data of the unframed data. Pipeline L8 is a settlement process. If latched valid data is generated in L0~L7, it can be output to the subsequent unit in L8, and the framing information is updated to the framing information table entry. At time T, 9 pipelines can work simultaneously, L0~L7 process the data of 8 channels simultaneously, and L8 performs settlement processing, that is, concurrent pipeline HDLC framing processing is realized.

[0055] S4-5. When outputting valid data, it is also necessary to judge the integrity of the data frame. If the valid value of the bits in the HDLC frame parsed and output in the EOP frame tail state is not 8, it means that the data frame is incomplete. At this time, it is necessary to output frame error information to the subsequent unit.

[0056] like Figure 1 As shown, the specific method of step S5 includes the following sub-steps:

[0057] S5-1, the data distribution unit allocates N buffer spaces according to the channel number, for buffering the HDLC framed data of the N channels;

[0058] S5-2, when receiving the frame error information, the data distribution unit will discard the entire HDLC frame;

[0059] S5-3. The data distribution unit distributes the framed data of the HDLC to N channels according to the channel number, and stores the data in the buffer of the corresponding channel for the subsequent data forwarding module to call.

[0060] A specific embodiment is used below to describe the working process of the present invention in detail:

[0061] This embodiment can realize the HDLC deframing work after demultiplexing the STM-1 interface in the communication network to 63 E1 interfaces. The application scenario is that some users use low-end routers to access the transmission network through the E1 interface. The bandwidth of multiple users is aggregated to an STM-1 interface through the transmission network and then connected to a high-end router. Figure 4 As shown in the figure, the STM-1 interface is an aggregation interface that multiplexes 63 E1s. The C-12 container structure unit contains a single-channel E1 interface and transmits HDLC frame data in the E1. The remaining containers (Cn), virtual containers (VC-n), tributary units (TU-n), tributary unit groups (TUG-n), management units (AU-n) and management unit groups (AUG-n) are all structural units of the multiplexing process. Further, Figure 4 As shown in the figure, 3 TU-12s are multiplexed into 1 TUG-2, 7 TUG-2s are multiplexed into 1 TUG-3, and 3 TUG-3s are multiplexed into 1 VC-4, that is, 1 STM-1 is multiplexed from 3×7×3=63 E1s.

[0062] In this embodiment, the XC7K325T-FPGA device is used to implement multi-channel HDLC frame parsing processing. The system of this embodiment communicates with the router of the STM-1 interface, the router sends data, and the system receives data. First, the front-stage demultiplexing module realizes the processing of demultiplexing the STM-1 interface into 63 E1 interface data, and outputs the unframed data and the corresponding channel number. The implementation of this module is not within the scope of the present invention. When the FPGA is initialized, 63 waiting room model memories, 63 bit offset table entries and 63 framing information table entries are established respectively. After receiving the unframed E1 data, the FPGA first stores the data in the memory of the waiting room model according to the channel numbers 0 to 62, and then pre-takes the first 3 bytes of data content of each channel in turn through uniform scheduling. FPGA then continuously monitors the pre-fetched 3-byte data content, and marks the frame header, frame tail, frame validity and frame abnormality information on the data according to the determined frame delimiter (8'b01111110), and determines the bit offset of 0 to 7. FPGA discards the data with frame abnormality, and reassembles the frame header, frame tail and frame valid data according to the result of querying the corresponding channel bit offset table item and transmits them to the next stage. FPGA uses the operation of a concurrent 9-stage pipeline and queries the corresponding framing information table items of 63 channels, and performs HDLC framing processing on the reassembled data of 63 channels. FPGA discards the data with frame errors, and stores the correctly parsed data in 63 system memories respectively, waiting for the reading of the 63 user interfaces of the next stage. Finally, the received data of the 63 user interfaces is compared with the sent data of the router. The data is completely correct, and there is no error frame or frame loss.

[0063] The technical solution of the present invention is not limited to the above-mentioned specific embodiments. All technical variations made according to the technical solution of the present invention fall within the protection scope of the present invention.

Claims

1. A multi-channel HDLC de-framing scheduling method, It is characterized in that The following steps are involved: S1: The data pre-fetching unit obtains the unframed data and the channel number information, and pre-fetches the unframed data according to the waiting hall model; S1-1: The data pre-fetching unit divides the memory into corresponding N waiting halls according to a total of N data channels, and the received data of the Mth channel will be temporarily stored in the memory of the corresponding Mth waiting hall; S1-2: The data pre-fetch unit receives the unframed data and channel number transmitted by the previous module. The unframed data and channel number are valid in the same clock cycle. The data pre-fetch unit first writes the unframed data byte sequence into the corresponding memory in the waiting hall model according to the channel number; S1-3: The data pre-fetching unit polls the memory of N waiting room models, pre-fetches the earliest 3 bytes of data written in the memory each time, and releases the earliest 1 byte of memory space stored, and the unframed data is written into the corresponding memory space in the order of data; S1-4: The data pre-fetch unit outputs the pre-fetched 3 bytes of data and the channel number to the data monitoring unit at the same time; S2: The data monitoring unit monitors the pre-fetched data, and prints the frame status information including the frame header, frame tail, frame validity, and frame abnormality at all times, and provides the bit offset; S3: The data extraction unit queries the bit offset table item and outputs the unprocessed HDLC frame data reassembled after the bit offset; S4: The HDLC framing unit uses a pipeline model to concurrently remove zero-bit padding from the unprocessed HDLC frame to obtain processed HDLC frame data; S4-1: The HDLC framing unit will establish a framing information table entry according to a total of N data channels. The table entry records the framing information of the N channels. The framing information includes the data to be reassembled unrecon_data, the consecutive "1" count serial_one_cnt, and the bit valid value bit_keep; S4-2: When the HDLC framing unit receives the SOP frame header status, it will initialize the data to be reassembled, the consecutive "1" count and the bit valid indication; when the DVAL frame valid status is received, the framing information will be read from the table entry of the corresponding channel; the framing unit performs concurrent pipeline zero-bit filling processing on the unframed data, and up to 9 pipelines work simultaneously in each clock cycle, and each pipeline can process single-bit data; S4-3: The single-bit zero-filling process can be processed according to the current bit being "1" or "0". S4-4: The single-bit zero-removal bit filling process described in the aforementioned step S4-3 is U(i,j), where i represents the valid data of the i-th channel, and j represents the current j-th pipeline; the data processing operation of pipelines L0 to L7 is a single single-bit zero-removal bit filling process, that is, L0 processes the bit 7 data of the unframed data, L1 processes the bit 6 data of the unframed data, and so on, L7 processes the bit 0 data of the unframed data; pipeline L8 is a settlement process, if latched valid data is generated in L0~L7, it is output to the subsequent unit in L8, and the framing information is updated to the framing information table item; at time T, 9 pipelines can work simultaneously, L0~L7 process the data of 8 channels simultaneously, and L8 performs settlement processing, that is, concurrent pipeline HDLC framing processing is realized; S4-5: When outputting valid data, it is necessary to judge the integrity of the data frame. If the valid value of the bit in the HDLC frame parsed and output in the EOP frame tail state is not 8, it means that the data frame is incomplete. At this time, it is necessary to output frame error information to the subsequent unit; S5: The data distribution unit distributes the HDLC frames by channel according to the channel number and stores them in the cache, waiting for the subsequent module to call.

2. The method for multi-channel HDLC de-framing scheduling according to claim 1, It is characterized in that The step S2 is specifically as follows: S2-1: The data monitoring unit will always monitor the pre-fetched 3-byte data content, and continuously determine the number of consecutive "1"s, and will label the data with different frame statuses; the frame status includes idle (IDLE), abnormal frame (ERR), frame start (SOP), frame end (EOP) and frame valid (DVAL); S2-2: When more than 6 consecutive "1"s appear in the pre-fetched 3-byte data content, it is judged as ERR state; S2-3: When six consecutive "1s" appear in the pre-fetched 3-byte data content, it is judged as a frame delimiter; when all the 3-byte data content is judged to be a frame delimiter, it is judged to be an IDLE state; S2-4: If the pre-fetched 3-byte data content is judged to be a frame delimiter, followed by a non-frame delimiter, it is judged to be in SOP state; S2-5: If the pre-fetched 3-byte data content is judged to be a non-frame delimiter followed by a frame delimiter, it is judged to be in the EOP state; S2-6: The state between the SOP frame header state and the EOP frame tail state is the DVAL state; the data monitoring unit can output valid pre-fetch data only in the SOP, DVAL and EOP states; S2-7: When the data monitoring unit determines that the pre-fetched data of the Mth channel is in the frame header state, the bit offset of the current channel data can be calculated according to the position of the frame delimiter in the first 2 bytes; S2-8: The data monitoring unit simultaneously outputs the pre-fetched data, channel number, bit offset and frame status information to the subsequent data extraction unit.

3. The method for multi-channel HDLC de-framing scheduling according to claim 2, It is characterized in that The step S3 is specifically as follows: S3-1: The data extraction unit creates a table entry of a bit offset according to a total of N data channels, and the table entry records the offset values ​​of the N channels, i.e., the bit offsets; S3-2: When the data extraction unit receives the SOP frame header status, it writes and updates the offset value into the table entry of the current channel M, and after bit shifting the first 2 bytes of pre-fetched data, obtains 1 byte of reorganized unframed data and transmits it to the subsequent unit; S3-3: When receiving the DVAL frame valid state or the EOP frame tail state, the bit offset of the current channel is read from the table entry, and the first 2 bytes of pre-fetched data are bit-shifted to obtain 1 byte of reassembled unframed data and transmit it to the subsequent unit; S3-4: The data extraction unit transmits the frame status information, channel number and reassembled data to the subsequent HDLC framing unit.

4. The method for multi-channel HDLC de-framing scheduling according to claim 3, It is characterized in that The specific processing flow of step S4-3 is as follows: S4-3-1: If the currently processed data bit is "1": add 1 to the "1" count value; if the valid bit of the data to be reassembled is not 8, shift "1" to the lowest bit of the data to be reassembled, and add 1 to the bit effective value; if the valid bit of the data to be reassembled is 8, latch the byte and wait for output, and set the data to be reassembled and the bit effective value to zero; S4-3-2: If the data bit currently being processed is "0": if the count value of consecutive "1s" is not 5, it means that the bit "0" is normal data and does not need to be processed by removing the 0 bit; if the valid bit of the data to be reassembled is not 8, then "0" is added to the lowest bit of the data to be reassembled, and the bit value is effectively increased by 1; if the valid bit of the data to be reassembled is 8, the byte is latched and waits for output, and the data to be reassembled and the bit effective value are set to zero; if the count value of consecutive "1s" is 5, it means that the bit "0" is a filler number and needs to be processed by removing the 0 bit. At this time, the data to be reassembled remains unchanged, the bit effective value also remains unchanged, and finally the count value of consecutive "1s" is cleared.

5. The method for multi-channel HDLC de-framing scheduling according to claim 4, It is characterized in that The specific method of step S5 includes the following sub-steps: S5-1: The data distribution unit allocates N buffer spaces according to the channel number to buffer the HDLC framed data of the N channels; S5-2: When the data distribution unit receives the frame error information, it will discard the entire HDLC frame; S5-3: The data distribution unit distributes the framed data of the HDLC to N channels according to the channel number, and stores the data in the buffer of the corresponding channel for the subsequent data forwarding module to call.

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