A multi-channel analog signal parallel acquisition system

Abstract

The present invention discloses a multi-channel analog signal parallel acquisition system, which relates to the field of signal acquisition technology, and includes an ADC signal acquisition module, an isolation module, an interface processing module and a processor; the isolation module is used to digitally isolate the field side and the logic side of the acquisition signal; the interface processing module includes, the processor controls each ADC channel by controlling the decoding circuit to pull down the chip select signal, and controls the gating circuit to determine the opening and closing of the corresponding gating port of the ADC channel to transmit data; when the channel is opened, the clock signal and the data input signal are collectively connected, and the data output signal is transmitted through the gating port, that is, each channel shares a data line, and transmits data between multiple ADCs through a group of SPI interfaces. The present invention uses a group of SPI interfaces to realize the parallel acquisition of multi-channel analog signals, and an isolation design is performed for each channel, thereby enhancing the anti-interference ability of the entire system.

Description

Technical Field

[0001] The invention relates to the technical field of signal acquisition, in particular to a multi-channel analog signal parallel acquisition system. Background Art

[0002] As an important part of the DCS system, the I / O data acquisition station receives signals sent by field equipment, performs some necessary conversion and processing on them, and then exchanges data with the field control station through the I / O communication network. Among them, the acquisition of analog signals is particularly important.

[0003] For the measurement of I / O analog quantities, the national standard GB / T 36293-2018 "Technical Conditions for Distributed Control Systems of Thermal Power Plants" has the following requirements: The acquisition speed of I / O modules is specified: the acquisition speed of general analog signals is 4 times / S, and the acquisition speed of analog signals for protection and rapid processing is 8 times / S. Channel isolation requirements: input channels, output channels and their working power supplies should be isolated from each other. Isolation measures are taken between signals and internal circuits, such as photoelectric isolation or other isolation. Accuracy requirements: analog input signal (high level) +-0.1%, analog input signal (low level) +-0.2%, etc.

[0004] There are two main types of existing multi-channel analog acquisition technologies:

[0005] 1. Multiple channels share one ADC chip. The analog signal is converted to digital through the analog switching switch. The conversion results are transmitted to the core processor in sequence through the same set of SPI interfaces. This method has two disadvantages. First, multiple channels share one ADC chip. Each channel must wait for the previous channel to complete the conversion before it can start the conversion. The time required to complete the conversion of all channels is long. Second, sharing one ADC means that the channels are connected to each other, and there is a risk of mutual interference between channel signals.

[0006] Second, each channel uses an ADC chip for analog-to-digital conversion. After the conversion is successful, the data is transmitted to the core processor through their respective SPI interfaces. This method can achieve simultaneous acquisition of multiple channels, but it has high requirements on processor resources, such as the number of SPI interfaces and PIO interfaces required. However, there are not many processors on the market that can provide more interfaces. And when the number of channels is large enough, there are almost no processors that can meet the requirements.

[0007] In view of the defects of the prior art, the present invention provides a multi-channel analog signal parallel acquisition system, which adopts a high-performance domestic ADC chip and is equipped with a domestic FPGA hardware platform. It is specifically composed of four modules: a processor, an interface processing module, an isolation module, and an ADC signal acquisition module. Its function is to perform analog-to-digital conversion on the analog signal of the DCS field side, and pass the converted value to the core processor for logical operation. The system can use a set of SPI interfaces to realize the parallel acquisition of multi-channel analog signals, and can still ensure high-speed acquisition when the processor interface resources are less. The whole system has the advantages of fast acquisition speed, high precision, good reliability, strong anti-interference ability, etc., and can meet the requirements of national standards. Summary of the invention

[0008] In view of the above-mentioned problems, the present invention is proposed.

[0009] Therefore, the problem to be solved by the present invention is: how to collect analog signal data more efficiently under the condition of limited processor resources, and provide a feasible way for the domestic analog signal acquisition system.

[0010] In order to solve the above technical problems, the present invention provides the following technical solutions: a multi-channel analog signal parallel acquisition system, which includes an ADC signal acquisition module, an isolation module, an interface processing module and a processor; the ADC signal acquisition module is used to acquire field signals; the isolation module is used to digitally isolate the field side and the logic side of the acquired signal, and isolate the power supply, and isolate a power supply for each channel; the interface processing module includes a decoding circuit and a multi-channel analog switch gating circuit, the processor controls each ADC channel by controlling the decoding circuit to pull down the chip select signal, and controls the gating circuit to determine the opening and closing of the corresponding gating port of the ADC channel to transmit data; when the ADC channel is turned on, data is transmitted between the processor through the SPI interface, the clock signal and the data input signal are collectively connected, and the data output signal is transmitted through the gating port, that is, each channel uses a common data line to transmit data between multiple ADCs through a group of SPI interfaces; the processor is used to control the acquisition of field analog signals, and receive the acquired signals and perform logical operations.

[0011] As a preferred solution of the multi-channel analog signal parallel acquisition system described in the present invention, the ADC signal acquisition module adopts a single-channel single ADC acquisition method to collect field signals and output a group of SPI interface signals to the SPI interface.

[0012] As a preferred solution of the multi-channel analog signal parallel acquisition system described in the present invention, the SPI interface signal includes a chip select signal, a clock signal, a data input signal and a data output signal.

[0013] As a preferred solution of the multi-channel analog signal parallel acquisition system described in the present invention, the acquisition of field signals includes equipping each channel with an ADC chip, and the ADC chip of each channel performs analog-to-digital conversion on the field-side acquisition signal, and transmits the converted value to the core processor through the SPI interface for logical operation.

[0014] As a preferred solution of the multi-channel analog signal parallel acquisition system described in the present invention, each channel sends ADC continuous conversion commands in sequence, without waiting for the channel conversion to be completed, and the ADC of each channel is converted simultaneously, and the value is stored in the data register after the conversion is completed.

[0015] As a preferred solution of the multi-channel analog signal parallel acquisition system described in the present invention, the processor controls each ADC channel by controlling the decoding circuit to pull down the chip select signal, and controls the selection circuit to determine the opening and closing of the selection port corresponding to the ADC channel to transmit data, including that the processor sends a number of control chip select signals, the output of each control chip select signal is 0 or 1, the decoding circuit and the selection circuit receive all the control chip select signals, obtain a sorted sequence composed of 0 and 1, and find the corresponding ADC channel and selection port based on the control law for logical control.

[0016] As a preferred solution of the multi-channel analog signal parallel acquisition system described in the present invention, the control law includes the control law of the decoding circuit and the control law of the multi-channel analog switch gating circuit; the control law of the decoding circuit is that one sorting sequence corresponds to one ADC channel; the control law of the multi-channel analog switch gating circuit is that one sorting sequence corresponds to one gating port.

[0017] The beneficial effects of the present invention are as follows: for the traditional method of multiple channels sharing one ADC chip, the present invention sets an ADC chip for each channel to increase the acquisition speed. For the traditional method of each channel using an SPI interface to transmit data to the core processor, this method has high requirements on processor resources. The multi-channel analog signal parallel acquisition system provided by the present invention can overcome this problem, and a group of SPI interfaces are used to realize the parallel acquisition of multi-channel analog signals, and high-speed acquisition can still be guaranteed when the processor interface resources are less. In addition, each channel of the system has a power supply and signal digital isolation design, and the field side acquisition signal is digitally isolated from the logic side. The analog signals of each channel do not affect each other. The design of this module enhances the anti-interference ability of the entire system, and solves the problem that the output signal of the traditional method cannot be connected after isolation. The entire system has the advantages of fast acquisition speed, high precision, good reliability, strong anti-interference ability, etc., and can meet the requirements of national standards. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0019] Figure 1 This is a diagram of the system architecture 1 of a multi-channel analog signal parallel acquisition system in Example 1.

[0020] Figure 2 FIG2 is a system architecture diagram of a multi-channel analog signal parallel acquisition system in Example 1.

[0021] Figure 3 This is a logic control diagram of a decoding circuit of a multi-channel analog signal parallel acquisition system in Example 1.

[0022] Figure 4 This is a logic control diagram of a multi-channel analog switch gating circuit of a multi-channel analog signal parallel acquisition system in Example 1.

[0023] Figure 5 8-channel ADC continuous conversion flow chart of a multi-channel analog signal parallel acquisition system in Example 1 DETAILED DESCRIPTION

[0024] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings.

[0025] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0026] Example 1

[0027] Reference Figure 1-Figure 5 , which is the first embodiment of the present invention, provides a multi-channel analog signal parallel acquisition system including four major modules: ADC signal acquisition module, isolation module, interface processing module and processor.

[0028] The specific system architecture is as follows Figure 1 As shown (this example takes 8 channels as an example):

[0029] ADC signal acquisition module: To ensure the acquisition speed, each channel is equipped with a 16-bit resolution ADC chip. The ADC chip of each channel converts the signal collected on the field side into analog-to-digital, and transmits the converted value to the core processor FPGA through the SPI communication interface for logical operation. The ADC model of this example is Hangzhou Ruimeng MS5192T.

[0030] Isolation module: Each channel of this system uses an isolation chip to digitally isolate the field side acquisition signal from the logic side, and isolates 8 power supplies and 8 grounds. The analog signal acquisition of each channel does not affect each other. The design of this module enhances the anti-interference ability of the entire system and meets the isolation requirements of 5.6.1.7 of the national standard "GB / T 36293-2018 Technical Conditions for Distributed Control Systems of Thermal Power Plants". This example uses the digital isolation chip of Nanochip, model: NSIP8841.

[0031] like Figure 2 As shown. Interface processing module: Through the decoding circuit and the multi-channel analog switch selection circuit, a group of SPI interfaces are used to realize the parallel acquisition of multi-channel analog signals. This processing module is the core content of the present invention. The system adopts a single-channel single ADC acquisition method, so each channel has a group of SPI interface signals, namely, chip select signal CH_ENA_L, clock signal SCLK_L, data input signal DIN_L, and data output signal DOUT_L. Command control and data transmission between the processor FPGA and each ADC are completed through this interface. Taking 8 channels as an example, the chip select signal CH_ENA_L has 8 CH1_ENA_L, CH2_ENA_L..........CH8_ENA_L. The processor controls each ADC by pulling down the chip select signal. Under normal circumstances, the clock signal SCLK_L, the data input signal DIN_L, and the data output signal DOUT_L can be collectively connected, that is, 8 channels share a data line to realize a group of SPI interfaces for data transmission between multiple ADCs.

[0032] Processor: realizes the functions of field analog signal acquisition and control. This example uses the domestic Gaoyun FPGA as the core processor, model: GW2A-LV18PG484C8 / I7, which has an embedded ARM soft core.

[0033] The core design idea of ​​the present invention is to design an isolation module in order to enhance the anti-interference ability. The traditional method does not design a separation module not because it is not thought of but because it cannot be done. In the parallel output, the data output signal DOUT_L of each channel cannot be connected together after isolation. This is because the isolated DOUT_L signal is pulled up to a high level by default. If it is connected together, it will affect the output of data between channels. The present invention can also use parallel mode to transmit data after isolation, which solves the problem that the DOUT_L signal cannot be connected collectively. Moreover, traditional multi-channels share a power supply. If you also want to perform power isolation, you need to design multiple dcdc power conversions. The isolation module of the present invention can not only perform digital isolation, but also integrate a power DC converter, including power isolation. The specific solution is as follows:

[0034] This example uses an 8-channel analog switch to simulate a multi-channel analog switch gating circuit, specifically through which the DOUT signals (DOUT_L1, DOUT_L2, ..... DOUT_L8) of 8 ADCs are selected. Model: Anshi XS3A4051. After the algorithm of the interface processing module, the data input signal DIN_L and the data output signal DOUT_L that are actually connected to the processor have only one data line, which perfectly solves the problem that the data lines cannot be connected together due to the isolation design. This example uses a 38 decoder as a decoding circuit to control the chip select signals (CH1_ENA_L, CH2_ENA_L.......... CH8_ENA_L) of 8 ADCs. Model: Anshi 74LVC138A, which can convert one of the three input bits (A0, A1, A2) into one of the eight output bits (Y0 / Y1 / Y2 / Y3 / Y4 / Y5 / Y6 / Y7), which can save 5 PIO interfaces.

[0035] The connection relationship of the system is as follows Figure 1 and Figure 2As shown: Pin 1: SCLK of each channel ADC is connected to processor U19 pin 7: SCLK_L after being connected through isolation chips of each channel. Pin 2: DIN of each channel ADC is connected to processor U19 pin 8: DIN_L after being connected through isolation chips of each channel. Processor U19 sends out three control signals: pin 1: CH_ENA_LA / pin 2: CH_ENA_LB / pin 3: CH_ENA_LC. These three signals are connected to control pins 1 / 2 / 3 of 38 decoder U17 and control pins 11 / 10 / 9 of 8-channel analog switch U18. Pins 15 / 14 / 13 / 12 / 11 / 10 / 9 / 7 of U17 are connected to pin 3: CS of each ADC through isolation chips of each channel. Pins 13 / 14 / 15 / 12 / 1 / 5 / 2 / 4 of U18 are connected to pin 4: DOUT of each ADC through isolation chips of each channel, and pin 3 of U18 is connected to pin 9: DOUT_L of processor U19.

[0036] The logical control of the system is as follows:

[0037] (1) The processor sends three control chip select signals: CH_ENA_LA, CH_ENA_LB and CH_ENA_LC. Based on the control law (the control law of the decoding circuit is as follows Figure 3 As shown, 0A, 1A, 2A are input control pins, 0Y / 1Y....7Y are output pins, H is a high level, L is a low level, and X represents any level, either a high level or a low level; and Figure 3 The first three lines in the figure are the preparatory stage, and the input does not affect the output. The control law of the multi-channel analog switch selection circuit is as follows: Figure 4 As shown, E, S3, S2, S1 are input control pins, Y0 / Y1...Y7 are switch channel pins, Z is the total output pin, H is high level, L is low level, X represents any level, one of high level or low level), select 1--8 channels in turn, the interface control is analyzed in 8 cases as follows (channels 3-7 are omitted):

[0038] When CH_ENA_LA=0 / CH_ENA_LB=0 / CH_ENA_LC=0, channel 1 chip select signal CH1_ENA_L=0 (low level selection), the other chip select signals are all high level, and the data output signal DOUT_L=DOUT_L1, that is, the channel 1 signal is collected normally.

[0039] When CH_ENA_LA=1 / CH_ENA_LB=0 / CH_ENA_LC=0, the 2-channel chip select signal CH2_ENA_L=0 (low level selection), the other chip select signals are all high level, and the data output signal DOUT_L=DOUT_L2, that is, the channel 2 signal is collected normally.

[0040] When CH_ENA_LA=1 / CH_ENA_LB=1 / CH_ENA_LC=1, the 8-channel chip select signal CH8_ENA_L=0 (low level selection), the other chip select signals are all high level, and the data output signal DOUT_L=DOUT_L8, that is, the channel 8 signal is collected normally.

[0041] like Figure 5 Each channel sends the ADC continuous conversion command in turn (no need to wait for the channel conversion to complete, the total time does not exceed 1ms)

[0042] At this time, the ADCs of the eight channels are converted simultaneously (each ADC conversion time is 60ms), and the values ​​are stored in the data registers after the conversion is completed.

[0043] The value in the data register is transmitted to the main control FPGA through the DOUT_L data line for logic operation (the principle of transmission is that the value of the channel whose conversion is completed is transmitted, and there is no need for channels to wait for each other).

[0044] The algorithm realizes the simultaneous control and conversion of 8 ADCs by one group of SPI interfaces through interface control. There is no need for channels to wait for each other. The conversion of all 8 channels can be completed in no more than 65ms, which far exceeds the national standard "GB / T 36293-2018 Technical Conditions for Distributed Control Systems of Thermal Power Plants" 5.6.1.3's requirement of 8 times / S for high-speed analog signals of I / O modules, thus realizing high-speed signal acquisition.

[0045] Example 2

[0046] The second embodiment of the present invention is different from the first embodiment in that: a multi-channel analog signal parallel acquisition system also includes: in order to verify and illustrate the technical effects adopted in this method, this embodiment adopts a traditional technical solution and the method of the present invention for comparative testing, and compares the test results by means of scientific demonstration to verify the real effect of this method.

[0047] Traditional method 1: Using multiple channels to share one ADC chip, the analog signal is converted to digital through the analog switching switch patrolling the ADC chip, and the conversion results are transmitted to the core processor in sequence through the same set of SPI interfaces.

[0048] Traditional method 2: Each channel uses an ADC chip for analog-to-digital conversion. After the conversion is successful, the data is transmitted to the core processor through their respective SPI interfaces.

[0049] The system of the present invention is compared with traditional method 1 and traditional method 2 through simulation experiments, and the experimental data obtained are shown in Table 1:

[0050] Table 1: Experimental comparison table

[0051]

[0052] It can be seen that the sampling rate advantage is that the system of the present invention achieves a sampling rate of 62ms / 8 channels, which can still ensure almost the same speed as 61ms / 8 channels of traditional method 2 under the condition of limited processor resources, and is much higher than 650ms / 8 channels of traditional method 1, showing a faster data acquisition speed. This means that in the same time, the system of the present invention can process more data, improving the efficiency of data processing and the response speed of the system.

[0053] Resource utilization: Compared with the traditional method 2 in which each channel requires a set of separate SPI interfaces, the present invention utilizes the FPGA platform and high-performance domestic ADC chips to achieve resource integration and optimized use, significantly reducing the occupancy of processor resources and system costs.

[0054] Anti-interference ability: The system of the present invention has strong anti-interference ability, which is achieved through the isolation module. The isolation chip selected by this system can not only digitally isolate the collected signals on the field side from the logic side, but also isolate 8 power supplies and 8 grounds. In the process of collecting analog signals, the isolation module can effectively isolate external interference, ensure the purity and accuracy of the signal, and the channels do not interfere with each other. Compared with traditional method 1, this has a significant improvement in anti-interference ability. Compared with traditional method 2, although it also has strong anti-interference ability, the isolation chip selected can only digitally isolate the signal, and each channel still shares a power supply. Therefore, the present invention performs best in terms of the main EMC electromagnetic compatibility indicators, and the present invention has better performance in resource utilization.

[0055] System integration and scalability: Using the FPGA hardware platform, the system of the present invention provides a high degree of programmability and flexibility, allowing the system configuration to be adjusted and optimized according to actual needs to cope with different application scenarios. This highly integrated design not only optimizes the use of hardware resources, but also simplifies the system maintenance and upgrade process.

[0056] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A multi-channel analog signal parallel acquisition system, characterized in that: It includes an ADC signal acquisition module, an isolation module, an interface processing module and a processor; The ADC signal acquisition module is used to collect field signals; The isolation module is used to digitally isolate the field side of the collected signal from the logic side, and to isolate the power supply, isolating a power supply for each channel; The interface processing module includes a decoding circuit and a multi-channel analog switch gating circuit. The processor controls each ADC channel by controlling the decoding circuit to pull down the chip select signal, and controls the multi-channel analog switch gating circuit to determine the opening and closing of the corresponding gating port of the ADC channel to transmit data; when the ADC channel is turned on, data is transmitted between the processor through the SPI interface, the clock signal and the data input signal are collectively connected, and the data output signal is transmitted through the gating port, that is, each channel shares a data line, and data is transmitted to multiple ADCs through a group of SPI interfaces; An 8-channel analog switch is used to simulate a multi-channel analog switch gating circuit. Specifically, the DOUT signals of 8 ADCs are selected. After the algorithm of the interface processing module, the data input signal DIN_L and the data output signal DOUT_L connected to the processor have only one data line. The processor is used to control the collection of on-site analog signals, and receive the collected signals and perform logical operations; The processor controls each ADC channel by controlling the decoding circuit to pull down the chip select signal, and controls the multi-channel analog switch gating circuit to determine the opening and closing of the gating port corresponding to the ADC channel to transmit data, including: the processor sends a plurality of control chip select signals, the output of each control chip select signal is 0 or 1, the decoding circuit and the multi-channel analog switch gating circuit receive all the control chip select signals, obtain a sequence of 0s and 1s, and find the corresponding ADC channel and gating port based on the control law for logic control; The control law includes the control law of the decoding circuit and the control law of the multi-channel analog switch gating circuit; The control rule of the decoding circuit is that one sorting sequence corresponds to one ADC channel; The control rule of the multi-channel analog switch gating circuit is that one sorting sequence corresponds to one gating port.

2. A multi-channel analog signal parallel acquisition system as claimed in claim 1, characterized in that: The ADC signal acquisition module adopts a single-channel single-ADC acquisition mode, and each channel has a group of SPI interface signals.

3. A multi-channel analog signal parallel acquisition system as claimed in claim 2, characterized in that: The SPI interface signal includes a chip selection signal, a clock signal, a data input signal and a data output signal.

4. A multi-channel analog signal parallel acquisition system as claimed in claim 3, characterized in that: The collecting of the field signal includes equipping each channel with an ADC chip, the ADC chip of each channel performs analog-to-digital conversion on the field side collected signal, and transmits the converted value to the processor through the SPI interface for logic operation.

5. A multi-channel analog signal parallel acquisition system as claimed in claim 4, characterized in that: Each channel sends the ADC continuous conversion command in turn, without waiting for the channel conversion to be completed, and the ADC of each channel is converted at the same time, and the value is stored in the data register after the conversion is completed.

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