Aging test machine drive circuit and method

Abstract

This invention discloses a driving circuit and method for an aging tester, relating to the field of aging test technology. The circuit includes a driving board, an aging test board, and a power supply board. The driving board includes a master control module, a first slave module, a driving circuit, and a comparator circuit. The master control module is connected to a host computer, the first slave module is connected to the master control module, the driving circuit is connected to the first slave module and the aging test board, the comparator circuit is connected to the aging test board and the first slave module, and the power supply board is connected to the master control module. According to the aging tester driving circuit of this embodiment, the output pins of the driving circuit can function as ordinary output pins to drive multiple loads, or as high-speed clock output pins, thereby increasing the number of clock pins on the entire board and increasing the number of chips that can be tested simultaneously, thus improving the testing efficiency of the aging tester without increasing cost.

Description

Technical Field

[0001] This invention relates to the field of aging testing technology, and in particular to an aging testing machine drive circuit and method. Background Technology

[0002] Aging test chambers are primarily used to screen out defective chips through prolonged aging tests, thereby improving the quality of chip products. During aging tests, a test chamber driver circuit typically drives the machine. Most existing test chamber driver circuits use a push-pull circuit approach, generally including a low-speed DRV (drive) output channel and a high-speed I / O channel. Increasing the number of high-speed I / O channels increases the number of chips that can be tested simultaneously, but this also increases the cost. Summary of the Invention

[0003] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a driving circuit and method for an aging test machine, which can improve the testing efficiency of the aging test machine at a low cost.

[0004] On one hand, the aging test machine drive circuit according to an embodiment of the present invention includes:

[0005] A driver board includes a master control module, a first slave module, a drive circuit, and a comparator circuit. The master control module is connected to a host computer and is used to receive a first control command and a test vector sent by the host computer. The first slave module is connected to the master control module and is used to send a control signal to the drive circuit according to a second control command from the master control module. The drive circuit is connected to the first slave module and is used to generate a drive signal or a clock signal according to the control signal. The comparator circuit is connected to the first slave module.

[0006] An aging test board is connected to the drive circuit and the comparison circuit. The aging test board is used to perform aging tests according to the drive signal or the clock signal, and generate a response signal according to the test result, and send the response signal to the comparison circuit. The comparison circuit is used to compare the response signal with the reference signal and output the comparison result to the first slave module. The first slave module is used to feed back the comparison result to the master control module, so that the master control module feeds back the test result to the host computer.

[0007] A power supply board is connected to the main control module, and the power supply board is used to supply power to the aging test board according to the third control command of the main control module.

[0008] According to some embodiments of the present invention, the driving circuit includes:

[0009] A DAC chip has a high-level channel and a low-level channel;

[0010] A first switch, wherein the first input terminal of the first switch is connected to the high-level channel, the second input terminal of the first switch is connected to the low-level channel, and the controlled terminal of the first switch is connected to a high-speed clock;

[0011] A first operational amplifier, wherein the non-inverting input terminal of the first operational amplifier is connected to the output terminal of the first switch, and the inverting input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier;

[0012] A first impedance matching resistor, one end of which is connected to the output terminal of the first operational amplifier, and the other end of which is connected to the aging test board;

[0013] The second switch is connected in parallel with the first impedance matching resistor, and the controlled terminal of the second switch is connected to a switch signal.

[0014] According to some embodiments of the present invention, each of the first switch, the first operational amplifier, the first impedance matching resistor, and the second switch constitutes a test channel. The driving circuit has multiple test channels. The high-level channel is connected to the first input terminal of the first switch of each test channel through multiple first voltage followers, and the low-level channel is connected to the second input terminal of the first switch of each test channel through multiple second voltage followers.

[0015] According to some embodiments of the present invention, the comparison circuit includes:

[0016] A second operational amplifier, wherein the inverting input of the second operational amplifier is connected to the first reference voltage, and the non-inverting input of the second operational amplifier is connected to the response signal;

[0017] A third operational amplifier, wherein the inverting input terminal of the third operational amplifier is connected to a second reference voltage, and the non-inverting input terminal of the third operational amplifier is connected to the response signal;

[0018] A first level conversion chip, the input terminal of which is connected to the output terminal of the second operational amplifier, and the output terminal of which is connected to the first slave module;

[0019] The second level conversion chip has its input terminal connected to the output terminal of the third operational amplifier, and its output terminal connected to the first slave module.

[0020] According to some embodiments of the present invention, the comparison circuit further includes:

[0021] The second impedance matching resistor connects the output of the second operational amplifier to the input of the first level conversion chip.

[0022] The third impedance matching resistor is used to connect the output of the third operational amplifier to the input of the second level conversion chip.

[0023] According to some embodiments of the present invention, the power supply board includes a second slave module and a programmable power module, the second slave module is connected to the main control module, and the programmable power module is connected to the second slave module and the aging test board respectively.

[0024] According to some embodiments of the present invention, the communication signal between the master control module and the first slave module includes a first LVDS signal, a first clock signal and a first synchronization signal, and the communication signal between the master control module and the second slave module includes a second LVDS signal, a second clock signal and a second synchronization signal; the first clock signal and the second clock signal are co-source clocks, and the first synchronization signal and the second synchronization signal are synchronization signals.

[0025] On the other hand, the aging tester driving method according to embodiments of the present invention is applied to the aging tester driving circuit as described in the above-mentioned aspects of the embodiments, the method comprising:

[0026] The host computer sends the first control command and test vector to the main control module;

[0027] The main control module generates a second control command and a third control command based on the first control command and the test vector, and sends the second control command to the first slave module and the third control command to the power supply board;

[0028] The power supply board supplies power to the aging test board according to the third control command;

[0029] The first slave module controls the drive circuit to generate a drive signal or a clock signal according to the second control command, so that the aging test board performs aging test according to the drive signal or the clock signal;

[0030] The aging test board generates a response signal based on the test results and sends the response signal to the comparison circuit.

[0031] The comparison circuit is used to compare the response signal with the reference signal and output the comparison result to the first slave module;

[0032] The first slave module feeds back the comparison result to the master control module, so that the master control module feeds back the test result to the host computer.

[0033] According to some embodiments of the present invention, the driving circuit includes a DAC chip, a first switch, a first operational amplifier, a first impedance matching resistor, and a second switch. The DAC chip has a high-level channel and a low-level channel. A first input terminal of the first switch is connected to the high-level channel, and a second input terminal of the first switch is connected to the low-level channel. The controlled terminal of the first switch is connected to a high-speed clock. The non-inverting input terminal of the first operational amplifier is connected to the output terminal of the first switch, and the inverting input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier. One end of the first impedance matching resistor is connected to the output terminal of the first operational amplifier, and the other end of the first impedance matching resistor is connected to the aging test board. The second switch is connected in parallel with the impedance matching resistor, and the controlled terminal of the second switch is connected to a switching signal.

[0034] The first slave module controls the drive circuit to generate a drive signal or a clock signal according to the second control command, so that the aging test board performs aging tests according to the drive signal or the clock signal. The specific steps include:

[0035] The first slave module controls the high-speed clock to switch the conduction state of the first input terminal and the second input terminal of the first switch at a preset frequency according to the second control instruction, and controls the second switch to be in the off state.

[0036] The output terminal of the first switch outputs the clock signal of the preset frequency to the first operational amplifier, and the first operational amplifier amplifies the clock signal;

[0037] After the first impedance matching resistor performs impedance matching on the amplified clock signal, it outputs the signal to the aging test board, so that the aging test board performs aging tests according to the clock signal.

[0038] According to some embodiments of the present invention, the step of the first slave module controlling the drive circuit to generate a drive signal or a clock signal according to the second control instruction, so that the aging test board performs aging test according to the drive signal or the clock signal, further includes:

[0039] The first slave module, according to the second control command and test vector, connects the first input terminal and the output terminal of the first switch and closes the second switch, causing the driving circuit to output a first driving signal; or, connects the second input terminal and the output terminal of the first switch and closes the second switch, causing the driving circuit to output a second driving signal.

[0040] The driving circuit drives the aging test board according to the first driving signal or the second driving signal.

[0041] The aging tester drive circuit and method according to embodiments of the present invention have at least the following beneficial effects: the output pins of the drive circuit can be used as ordinary output pins to drive multiple loads, or as high-speed clock output pins, thereby increasing the number of clock pins on the entire board and increasing the number of chips tested simultaneously, thus improving the testing efficiency of the aging tester without increasing costs; the high level VOH and low level VOL of the DAC chip can be arbitrarily set within a certain range; each functional board of the entire circuit is independent, and boards of corresponding specifications can be conveniently deployed according to the requirements of the test specifications, facilitating product upgrades, reuse, and saving development costs.

[0042] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0043] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0044] Figure 1 This is a schematic diagram of the aging tester drive circuit according to an embodiment of the present invention;

[0045] Figure 2 This is a circuit schematic diagram of the driving circuit according to an embodiment of the present invention;

[0046] Figure 3 This is a circuit schematic diagram of a driving circuit according to another embodiment of the present invention;

[0047] Figure 4 This is a circuit schematic diagram of the comparison circuit according to an embodiment of the present invention;

[0048] Figure 5 This is a flowchart illustrating the steps of the aging tester driving method according to an embodiment of the present invention.

[0049] Driver board 100, main control module 110, first slave module 120, drive circuit 130, test channel 131, comparison circuit 140, aging test board 200, power supply board 300, second slave module 310, programmable power supply module 320. Detailed Implementation

[0050] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0051] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0052] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0053] In this invention, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0054] Aging test chambers are primarily used to screen out defective chips through prolonged aging tests, thereby improving the quality of chip products. During aging tests, a test chamber driver circuit typically drives the machine. Most existing test chamber driver circuits use a push-pull circuit approach, generally including a low-speed DRV (drive) output channel and a high-speed I / O channel. Increasing the number of high-speed I / O channels increases the number of chips that can be tested simultaneously, but this also increases the cost.

[0055] To address this, embodiments of the present invention provide a driving circuit and method for an aging tester. The output pins of the driving circuit can function as ordinary output pins to drive multiple loads, or as high-speed clock output pins, thereby increasing the number of clock pins on the entire board and increasing the number of chips that can be tested simultaneously. This improves the testing efficiency of the aging tester without increasing costs. The high-level VOH and low-level VOL of the DAC chip can be arbitrarily set within a certain range. Each functional board in the entire circuit is independent, and boards of corresponding specifications can be easily deployed according to the requirements of the test specifications, facilitating product upgrades, reuse, and saving development costs.

[0056] The aging test machine drive circuit and method of the present invention will be described in detail below with reference to the accompanying drawings.

[0057] On the one hand, such as Figure 1 As shown, this embodiment of the invention proposes a driving circuit for an aging tester, including a driving board 100 (i.e., Figure 1 The DCL functional board in the middle), aging test board 200 (i.e. Figure 1 BI board) and power supply board 300 (i.e. Figure 1 The DPS function board in the middle); the driver board 100 includes the main control module 110 (i.e., Figure 1 The system comprises a core board, a first slave module 120, a drive circuit 130, and a comparator circuit 140; a master control module 110 connected to a host computer to receive a first control command and test vector sent by the host computer; a first slave module 120 connected to the master control module 110 to send control signals to the drive circuit 130 according to a second control command from the master control module 110; and a drive circuit 130 connected to the first slave module 120 and the aging test board 200 to generate a drive signal (DRV) or a clock signal (CLK) according to the control signal and send it to the aging test board 200, so that the aging test board 200 responds to the drive signal or clock signal. The clock signal is subjected to aging test and a response signal is generated according to the test result. The response signal is sent to the comparison circuit 140. The comparison circuit 140 is connected to the aging test board 200 and the first slave module 120. The comparison circuit 140 is used to compare the response signal with the reference signal and output the comparison result to the first slave module 120, so that the first slave module 120 feeds back the comparison result to the master control module 110, so that the master control module 110 feeds back the test result to the host computer. The power supply board 300 is connected to the master control module 110 and is used to supply power to the aging test board 200 according to the third control command of the master control module 110.

[0058] It should be noted that the main control module 110 (core board) includes a main FPGA (Field Programmable Gate Array), memory (not shown), and interface circuits (not shown). The main control module 110 communicates with the host computer (industrial control computer) via Ethernet using a gigabit network. The main control module 110 receives the first control command and test vectors issued by the host computer, and controls the aging test process of the aging test board 200 according to the first control command and test vectors, and then sends the final test results to the host computer. The main control module 110 is mainly responsible for executing test programs, managing test vectors, and recording test results. The first slave module 120 includes a slave FPGA. The main FPGA of the main control module 110 and the slave FPGA of the first slave module 120 communicate via LVDS. After receiving the first control command and test vectors issued by the host computer, the main control module 110 generates a second control command and sends it to the first slave module 120 via LVDS (Low-Voltage Differential Signaling). After receiving the second control command, the first slave module 120 sends a control signal to the drive circuit 130, causing the drive circuit 130 to generate a drive signal (DRV) or a clock signal (CLK), and then sends the drive signal (DRV) or clock signal (CLK) to the aging test board 200 to control the aging test board 200 to perform aging tests. After the aging test, the aging test board 200 sends response signals from each channel to the comparison circuit 140. The comparison circuit 140 compares the response signals with the reference signal and outputs the comparison result to the first slave module 120, so that the first slave module 120 feeds back the comparison result to the master control module 110, so that the master control module 110 feeds back the test result to the host computer.

[0059] It should be noted that the driver board 100 and the aging test board 200 are connected via connectors, as are the driver board 100 and the power supply board 300, and the power supply board 300 and the aging test board 200. In this example, the power supply board 300 includes a second slave module 310 and a programmable power module 320. The second slave module 310 is connected to the main control module 110, and the programmable power module 320 is connected to both the second slave module 310 and the aging test board 200. The second slave module 310 includes a slave FPGA, and it communicates with the main control module 110 via LVDS. After receiving the first control command and test vector from the host computer, the main control module 110 generates a third control command and sends it to the second slave module 310 via LVDS. This causes the second slave module 310 to configure the voltage of the programmable power module 320 to supply power to the aging test board 200.

[0060] It should be noted that the communication signals between the master control module 110 and the first slave module 120 include a first LVDS signal, a first clock signal (CLK1), and a first synchronization signal (RUN1). The communication signals between the master control module 110 and the second slave module 310 include a second LVDS signal, a second clock signal (CLK2), and a second synchronization signal (RUN2). The first clock signal and the second clock signal are from the same source, and the first synchronization signal and the second synchronization signal are synchronization signals. The number of LVDS signals depends on the data bandwidth. CLK1 and CLK2 are from the same source, and RUN1 and RUN2 are synchronization signals. To ensure the synchronization of the driver board 100 and the power supply board 300, CLK1 and CLK2 are of equal length, and RUN1 and RUN2 are of equal length.

[0061] like Figure 2 As shown, in some embodiments of the present invention, the driving circuit 130 includes: a DAC chip, a first switch K1, and a first operational amplifier U3, wherein the DAC chip has a high-level channel (DAC VOH) and a low-level channel (DAC VOL); the first input terminal of the first switch K1 is connected to the high-level channel (DAC VOH), the second input terminal of the first switch K1 is connected to the low-level channel (DAC VOL), and the controlled terminal of the first switch K1 is connected to a high-speed clock (CLK); the non-inverting input terminal of the first operational amplifier U3 is connected to the output terminal of the first switch K1, and the inverting input terminal of the first operational amplifier U3 is connected to the output terminal of the first operational amplifier U3; the output terminal of the first operational amplifier U3 is connected to one end of a first impedance matching resistor R1, and the other end of the first impedance matching resistor R1 is connected to an aging test board 200; the second switch K2 is connected in parallel with the first impedance matching resistor R1, and the controlled terminal of the second switch K2 is connected to a switching signal (H / L).

[0062] It should be noted that the DAC chip has two output channels, one set to output a high level VOH and the other set to output a low level VOL. Both output channels of the DAC chip are connected to a high-speed analog switch (first switch K1). The analog switch selects the desired output level to a high-current operational amplifier (first operational amplifier U3) via a control pin. A first impedance matching resistor R1 (with a value of 50Ω, etc.) is connected after the first operational amplifier U3. When the output pin of the driver circuit 130 is used as a clock pin, the first impedance matching resistor R1 is connected in series in the circuit for impedance matching, and the second switch K2 is open. When the output pin of the driver circuit 130 is used as a normal output pin to drive a high-current load, the second switch K2 is closed, shorting the first impedance matching resistor R1 to prevent a voltage drop across R1 from affecting the load level. When the output pin of the driver circuit 130 is used as a clock pin to output a clock signal (CLK), the maximum frequency of the output clock signal is limited by the switching speed of the first switch K1 and the bandwidth of the first operational amplifier U3. When the driver circuit 130 is in drive mode:

[0063] Output voltage VOH: When the first switch K1 is switched to DAC VOH, the second switch K2 is closed, and the output drive signal is generated.

[0064] Output voltage VOL: When the first switch K1 is turned on to DAC VOL, the second switch K2 is closed, and the output drive signal is generated.

[0065] When the drive circuit 130 is in clock mode: the first switch K1 continuously switches the output VOH and VOL through a high-speed clock, the second switch K2 is in the open state, performs 50Ω impedance matching, and outputs a clock signal. The frequency of the clock signal is equal to the switching frequency of the first switch K1. The high level of the clock signal is VOH, and the low level is VOL.

[0066] Furthermore, such as Figure 3 As shown, each first switch K1, first operational amplifier U3, first impedance matching resistor R1, and second switch K2 constitute a test channel 131. The drive circuit 130 has multiple test channels. The high-level channel (DACVOH) is connected to the first input terminal of the first switch K1 of each test channel 131 through multiple first voltage followers U6, and the low-level channel (DAC VOL) ​​is connected to the second input terminal of the first switch K1 of each test channel 131 through multiple second voltage followers U7. To reduce costs, when multiple output stages (i.e., multiple test channels 131) share a single DAC chip, an operational amplifier can be used as a voltage follower to increase the driving capability of the DAC chip and reduce the impact of parasitic inductance caused by long-distance traces.

[0067] like Figure 4As shown, in some embodiments of the present invention, the comparator circuit 140 includes a second operational amplifier U1, a third operational amplifier U2, a first level conversion chip U4, and a second level conversion chip U5. The inverting input terminal of the second operational amplifier U1 is connected to the first reference voltage DAC_CVOH, and the non-inverting input terminal of the second operational amplifier U1 is connected to the response signal. The inverting input terminal of the third operational amplifier U2 is connected to the second reference voltage DAC_CVOL, and the non-inverting input terminal of the third operational amplifier U2 is connected to the response signal. The input terminal of the first level conversion chip U4 is connected to the output terminal of the second operational amplifier U1, and the output terminal of the first level conversion chip U4 is connected to the first slave module 120. The input terminal of the second level conversion chip U5 is connected to the output terminal of the third operational amplifier U2, and the output terminal of the second level conversion chip U5 is connected to the first slave module 120.

[0068] It should be noted that the second operational amplifier U1 and the third operational amplifier U2 constitute a window comparator. The positive supply voltage of the op-amp is 5V, and the negative supply voltage is 0V. DAC_CVOH and DAC_CVOL serve as the upper and lower reference voltages of the window comparator. Because the op-amp has extremely high open-loop gain, when the input voltage of the response signal is greater than the reference voltage, the op-amp output is the positive supply voltage of 5V; when the input voltage of the response signal is less than the reference voltage, the op-amp output is the negative supply voltage of 0V. The function of the level conversion chip is mainly to convert the voltage output by the op-amp (0-5V) into a voltage (0-1.8V) that can be received by the FPGA.

[0069] Furthermore, such as Figure 4 As shown, in some embodiments of the present invention, the comparator circuit 140 further includes a second impedance matching resistor R2 and a third impedance matching resistor R3. The output terminal of the second operational amplifier U1 is connected to the input terminal of the first level conversion chip U4 through the second impedance matching resistor R2, and the output terminal of the third operational amplifier U2 is connected to the input terminal of the second level conversion chip U5 through the third impedance matching resistor R3. When the input response signal is a high-frequency signal, because the output impedance of the operational amplifier is very small, the impedance mismatch with the transmission line can easily cause reflection. In order to reduce the overshoot caused by reflection of the input signals of the first level conversion chip U4 and the second level conversion chip U5, the second impedance matching resistor R1 and the third impedance matching resistor R3 are connected in series near the output terminal of the operational amplifier for impedance matching.

[0070] According to the aging tester drive circuit of the present invention, the output pins of the drive circuit 130 can be used as ordinary output pins to drive multiple loads, or as high-speed clock output pins, thereby increasing the number of clock pins on the entire board and increasing the number of chips tested simultaneously, thus improving the testing efficiency of the aging tester without increasing costs; the high level VOH and low level VOL of the DAC chip can be arbitrarily set within a certain range; each functional board of the entire circuit is independent, and boards of corresponding specifications can be conveniently deployed according to the requirements of the test specifications, facilitating product upgrades, reuse, and saving development costs.

[0071] On the other hand, based on the aging tester drive circuit described in the above embodiments, this invention also proposes an aging tester drive method, such as... Figure 5 As shown, the method includes the following steps:

[0072] Step S100: The host computer sends the first control command and test vector to the main control module 110;

[0073] The main control module 110 communicates with the host computer (industrial control computer) via Ethernet using a gigabit network. The first control command and test vector issued by the host computer are sent to the main control module 110 through the network port. The main control module 110 is used to control the aging test process of the aging test board 200 according to the first control command and test vector, and then sends the final test results to the host computer.

[0074] Step S200: The main control module 110 generates a second control command and a third control command based on the first control command and the test vector, and sends the second control command to the first slave module 120 and the third control command to the power supply board 300.

[0075] After receiving the first control command and test vector from the host computer, the main control module 110 generates a second control command and sends it to the first slave module 120 via LVDS; at the same time, the main control module 110 generates a third control command and sends the third control command to the power supply board 300 via LVDS.

[0076] Step S300: The power supply board 300 supplies power to the aging test board 200 according to the third control command;

[0077] After receiving the third control command, the second slave module 310 of the power supply board 300 configures the voltage of the programmable power supply module 320 to supply power to the aging test board 200.

[0078] Step S400: The first slave module 120 controls the drive circuit 130 to generate a drive signal or a clock signal according to the second control instruction, so that the aging test board 200 performs aging test according to the drive signal or clock signal.

[0079] After receiving the second control command from module 120, the first module sends a control signal to drive circuit 130, causing drive circuit 130 to generate a drive signal (DRV) or a clock signal (CLK), and then sends the drive signal (DRV) or clock signal (CLK) to aging test board 200 to control aging test board 200 to perform aging test. When the output pin of drive circuit 130 is used as a clock pin to output a clock signal, the first impedance matching resistor R1 is connected in series in the circuit for impedance matching, and the second switch K2 is open. When the output pin of drive circuit 130 is used as a normal output pin to output a drive signal for driving a high current load, the second switch K2 is closed, so that the first impedance matching resistor R1 is short-circuited to prevent the voltage drop on the first impedance matching resistor R1 from affecting the load level. When the output pin of drive circuit 130 is used as a clock pin to output a clock signal (CLK), the maximum frequency of the output clock signal is limited by the switching speed of the first switch K1 and the bandwidth of the first operational amplifier U3.

[0080] When the drive circuit 130 is in clock mode, the above step S400 includes the following three steps:

[0081] ①The first slave module 120 controls the high-speed clock to switch the conduction state of the first input terminal and the second input terminal of the first switch K1 at a preset frequency according to the second control instruction, and controls the second switch K2 to be in the off state;

[0082] ② The output terminal of the first switch K1 outputs a clock signal of a preset frequency to the first operational amplifier U3, and the first operational amplifier U3 amplifies the clock signal;

[0083] ③ After the first impedance matching resistor R1 performs impedance matching on the amplified clock signal, it is output to the aging test board 200, so that the aging test board 200 performs aging test according to the clock signal.

[0084] When the drive circuit 130 is in clock mode: the first switch K1 continuously switches the output VOH and VOL through a high-speed clock, the second switch K2 is in the open state, performs 50Ω impedance matching, and outputs a clock signal. The frequency of the clock signal is equal to the switching frequency of the first switch K1. The high level of the clock signal is VOH, and the low level is VOL.

[0085] When the drive circuit 130 is in drive mode, the above step S400 includes the following two steps:

[0086] ① The first slave module 120, according to the second control command and the test vector, connects the first input terminal and the output terminal of the first switch K1 and closes the second switch K2, so that the drive circuit 130 outputs the first drive signal; or, connects the second input terminal and the output terminal of the first switch K1 and closes the second switch K2, so that the drive circuit 130 outputs the second drive signal.

[0087] ② The driving circuit 130 drives the aging test board 200 according to the first driving signal or the second driving signal.

[0088] When the drive circuit 130 is in drive mode, there are two options:

[0089] Output voltage VOH: When the first switch K1 is switched to DAC VOH, the second switch K2 is closed, and the first drive signal is output.

[0090] Output voltage VOL: When the first switch K1 is turned on to DAC VOL, the second switch K2 is closed, and the second drive signal is output.

[0091] Step S500: The aging test board 200 generates a response signal based on the test results and sends the response signal to the comparison circuit 140;

[0092] After the aging test board 200 performs the aging test, it sends the response signals of each channel to the comparison circuit 140.

[0093] Step S600: The comparison circuit 140 is used to compare the response signal with the reference signal and output the comparison result to the first slave module 120;

[0094] The comparator circuit 140 includes a second operational amplifier U1, a third operational amplifier U2, a first level conversion chip U4, and a second level conversion chip U5. The inverting input of the second operational amplifier U1 is connected to the first reference voltage DAC_CVOH, and the non-inverting input of the second operational amplifier U1 is connected to the response signal. The inverting input of the third operational amplifier U2 is connected to the second reference voltage DAC_CVOL, and the non-inverting input of the third operational amplifier U2 is connected to the response signal. The input of the first level conversion chip U4 is connected to the output of the second operational amplifier U1, and the output of the first level conversion chip U4 is connected to the first slave module 120. The input of the second level conversion chip U5 is connected to the output of the third operational amplifier U2, and the output of the second level conversion chip U5 is connected to the first slave module 120.

[0095] It should be noted that the second operational amplifier U1 and the third operational amplifier U2 constitute a window comparator. The positive supply voltage of the op-amp is 5V, and the negative supply voltage is 0V. DAC_CVOH and DAC_CVOL serve as the upper and lower reference voltages of the window comparator. Because the op-amp has extremely high open-loop gain, when the input voltage of the response signal is greater than the reference voltage, the op-amp output is the positive supply voltage of 5V; when the input voltage of the response signal is less than the reference voltage, the op-amp output is the negative supply voltage of 0V. The function of the level conversion chip is mainly to convert the voltage output by the op-amp (0-5V) into a voltage of 0-1.8V that can be received by the FPGA.

[0096] Step S700: The first slave module 120 feeds back the comparison result to the master control module 110, so that the master control module 110 feeds back the test result to the host computer.

[0097] According to the aging tester driving method of the present invention, the output pin of the driving circuit 130 can be used as a normal output pin to drive multiple loads, or as a high-speed clock output pin, thereby increasing the number of clock pins on the entire board and increasing the number of chips tested simultaneously, thus improving the testing efficiency of the aging tester without increasing costs; the high level VOH and low level VOL of the DAC chip can be arbitrarily set within a certain range; each functional board of the entire circuit is independent, and boards of corresponding specifications can be conveniently deployed according to the requirements of the test specifications, which facilitates product upgrades, reuse, and saves development costs.

[0098] It should be noted that the contents of the above circuit embodiments are all applicable to this method embodiment. The specific functions implemented in this embodiment are the same as those in the above circuit embodiments, and the beneficial effects achieved are also the same as those achieved in the above circuit embodiments.

[0099] On the other hand, embodiments of the present invention also propose an electronic device, comprising:

[0100] Memory, used to store program instructions;

[0101] The processor is used to call the program instructions stored in the memory and execute the above-described aging test machine driving method according to the obtained program instructions.

[0102] The processor can be implemented using a general-purpose central processing unit (CPU), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to achieve the technical solutions provided in the embodiments of this application.

[0103] The memory can be implemented in the form of read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory can store the operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory and called and executed by the processor from the aging test machine drive circuit of the embodiments of this application. The memory and the processor can be connected via a bus or similar means.

[0104] On the other hand, embodiments of the present invention also provide a storage medium, which is a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described aging test machine driving method.

[0105] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof. The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate, and may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0106] Although specific embodiments are described herein, those skilled in the art will recognize that many other modifications or alternative embodiments are also within the scope of this disclosure. For example, any of the functions and / or processing capabilities described in connection with a particular device or component can be performed by any other device or component. Furthermore, while various exemplary embodiments and architectures have been described according to embodiments of this disclosure, those skilled in the art will recognize that many other modifications to the exemplary embodiments and architectures described herein are also within the scope of this disclosure.

[0107] The foregoing description, with reference to block diagrams and flowcharts of systems, methods, systems, and / or computer program products according to exemplary embodiments, has described certain aspects of this disclosure. It should be understood that one or more blocks in the block diagrams and flowcharts, as well as combinations of blocks in the block diagrams and flowcharts, can be implemented by executing computer-executable program instructions, respectively. Similarly, according to some embodiments, some blocks in the block diagrams and flowcharts may not need to be executed in the order shown, or may not all need to be executed. Furthermore, additional components and / or operations beyond those shown in the blocks in the block diagrams and flowcharts may exist in some embodiments.

[0108] Therefore, blocks in block diagrams and flowcharts support combinations of means for performing a specified function, combinations of elements or steps for performing a specified function, and program instruction means for performing a specified function. It should also be understood that each block in a block diagram and flowchart, and combinations of blocks in block diagrams and flowcharts, can be implemented by a dedicated hardware computer system or a combination of dedicated hardware and computer instructions that performs a specific function, element, or step.

[0109] The program modules, applications, etc., described herein may include one or more software components, including, for example, software objects, methods, data structures, etc. Each such software component may include computer-executable instructions that, in response to execution, cause at least a portion of the functionality described herein (e.g., one or more operations of the exemplary methods described herein) to be performed.

[0110] Software components can be coded using any of a variety of programming languages. An exemplary programming language could be a low-level programming language, such as assembly language associated with a specific hardware architecture and / or operating system platform. Software components including assembly language instructions may need to be converted into executable machine code by an assembler before being executed by the hardware architecture and / or platform. Another exemplary programming language could be a higher-level programming language that is portable across multiple architectures. Software components including higher-level programming languages ​​may need to be converted into an intermediate representation by an interpreter or compiler before execution. Other examples of programming languages ​​include, but are not limited to, macro languages, shell or command languages, job control languages, scripting languages, database query or search languages, or report writing languages. In one or more exemplary embodiments, a software component containing instructions from one of the above-described programming language examples can be executed directly by the operating system or other software components without first being converted into another form.

[0111] Software components can be stored as files or other data storage structures. Software components of similar type or related function can be stored together in a specific directory, folder, or library. Software components can be static (e.g., pre-defined or fixed) or dynamic (e.g., created or modified at runtime).

[0112] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A driving circuit for an aging tester, characterized in that, include: The driver board includes a master control module, a first slave module, a drive circuit, and a comparison circuit. The master control module is connected to a host computer and is used to receive a first control command and a test vector sent by the host computer. The first slave module is connected to the master control module and is used to send control signals to the drive circuit according to a second control command from the master control module. The driving circuit is connected to the first slave module and is used to generate a driving signal or a clock signal according to the control signal; the comparison circuit is connected to the first slave module. An aging test board is connected to the driving circuit and the comparison circuit. The aging test board is used to perform aging tests according to the driving signal or the clock signal, and generate a response signal according to the test results, and send the response signal to the comparison circuit. The comparison circuit is used to compare the response signal with the reference signal and output the comparison result to the first slave module; The first slave module is used to feed back the comparison result to the master control module, so that the master control module feeds back the test result to the host computer; A power supply board is connected to the main control module, and the power supply board is used to supply power to the aging test board according to the third control command of the main control module; The driving circuit includes: A DAC chip has a high-level channel and a low-level channel; A first switch, wherein the first input terminal of the first switch is connected to the high-level channel, the second input terminal of the first switch is connected to the low-level channel, and the controlled terminal of the first switch is connected to a high-speed clock; A first operational amplifier, wherein the non-inverting input terminal of the first operational amplifier is connected to the output terminal of the first switch, and the inverting input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier; A first impedance matching resistor, one end of which is connected to the output terminal of the first operational amplifier, and the other end of which is connected to the aging test board; The second switch is connected in parallel with the first impedance matching resistor, and the controlled terminal of the second switch is connected to a switch signal.

2. The aging tester drive circuit according to claim 1, characterized in that, Each of the first switch, the first operational amplifier, the first impedance matching resistor, and the second switch constitutes a test channel. The driving circuit has multiple test channels. The high-level channel is connected to the first input terminal of the first switch of each test channel through multiple first voltage followers. The low-level channel is connected to the second input terminal of the first switch of each test channel through multiple second voltage followers.

3. The aging tester drive circuit according to claim 1, characterized in that, The comparison circuit includes: A second operational amplifier, wherein the inverting input of the second operational amplifier is connected to the first reference voltage, and the non-inverting input of the second operational amplifier is connected to the response signal; A third operational amplifier, wherein the inverting input terminal of the third operational amplifier is connected to a second reference voltage, and the non-inverting input terminal of the third operational amplifier is connected to the response signal; A first level conversion chip, the input terminal of which is connected to the output terminal of the second operational amplifier, and the output terminal of which is connected to the first slave module; The second level conversion chip has its input terminal connected to the output terminal of the third operational amplifier, and its output terminal connected to the first slave module.

4. The aging tester drive circuit according to claim 3, characterized in that, The comparison circuit further includes: The second impedance matching resistor connects the output of the second operational amplifier to the input of the first level conversion chip. The third impedance matching resistor is used to connect the output of the third operational amplifier to the input of the second level conversion chip.

5. The aging tester drive circuit according to claim 1, characterized in that, The power supply board includes a second slave module and a programmable power module. The second slave module is connected to the main control module, and the programmable power module is connected to both the second slave module and the aging test board.

6. The aging tester drive circuit according to claim 5, characterized in that, The communication signals between the master control module and the first slave module include a first LVDS signal, a first clock signal, and a first synchronization signal. The communication signals between the master control module and the second slave module include a second LVDS signal, a second clock signal, and a second synchronization signal. The first clock signal and the second clock signal are from the same source clock, and the first synchronization signal and the second synchronization signal are synchronization signals.

7. A driving method for an aging test machine, characterized in that, The method, applied to the aging tester drive circuit as described in any one of claims 1-6, comprises: The host computer sends the first control command and test vector to the main control module; The main control module generates a second control command and a third control command based on the first control command and the test vector, and sends the second control command to the first slave module and the third control command to the power supply board; The power supply board supplies power to the aging test board according to the third control command; The first slave module controls the drive circuit to generate a drive signal or a clock signal according to the second control command, so that the aging test board performs aging test according to the drive signal or the clock signal; The aging test board generates a response signal based on the test results and sends the response signal to the comparison circuit. The comparison circuit is used to compare the response signal with the reference signal and output the comparison result to the first slave module; The first slave module feeds back the comparison result to the master control module, so that the master control module feeds back the test result to the host computer.

8. The aging test machine driving method according to claim 7, characterized in that, The driving circuit includes a DAC chip, a first switch, a first operational amplifier, a first impedance matching resistor, and a second switch. The DAC chip has a high-level channel and a low-level channel. The first input terminal of the first switch is connected to the high-level channel, and the second input terminal of the first switch is connected to the low-level channel. The controlled terminal of the first switch is connected to a high-speed clock. The non-inverting input terminal of the first operational amplifier is connected to the output terminal of the first switch, and the inverting input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier. One end of the first impedance matching resistor is connected to the output terminal of the first operational amplifier, and the other end of the first impedance matching resistor is connected to the aging test board. The second switch is connected in parallel with the impedance matching resistor, and the controlled terminal of the second switch is connected to a switching signal. The first slave module controls the drive circuit to generate a drive signal or a clock signal according to the second control command, so that the aging test board performs aging tests according to the drive signal or the clock signal. The specific steps include: The first slave module controls the high-speed clock to switch the conduction state of the first input terminal and the second input terminal of the first switch at a preset frequency according to the second control instruction, and controls the second switch to be in the off state. The output terminal of the first switch outputs the clock signal of the preset frequency to the first operational amplifier, and the first operational amplifier amplifies the clock signal; After the first impedance matching resistor performs impedance matching on the amplified clock signal, it outputs the signal to the aging test board, so that the aging test board performs aging tests according to the clock signal.

9. The aging test machine driving method according to claim 8, characterized in that, The step of the first slave module controlling the drive circuit to generate a drive signal or a clock signal according to the second control command, so that the aging test board performs aging test according to the drive signal or the clock signal, further includes: The first slave module, according to the second control command and test vector, connects the first input terminal and the output terminal of the first switch and closes the second switch, causing the driving circuit to output a first driving signal; or, connects the second input terminal and the output terminal of the first switch and closes the second switch, causing the driving circuit to output a second driving signal. The driving circuit drives the aging test board according to the first driving signal or the second driving signal.

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