A method for current synchronization control of parallel converters

Abstract

The present invention relates to a current synchronization control method for a parallel converter, analyzes the multi-interference characteristics existing in the parallel converter system, establishes a dynamic mathematical model of the parallel converter that comprehensively considers factors such as line impedance mismatch, structural parameter differences, and load uncertainty caused by temperature rise, designs a finite-time voltage outer loop tracking controller and a load observer to achieve voltage constancy; designs an integral terminal sliding mode current inner loop controller to achieve the tracking speed and control accuracy of the current loop; designs a finite-time mismatched line impedance differentiator and a fractional-order adaptive controller to achieve current synchronization of the parallel converter system. While ensuring the rapid tracking capability of the system, the present invention can effectively suppress the influence of many interferences on current synchronization, ensuring the optimal current synchronization performance during the entire operation of the multi-converter system.

Description

Technical Field

[0001] The present invention relates to a control method, in particular to a current synchronization control method under comprehensive consideration of various interferences such as line impedance mismatch between parallel converters and structural parameter differences, and belongs to the technical field of electrical engineering. Background Art

[0002] Compared with the traditional single power supply, parallel power supply has more advantages, such as large capacity, high efficiency, higher reliability and fault tolerance. However, due to the mismatch of line impedance between parallel converters, differences in structural parameters, and load uncertainty caused by temperature rise, the current synchronization problem between multiple converters is particularly prominent.

[0003] In the study of multi-converter current synchronization, some adopt the output voltage droop control method, which is to change the gain of voltage feedback or adjust the output voltage according to the output current, so that the output voltage has a certain droop characteristic, so that the current synchronization between parallel systems can be achieved to a certain extent. This method does not need to control each parallel subsystem separately, and the control idea is relatively simple. However, this method has certain limitations. When there are many parallel subsystems, the current synchronization effect will be worse; some adopt the master-slave current sharing control method, which is to select one as the master subsystem among all the parallel subsystems, and control the output voltage stability of the parallel system through the voltage feedback of the subsystem. The output currents of other subsystems track the output current of the master subsystem, and each subsystem has a separate current feedback control, so there are parameter differences and other mismatches between each subsystem, and the current synchronization effect can also be achieved better. Some adopt the average current automatic current sharing control method, which is to actively control the current of each subsystem when each subsystem is mismatched, so as to achieve the current synchronization of each subsystem.

[0004] However, it is worth pointing out that the existing research on current synchronization of multi-converters almost exclusively focuses on the current synchronization of multi-converters in the steady state phase, without considering the current synchronization in the transient phase when starting and interference is applied, which makes it difficult to ensure the optimal overall performance of the entire parallel system. In fact, the existence of various interferences such as line impedance mismatch and structural parameter differences between multi-converter systems poses a severe challenge to the current synchronization in the transient phase. The current asynchrony in the transient phase increases the burden on the converter, seriously affecting the service life and safety of the multi-converter system, which cannot be ignored. Summary of the invention

[0005] The main purpose of the present invention is to: in view of the shortcomings and gaps in the prior art, the present invention provides a cabin suspension converter system model that comprehensively considers multiple interferences and proposes an integral terminal sliding mode control method to ensure the tracking speed and control accuracy of the current loop, and designs a finite-time interference observer and a fractional-order adaptive accurate estimation with a terminal sliding mode finite-time convergence characteristic for the mismatched line impedance devices, differences in structural parameters, load uncertainty caused by temperature rise, and actuator failures between multiple converters to improve the system's anti-interference ability and transient performance, solve the current synchronization problem of the multi-converter system during startup and interference application, and ensure the optimal system synchronization performance during the entire operation of the multi-converter.

[0006] In order to achieve the above objectives, the present invention provides a current synchronization control method under various interferences such as line impedance mismatch and structural parameter differences between parallel converters, including the following steps:

[0007] Step 1, establish a dynamic mathematical model of the parallel converter that comprehensively considers line impedance mismatch, structural parameter differences, actuator aging, and load uncertainty;

[0008] Step 2, design a load uncertainty observer for the parallel converter;

[0009] Step 3, designing a finite time voltage outer loop tracking controller for the parallel converter;

[0010] Step 4, designing a fractional-order integral terminal sliding mode current controller in the current synchronization controller of the parallel converter;

[0011] Step 5, design the finite time differentiator for unmatched line resistance and the fractional-order adaptive law for actuator aging in the current synchronous controller of the parallel converter.

[0012] In step 1, the dynamic mathematical model of the parallel converter that comprehensively considers line impedance mismatch, structural parameter differences, actuator aging, and load uncertainty is established as follows:

[0013] The first step is to calculate the power flowing through the two parallel subsystems according to the lever method:

[0014]

[0015] Among them, 1 , Υ 2 are the power of the two circuits, U c is the load terminal voltage, are the impedances of the two paths respectively;

[0016] The second step is to find the circulating power in the parallel circuit of the two parallel converters.

[0017]

[0018] Among them, c is the cycle power, μ 1 , μ 2 are the transformation ratios of the two converters, U in is the input voltage;

[0019] The third step is to find the actual power flowing through each of the two parallel subsystems:

[0020]

[0021] In the fourth step, the power difference between the two parallel subsystems is

[0022]

[0023] Where ΔΥ is the power difference between the two parallel circuits, i 1 、i 2 are the currents of the two circuits, R 0 is the nominal load value of the system, ΔR is the change in load during load temperature rise and load shedding;

[0024] In the fifth step, considering the aging of the actuator, the fault model is

[0025]

[0026] Where μ = [μ 1 μ 2 ] T is the control input of the actuator, ρ=diag(ρ 1 ,ρ 2 ) and η=[η 1 η 2 ] T are the effective coefficient and the uncertain fault part, respectively, 1 , 2 are the effective coefficients of the control inputs of the two loop actuators, η 1 , η 2 are the uncertain fault partial coefficients of the control inputs of the two loop actuators respectively;

[0027] Step 6: The power difference between the two converters including actuator aging is

[0028]

[0029] The seventh step is to attribute the differences in converter ratio and line structure, actuator aging, and load uncertainty to the voltage input terminal.

[0030]

[0031] Among them, d1 ,d 2 are the control inputs of the two loops, d 1 ′、d 2 ′ are the control inputs of the two loops that comprehensively consider the factors affecting the current sharing, To satisfy the actuator signal of current sharing control effect, Δμ, ΔR is the difference between the control input of the two loop actuators, the impedance of the line group, and the uncertainty of the load;

[0032] In the eighth step, the dynamic mathematical model of the parallel converter is established by comprehensively considering the line impedance mismatch, structural parameter difference, actuator aging and load uncertainty:

[0033]

[0034] Where C is the capacitance, are the currents of the two parallel converters, L 1 , L 2 Two converter inductors, E is the supply voltage, Θ 0 =ΔRU c / CR 0 (R 0 +ΔR) is the current uncertainty value caused by load switching, are the uncertainties due to the aging of the two converter drivers, χ 1 , χ 2 are the impedance mismatch values ​​of the two converter lines respectively.

[0035] The load uncertainty observer of the parallel converter in step 2 is designed as:

[0036]

[0037] Among them, β 1 ,β 2 >0, -0.5<τ<0 are adjustable controller parameters.

[0038] The finite time voltage outer loop tracking controller of the parallel converter in step 3 is designed as follows:

[0039] The first step is to define the voltage tracking error and the first-order derivative of the tracking error:

[0040]

[0041] Among them, e 0 is the voltage tracking error; is the reference voltage value;

[0042] The second step is to design a finite time voltage tracking controller according to equation (10):

[0043]

[0044] Among them, i ref is the voltage tracking controller output, k 1 ,k 2 >0,0<α 1 <1 is the adjustable controller parameter, is θ 0 The estimated value of .

[0045] The fractional-order integral terminal sliding mode current controller in the parallel converter current synchronization controller in step 4 is designed as follows:

[0046] The first step is to define the current tracking error as

[0047]

[0048] Among them, e 1 、e 2 are the tracking errors of the currents in the two converters respectively;

[0049] The second step is to select the integral terminal sliding surface that comprehensively considers the current tracking speed and control accuracy.

[0050]

[0051] Among them, s i is the constructed sliding surface; 0<r<1,β>0 are the adjustable controller parameters;

[0052] The third step is to differentiate the sliding surface of equation (13) to obtain

[0053]

[0054] The fourth step is to design a terminal sliding mode reaching law that comprehensively considers chattering suppression and convergence speed:

[0055]

[0056] Among them, k,ε>0 are adjustable controller parameters;

[0057] The fifth step is to design the current inner loop tracking controller by combining equations (8), (14), and (15):

[0058]

[0059] The finite time differentiator of the unmatched line resistance and the actuator aging fractional-order adaptive law in the current synchronous controller of the parallel converter in step 5 are designed as follows:

[0060] The first step is to calculate the actuator aging part Θ of equation (16)i ,i=1,2The designed fractional-order adaptive approximation law is

[0061]

[0062] in, is an adjustable parameter, is the adjustable controller parameter;

[0063] In the second step, a finite time differentiator is used to solve the line impedance mismatch χ in equation (16). i Estimation acquisition, the ideal estimation model of the parallel converter system is expressed as

[0064]

[0065] Combined with equation (8), the mismatch impedance factor can be expressed as

[0066]

[0067] The finite time differentiator is designed as follows

[0068]

[0069] in,

[0070] In the third step, the current tracking controller of the integrated fractional-order adaptive and finite-time differentiator is obtained by combining equation (16):

[0071]

[0072] in, are the uncertain values ​​caused by current changes due to temperature rise and load switching, and driver aging, respectively. are the line resistance mismatch values ​​of the two converters respectively.

[0073] The beneficial effects of the present invention are as follows: while ensuring the rapid tracking capability and stability of the system, the control method provides a current synchronization control method that comprehensively considers various interferences such as line impedance mismatch and structural parameter differences between parallel converters, designs a finite-time voltage outer loop tracking controller and a load observer to achieve voltage constancy; designs an integral terminal sliding mode current inner loop controller to achieve the tracking speed and control accuracy of the current loop; designs a finite-time mismatched line impedance differentiator and a fractional-order adaptive controller to achieve current synchronization of a parallel converter system that comprehensively considers mismatched line impedance devices, differences in structural parameters, uncertainty in load caused by temperature rise, and interference factors of actuator failures, thereby improving the system's anti-interference capability and transient performance, solving the current synchronization problem of a multi-converter system during startup and interference application, and ensuring optimal current synchronization performance during the entire operation of the multi-converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] Attached Figure 1 Schematic diagram of the parallel converter system of the present invention.

[0075] Attached Figure 2 It is a simulation diagram comparing the current tracking effect under load switching conditions of the present invention.

[0076] Attached Figure 3 This is a simulation diagram of the BUCK1 / BUCK2 mismatched line impedance under load switching conditions of the present invention.

[0077] Attached Figure 4 It is a simulation diagram comparing current synchronization errors under load switching conditions of the present invention.

[0078] Attached Figure 5 This is a simulation diagram comparing the current tracking effect under the condition of line resistance variation of the present invention.

[0079] Attached Figure 6 This is a simulation diagram of the BUCK1 / BUCK2 mismatched line impedance under the line resistance variation condition of the present invention.

[0080] Attached Figure 7 This is a simulation diagram comparing the current synchronization error under the line resistance variation condition of the present invention.

[0081] Attached Figure 8 It is a simulation diagram comparing the current tracking effect under the aging condition of the actuator of the present invention.

[0082] Attached Fig. 9 This is a simulation diagram of the impedance of the BUCK1 / BUCK2 mismatched lines under the aging condition of the actuator of the present invention.

[0083] Attached Fig.10 It is a simulation diagram comparing the current synchronization error under the aging condition of the actuator of the present invention.

[0084] Numbers in the figure: 1-DC power supply; 2, 3-actuator; 4, 5-freewheeling diode; 6, 7-inductor; 8, 9-unmatched line impedance; 10-capacitor; 11-load; 12-load uncertainty. DETAILED DESCRIPTION

[0085] The present invention will be further described in detail below in conjunction with the accompanying drawings.

[0086] The parallel converter system is shown in the attached Figure 1, specific parameters are as shown in Table 1, DC power supply voltage 50V, BUCK1 inductance 0.012H, BUCK2 inductance 0.013H, load 12Ω, BUCK1 line impedance 0.2Ω, BUCK2 line impedance 0.3Ω, capacitor 0.001F, the following three examples are carried out respectively, namely load switching simulation experiment, line resistance change simulation experiment and actuator aging simulation experiment, to illustrate the effective effect of the present invention.

[0087] Table 1 Parallel converter system parameters

[0088]

[0089] In the load switching simulation experiment, the load size is 12Ω at t = 0 to 2s, 8Ω at t = 2 to 4s, and 12Ω at t = 4 to 6s. Figure 3 The impedance diagram of the BUCK1 / BUCK2 mismatched line under load switching conditions. The designed mismatched line resistance observer can effectively observe the line mismatch value under this condition. Figure 2 The current tracking effect comparison simulation diagram shows that the current synchronization effect of the traditional PID control in the startup and load switching stages is worse than that of the present invention. Figure 4 It can be seen from the current synchronization error comparison simulation diagram that the synchronization error of the traditional PID control startup phase is 0.033A, the startup time is 0.055s, the synchronization error of the load switching phase is 0.095A, and the stabilization time is 0.03s. The synchronization error of the present invention startup phase is 0.3A, the startup time is 0.0035s, the synchronization error of the load switching phase is 0.043A, and the stabilization time is 0.00035s, which verifies that the present invention has a better current synchronization effect when facing load switching and load uncertainty conditions. Detailed performance comparison is shown in Table 2.

[0090] Table 2 Comparison of synchronous performance of changing load current

[0091]

[0092] Line resistance change simulation experiment, line resistance change simulation experiment, t = 0 ~ 2S, BUCK1 line resistance 0.2Ω, BUCK2 line resistance 0.3Ω, t = 2 ~ 4s, BUCK1 line resistance 0.2Ω, BUCK2 line resistance 3.3Ω, t = 4 ~ 6s, BUCK1 line resistance 0.2Ω, BUCK2 line resistance 0.3Ω, according to the attached Figure 6 The impedance diagram of the BUCK1 / BUCK2 mismatched line under the condition of line resistance variation. The designed mismatched line resistance observer can effectively observe the line mismatch value under this condition. Figure 5 The current tracking effect comparison simulation diagram shows that the current synchronization effect of the traditional PID control in the startup and line resistance change stages is worse than that of the present invention. Figure 7It can be seen from the current synchronization error comparison simulation diagram that the synchronization error of the traditional PID control startup phase is 0.34A, the startup time is 0.006s, the synchronization error of the line resistance change phase is 0.19A, and the stabilization time is 0.0028s. The synchronization error of the present invention startup phase is 0.265A, the startup time is 0.0028s, the synchronization error of the load switching phase is 0.005A, and the stabilization time is 0.00012s, which verifies that the present invention has a better current synchronization effect when facing the working condition of mismatched line impedance. Detailed performance comparison is shown in Table 3.

[0093] Table 3 Comparison of current synchronization performance of variable line groups

[0094]

[0095] Actuator aging simulation experiment, t = 0 ~ 2s drive signal d1, d2 normal, t = 2 ~ 4s drive signal d1 normal, drive signal d2 increased by 0.1, t = 4 ~ 6s drive signal d1, d2 normal, according to the attached Fig. 9 The impedance diagram of the BUCK1 / BUCK2 mismatch line under the actuator aging condition. The designed mismatch line resistance observer can effectively observe the line mismatch value under this condition. Figure 8 The current tracking effect comparison simulation diagram shows that the current synchronization effect of the traditional PID control in the startup and actuator aging stages is worse than that of the present invention. Fig.10 It can be seen from the current synchronization error comparison simulation diagram that the synchronization error of the traditional PID control startup phase is 0.34A, the startup time is 0.062s, the synchronization error of the actuator aging phase is 0.122A, and the stabilization time is 0.03s. The synchronization error of the present invention startup phase is 0.2A, the startup time is 0.003s, the synchronization error of the actuator aging phase is 0.05A, and the stabilization time is 0.0001s, which verifies that the present invention has a better current synchronization effect when facing the working condition of actuator aging. Detailed performance comparison is shown in Table 4.

[0096] Table 4 Comparison of actuator aging simulation current synchronization performance

[0097]

Claims

1. A current synchronization control method for parallel converters, characterized in that: The following steps are included: Step 1: Establish a dynamic mathematical model of the parallel converter that comprehensively considers line impedance mismatch, structural parameter differences, actuator aging, and load uncertainty The first step is to calculate the power flowing through the two parallel subsystems according to the lever method: Among them, Υ1 and Υ2 are the powers of the two circuits respectively, U c is the load terminal voltage, are the impedances of the two paths respectively; The second step is to find the circulating power in the parallel circuit of the two parallel converters. Among them, c is the circulating power, μ1 and μ2 are the transformation ratios of the two converters, U in is the input voltage; The third step is to find the actual power flowing through each of the two parallel subsystems: Step 4: The power difference between the two parallel subsystems is Among them, ΔΥ is the power difference between the two parallel circuits, i1 and i2 are the currents of the two circuits respectively, R0 is the nominal load value of the system, and ΔR is the change value of the load during the process of load temperature rise and load shedding; In the fifth step, considering the aging of the actuator, the fault model is Where μ = [μ1 μ2] T is the control input to the actuator, ρ = diag(ρ1, ρ2) and η = [η1 η2] T are the effective coefficient and the uncertain fault part, ρ1 and ρ2 are the effective coefficients of the control inputs of the two loop actuators, and η1 and η2 are the uncertain fault part coefficients of the control inputs of the two loop actuators; Step 6: The power difference between the two converters including actuator aging is The seventh step is to attribute the differences in converter ratio and line structure, actuator aging, and load uncertainty to the voltage input terminal. Among them, d1 and d2 are the control inputs of the two loops respectively, and d1′ and d2′ are the control inputs of the two loops that comprehensively consider the factors affecting the current sharing. To satisfy the actuator signal for current sharing control effect, Δμ, ΔR is the difference between the control input of the two loop actuators, the impedance of the line group, and the uncertainty of the load; In the eighth step, the dynamic mathematical model of the parallel converter is established by comprehensively considering the line impedance mismatch, structural parameter difference, actuator aging and load uncertainty: Where C is the capacitance, are the currents of the two parallel converters, L1 and L2 are the two converter inductors, E is the supply voltage, Θ0 = ΔRU c / CR0(R0+ΔR) is the current uncertainty value caused by load switching. i=1,2 are the uncertain values ​​caused by the aging of the two converter drivers, χ1 and χ2 are the impedance mismatch values ​​of the two converter lines respectively; Step 2, design a load uncertainty observer for the parallel converter; Step 3, designing a finite time voltage outer loop tracking controller for the parallel converter; Step 4: Design a fractional-order integral terminal sliding mode current controller in the current synchronization controller of the parallel converter The first step is to define the current tracking error as Among them, e1 and e2 are the tracking errors of the current in the two converters, i ref It is the output of voltage tracking controller; The second step is to select the integral terminal sliding surface that comprehensively considers the current tracking speed and control accuracy. Among them, s i is the constructed sliding surface, 0<r<1, β>0 are the adjustable controller parameters; The third step is to differentiate the sliding surface of equation (10) to obtain The fourth step is to design a terminal sliding mode reaching law that comprehensively considers chattering suppression and convergence speed: Among them, k,ε>0 are adjustable controller parameters; The fifth step is to design the current inner loop tracking controller by combining equations (8), (11), and (12): Step 5: Design the finite time differentiator for unmatched line resistance and the fractional-order adaptive law for actuator aging in the current synchronous controller of the parallel converter. The first step is to calculate the actuator aging part Θ of equation (13) i ,i=1,2The designed fractional-order adaptive approximation law is in, η1,η2>0,p0,q0>0,0<p0 / q0<1 are adjustable parameters. is the adjustable controller parameter; In the second step, a finite time differentiator is used to solve the line impedance mismatch χ in equation (13). i Estimation acquisition, the ideal estimation model of the parallel converter system is expressed as Combined with equation (8), the mismatch impedance factor can be expressed as The finite time differentiator is designed as follows in, i=1,j=2,i=2,j=1; In the third step, the current tracking controller of the integrated fractional-order adaptive and finite-time differentiator is obtained by combining equation (13): in, are the uncertain values ​​caused by current changes due to temperature rise and load switching, and driver aging, respectively. are the line resistance mismatch values ​​of the two converters respectively.

2. The method for current synchronization control of parallel converters according to claim 1, characterized in that: The load uncertainty observer of the parallel converter in step 2 is designed as: Among them, β1, β2>0, -0.5<τ<0 are adjustable controller parameters.

3. The method for current synchronization control of parallel converters according to claim 1, characterized in that: The finite time voltage outer loop tracking controller of the parallel converter in step 3 is designed as follows: The first step is to define the voltage tracking error and the first-order derivative of the tracking error: Where, e0 is the voltage tracking error; is the reference voltage value; The second step is to design a finite time voltage tracking controller according to equation (20): Among them, k1, k2>0, 0<α1<1 are adjustable controller parameters, is an estimate of Θ0.

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