Method, apparatus, non-transitory computer-readable storage medium, and computer program product for video decoding

Abstract

A method, an apparatus, a non-transitory computer-readable storage medium, and a computer program product for video decoding are provided. The method includes signaling one or more enable flags in a sequence parameter set (SPS) of a picture; selectively signaling a disable flag in a picture header (PH) associated with the picture, wherein the disable flag specifies whether a codec tool is disabled for one or more slices associated with the PH, wherein in response to the disable flag being determined to be not signaled in the PH, the value of the disable flag is inferred from the one or more enable flags signaled in the sequence parameter set (SPS) of the picture.

Description

[0001] This application is a divisional application of the invention application with application number 202180026936.X, application date April 7, 2021, and title “Method and device for signaling syntax elements in video encoding and decoding”. Technical Field

[0002] The present disclosure relates to video coding and compression, and in particular, but not limited to, methods and apparatus for signaling syntax elements in video codecs. Background Art

[0003] Various video codec technologies can be used to compress video data. Video coding is performed according to one or more video coding standards. For example, video coding standards include Versatile Video Codec (VVC), Joint Exploration Test Model (JEM), High Efficiency Video Codec (H.265 / HEVC), Advanced Video Codec (H.264 / AVC), Moving Picture Experts Group (MPEG) codec, etc. Video codecs typically utilize prediction methods (e.g., inter-frame prediction, intra-frame prediction, etc.), which utilize redundancy present in video pictures or sequences. An important goal of video coding technology is to compress video data into a form that uses a lower bit rate while avoiding or minimizing the degradation of video quality. Summary of the invention

[0004] This disclosure provides examples of techniques related to signaling syntax elements in video codecs.

[0005] According to a first aspect of the present disclosure, a method for video coding is provided. The method includes a decoder determining whether a disable flag is present in a picture header (PH) associated with a picture, wherein the disable flag specifies whether a codec tool is disabled in one or more slices associated with the PH. In addition, the method includes: the decoder, in response to determining that the disable flag is not present in the PH, inferring a value of the disable flag based on one or more enable flags signaled in a sequence parameter set (SPS) of the picture.

[0006] According to a second aspect of the present disclosure, a method for video encoding and decoding is provided. The method includes a decoder determining whether a flag is present in a PH associated with a picture, and the flag specifies whether the picture used for temporal motion vector prediction (TMVP) is derived from a reference picture list from a plurality of reference picture lists associated with the picture. In addition, the method includes: the decoder, in response to determining that the flag is not present in the PH, inferring the value of the flag according to the number of reference pictures in the reference picture list.

[0007] According to a third aspect of the present disclosure, a method for video encoding and decoding is provided. The method includes a decoder determining whether there is a flag in a PH associated with a picture, the flag specifying the number of weights signaled in a reference picture list according to a first weighted prediction (WP) flag in a picture parameter set (PPS) of the picture and a second WP flag in the PH of the picture, and the flag is in a WP syntax associated with the picture. In addition, the method includes: the decoder, in response to determining that the flag is not present in the PH, inferring the value of the flag according to the number of reference pictures in a reference picture list from a plurality of reference picture lists associated with the picture.

[0008] According to a fourth aspect of the present disclosure, a method for video coding is provided. The method includes a decoder using an enable flag to specify whether one or more temporal motion vector predictors are used for inter-frame prediction of one or more slices associated with a PH of a picture. In addition, the method includes: the decoder constraining the value of the enable flag according to a plurality of offsets applied to the size of the picture for scaling ratio calculation.

[0009] According to a fifth aspect of the present disclosure, a device for video decoding is provided. The device includes one or more processors and a memory, wherein the memory is configured to store instructions executable by the one or more processors. When executing the instructions, the one or more processors are configured to perform the method for video encoding and decoding according to the first aspect of the present disclosure.

[0010] According to a sixth aspect of the present disclosure, a device for video decoding is provided. The device includes one or more processors and a memory, wherein the memory is configured to store instructions executable by the one or more processors. When executing the instructions, the one or more processors are configured to perform the method for video encoding and decoding according to the second aspect of the present disclosure.

[0011] According to a seventh aspect of the present disclosure, a device for video decoding is provided. The device includes one or more processors and a memory, and the memory is configured to store instructions executable by the one or more processors. When executing the instructions, the one or more processors are configured to perform the method for video encoding and decoding according to the third aspect of the present disclosure.

[0012] According to an eighth aspect of the present disclosure, a device for video decoding is provided. The device includes one or more processors and a memory, wherein the memory is configured to store instructions executable by the one or more processors. When executing the instructions, the one or more processors are configured to perform the method for video encoding and decoding according to the fourth aspect of the present disclosure.

[0013] According to a ninth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer-executable instructions for video decoding is provided. When the instructions are executed by one or more computer processors, the one or more computer processors perform the method for video encoding and decoding according to the first aspect of the present disclosure.

[0014] According to a tenth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer-executable instructions for video decoding is provided. When the instructions are executed by one or more computer processors, the one or more computer processors perform the method for video encoding and decoding according to the second aspect of the present disclosure.

[0015] According to an eleventh aspect of the present disclosure, a non-transitory computer-readable storage medium for video decoding storing computer-executable instructions is provided. When the instructions are executed by one or more computer processors, the one or more computer processors perform the method for video encoding and decoding according to the third aspect of the present disclosure.

[0016] According to a twelfth aspect of the present disclosure, a non-transitory computer-readable storage medium for video decoding storing computer-executable instructions is provided. When the instructions are executed by one or more computer processors, the one or more computer processors perform the method for video encoding and decoding according to the fourth aspect of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] A more particular description of examples of the present disclosure will be presented by reference to specific examples shown in the accompanying drawings. Given that these drawings depict only some examples and are therefore not to be considered limiting in scope, the examples will be described and explained with additional specificity and detail through use of the accompanying drawings.

[0018] Figure 1 is a block diagram illustrating an exemplary video encoder according to some embodiments of the present disclosure.

[0019] Figure 2 is a block diagram illustrating an exemplary video decoder according to some embodiments of the present disclosure.

[0020] Figure 3 An example of a picture divided into multiple coding tree units (CTUs) according to some embodiments of the present disclosure is shown.

[0021] FIG. 4A to FIG. 4D is a schematic diagram illustrating multiple types of tree splitting modes according to some embodiments of the present disclosure.

[0022] Figure 5 is a block diagram illustrating an exemplary apparatus for video encoding and decoding according to some embodiments of the present disclosure.

[0023] Figure 6 is a flowchart illustrating an exemplary process of video encoding and decoding according to some embodiments of the present disclosure.

[0024] Figure 7 is a flowchart illustrating an exemplary process of video encoding and decoding according to some embodiments of the present disclosure.

[0025] Figure 8 is a flowchart illustrating an exemplary process of video encoding and decoding according to some embodiments of the present disclosure.

[0026] Fig. 9 is a flowchart illustrating an exemplary process of video encoding and decoding according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0027] Reference will now be made in detail to specific embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, many non-limiting specific details are set forth to aid in understanding the subject matter presented herein. However, it will be apparent to one of ordinary skill in the art that various alternatives may be used. For example, it will be apparent to one of ordinary skill in the art that the subject matter presented herein may be implemented on many types of electronic devices having digital video capabilities.

[0028] References throughout this specification to "one embodiment," "an embodiment," "an example," "some embodiments," "some examples," or similar language indicate that the particular features, structures, or characteristics being described are included in at least one embodiment or example. Unless explicitly stated otherwise, features, structures, elements, or characteristics described in conjunction with one or some embodiments are also applicable to other embodiments.

[0029] Throughout this disclosure, unless otherwise explicitly stated, the terms "first", "second", "third", etc. are used as nomenclatures for referring to related elements (e.g., devices, components, compositions, steps, etc.) only, without implying any spatial or temporal order. For example, "first device" and "second device" may refer to two separately formed devices, or two parts, components, or operating states of the same device, and may be named arbitrarily.

[0030] The terms "module", "sub-module", "circuit", "sub-circuit", "circuitry", "sub-circuitry", "unit", or "sub-unit" may include a memory (shared, dedicated, or group) that stores code or instructions that can be executed by one or more processors. A module may include one or more circuits with or without stored code or instructions. A module or circuit may include one or more components connected directly or indirectly. These components may or may not be physically attached to or located adjacent to each other.

[0031] As used herein, the terms "if" or "when..." may be understood to mean "upon..." or "in response to...", depending on the context. These terms, if they appear in a claim, may not indicate that the associated limitation or feature is conditional or optional. For example, a method may include the following steps: i) when condition X exists or if condition X exists, function or action X' is performed, and ii) when condition Y exists or if condition Y exists, function or action Y' is performed. The method may be implemented with both the ability to perform function or action X' and the ability to perform function or action Y'. Therefore, both function X' and function Y' may be performed at different times during multiple executions of the method.

[0032] A unit or module may be implemented purely by software, purely by hardware, or by a combination of hardware and software. In a pure software implementation, for example, a unit or module may include functionally related code blocks or software components that are linked together directly or indirectly to perform a specific function.

[0033] Figure 1 A block diagram of an exemplary block-based hybrid video encoder 100 that can be used in conjunction with many video codec standards that use block-based processing is shown. In the encoder 100, a video frame is segmented into multiple video blocks for processing. For each given video block, a prediction is formed based on an inter-frame prediction method or an intra-frame prediction method. In inter-frame prediction, one or more prediction values ​​are formed through motion estimation and motion compensation based on pixels from a previously reconstructed frame. In intra-frame prediction, prediction values ​​are formed based on reconstructed pixels in the current frame. Through mode decision, the best prediction value can be selected to predict the current block.

[0034] The prediction residual, which represents the difference between the current video block and its predicted value, is sent to the transform circuitry 102. The transform coefficients are then sent from the transform circuitry 102 to the quantization circuitry 104 for entropy reduction. The quantized coefficients are then fed to the entropy encoding circuitry 106 to generate a compressed video bitstream. Figure 1As shown, prediction-related information 110 from the inter-frame prediction circuitry and / or the intra-frame prediction circuitry 112, such as video block segmentation information, motion vectors, reference picture indexes, and intra-frame prediction modes, is also fed through the entropy encoding circuitry 106 and saved into a compressed video bitstream 114.

[0035] In encoder 100, decoder related circuitry is also required to reconstruct pixels for prediction purposes. First, the prediction residual is reconstructed by inverse quantization circuitry 116 and inverse transform circuitry 118. This reconstructed prediction residual is combined with block prediction value 120 to generate unfiltered reconstructed pixels for the current video block.

[0036] Intra prediction (also called "spatial prediction") uses pixels from samples of already coded neighboring blocks in the same video picture and / or slice (called reference samples) to predict the current video block. Spatial prediction reduces spatial redundancy inherent in video signals.

[0037] Inter prediction (also called "temporal prediction") uses reconstructed pixels from already coded video pictures to predict the current video block. Temporal prediction reduces the temporal redundancy inherent in video signals. The temporal prediction signal for a given coding unit (CU) or coding block is typically signaled by one or more motion vectors (MVs) that indicate the amount and direction of motion between the current CU and its temporal reference. In addition, if multiple reference pictures are supported, a reference picture index is additionally sent that identifies which reference picture in the reference picture repository the temporal prediction signal comes from.

[0038] After performing spatial and / or temporal prediction, the intra / inter mode decision circuit 121 in the encoder 100 selects the best prediction mode, for example based on a rate-distortion optimization method. The block prediction factor 120 is then subtracted from the current video block; and the resulting prediction residual is decorrelated using the transform circuit 102 and the quantization circuit 104. The resulting quantized residual coefficients are dequantized by the dequantization circuit 116 and inversely transformed by the inverse transform circuit 118 to form a reconstructed residual, which is then added back to the prediction block to form a reconstructed signal for the CU. In addition, loop filtering 115 (such as a deblocking filter, sample adaptive offset (SAO) and / or adaptive loop filter (ALF)) can be applied to the reconstructed CU before placing the reconstructed CU in the reference picture storage of the picture buffer 117 and used to encode and decode future video blocks. In order to form the output video bitstream 114, the coding mode (inter or intra), prediction mode information, motion information, and quantized residual coefficients are all sent to the entropy coding unit 106 to be further compressed and packaged to form a bitstream.

[0039] For example, deblocking filters are available in the current versions of AVC, HEVC, and VVC. In HEVC, an additional loop filter called sample adaptive offset (SAO) is defined to further improve the coding efficiency. In the current version of the VVC standard, another loop filter called adaptive loop filter (ALF) is being actively studied, and it is likely to be included in the final standard.

[0040] These loop filter operations are optional. Performing these operations helps improve codec efficiency and visual quality. As a decision presented by the encoder 100, they can also be turned off to save computational complexity.

[0041] It should be noted that if the encoder 100 turns on these filter options, intra prediction is typically based on unfiltered reconstructed pixels, while inter prediction is based on filtered reconstructed pixels.

[0042] Figure 2 is a block diagram illustrating an exemplary block-based video decoder 200 that can be used in conjunction with many video codec standards. The decoder 200 is similar to the one residing in Figure 1 The decoder 200 first decodes the incoming video bitstream 201 by entropy decoding 202 to derive quantized coefficient levels and prediction related information. The quantized coefficient levels are then processed by inverse quantization 204 and inverse transform 206 to obtain reconstructed prediction residuals. The block prediction value mechanism, which is implemented in the intra / inter mode selector 212, is configured to perform intra prediction 208 or motion compensation 210 based on the decoded prediction information. A set of unfiltered reconstructed pixels is obtained by summing the reconstructed prediction residuals from the inverse transform 206 and the prediction output generated by the block prediction value mechanism using a summer 214.

[0043] The reconstructed block may further pass through a loop filter 209 before being stored in a picture buffer 213 used as a reference picture repository. The reconstructed video in the picture buffer 213 may be sent to drive a display device and used to predict future video blocks. When the loop filter 209 is turned on, a filtering operation is performed on these reconstructed pixels to derive a final reconstructed video output 222.

[0044] The video coding / decoding standards mentioned above, such as VVC, JEM, HEVC, MPEG-4 Part 10, are similar in concept. For example, they all use block-based processing. The following details the block segmentation schemes in some standards.

[0045] Versatile Video Codec (VVC)

[0046] At the 10th JVET meeting held in San Diego, USA, April 10-20, 2018, JVET defined the first draft of the Universal Video Codec (VVC) and the VVC Test Model 1 (VTM1) as its reference software implementation. It was decided to include a quadtree with nested multi-type trees as the initial new codec feature of VVC. The multi-type tree is a coding block partitioning structure that includes both binary splits and ternary splits. Since then, the reference software VTM that implements the encoding and decoding processes has been developed and updated through the following JVET meetings.

[0047] In VVC, pictures of the input video are partitioned into blocks called CTUs. CTUs are split into CUs using a quadtree with a nested multi-type tree structure, where a CU defines an area of ​​pixels that share the same prediction mode (e.g., intra or inter). The term "unit" may define an area of ​​a picture covering all components (such as luminance and chrominance); the term "block" may be used to define an area covering a specific component (e.g., luminance), and blocks of different components (e.g., luminance and chrominance) may be spatially different when considering chrominance sampling formats (such as 4:2:0).

[0048] Split the image into CTUs

[0049] Figure 3 An example of a picture 300 divided into a plurality of CTUs 302 is shown in accordance with some embodiments of the present disclosure.

[0050] A picture can be divided into a sequence of CTUs. The CTU concept is the same as that of HEVC. For a picture with three sample arrays, a CTU consists of an N×N block of luma samples and two corresponding blocks of chroma samples.

[0051] The maximum allowed size of a luma block in a CTU is specified as 128x128 (although the maximum size of a luma transform block is 64x64).

[0052] Use tree structure to split CTU

[0053] In HEVC, a CTU is split into CUs to adapt to various local characteristics using a quadtree structure represented as a coding tree. The decision to encode and decode a picture area using inter-picture (temporal) prediction or intra-picture (spatial) prediction is made at the leaf-CU level. Each leaf-CU can be further split into one, two, or four PUs according to the PU split type. Within a PU, the same prediction process is applied and relevant information is sent to the decoder on a PU basis. After obtaining the residual block by applying the prediction process based on the PU split type, the leaf CU can be partitioned into transform units (TUs) according to another quadtree structure similar to the coding tree for the CU. A key feature of the HEVC structure is that it has multiple partitioning concepts including CU, PU, ​​and TU.

[0054] In VVC, a quadtree with nested multi-type trees using binary split and ternary split partition structures replaces the concept of multiple segmentation unit types. For example, it removes the separation of the concepts of CU, PU, ​​and TU, and supports greater flexibility for CU segmentation shapes, except that CUs with sizes too large for the maximum transform length require this separation. In the coding tree structure, the CU can have a square or rectangular shape. The CTU is first segmented by a quadtree (i.e., quadtree) structure. Then, the quadtree leaf nodes can be further segmented by a multi-type tree structure.

[0055] FIG. 4A to FIG. 4D is a schematic diagram showing a multi-type tree splitting mode according to some embodiments of the present disclosure. FIG. 4A to FIG. 4D As shown in , there are four types of splits in the multi-type tree structure: vertical binary split 402 (SPLIT_BT_VER), horizontal binary split 404 (SPLIT_BT_HOR), vertical ternary split 406 (SPLIT_TT_VER) and horizontal ternary split 408 (SPLIT_TT_HOR). The multi-type tree leaf node is called CU, and unless the CU is too large for the maximum transform length, this partition is used for prediction and transform processing without any further segmentation. This means that in most cases, CU, PU and TU can have the same block size in a quadtree with a nested multi-type tree coding block structure. An exception occurs when the maximum supported transform length is less than the width or height of the color component of the CU.

[0056] Syntax in VVC

[0057] In VVC, the first layer of syntax signaling for the bitstream is the Network Abstraction Layer (NAL), where the bitstream is divided into a set of NAL units. Some NAL units signal common control parameters such as sequence parameter sets (SPS) and picture parameter sets (PPS) to the decoder. Others contain video data. Video Coding Layer (VCL) NAL units contain slices of coded video. A coded picture is called an access unit and can be coded into one or more slices.

[0058] The coded video sequence starts with an instantaneous decoder refresh (IDR) picture. All subsequent video pictures are encoded and decoded as slices. A new IDR picture signals that the previous video segment has ended and a new video segment begins. Each NAL unit starts with a one-byte header, followed by a raw byte sequence payload (RBSP). The RBSP contains the coded slices. Slices are binary coded, so they can be padded with zero bits to ensure that the length is an integer number of bytes. A slice consists of a slice header and slice data. Slice data is specified as a series of CUs.

[0059] The PH concept was adopted in the 16th JVET meeting as the first VCL NAL unit of a picture transmitted once per picture. It was also proposed to group some syntax elements previously in the slice header into the picture header. Syntax elements that functionally only need to be transmitted once per picture can be moved to the picture header instead of being transmitted multiple times in the slice for a given picture.

[0060] In the VVC specification, the syntax table specifies a superset of the syntax of all allowed bitstreams. In other clauses, additional constraints on the syntax may be specified directly or indirectly. Table 1 below is a syntax table for slice headers and picture headers in VVC. The semantics of some syntax are also shown after the syntax table.

[0061] Table 1

[0062]

[0063]

[0064]

[0065]

[0066]

[0067]

[0068]

[0069]

[0070]

[0071] Semantics of the selected syntax elements

[0072] ph_temporal_mvp_enabled_flag specifies whether the temporal motion vector predictor can be used for inter prediction of the slices associated with the PH. If ph_temporal_mvp_enabled_flag is equal to 0, the syntax elements of the slices associated with the PH shall be constrained so that the temporal motion vector predictor is not used in the decoding of the slices. Otherwise, if ph_temporal_mvp_enabled_flag is equal to 1, the temporal motion vector predictor can be used for decoding the slices associated with the PH. When not present, the value of ph_temporal_mvp_enabled_flag is inferred to be equal to 0. The value of ph_temporal_mvp_enabled_flag shall be equal to 0 when no reference picture in the decoded picture buffer (DPB) has the same spatial resolution as the current picture.

[0073] The maximum number of sub-block-based merge MVP candidates, MaxNumSubblockMergeCand, is derived as follows:

[0074] if (SPS_affine_enabled_flag)

[0075] MaxNumSubblockMergeCand=5-five_minus_max_num_subblock_merge_cand

[0076] otherwise

[0077] MaxNumSubblockMergeCand=sps_sbtmvp_enabled_flag&&

[0078] ph_temporal_mvp_enabled_flag;

[0079] The value of MaxNumSubblockMergeCand should be in the range of 0 to 5 (inclusive).

[0080] slice_collocated_from_l0_flag equal to 1 specifies that the co-located picture used for temporal motion vector prediction is derived from reference picture list 0. slice_collocated_from_l0_flag equal to 0 specifies that the co-located picture used for temporal motion vector prediction is derived from reference picture list 1.

[0081] When slice_type is equal to B or P, ph_temporal_mvp_enabled_flag is equal to 1, and slice_collocated_from_l0_flag is not present, the following applies:

[0082] - If rpl_info_in_ph_flag is equal to 1, slice_collocated_from_l0_flag is inferred to be equal to ph_collocated_from_l0_flag.

[0083] - Otherwise (rpl_info_in_ph_flag is equal to 0 and slice_type is equal to P), the value of slice_collocated_from_l0_flag is inferred to be equal to 1.

[0084] slice_collocated_ref_idx specifies the reference index of the co-located picture used for temporal motion vector prediction.

[0085] When slice_type is equal to P or when slice_type is equal to B and slice_collocated_from_l0_flag is equal to 1, slice_collocated_ref_idx refers to the entry in reference picture list 0, and the value of slice_collocated_ref_idx shall be in the range of 0 to NumRefIdxActive[0]-1 (including 0 and NumRefIdxActive[0]-1).

[0086] When slice_type is equal to B and slice_collocated_from_l0_flag is equal to 0, slice_collocated_ref_idx refers to the entry in reference picture list 1, and the value of slice_collocated_ref_idx shall be in the range of 0 to NumRefIdxActive[1]-1 (including 0 and NumRefIdxActive[1]-1).

[0087] When slice_collocated_ref_idx does not exist, the following applies:

[0088] If rpl_info_in_ph_flag is equal to 1, the value of slice_collocated_ref_idx is inferred to be equal to ph_collocated_ref_idx.

[0089] Otherwise (rpl_info_in_ph_flag is equal to 0), the value of slice_collocated_ref_idx is inferred to be equal to 0.

[0090] A requirement for bitstream conformance is that the picture referenced by slice_collocated_ref_idx shall be the same for all slices of a coded picture.

[0091] The bitstream conformance requirement is that the values ​​of pic_width_in_luma_samples and pic_height_in_luma_samples of the reference picture referred to by slice_collocated_ref_idx shall be equal to the values ​​of pic_width_in_luma_samples and pic_height_in_luma_samples of the current picture, respectively, and RprConstraintsActive[slice_collocated_from_l0_flag? 0:1][slice_collocated_ref_idx] shall be equal to 0.

[0092] The value of RprConstraintsActive[i][j] is derived in section 8.3.2 of the VVC specification. The following describes the derivation of the value of RprConstraintsActive[i][j].

[0093] Decoding process for reference picture list construction

[0094] The decoding process for reference picture list construction is called at the beginning of the decoding process for each slice of a non-IDR picture.

[0095] A reference picture is addressed by a reference index. A reference index is an index into a reference picture list. When an I slice is decoded, the reference picture list is not used in the decoding of the slice data. When a P slice is decoded, only reference picture list 0 (i.e., RefPicList[0]) is used in the decoding of the slice data. When a B slice is decoded, only reference picture list 0 and reference picture list 1 (i.e., RefPicList[1]) are used in the decoding of the slice data.

[0096] At the beginning of the decoding process for each slice for non-IDR pictures, reference picture lists RefPicList[0] and RefPicList[1] are derived. The reference picture lists are used to mark reference pictures as specified in the video codec standard or the decoding of slice data.

[0097] For I slices of non-IDR pictures that are not the first slice of the picture, RefPicList[0] and RefPicList[1] may be derived for bitstream consistency checking purposes, but their derivation is not necessary for decoding the current picture or pictures that follow the current picture in decoding order. For P slices that are not the first slice of a picture, RefPicList[1] may be derived for bitstream consistency checking purposes, but its derivation is not necessary for decoding the current picture or pictures that follow the current picture in decoding order.

[0098] The reference picture lists RefPicList[0] and RefPicList[1], the reference picture scaling ratios RefPicScale[i][j][0] and RefPicScale[i][j][1], and the reference picture scaling flags RprConstraintsActive[0][j] and RprConstraintsActive[1][j] are derived as follows:

[0099]

[0100]

[0101]

[0102] scaling_win_left_offset, scaling_win_right_offset, scaling_win_top_offset, and scaling_win_bottom_offset specify offsets applied to the picture dimensions for scaling ratio calculations. When not present, scaling_win_left_offset, scaling_win_right_offset, scaling_win_top_offset, and scaling_win_bottom_offset are inferred to be equal to pps_conf_win_left_offset, pps_conf_win_right_offset, pps_conf_win_top_offset, and pps_conf_win_bottom_offset, respectively.

[0103] The value of SubWidthC×(scaling_win_left_offset+scaling_win_right_offset) should be less than pic_width_in_luma_samples, and the value of SubHeightC×(scaling_win_top_offset+scaling_win_bottom_offset) should be less than pic_height_in_luma_samples.

[0104] The variables PicOutputWidthL and PicOutputHeightL are derived as follows:

[0105] PicOutputWidthL=pic_width_in_luma_samples-SubWidthC×(scaling_win_right_offset+scaling_win_left_offset)

[0106] PicOutputHeightL=pic_height_in_luma_samples-SubWidthC×(scaling_win_bottom_offset+scaling_win_top_offset).

[0107] Let refPicOutputWidthL and refPicOutputHeightL be the PicOutputWidthL and PicOutputHeightL of the reference picture of the current picture that refers to this PPS, respectively. Bitstream conformance requirements satisfy all of the following conditions:

[0108] -PicOutputWidthL×2 should be greater than or equal to refPicWidthInLumaSamples.

[0109] -PicOutputHeightL×2 should be greater than or equal to refPicHeightInLumaSamples.

[0110] -PicOutputWidthL should be less than or equal to refPicWidthInLumaSamples×8.

[0111] -PicOutputHeightL should be less than or equal to refPicHeightInLumaSamples×8.

[0112] - PicOutputWidthL×pic_width_max_in_luma_samples shall be greater than or equal to refPicOutputWidthL×(pic_width_in_luma_samples−Max(8, MinCbSizeY)).

[0113] - PicOutputHeightL×pic_height_max_in_luma_samples shall be greater than or equal to refPicOutputHeightL×(pic_height_in_luma_samples−Max(8, MinCbSizeY)).

[0114] In the current VVC, mvd_l1_zero_flag is signaled in the PH without any conditional constraints. However, the feature controlled by the flag mvd_l1_zero_flag is only applicable when the slice is a bidirectional prediction slice (B slice). Therefore, when the slice associated with the picture header is not a B slice, the flag signaling is redundant.

[0115] In another example, ph_disable_bdof_flag and ph_disable_dmvr_flag are signaled in the PH only when the corresponding enable flags (sps_bdof_pic_present_flag, sps_dmvr_pic_present_flag) signaled in the sequence parameter set (SPS) are true, respectively. However, as shown in Table 2 below, the features controlled by the flags ph_disable_bdof_flag and ph_disable_dmvr_flag are only applicable when the slice is a bidirectional prediction slice (B slice). Therefore, when the slice associated with the picture header is not a B slice, signaling these two flags is redundant or useless.

[0116] Table 2

[0117]

[0118] One or more examples can also be seen on the syntax element ph_collocated_from_l0_flag to indicate that the co-located picture is from list 0 or list 1. And another example can be seen on the syntax pred_weight_table(), which is a syntax element related to weighting tables for bi-directional prediction, as shown below.

[0119] if(ph_temporal_mvp_enabled_flag&&rpl_info_in_ph_flag){ ph_collocated_from_l0_flag

[0120]

[0121]

[0122]

[0123]

[0124] The third issue is associated with the syntax ph_temporal_mvp_enabled_flag. In current VVC, because the resolution of the co-located picture selected for TMVP derivation should be the same as the resolution of the current picture, there is a bitstream conformance constraint for checking the value of ph_temporal_mvp_enabled_flag, as shown below.

[0125] When there is no reference picture in the DPB with the same spatial resolution as the current picture, the value of ph_temporal_mvp_enabled_flag shall be equal to 0.

[0126] However, in the current VVC, not only the resolution of the co-located picture will affect the enabling of TMVP, but also the offset applied to the picture size for scaling ratio calculation. However, in the current VVC, the offset is not considered in the bitstream consistency of ph_temporal_mvp_enabled_flag.

[0127] Furthermore, there is a requirement for bitstream conformance that the picture referenced by slice_collocated_ref_idx should be the same for all slices of a coded picture. However, this bitstream conformance cannot be met when a coded picture has multiple slices and there is no common reference picture between all these slices. And in this case, ph_temporal_mvp_enabled_flag should be constrained to 0.

[0128] Several methods are proposed to solve the above problems. The proposed methods can be applied independently or in combination.

[0129] Since the features controlled by the flags mvd_l1_zero_flag, ph_disable_bdof_flag, and ph_disable_dmvr_flag are applicable only when the slice is a bidirectionally predicted slice (B slice), according to the method of the present disclosure, it is proposed to signal these flags only when the associated slice is a B slice. Note that when a reference picture list is signaled in PH (e.g., rpl_info_in_ph_flag=1), this means that all slices of the coded picture use the same reference picture signaled in PH. Therefore, when a reference picture list is signaled in PH and the signaled reference picture list indicates that the current picture is not bidirectionally predicted, the flags mvd_l1_zero_flag, ph_disable_bdof_flag, and ph_disable_dmvr_flag do not need to be signaled.

[0130] In some examples, some conditions are added to those syntaxes set in the PH to prevent redundant signaling or undefined decoding behavior due to incorrect values ​​sent for some syntaxes in the picture header. Some examples are shown below, where the variable num_ref_entries[i][RplsIdx[i]] represents the number of reference pictures in list i.

[0131] In some examples, the conditions may be as follows:

[0132] if (rpl_info_in_ph_flag&&num_ref_entries[0][RplsIdx[0]]>1&&num_ref_entries[1][RplsIdx[1]]>1)

[0133] mvd_l1_zero_flag

[0134] In some examples, the conditions may be as follows:

[0135] if (!rpl_info_in_ph_flag||(rpl_info_in_ph_flag&&num_ref_entries[0][RplsIdx[0]]>1&&num_ref_entries[1][RplsIdx[1]]>1))

[0136] mvd_l1_zero_flag

[0137] In some examples, the conditions may be as follows:

[0138] if (!rpl_info_in_ph_flag||(rpl_info_in_ph_flag&&num_ref_entries[0][RplsIdx[0]]>0&&num_ref_entries[1][RplsIdx[1]]>0)

[0139] mvd_l1_zero_flag

[0140] Alternatively, the condition can be rewritten in a more compact form that gives the same result. Since a bidirectionally predicted slice (B slice) or a bidirectionally predicted picture must have at least one list 1 reference picture, it can only check whether the current slice / picture has a list 1 reference picture. An example of an alternative conditional check is shown below:

[0141] if(!rpl_info_in_ph_flag||(rpl_info_in_ph_flag&&num_ref_entries[1][RplsIdx[1]]>0))

[0142] mvd_l1_zero_flag

[0143] The semantics of mvd_l1_zero_flag has also been modified to handle the case where it is not signaled.

[0144] mvd_l1_zero_flag equal to 1 indicates that the mvd_coding(x0, y0, 1) syntax structure is not parsed, and MvdL1[x0][y0][compIdx] and MvdCpL1[x0][y0][cpIdx][compIdx] are set equal to 0, where compIdx=0..1 and cpIdx=0..2. mvd_l1_zero_flag equal to 0 indicates that the mvd_coding(x0, y0, 1) syntax structure is parsed. When not present, the value of mvd_l1_zero_flag is inferred to be 0.

[0145] Several examples of conditionally signaling the syntax element ph_disable_dmvr_flag are shown below:

[0146] if(sps_dmvr_pic_present_flag&&rpl_info_in_ph_flag&&num_ref_entries[0][RplsIdx[0]]>1&&num_ref_entries[1][RplsIdx[1]]>1)

[0147] ph_disable_dmvr_flag

[0148] or if (sps_dmvr_pic_present_flag&&(!rpl_info_in_ph_flag||(rpl_info_in_ph_flag&&num_ref_entries[0][RplsIdx[0]]>1&&num_ref_entries[1][RplsIdx[1]]>1)))

[0149] ph_disable_dmvr_flag

[0150] or if (sps_dmvr_pic_present_flag&&(!rpl_info_in_ph_flag||(rpl_info_in_ph_flag&&num_ref_entries[0][RplsIdx[0]]>0&&num_ref_entries[1][RplsIdx[1]]>0)))

[0151] ph_disable_dmvr_flag

[0152] Another example of an alternative conditional check is shown below:

[0153] if (sps_dmvr_pic_present_flag&&(!rpl_info_in_ph_flag||(rpl_info_in_ph_flag&&num_ref_entries[1][RplsIdx[1]]>0)))

[0154] ph_disable_dmvr_flag

[0155] The semantics of ph_disable_dmvr_flag has also been modified to handle the case where it is not signaled.

[0156] ph_disable_dmvr_flag equal to 1 specifies that inter bi-prediction based on decoder motion vector refinement is disabled in slices associated with the PH. ph_disable_dmvr_flag equal to 0 specifies that inter bi-prediction based on decoder motion vector refinement may or may not be enabled in slices associated with the PH.

[0157] When ph_disable_dmvr_flag is not present, the following applies:

[0158] - If sps_dmvr_enabled_flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 0, then the value of ph_disable_dmvr_flag is inferred to be equal to 0.

[0159] - Otherwise, if sps_dmvr_enabled_flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 1, then the value of ph_disable_dmvr_flag is inferred to be equal to 1.

[0160] - Otherwise (sps_dmvr_enabled_flag is equal to 0), the value of ph_disable_dmvr_flag is inferred to be equal to 1.

[0161] Another example of deriving the value of ph_disable_dmvr_flag when ph_disable_dmvr_flag is not present is shown below:

[0162] If and when the value of ph_disable_dmvr_flag is explicitly signaled or implicitly derived, all conditions are considered for deriving the value of ph_disable_dmvr_flag:

[0163] - If sps_dmvr_enabled_flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 0, then the value of ph_disable_dmvr_flag is inferred to be equal to 0.

[0164] - Otherwise, if sps_dmvr_enabled_flag is equal to 0 and sps_dmvr_pic_present_flag is equal to 0, then the value of ph_disable_dmvr_flag is inferred to be equal to 1.

[0165] - Otherwise, if sps_dmvr_enabled_flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 0, then the value of ph_disable_dmvr_flag is inferred to be equal to X (X is explicitly signaled).

[0166] - Otherwise, if sps_dmvr_enabled_flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[1][RplsIdx[1]]>0, then the value of ph_disable_dmvr_flag is inferred to be equal to X (X is explicitly signaled).

[0167] Otherwise (sps_dmvr_enabled_flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[1][RplsIdx[1]]==0), the value of ph_disable_dmvr_flag is inferred to be equal to 1.

[0168] Since the syntax element ph_disable_dmvr_flag is explicitly signaled in the third and fourth conditions, this syntax element may be removed from the derivation of ph_disable_dmvr_flag when ph_disable_dmvr_flag is not present.

[0169] When ph_disable_dmvr_flag is not present, the following applies:

[0170] - If sps_dmvr_enabled_flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 0, then the value of ph_disable_dmvr_flag is inferred to be equal to 0.

[0171] - Otherwise, if sps_dmvr_enabled_flag is equal to 0 and sps_dmvr_pic_present_flag is equal to 0, then the value of ph_disable_dmvr_flag is inferred to be equal to 1.

[0172] Otherwise (sps_dmvr_enabled_flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[1][RplsIdx[1]]==0), the value of ph_disable_dmvr_flag is inferred to be equal to 1.

[0173] The conditions can be simplified editorially as follows:

[0174] When ph_disable_dmvr_flag is not present, the following applies:

[0175] - If sps_dmvr_enabled_flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 0, then the value of ph_disable_dmvr_flag is inferred to be equal to 0.

[0176] - Otherwise (sps_dmvr_enabled_flag is equal to 0 or sps_dmvr_pic_present_flag is equal to 1), the value of ph_disable_dmvr_flag is inferred to be equal to 1.

[0177] Another example of deriving the value of ph_disable_dmvr_flag when ph_disable_dmvr_flag is not present is shown below:

[0178] When ph_disable_dmvr_flag is not present, the following applies:

[0179] - If sps_dmvr_pic_present_flag is equal to 0, then the value of ph_disable_dmvr_flag is inferred to be equal to 1 - sps_dmvr_enabled_flag.

[0180] - Otherwise, if sps_dmvr_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 0, then the value of ph_disable_dmvr_flag is inferred to be equal to 1-sps_dmvr_enabled_flag.

[0181] - Otherwise, if sps_dmvr_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[1][RplsIdx[1]]>0, then the value of ph_disable_dmvr_flag is inferred to be equal to 1-sps_dmvr_enabled_flag.

[0182] Otherwise (sps_dmvr_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[1][RplsIdx[1]]==0), the value of ph_disable_dmvr_flag is inferred to be equal to 1.

[0183] In some examples, because the syntax element ph_disable_dmvr_flag is explicitly signaled under the second and third conditions above, the syntax element may be removed from the derivation of ph_disable_dmvr_flag when it is not present.

[0184] In some examples, when ph_disable_dmvr_flag is not present, the following applies: if sps_dmvr_pic_present_flag is equal to 0, then the value of ph_disable_dmvr_flag is inferred to be equal to 1-sps_dmvr_enabled_flag; otherwise, the value of ph_disable_dmvr_flag is inferred to be equal to 1.

[0185] Several examples of conditionally signaling the syntax element ph_disable_bdof_flag are shown below:

[0186] if(sps_bdof_pic_present_flag&&rpl_info_in_ph_flag&&num_ref_entries[0][RplsIdx[0]]>1&&nu m_ref_entries[1][RplsIdx[1]]>1)

[0187] ph_disable_bdof_flag

[0188] or if (sps_bdof_pic_present_flag&&(!rpl_info_in_ph_flag||(rpl_info_in_ph_flag&&num_ref_entries[0][RplsIdx[0]]>1&&num_ref_entries[1][RplsIdx[1]]>1)))

[0189] ph_disable_bdof_flag

[0190] In some examples, examples of alternative condition checks are shown below:

[0191] if (sps_bdof_pic_present_flag&&(!rpl_info_in_ph_flag||(rpl_info_in_ph_flag&&num_ref_entries[1][RplsIdx[1]]>0)))

[0192] ph_disable_bdof_flag

[0193] The semantics of ph_disable_bdof_flag has also been modified to handle the case where no signaling is done.

[0194] ph_disable_bdof_flag equal to 1 specifies that inter bi-prediction based on bi-directional optical flow inter prediction is disabled in slices associated with the PH. ph_disable_bdof_flag equal to 0 specifies that inter bi-prediction based on bi-directional optical flow inter prediction may or may not be enabled in slices associated with the PH.

[0195] When ph_disable_bdof_flag is not present, the following applies:

[0196] - If sps_bdof_enabled_flag is equal to 1 and sps_bdof_pic_present_flag is equal to 0, the value of ph_disable_bdof_flag is inferred to be equal to 0.

[0197] - Otherwise, if sps_bdof_enabled_flag is equal to 1 and sps_bdof_pic_present_flag is equal to 1, then the value of ph_disable_dmvr_flag is inferred to be equal to 1.

[0198] - Otherwise (sps_bdof_enabled_flag is equal to 0), the value of ph_disable_bdof_flag is inferred to be equal to 1.

[0199] An alternative way of deriving the value of ph_disable_bdof_flag when ph_disable_bdof_flag is not present is shown below:

[0200] If and when the value of ph_disable_bdof_flag is explicitly signaled or implicitly derived, all conditions are considered for deriving the value of ph_disable_bdof_flag:

[0201] - If sps_bdof_enabled_flag is equal to 1 and sps_bdof_pic_present_flag is equal to 0, the value of ph_disable_bdof_flag is inferred to be equal to 0.

[0202] - Otherwise, if sps_bdof_enabled_flag is equal to 0 and sps_bdof_pic_present_flag is equal to 0, then the value of ph_disable_bdof_flag is inferred to be equal to 1.

[0203] - Otherwise, if sps_bdof_enabled_flag is equal to 1 and sps_bdof_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 0, then the value of ph_disable_bdof_flag is inferred to be equal to X (X is explicitly signaled).

[0204] - Otherwise, if sps_bdof_enabled_flag is equal to 1 and sps_bdof_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[1][RplsIdx[1]]>0, then the value of ph_disable_bdof_flag is inferred to be equal to X (X is explicitly signaled).

[0205] - Otherwise (sps_bdof_enabled_flag is equal to 1 and sps_bdof_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[1][RplsIdx[1]]==0), the value of ph_disable_bdof_flag is inferred to be equal to 1.

[0206] Since the syntax element ph_disable_bdof_flag is explicitly signaled in the third and fourth conditions, this syntax element may be removed from the derivation of ph_disable_bdof_flag when it is not present:

[0207] When ph_disable_bdof_flag is not present, the following applies:

[0208] - If sps_bdof_enabled_flag is equal to 1 and sps_bdof_pic_present_flag is equal to 0, the value of ph_disable_bdof_flag is inferred to be equal to 0.

[0209] - Otherwise, if sps_bdof_enabled_flag is equal to 0 and sps_bdof_pic_present_flag is equal to 0, then the value of ph_disable_bdof_flag is inferred to be equal to 1.

[0210] - Otherwise (sps_bdof_enabled_flag is equal to 1 and sps_bdof_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[1][RplsIdx[1]]==0), the value of ph_disable_bdof_flag is inferred to be equal to 1.

[0211] The conditions can be simplified editorially as follows:

[0212] When ph_disable_bdof_flag is not present, the following applies:

[0213] - If sps_bdof_enabled_flag is equal to 1 and sps_bdof_pic_present_flag is equal to 0, the value of ph_disable_bdof_flag is inferred to be equal to 0.

[0214] - Otherwise (sps_bdof_enabled_flag is equal to 0 or sps_bdof_pic_present_flag is equal to 1), the value of ph_disable_bdof_flag is inferred to be equal to 1.

[0215] Another alternative way to derive the value of ph_disable_bdof_flag when it is not present is shown below:

[0216] When ph_disable_bdof_flag is not present, the following applies:

[0217] - If sps_bdof_pic_present_flag is equal to 0, then the value of ph_disable_bdof_flag is inferred to be equal to 1 - sps_bdof_enabled_flag.

[0218] - Otherwise, if sps_bdof_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 0, then the value of ph_disable_bdof_flag is inferred to be equal to 1-sps_bdof_enabled_flag.

[0219] - Otherwise, if sps_bdof_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[1][RplsIdx[1]]>0, then the value of ph_disable_bdof_flag is inferred to be equal to 1-sps_bdof_enabled_flag.

[0220] Otherwise (sps_bdof_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[1][RplsIdx[1]]==0), the value of ph_disable_bdof_flag is inferred to be equal to 1.

[0221] In some examples, because the syntax element ph_disable_bdof_flag is explicitly signaled in the second and third conditions, the syntax element may be removed from the derivation of ph_disable_bdof_flag when it is not present.

[0222] When ph_disable_bdof_flag is not present, the following applies:

[0223] - If sps_bdof_pic_present_flag is equal to 0, then the value of ph_disable_bdof_flag is inferred to be equal to 1 - sps_bdof_enabled_flag.

[0224] - Otherwise, the value of ph_disable_bdof_flag is inferred to be equal to 1.

[0225] Furthermore, the signaling conditions of the syntax elements ph_collocated_from_l0_flag and weight_table() are modified because both types of syntax elements are applicable only when the associated slice is a B slice. An example of the modified syntax element signaling is shown below.

[0226]

[0227] or

[0228]

[0229] The semantics of ph_collocated_from_l0_flag is also modified to handle the case when it is not signaled.

[0230] ph_collocated_from_l0_flag equal to 1 specifies that the co-located picture used for temporal motion vector prediction is derived from reference picture list 0. ph_collocated_from_l0_flag equal to 0 specifies that the co-located picture used for temporal motion vector prediction is derived from reference picture list 1.

[0231] When ph_collocated_from_l0_flag is not present, the following applies:

[0232] - If num_ref_entries[0][RplsIdx[0]] is greater than 1, the value of ph_collocated_from_l0_flag is inferred to be 1.

[0233] - Otherwise (num_ref_entries[1][RplsIdx[1]] is greater than 1), the value of ph_collocated_from_l0_flag is inferred to be 0.

[0234]

[0235]

[0236]

[0237] Similarly, an example of an alternative conditional check is shown below:

[0238] if (pps_weighted_bipred_flag&&wp_info_in_ph_flag&&(!rpl_info_in_ph_flag||(rpl_info_in_ph_flag&&num_ref_entries[1][RplsIdx[1]]>0)))

[0239] num_l1_weights

[0240] The semantics of the syntax elements in pred_weight_table() are also modified to handle the case when the syntax element is not signaled.

[0241] num_l1_weights specifies the number of weights signaled for entries in reference picture list 1 when pps_weighted_bipred_flag and wp_info_in_ph_flag are both equal to 1. The value of num_l1_weights shall be in the range of 0 to Min(15, num_ref_entries[1][RplsIdx[1]]), inclusive.

[0242] The variable NumWeightsL1 is derived as follows:

[0243] if (!pps_weighted_bipred_flag)

[0244] NumWeightsL1=0

[0245] else if (wp_info_in_ph_flag && rpl_info_in_ph_flag && (num_ref_entries[0][RplsIdx[0]] == 0 || num_ref_entries[1][RplsIdx[1]] > == 0))

[0246] NumWeightsL1=0

[0247] else if (wp_info_in_ph_flag)

[0248] NumWeightsL1 = num_l1_weights

[0249] otherwise

[0250] NumWeightsL1=NumRefIdxActive[1]

[0251] In the semantics of the syntax element in pred_weight_table(), an alternative way of deriving the value of num_l1_weights when num_l1_weights is not present is shown below:

[0252] num_l1_weights specifies the number of weights signaled for entries in reference picture list 1 when pps_weighted_bipred_flag and wp_info_in_ph_flag are both equal to 1. The value of num_l1_weights shall be in the range of 0 to Min(15, num_ref_entries[1][RplsIdx[1]]), inclusive. When not present, the value of num_l1_weights is inferred to be 0.

[0253] The variable NumWeightsL1 is derived as follows:

[0254] if (!pps_weighted_bipred_flag)

[0255] NumWeightsL1=0

[0256] else if (wp_info_in_ph_flag)

[0257] NumWeightsL1 = num_l1_weights

[0258] otherwise

[0259] NumWeightsL1=NumRefIdxActive[1]

[0260] In the semantics of the syntax element in pred_weight_table(), another alternative way to derive the value of num_l1_weights when num_l1_weights is not present is shown as follows:

[0261] if (!pps_weighted_bipred_flag||(wp_info_in_ph_flag&&num_ref_entries[1][RplsIdx[1]]===0))

[0262] NumWeightsL1=0

[0263] else if (wp_info_in_ph_flag)

[0264] NumWeightsL1 = num_l1_weights

[0265] otherwise

[0266] NumWeightsL1=NumRefIdxActive[1]

[0267] Conceptually, for any syntax element applicable only to B slices, it is proposed to add a signaling condition to check whether the current picture has reference pictures from both list 0 and list 1 reference picture lists to avoid signaling redundant bits. The checking condition is not limited to the above-mentioned method for checking the size of two reference picture lists (e.g., list 0 / list 1 reference picture lists), and the checking condition may be any other method for indicating whether the current picture has reference pictures from both list 0 and list 1 reference picture lists. For example, a flag may be signaled to indicate whether the current picture has both list 0 and list 1 reference pictures.

[0268] When the syntax element is not signaled and the reference picture list information is signaled in the picture header (PH), the value of the syntax element is derived using information whether the current picture has both table 0 and list 1 reference pictures or it has only table 0 reference pictures or list 1 reference pictures. In one example, when ph_collocated_from_l0_flag is not signaled, its value is inferred to be the only reference picture that the current picture has. In another example, when sps_bdof_enabled_flag is equal to 1 and sps_bdof_pic_present_flag is equal to 1 but ph_disable_bdof_flag is not signaled, it implies that num_ref_entries[0][RplsIdx[0]] is equal to 0 or num_ref_entries[1][rplsidx[1]] is equal to 0 according to the proposed signaling conditions for ph_disable_bdof_flag. Therefore, in this condition, ph_disable_bdof_flag is not signaled and is inferred to be 1. In the current VVC, not only the resolution of the co-located picture can affect the enabling of TMVP, but also the offset applied to the picture size for scaling ratio calculation can affect the enabling of TMVP. However, in the current VVC, the offset is not considered in the bitstream consistency of ph_temporal_mvp_enabled_flag. In a second embodiment, it is proposed to add a bitstream consistency constraint to the current VVC, which requires that the value of ph_temporal_mvp_enabled_flag should depend on the offset applied to the picture size for scaling ratio calculation, as shown below.

[0269] The value of ph_temporal_mvp_enabled_flag shall be equal to 0 when there is no reference picture in the DPB having the same spatial resolution as the current picture and the same offset applied to the picture size for scaling ratio calculation.

[0270] The above semantics can also be written in another way as follows:

[0271] The value of ph_temporal_mvp_enabled_flag shall be equal to 0 when the reference picture in the DPB does not have the associated variable value RprConstraintsActive[i][j] equal to 0.

[0272] In the current VVC, there is a requirement for bitstream consistency: the picture referenced by slice_collocated_ref_idx should be the same for all slices of the coded picture. However, when the coded picture has multiple slices and there is no common reference picture between all these slices, this bitstream consistency cannot be met. In the third embodiment of the present disclosure, the requirement for bitstream consistency of ph_temporal_mvp_enabled_flag is modified to take into account whether there is a common reference picture between all slices in the current picture. Based on this embodiment, several exemplary modifications to the VVC specification are shown below.

[0273] ph_temporal_mvp_enabled_flag specifies whether the temporal motion vector predictor can be used for inter prediction of the slices associated with the PH. If ph_temporal_mvp_enabled_flag is equal to 0, the syntax elements of the slices associated with the PH shall be constrained so that the temporal motion vector predictor is not used in the decoding of the slices. Otherwise (ph_temporal_mvp_enabled_flag is equal to 1), the temporal motion vector predictor can be used for decoding the slices associated with the PH. When not present, the value of ph_temporal_mvp_enabled_flag is inferred to be equal to 0. The value of ph_temporal_mvp_enabled_flag shall be equal to 0 when no reference picture in the DPB has the same spatial resolution as the current picture. The value of ph_temporal_mvp_enabled_flag shall be equal to 0 when there is no common reference picture in all slices associated with the PH.

[0274] ph_temporal_mvp_enabled_flag specifies whether the temporal motion vector predictor can be used for inter prediction of the slices associated with the PH. If ph_temporal_mvp_enabled_flag is equal to 0, the syntax elements of the slices associated with the PH shall be constrained so that the temporal motion vector predictor is not used in the decoding of the slices. Otherwise (ph_temporal_mvp_enabled_flag is equal to 1), the temporal motion vector predictor can be used for decoding the slices associated with the PH. When not present, the value of ph_temporal_mvp_enabled_flag is inferred to be equal to 0. The value of ph_temporal_mvp_enabled_flag shall be equal to 0 when no reference picture in the DPB has the same spatial resolution as the current picture. The value of ph_temporal_mvp_enabled_flag shall be equal to 0 when there is no common reference picture among all inter slices associated with the PH.

[0275] ph_temporal_mvp_enabled_flag specifies whether the temporal motion vector predictor can be used for inter prediction of the slices associated with the PH. If ph_temporal_mvp_enabled_flag is equal to 0, the syntax elements of the slices associated with the PH shall be constrained so that the temporal motion vector predictor is not used in the decoding of the slices. Otherwise (ph_temporal_mvp_enabled_flag is equal to 1), the temporal motion vector predictor can be used for decoding the slices associated with the PH. When not present, the value of ph_temporal_mvp_enabled_flag is inferred to be equal to 0. The value of ph_temporal_mvp_enabled_flag shall be equal to 0 when no reference picture in the DPB has the same spatial resolution as the current picture. The value of ph_temporal_mvp_enabled_flag shall be equal to 0 when there is no common reference picture among all non-intra slices associated with the PH.

[0276] In one example, the bitstream conformance with respect to slice_collocated_ref_idx is simplified as follows:

[0277] The bitstream conformance requirement is that the values ​​of pic_width_in_luma_samples and pic_height_in_luma_samples of the reference picture referred to by slice_collocated_ref_idx shall be equal to the values ​​of pic_width_in_luma_samples and pic_height_in_luma_samples of the current picture, respectively, and RprConstraintsActive[slice_collocated_from_l0_flag? 0:1][slice_collocated_ref_idx] shall be equal to 0.

[0278] The above method can be implemented using an apparatus including one or more circuits, including an application specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a controller, a microcontroller, a microprocessor or other electronic components. The apparatus can use the circuit in combination with other hardware or software components to perform the above method. Each module, submodule, unit or subunit disclosed above can be implemented at least in part using one or more circuits.

[0279] In the current VVC specification, we have two bitstream conformances for the restriction of the resolution of co-located pictures. One is proposed for ph_temporal_mvp_enabled_flag, and the other is proposed for the bitstream conformance regarding slice_collocated_ref_idx. However, in the VVC specification, having two bitstream conformances is redundant in terms of functionality because they both prohibit the use of co-located pictures with different resolutions and / or different scaling offsets than the current picture. In order to reduce the burden on the encoder to check bitstream consistency, in the fifth embodiment, it is recommended to apply only the bitstream conformance slice_collocated_ref_idx. An example of the revised specification of VVC is shown below. The changed parts are highlighted.

[0280]

[0281] In one example, it is proposed to apply only the bitstream conformance ph_temporal_mvp_enabled_flag. An example of a revised specification of VVC is shown below.

[0282]

[0283] Figure 55 is a block diagram showing an exemplary apparatus for video encoding and decoding according to some embodiments of the present disclosure. Apparatus 500 may be a terminal, such as a mobile phone, a tablet computer, a digital broadcast terminal, a tablet device, or a personal digital assistant.

[0284] like Figure 5 As shown, device 500 may include one or more of the following components: processing component 502, memory 504, power component 506, multimedia component 508, audio component 510, input / output (I / O) interface 512, sensor component 514 and communication component 516.

[0285] The processing component 502 generally controls the overall operation of the device 500, such as operations related to display, phone calls, data communications, camera operations, and recording operations. The processing component 502 may include one or more processors 1020 for executing instructions to perform all or part of the steps of the above method. In addition, the processing component 502 may include one or more modules to facilitate interaction between the processing component 502 and other components. For example, the processing component 502 may include a multimedia module to facilitate interaction between the multimedia component 508 and the processing component 502.

[0286] The memory 504 is configured to store different types of data to support the operation of the device 500. Examples of such data include instructions for any application or method operating on the device 500, contact data, phone book data, messages, pictures, videos, etc. The memory 504 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, and the memory 504 can be a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, a magnetic disk, or a compact disk.

[0287] The power supply component 506 provides power to the various components of the device 500. The power supply component 506 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the device 500.

[0288] The multimedia component 508 includes a screen that provides an output interface between the device 500 and the user. In some examples, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen that receives input signals from the user. The touch panel may include one or more touch sensors for sensing touches, slides, and gestures on the touch panel. The touch sensor can not only sense the boundaries of a touch action or a slide action, but also detect the duration and pressure associated with the touch operation or the slide operation. In some examples, the multimedia component 508 may include a front camera and / or a rear camera. When the device 500 is in an operating mode (such as a shooting mode or a video mode), the front camera and / or the rear camera may receive external multimedia data.

[0289] The audio component 510 is configured to output and / or input audio signals. For example, the audio component 510 includes a microphone (MIC). When the device 500 is in an operating mode (such as a call mode, a recording mode, and a speech recognition mode), the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 504 or sent via the communication component 516. In some examples, the audio component 510 also includes a speaker for outputting an audio signal.

[0290] I / O interface 512 provides an interface between processing component 502 and peripheral interface modules. The above peripheral interface modules can be keyboards, click wheels, buttons, etc. These buttons can include but are not limited to home buttons, volume buttons, start buttons, and lock buttons.

[0291] Sensor assembly 514 includes one or more sensors for providing status assessment in different aspects of device 500. For example, sensor assembly 514 can detect the on / off state of device 500 and the relative position of components. For example, the components are the display and keyboard of device 500. Sensor assembly 514 can also detect position changes of device 500 or components of device 500, the presence or absence of user contact on device 500, the direction or acceleration / deceleration of device 500, and temperature changes of device 500. Sensor assembly 514 can include a proximity sensor, which is configured to detect the presence of nearby objects without any physical contact. Sensor assembly 514 can also include an optical sensor, such as a CMOS or CCD image sensor used in imaging applications. In some examples, sensor assembly 514 can also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0292] The communication component 516 is configured to facilitate wired or wireless communication between the device 500 and other devices. The device 500 can access the wireless network based on communication standards such as WiFi, 4G or a combination thereof. In one example, the communication component 516 receives broadcast signals or broadcast related information from an external broadcast management system via a broadcast channel. In one example, the communication component 516 may also include a near field communication (NFC) module for facilitating short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0293] In one example, the apparatus 500 may be implemented by one or more of an application specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a controller, a microcontroller, a microprocessor, or other electronic components to perform the above method.

[0294] The non-transitory computer-readable storage medium may be, for example, a hard disk drive (HDD), a solid-state drive (SSD), a flash memory, a hybrid drive or a solid-state hybrid drive (SSHD), a read-only memory (ROM), a compact disk-read-only memory (CD-ROM), a tape, a floppy disk, etc.

[0295] Figure 6 is a flowchart illustrating an exemplary process of video encoding and decoding according to some embodiments of the present disclosure.

[0296] In step 602, the processor 520 determines whether a disable flag exists in the PH associated with the picture.

[0297] In some examples, the disable flag specifies whether to disable the codec tool in one or more slices associated with the PH.

[0298] In step 604, the processor 520, in response to determining that the disable flag is not present in the PH, infers a value of the disable flag from one or more enable flags signaled in the SPS of the picture.

[0299] In some examples, processor 520 disables the codec tool when decoding one or more slices in response to determining that the value of the disable flag is equal to 1, and enables the codec tool when decoding one or more slices in response to determining that the value of the disable flag is equal to 0.

[0300] In some examples, the codec tool includes at least one of DMVR-based inter-frame bi-directional prediction and BDOF-based inter-frame bi-directional prediction.

[0301] In some examples, processor 520 skips parsing of the disable flag in response to determining that one or more reference picture lists indicate that one or more slices associated with the picture are not bi-predicted.

[0302] In some examples, the disable flag specifies whether to disable DMVR-based inter-frame bi-directional prediction in one or more slices associated with the PH, the processor 520 disables the codec tool when decoding the one or more slices by disabling DMVR-based inter-frame bi-directional prediction when decoding the one or more slices, and the processor 520 enables the codec tool when decoding the one or more slices by enabling DMVR-based inter-frame bi-directional prediction when decoding the one or more slices.

[0303] In some examples, in response to determining to skip parsing of a disable flag, the processor 520 infers the value of the disable flag based on one or more enable flags signaled in the SPS of the picture by performing the following operations: in response to determining that a first enable flag in the SPS is equal to 1 and a second enable flag in the SPS is equal to 0, inferring that the value of the disable flag is 0.

[0304] In some examples, a first enable flag in the SPS specifies whether DMVR-based inter-frame bidirectional prediction is enabled, the first enable flag equal to 1 specifies enabling DMVR-based inter-frame bidirectional prediction, and the first enable flag equal to 0 specifies disabling DMVR-based inter-frame bidirectional prediction.

[0305] In some examples, a second enable flag in the SPS specifies whether a disable flag exists in the PH of the reference SPS, the second enable flag equal to 0 specifies that a disable flag does not exist in the PH of the reference SPS, and the second enable flag equal to 1 specifies that a disable flag exists in the PH of the reference SPS.

[0306] In some examples, the processor 520, in response to determining to skip parsing of the disable flag, infers the value of the disable flag based on one or more enable flags signaled in the SPS of the picture by performing the following operations: in response to determining that a first enable flag in the SPS is equal to 1 and a second enable flag in the SPS is equal to 1, inferring the value of the disable flag to be 1, and in response to determining that the first enable flag in the SPS is equal to 0, inferring the value of the disable flag to be 1.

[0307] In some examples, processor 520, in response to determining to skip parsing of the disable flag, infers a value of the disable flag from one or more enable flags signaled in an SPS for the picture by: in response to determining that a first enable flag in the SPS is equal to 0 and a second enable flag in the SPS is equal to 0, inferring that the disable flag is 1, and in response to determining that the first enable flag in the SPS is equal to 1, the second enable flag in the SPS is equal to 1, one or more reference picture lists are signaled in the PH, and the number of reference pictures in the second reference picture list is equal to 0, inferring that the value of the disable flag is 1. The one or more reference picture lists include a first reference picture list and a second reference picture list.

[0308] In some examples, the processor 520, in response to determining to skip parsing of a disable flag, infers the value of the disable flag based on one or more enable flags signaled in the SPS of the picture by performing the following operations: in response to determining that a first enable flag in the SPS is equal to 0, inferring the value of the disable flag is 1, and in response to determining that a second enable flag in the SPS is equal to 1, inferring the value of the disable flag is 1.

[0309] In some examples, the processor 520 determines the value of the first enable flag in the SPS to be W, and the first enable flag in the SPS specifies whether DMVR-based inter-frame bidirectional prediction is enabled, the first enable flag equal to 1 specifies that DMVR-based inter-frame bidirectional prediction is enabled, and the first enable flag equal to 0 specifies that DMVR-based inter-frame bidirectional prediction is disabled. In response to determining to skip parsing of the disable flag, the processor 520 infers the value of the disable flag based on one or more enable flags signaled in the SPS of the picture by the following operations: In response to determining that the second enable flag in the SPS is equal to 0, inferring the value of the disable flag to be 1-W. The second enable flag in the SPS specifies whether a disable flag exists in the PH of the reference SPS, the second enable flag equal to 0 specifies that the disable flag does not exist in the PH of the reference SPS, and the second enable flag equal to 1 specifies that the disable flag exists in the PH of the reference SPS.

[0310] In some examples, in response to determining to skip parsing of a disable flag, processor 520 infers the value of the disable flag based on one or more enable flags signaled in the SPS of the picture by performing the following operations: in response to determining that a second enable flag in the SPS is not equal to 0, inferring that the value of the disable flag is 1.

[0311] In some examples, processor 520 infers a value of the disable flag to be 1 in response to determining that the second enable flag in the SPS is not equal to 0 by inferring a value of the disable flag to be 1 in response to determining that the second enable flag in the SPS is equal to 1, one or more reference picture lists are signaled in the PH, and the number of reference pictures in the second reference picture list is equal to 0. The one or more reference picture lists include a first reference picture list and a second reference picture list.

[0312] In some examples, processor 520 infers a value of a disable flag from one or more enable flags in the SPS in response to determining that a disable flag is signaled in the PH.

[0313] In some examples, the processor 520 infers the value of the disable flag based on one or more enable flags in the SPS in response to determining that the disable flag is signaled in the PH by performing the following operations: determining the value of the first enable flag in the SPS to be W; in response to determining that the second enable flag in the SPS is equal to 1 and one or more reference picture lists are not signaled in the PH, inferring the value of the disable flag to be 1-W; in response to determining that the second enable flag in the SPS is equal to 1, one or more reference picture lists are signaled in the PH and the number of reference pictures in reference picture list 1 is greater than 0, inferring the value of the disable flag to be 1-W.

[0314] In some examples, the processor 520 infers the value of the disable flag based on one or more enable flags in the SPS in response to determining that the disable flag is signaled in the PH by performing the following operations: in response to determining that a first enable flag in the SPS is equal to 1, a second enable flag in the SPS is equal to 1, and one or more reference picture lists are not signaled in the PH, inferring that the value of the disable flag is the value of the disable flag explicitly signaled in the PH; in response to determining that the first enable flag in the SPS is equal to 1, the second enable flag in the SPS is equal to 1, one or more reference picture lists are signaled in the PH and the number of reference pictures in reference picture list 1 is greater than 0, inferring that the value of the disable flag is the value of the disable flag explicitly signaled in the PH.

[0315] In some examples, the disable flag specifies whether to disable BDOF-based inter-frame bidirectional prediction in one or more slices associated with the PH. The processor 520 disables the codec tool when decoding the one or more slices by disabling BDOF-based inter-frame bidirectional prediction when decoding the one or more slices, and enables the codec tool when decoding the one or more slices by enabling BDOF-based inter-frame bidirectional prediction when decoding the one or more slices.

[0316] In some examples, the processor 520, in response to determining to skip parsing of the disable flag, infers the value of the disable flag from one or more enable flags signaled in the SPS of the picture by performing the following operations: in response to determining that a third enable flag in the SPS is equal to 1 and a fourth enable flag in the SPS is equal to 0, inferring the value of the disable flag to be 0. The third enable flag in the SPS specifies whether BDOF-based inter-frame bidirectional prediction is enabled, the third enable flag equal to 1 specifies that BDOF-based inter-frame bidirectional prediction is enabled, and the third enable flag equal to 0 specifies that BDOF-based inter-frame bidirectional prediction is disabled. The fourth enable flag in the SPS specifies whether a disable flag exists in the PH of the reference SPS, the fourth enable flag equal to 0 specifies that the disable flag does not exist in the PH of the reference SPS, and the fourth enable flag equal to 1 specifies that the disable flag exists in the PH of the reference SPS.

[0317] In some examples, the processor 520, in response to determining to skip parsing of the disable flag, infers the value of the disable flag based on one or more enable flags signaled in the SPS of the picture by performing the following operations: in response to determining that a third enable flag in the SPS is equal to 1 and a fourth enable flag in the SPS is equal to 1, inferring the value of the disable flag to be 1, and in response to determining that the third enable flag in the SPS is equal to 0, inferring the value of the disable flag to be 1.

[0318] In some examples, processor 520, in response to determining to skip parsing of the disable flag, infers a value of the disable flag from one or more enable flags signaled in the SPS of the picture by: in response to determining that a third enable flag in the SPS is equal to 0 and a fourth enable flag in the SPS is equal to 0, inferring that the disable flag is 1, and in response to determining that the third enable flag in the SPS is equal to 1, the fourth enable flag in the SPS is equal to 1, one or more reference picture lists are signaled in the PH, and the number of reference pictures in the second reference picture list is equal to 0, inferring that the value of the disable flag is 1. The one or more reference picture lists include a first reference picture list and a second reference picture list.

[0319] In some examples, in response to determining to skip parsing of a disable flag, the processor 520 infers the value of the disable flag based on one or more enable flags signaled in the SPS of the picture by performing the following operations: in response to determining that a third enable flag in the SPS is equal to 0, inferring the value of the disable flag is 1, and in response to determining that a fourth enable flag in the SPS is equal to 1, inferring the value of the disable flag is 1.

[0320] In some examples, the processor 520 determines the value of the third enable flag in the SPS to be V, and infers the value of the disable flag based on one or more enable flags signaled in the SPS of the picture by the following operations: in response to determining that the fourth enable flag in the SPS is equal to 0, inferring the value of the disable flag to be 1-V.

[0321] In some examples, in response to determining to skip parsing of a disable flag, processor 520 infers the value of the disable flag based on one or more enable flags signaled in the SPS of the picture by performing the following operations: in response to determining that a fourth enable flag in the SPS is not equal to 0, inferring that the value of the disable flag is 1.

[0322] In some examples, processor 520 infers a value of the disable flag to be 1 in response to determining that the fourth enable flag in the SPS is not equal to 0 by inferring a value of the disable flag to be 1 in response to determining that the fourth enable flag in the SPS is equal to 1, one or more reference picture lists are signaled in the PH, and the number of reference pictures in the second reference picture list is equal to 0. The one or more reference picture lists include a first reference picture list and a second reference picture list.

[0323] In some examples, the processor 520 determines the value of the third enable flag in the SPS to be V and infers the value of the disable flag based on one or more enable flags in the SPS in response to determining that the disable flag is signaled in the PH by the following operations: in response to determining that the fourth enable flag in the SPS is equal to 1 and one or more reference picture lists are not signaled in the PH, inferring the value of the disable flag to be 1-V; and in response to determining that the fourth enable flag in the SPS is equal to 1, one or more reference picture lists are signaled in the PH and the number of reference pictures in reference picture list 1 is greater than 0, inferring the value of the disable flag to be 1-V.

[0324] In some examples, processor 520 infers the value of the disable flag to be the value of the disable flag explicitly signaled in the PH in response to determining that a third enable flag in the SPS is equal to 1, a fourth enable flag in the SPS is equal to 1, and one or more reference picture lists are not signaled in the PH, and in response to determining that a third enable flag in the SPS is equal to 1, a fourth enable flag in the SPS is equal to 1, one or more reference picture lists are signaled in the PH, and the number of reference pictures in reference picture list 1 is greater than 0, infers the value of the disable flag to be the value of the disable flag explicitly signaled in the PH.

[0325] Figure 7 is a flowchart illustrating an exemplary process of video encoding and decoding according to some embodiments of the present disclosure.

[0326] In step 702, processor 520 determines whether a flag is present in the PH associated with the picture.

[0327] In some examples, this flag specifies whether the picture used for TMVP is derived from a reference picture list from among multiple reference picture lists associated with the picture.

[0328] In step 704 , the processor 520 , in response to determining that the flag exists in the PH, infers the value of the flag according to the number of reference pictures in the reference picture list.

[0329] In some examples, processor 520 skips parsing of this flag in response to determining that the plurality of reference picture lists indicates that one or more slices associated with the picture are not bi-predicted.

[0330] In some examples, the multiple reference picture lists include a first reference picture list and a second reference picture list.

[0331] In some examples, this flag equal to 1 specifies that pictures for TMVP are derived from a first reference picture list, and this flag equal to 0 specifies that pictures for TMVP are derived from a second reference picture list.

[0332] In some examples, in response to determining to skip parsing of this flag, the processor 520 infers the value of this flag based on the number of reference pictures in the reference picture list by performing the following operations: in response to determining that the number of reference pictures in the first reference picture list is greater than 1, inferring the value of this flag to be 1, and in response to determining that the number of reference pictures in the second reference picture list is greater than 1, inferring the value of this flag to be 0.

[0333] Figure 8 is a flowchart illustrating an exemplary process of video encoding and decoding according to some embodiments of the present disclosure.

[0334] In step 802, processor 520 determines whether a flag is present in the PH associated with the picture.

[0335] In some examples, this flag specifies the number of weights signaled in the reference picture list according to a first WP flag in the PPS of the picture and a second WP flag in the PH of the picture, and this flag is in the WP syntax associated with the picture.

[0336] In step 804 , the processor 520 , in response to determining that the flag is present in the PH, infers a value of the flag based on the number of reference pictures in a reference picture list in a plurality of reference picture lists associated with the picture.

[0337] In some examples, processor 520 skips parsing of this flag in response to determining that the plurality of reference picture lists indicates that one or more slices associated with the picture are not bi-predicted.

[0338] In some examples, the multiple reference picture lists include a first reference picture list and a second reference picture list, and this flag specifies the number of weights signaled in the second reference picture list in response to determining that the first WP flag in the PPS is equal to 1 and the second WP flag in the PH is equal to 1.

[0339] In some examples, the processor 520, in response to determining to skip parsing of this flag, infers the value of this flag based on the number of reference pictures in the reference picture list associated with the picture by: in response to determining that the first WP flag in the PPS is equal to 0, the second WP flag in the PH is equal to 1, and the number of reference pictures in the second reference picture list is equal to 0, inferring the value of this flag to be 0, and in response to determining that the first WP flag in the PPS is not equal to 0 and the second WP flag in the PH is equal to 1, inferring the value of this flag to be the value of this flag explicitly signaled in the PH, and in response to determining that the first WP flag in the PPS is not equal to 0 and the second WP flag in the PH is not equal to 1, inferring the value of this flag to be the value of NumRefIdxActive[1].

[0340] In some examples, the value of NumRefIdxActive[i]-1 specifies the maximum reference index for reference picture list i, where i is equal to 0 or 1.

[0341] For example, a value of NumRefIdxActive[1]-1 specifies the maximum reference index of reference picture list 1 (ie, the second reference picture list).

[0342] In some examples, the processor 520 determines the value of this flag in response to determining that this flag is present in the PH by: determining the value of this flag to be 0 in response to determining that the first WP flag in the PPS is equal to 0, determining the value of this flag to be the value of this flag explicitly signaled in the PH in response to determining that the first WP flag in the PPS is not equal to 0 and the second WP flag in the PH is equal to 1, and determining the value of this flag to be the value of NumRefIdxActive[1] in response to determining that the first WP flag in the PPS is not equal to 0 and the second WP flag in the PH is not equal to 1.

[0343] Fig. 9 is a flowchart illustrating an exemplary process of video encoding and decoding according to some embodiments of the present disclosure.

[0344] In step 902, the processor 520 uses an enable flag to specify whether one or more temporal motion vector predictors are used for inter prediction of one or more slices associated with a PH of a picture.

[0345] In step 904 , processor 520 constrains the value of the enable flag according to a number of offsets applied to the size of the picture for scaling ratio calculation.

[0346] In some examples, the processor sets the enable flag to 0 in response to determining that there is no common reference picture in one or more inter slices. The one or more slices include one or more inter slices associated with the PH.

[0347] In some examples, the processor sets the enable flag to 0 in response to determining that there is no common reference picture in one or more non-intra slices.

[0348] In some examples, a device for video encoding and decoding is provided. The device includes one or more processors 520; and a memory 504 configured to store instructions executable by one or more processors; wherein the processor is configured to perform the following when executing the instructions: Figure 6 The method shown.

[0349] In some examples, a device for video encoding and decoding is provided. The device includes one or more processors 520; and a memory 504 configured to store instructions executable by one or more processors; wherein the processor is configured to perform the following when executing the instructions: Figure 7 The method shown.

[0350] In some examples, a device for video encoding and decoding is provided. The device includes one or more processors 520; and a memory 504 configured to store instructions executable by one or more processors; wherein the processor is configured to perform the following when executing the instructions: Figure 8 The method shown.

[0351] In some examples, a device for video encoding and decoding is provided. The device includes one or more processors 520; and a memory 504 configured to store instructions executable by one or more processors; wherein the processor is configured to perform the following when executing the instructions: Fig. 9 The method shown.

[0352] In some other examples, a non-transitory computer-readable storage medium 504 is provided having instructions stored therein. When the instructions are executed by one or more processors 520, the instructions cause the processor to perform the following steps: Figure 6 The method shown.

[0353] In some other examples, a non-transitory computer-readable storage medium 504 is provided having instructions stored therein. When the instructions are executed by one or more processors 520, the instructions cause the processor to perform the following steps: Figure 7 The method shown.

[0354] In some other examples, a non-transitory computer-readable storage medium 504 is provided having instructions stored therein. When the instructions are executed by one or more processors 520, the instructions cause the processor to perform the following steps: Figure 8 The method shown.

[0355] In some other examples, a non-transitory computer-readable storage medium 504 is provided having instructions stored therein. When the instructions are executed by one or more processors 520, the instructions cause the processor to perform the following steps: Fig. 9 The method shown.

[0356] The description of the present disclosure has been presented for purposes of illustration and is not intended to be exhaustive or limited to the present disclosure. Many modifications, variations, and alternative embodiments will be apparent to one of ordinary skill in the art having the benefit of the teachings presented in the foregoing description and the associated drawings.

[0357] The examples are chosen and described in order to explain the principles of the present disclosure and to enable other persons skilled in the art to understand the various embodiments of the present disclosure and to best utilize the basic principles and various embodiments with various modifications suitable for the specific use contemplated. Therefore, it will be understood that the scope of the present disclosure is not limited to the specific examples of the disclosed embodiments, and modifications and other embodiments are intended to be included within the scope of the present disclosure.

Claims

1. A method for video decoding, comprising: determining whether there is a disable flag in a picture header PH associated with the picture, wherein the disable flag specifies whether a codec tool is disabled for one or more slices associated with the PH, the disable flag being equal to 1 specifies that the codec tool is disabled when decoding the one or more slices, and the disable flag being equal to 0 specifies that the codec tool is enabled when decoding the one or more slices; In response to determining that the disable flag is not present in the PH, inferring a value of the disable flag according to one or more enable flags signaled in a sequence parameter set (SPS) of the picture, The inferring the value of the disabling flag according to the one or more enabling flags signaled in a sequence parameter set SPS of the picture comprises: In response to determining that a first enable flag in the SPS is equal to 1 and a second enable flag in the SPS is equal to 0, inferring that the value of the disable flag is 0; and In response to determining that the first enable flag in the SPS is equal to 1 and the second enable flag in the SPS is equal to 1, inferring that the value of the disable flag is 1; wherein the first enable flag in the SPS specifies whether to enable the codec tool, the first enable flag being equal to 1 specifies enabling the codec tool, and the first enable flag being equal to 0 specifies disabling the codec tool; The second enable flag in the SPS specifies whether the disable flag exists in the PH that references the SPS, the second enable flag equal to 0 specifies that the disable flag does not exist in the PH that references the SPS, and the second enable flag equal to 1 specifies that the disable flag can exist in the PH that references the SPS.

2. The method according to claim 1, wherein the codec tool comprises at least one of inter-frame bidirectional prediction based on decoder motion vector refinement (DMVR) and inter-frame bidirectional prediction based on bidirectional optical flow (BDOF).

3. The method according to claim 2, further comprising: In response to determining from one or more reference picture lists that one or more slices associated with the picture are not bi-directionally predicted, determining that the disable flag is not present in the PH.

4. The method of claim 2, wherein the disable flag specifies whether DMVR-based inter-frame bidirectional prediction is disabled for the one or more slices associated with the PH; wherein disabling the codec tool when decoding the one or more slices comprises: disabling DMVR-based inter-frame bidirectional prediction when decoding the one or more slices; and The enabling of the codec tool when decoding the one or more slices includes: enabling DMVR-based inter-frame bidirectional prediction when decoding the one or more slices.

5. The method of claim 4, wherein the value of the disable flag is inferred from the one or more enable flags signaled in a sequence parameter set (SPS) of the picture, further comprising: In response to determining that the first enable flag in the SPS is equal to 0, the value of the disable flag is inferred to be 1.

6. The method according to claim 4, further comprising: In response to determining that one or more reference picture lists are signaled in the PH and a number of reference pictures in a second reference picture list is equal to zero, determining that the one or more slices associated with the picture are not bi-directionally predicted, wherein the one or more reference picture lists include a first reference picture list and the second reference picture list, The method further comprises inferring the value of the disabling flag according to the one or more enabling flags signaled in the sequence parameter set SPS of the picture, and further comprising: In response to determining that the first enable flag in the SPS is equal to 0 and the second enable flag in the SPS is equal to 0, inferring that the disable flag is 1; and In response to determining that the first enable flag in the SPS is equal to 1 and the second enable flag in the SPS is equal to 1, the value of the disable flag is inferred to be 1.

7. The method of claim 4, wherein the value of the disable flag is inferred from the one or more enable flags signaled in a sequence parameter set (SPS) of the picture, further comprising: In response to determining that the first enable flag in the SPS is equal to 0, inferring that the value of the disable flag is 1; as well as In response to determining that the second enable flag in the SPS is equal to 1, the value of the disable flag is inferred to be 1.

8. The method according to claim 4, further comprising: Determine the value of the first enable flag in the SPS as W, wherein the first enable flag in the SPS specifies whether to enable DMVR-based inter-frame bidirectional prediction, the first enable flag being equal to 1 specifies enabling DMVR-based inter-frame bidirectional prediction, and the first enable flag being equal to 0 specifies disabling the DMVR-based inter-frame bidirectional prediction; The value of the disabling flag is inferred according to the one or more enabling flags signaled in a sequence parameter set SPS of the picture, further comprising: In response to determining that a second enable flag in the SPS is equal to 0, it is inferred that the value of the disable flag is 1-W, wherein the second enable flag in the SPS specifies whether the disable flag exists in the PH referenced to the SPS, the second enable flag equal to 0 specifies that the disable flag does not exist in the PH referenced to the SPS, and the second enable flag equal to 1 specifies that the disable flag can exist in the PH referenced to the SPS.

9. The method of claim 8, wherein the value of the disable flag is inferred from the one or more enable flags signaled in a sequence parameter set (SPS) of the picture, further comprising: In response to determining that the second enable flag in the SPS is not equal to 0, the value of the disable flag is inferred to be 1.

10. The method according to claim 9, further comprising: In response to determining that one or more reference picture lists are signaled in the PH and a number of reference pictures in a second reference picture list is equal to zero, determining that the one or more slices associated with the picture are not bi-directionally predicted, wherein the one or more reference picture lists include a first reference picture list and the second reference picture list, In response to determining that the second enable flag in the SPS is not equal to 0, inferring that the value of the disable flag is 1 further includes: In response to determining that the second enable flag in the SPS is equal to 1, the value of the disable flag is inferred to be 1.

11. The method according to claim 2, further comprising: In response to determining that the disable flag is signaled in the PH, a value of the disable flag is inferred from the first enable flag and the second enable flag in the SPS.

12. The method of claim 11, wherein inferring the value of the disable flag according to the first enable flag and the second enable flag in the SPS comprises: Determine the value of the first enable flag in the SPS as W, wherein the first enable flag in the SPS specifies whether to enable DMVR-based inter-frame bidirectional prediction, the first enable flag being equal to 1 specifies enabling DMVR-based inter-frame bidirectional prediction, and the first enable flag being equal to 0 specifies disabling DMVR-based inter-frame bidirectional prediction; In response to determining that a second enable flag in the SPS is equal to 1 and one or more reference picture lists are not signaled in the PH, inferring that the value of the disable flag is 1-W; as well as In response to determining that the second enable flag in the SPS is equal to 1, the one or more reference picture lists are signaled in the PH, and the number of reference pictures in the second reference picture list is greater than 0, inferring that the value of the disable flag is 1-W; Wherein the second enable flag in the SPS specifies whether the disable flag exists in the PH referenced to the SPS, the second enable flag equal to 0 specifies that the disable flag does not exist in the PH referenced to the SPS, and the second enable flag equal to 1 specifies that the disable flag exists in the PH referenced to the SPS.

13. The method of claim 11, wherein inferring the value of the disable flag according to the first enable flag and the second enable flag in the SPS comprises: in response to determining that a first enable flag in the SPS is equal to 1, a second enable flag in the SPS is equal to 1, and one or more reference picture lists are not signaled in the PH, inferring that the value of the disable flag is the value of the disable flag explicitly signaled in the PH; in response to determining that the first enable flag in the SPS is equal to 1, the second enable flag in the SPS is equal to 1, the one or more reference picture lists are signaled in the PH and the number of reference pictures in the second reference picture list is greater than 0, inferring the value of the disable flag to be the value of the disable flag explicitly signaled in the PH, wherein the first enable flag in the SPS specifies whether to enable DMVR-based inter-frame bidirectional prediction, the first enable flag being equal to 1 specifies enabling DMVR-based inter-frame bidirectional prediction, and the first enable flag being equal to 0 specifies disabling DMVR-based inter-frame bidirectional prediction; as well as Wherein the second enable flag in the SPS specifies whether the disable flag exists in the PH referenced to the SPS, the second enable flag equal to 0 specifies that the disable flag does not exist in the PH referenced to the SPS, and the second enable flag equal to 1 specifies that the disable flag exists in the PH referenced to the SPS.

14. The method of claim 2, wherein the disable flag specifies whether BDOF-based inter-frame bidirectional prediction is disabled for the one or more slices associated with the PH; wherein disabling the codec tool when decoding the one or more slices comprises: disabling BDOF-based inter-frame bidirectional prediction when decoding the one or more slices; and The enabling of the codec tool when decoding the one or more slices includes: enabling BDOF-based inter-frame bidirectional prediction when decoding the one or more slices.

15. The method of claim 14, wherein the value of the disable flag is inferred from the one or more enable flags signaled in a sequence parameter set (SPS) of the picture, further comprising: In response to determining that the first enable flag in the SPS is equal to 0, the value of the disable flag is inferred to be 1.

16. The method according to claim 14, further comprising: In response to determining that one or more reference picture lists are signaled in the PH and a number of reference pictures in a second reference picture list is equal to zero, determining that the one or more slices associated with the picture are not bi-directionally predicted, wherein the one or more reference picture lists include a first reference picture list and the second reference picture list, The method further comprises inferring the value of the disabling flag according to the one or more enabling flags signaled in the sequence parameter set SPS of the picture, and further comprising: In response to determining that the first enable flag in the SPS is equal to 0 and the second enable flag in the SPS is equal to 0, inferring that the disable flag is 1; and In response to determining that the first enable flag in the SPS is equal to 1 and the second enable flag in the SPS is equal to 1, it is inferred that the value of the disable flag is 1.

17. The method of claim 14, wherein the value of the disable flag is inferred from the one or more enable flags signaled in a sequence parameter set (SPS) of the picture, further comprising: In response to determining that the first enable flag in the SPS is equal to 0, inferring that the value of the disable flag is 1; as well as In response to determining that the second enable flag in the SPS is equal to 1, the value of the disable flag is inferred to be 1.

18. The method according to claim 14, further comprising: Setting the value of the first enable flag in the SPS to V, wherein the first enable flag in the SPS specifies whether to enable BDOF-based inter-frame bidirectional prediction, the first enable flag being equal to 1 specifies enabling BDOF-based inter-frame bidirectional prediction, and the first enable flag being equal to 0 specifies disabling BDOF-based inter-frame bidirectional prediction; The value of the disabling flag is inferred according to the one or more enabling flags signaled in a sequence parameter set SPS of the picture, further comprising: In response to determining that a second enable flag in the SPS is equal to 0, it is inferred that the value of the disable flag is 1-V, wherein the second enable flag in the SPS specifies whether the disable flag exists in the PH referenced to the SPS, the second enable flag equal to 0 specifies that the disable flag does not exist in the PH referenced to the SPS, and the second enable flag equal to 1 specifies that the disable flag exists in the PH referenced to the SPS.

19. The method of claim 18, wherein the value of the disable flag is inferred from the one or more enable flags signaled in a sequence parameter set (SPS) of the picture, further comprising: In response to determining that the second enable flag in the SPS is not equal to 0, the value of the disable flag is inferred to be 1.

20. The method according to claim 19, further comprising: In response to determining that one or more reference picture lists are signaled in the PH and a number of reference pictures in a second reference picture list is equal to zero, determining that the one or more slices associated with the picture are not bi-directionally predicted, wherein the one or more reference picture lists include a first reference picture list and the second reference picture list, In response to determining that the second enable flag in the SPS is not equal to 0, inferring that the value of the disable flag is 1 further includes: In response to determining that the second enable flag in the SPS is equal to 1, the value of the disable flag is inferred to be 1.

21. The method according to claim 11, wherein: Inferring the value of the disable flag according to the first enable flag and the second enable flag in the SPS, further comprising: Determine the value of a first enable flag in the SPS as V, wherein the first enable flag in the SPS specifies whether to enable inter-frame bidirectional prediction based on bidirectional optical flow BDOF, the first enable flag being equal to 1 specifies enabling inter-frame bidirectional prediction based on BDOF, and the first enable flag being equal to 0 specifies disabling inter-frame bidirectional prediction based on BDOF; In response to determining that a second enable flag in the SPS is equal to 1 and one or more reference picture lists are not signaled in the PH, inferring a value of the disable flag to be 1-V; and In response to determining that the second enable flag in the SPS is determined to be equal to 1, the one or more reference picture lists are signaled in the PH and the number of reference pictures in the second reference picture list is greater than 0, inferring that the value of the disable flag is 1-V, Wherein the second enable flag in the SPS specifies whether the disable flag exists in the PH referenced to the SPS, the second enable flag equal to 0 specifies that the disable flag does not exist in the PH referenced to the SPS, and the second enable flag equal to 1 specifies that the disable flag exists in the PH referenced to the SPS.

22. The method according to claim 11, wherein: Inferring the value of the disable flag according to the first enable flag and the second enable flag in the SPS, further comprising: in response to determining that a first enable flag in the SPS is equal to 1, a second enable flag in the SPS is equal to 1, and one or more reference picture lists are not signaled in the PH, inferring that the value of the disable flag is the value of the disable flag explicitly signaled in the PH; in response to determining that the first enable flag in the SPS is equal to 1, the second enable flag in the SPS is equal to 1, one or more reference picture lists are signaled in the PH and the number of reference pictures in the second reference picture list is greater than 0, inferring the value of the disable flag to be the value of the disable flag explicitly signaled in the PH, Wherein the first enable flag in the SPS specifies whether to enable inter-frame bidirectional prediction based on bidirectional optical flow BDOF, the first enable flag equal to 1 specifies that inter-frame bidirectional prediction based on BDOF is enabled, and the first enable flag equal to 0 specifies that inter-frame bidirectional prediction based on BDOF is disabled; and wherein the second enable flag in the SPS specifies whether the disable flag exists in the PH referring to the SPS, the second enable flag equal to 0 specifies that the disable flag does not exist in the PH referring to the SPS, and the second enable flag equal to 1 specifies that the disable flag exists in the PH referring to the SPS.

23. An apparatus for video decoding, comprising: one or more processors; as well as a memory configured to store instructions executable by the one or more processors; Wherein the one or more processors are configured to perform the method according to any one of claims 1-22 when executing the instructions.

24. A non-transitory computer-readable storage medium for video decoding, the non-transitory computer-readable storage medium storing computer-executable instructions, which, when executed by one or more computer processors, cause the one or more computer processors to perform the method according to any one of claims 1-22 and store a bitstream to be decoded by the method according to any one of claims 1-22.

25. A method for storing a bit stream, comprising: The bit stream decoded by the method according to any one of claims 1-22 is stored on a non-transitory computer-readable storage medium.

26. A computer program product comprising computer instructions, characterized in that When the computer instructions are executed by at least one processor, the method according to any one of claims 1-22 is implemented.

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