Control method, device and apparatus for third harmonic injection double-stage matrix converter

Abstract

The present application relates to a control method, device and equipment for a third harmonic injection double-stage matrix converter. The method comprises: at the beginning of a switching cycle, obtaining a target inverter stage vector group of the inverter stage three-phase bridge arm in a target converter; obtaining an initial vector synthesis order of the target inverter stage vector group based on the target inverter stage vector group and the initial inverter stage sector where the phase of the desired output voltage is located; obtaining estimated output current information within the switching cycle based on the initial vector synthesis order and the duty cycle of the target inverter stage vector group, and adjusting the initial inverter stage sector based on the estimated output current information to obtain a target inverter stage sector; obtaining a target vector synthesis order of the target inverter stage vector group based on the target inverter stage sector and the target inverter stage vector group, and performing pulse width modulation using the target vector synthesis order and the duty cycle. The common mode voltage can be suppressed by using this method.

Description

Technical Field

[0001] The present application relates to the technical field of third harmonic injection matrix converters, and in particular to a control method, device and equipment for a third harmonic injection double-stage matrix converter. Background Art

[0002] The third harmonic injection two-stage matrix converter (3TSMC) is a new type of matrix converter (MC) based on a hybrid third harmonic injection rectifier. It inherits most of the advantages of the traditional MC, and also has the advantages of decoupling of the rectifier stage and the inverter stage, strong reactive power control capability, and low current stress. Therefore, it is more suitable for AC motor drives, wind energy conversion systems, flexible AC transmission, aviation starting and generating systems, and other occasions.

[0003] However, 3TSMC inverter stages usually use space vector modulation, which will generate high-frequency, high-voltage change rate common-mode voltage. Due to its high-frequency oscillation characteristics, the common-mode voltage will increase the heat loss of the motor and affect the system efficiency; the current induced in the motor bearing will affect the insulation of the motor and shorten the service life of the bearing; the leakage current generated may cause electromagnetic interference and affect the normal operation of other equipment; when the converter is connected in parallel, it will cause circulating current problems, reduce the quality of the input and output current waveforms, and reduce the system efficiency. In summary, the negative effects brought by the common-mode voltage will seriously affect the normal operation of the system. Summary of the invention

[0004] Based on this, it is necessary to provide a control method, device and equipment for a two-stage matrix converter that can suppress the third harmonic injection of the common-mode voltage in order to solve the above technical problems.

[0005] In a first aspect, the present application provides a control method for a third harmonic injection double-stage matrix converter.

[0006] The method includes:

[0007] At the beginning of the switching cycle, a target inverter level vector group of the inverter level three-phase bridge arm in the target converter is obtained; the target inverter level vector group is used to synthesize the desired output voltage;

[0008] Based on the target inverter stage vector group and the initial inverter stage sector where the phase of the desired output voltage is located, acquiring an initial vector synthesis order of the target inverter stage vector group;

[0009] Based on the initial vector synthesis order and the duty cycle of the target inverter stage vector group, the estimated output current information within the switching cycle is acquired, and based on the estimated output current information, the initial inverter stage sector is adjusted to obtain a target inverter stage sector;

[0010] Based on the target inverter stage sector and the target inverter stage vector group, a target vector synthesis order of the target inverter stage vector group is acquired, and pulse width modulation is performed using the target vector synthesis order and the duty cycle.

[0011] In one embodiment, the adjusting the initial inverter level sector based on the estimated output current information to obtain a target inverter level sector includes:

[0012] Obtaining the positive and negative conditions of the target two-phase output current in the estimated output current information, wherein the target two-phase output current is used to indicate two-phase output currents with the same polarity among the three-phase output currents corresponding to the estimated output current information under theoretical conditions;

[0013] When the target two-phase output current changes from positive to negative, the initial inverter stage sector is adjusted to obtain the target inverter stage sector.

[0014] In one embodiment, the obtaining of the positive and negative conditions of the target two-phase output current in the estimated output current information includes:

[0015] When the polarity of the target two-phase output current is positive, obtaining the valley value of the target two-phase output current;

[0016] If the valley value of the target two-phase output current is less than zero, the target two-phase output current changes positively or negatively.

[0017] In one embodiment, the obtaining of the positive and negative conditions of the target two-phase output current in the estimated output current information includes:

[0018] When the polarity of the target two-phase output current is negative, obtaining the peak value of the target two-phase output current;

[0019] If the peak value of the target two-phase output current is greater than zero, the target two-phase output current changes positively or negatively.

[0020] In one embodiment, when the target two-phase output current changes from positive to negative, the initial inverter stage sector is adjusted to obtain the target inverter stage sector, including:

[0021] When the target two-phase output current changes from positive to negative, the initial inverter stage sector is adjusted to the inverter stage sector on the adjacent side in combination with the phase of the desired output voltage to obtain the target inverter stage sector.

[0022] In one embodiment, the initial inverter-stage sector is obtained by the following steps:

[0023] Obtain the original partition area corresponding to the inverter-level sector;

[0024] Rotate the original divided area counterclockwise by the impedance angle of the load to obtain the initial divided area corresponding to the inverter stage sector;

[0025] The initial inverter stage sector is determined from the initial division area of ​​the inverter stage sector by the phase of the desired output voltage.

[0026] In a second aspect, the present application also provides a control device for a third harmonic injection double-stage matrix converter. The device comprises:

[0027] An acquisition module, used for acquiring a target inverter level vector group of the inverter level three-phase bridge arm in the target converter at the beginning of a switching cycle; the target inverter level vector group is used for synthesizing a desired output voltage;

[0028] An initial module, configured to obtain an initial vector synthesis order of the target inverter stage vector group based on the target inverter stage vector group and an initial inverter stage sector where the phase of the desired output voltage is located;

[0029] an adjustment module, configured to obtain estimated output current information within the switching cycle based on the initial vector synthesis order and the duty cycle of the target inverter stage vector group, and adjust the initial inverter stage sector based on the estimated output current information to obtain a target inverter stage sector;

[0030] The modulation module is used to obtain a target vector synthesis order of the target inverter stage vector group based on the target inverter stage sector and the target inverter stage vector group, and perform pulse width modulation using the target vector synthesis order and the duty cycle.

[0031] In a third aspect, the present application further provides a computer device, which includes a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the control method for the third harmonic injection double-stage matrix converter provided in the first aspect of the present application are implemented.

[0032] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the control method for a double-stage matrix converter with third harmonic injection provided in the first aspect of the present application.

[0033] In a fifth aspect, the present application further provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the steps of the control method for the third harmonic injection double-stage matrix converter provided in the first aspect of the present application are implemented.

[0034] The control method, device and equipment of the above-mentioned third harmonic injection two-stage matrix converter obtains the target inverter stage vector group of the three-phase bridge arm of the inverter stage in the target converter at the beginning of the switching cycle; the target inverter stage vector group is used to synthesize the desired output voltage; based on the target inverter stage vector group and the initial inverter stage sector where the phase of the desired output voltage is located, the initial vector synthesis order of the target inverter stage vector group is obtained; based on the initial vector synthesis order and the duty cycle of the target inverter stage vector group, the estimated output current information within the switching cycle is obtained, and the initial inverter stage sector is adjusted based on the estimated output current information to obtain the target inverter stage sector; based on the target inverter stage sector and the target inverter stage vector group, the target vector synthesis order of the target inverter stage vector group is obtained, and the target vector synthesis order and the duty cycle are used to perform pulse width modulation. The above method can effectively suppress the amplitude of the 3TSMC common-mode voltage; can effectively reduce the high-frequency component of the 3TSMC common-mode voltage; is simple and reliable, does not require additional hardware, and is easy to implement compared to traditional control algorithms, only changing the modulation strategy of the inverter stage, and reduces the impact of the inverter stage bridge arm dead zone on this method. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 An application environment diagram of a control method for a double-stage matrix converter injected with third harmonics in one embodiment;

[0036] Figure 2 A schematic flow chart of a control method for a double-stage matrix converter injected with a third harmonic in one embodiment;

[0037] Figure 3 A topology diagram of a double-stage matrix converter for third harmonic injection in one embodiment;

[0038] Figure 4 A schematic diagram of the division of the rectifying stage sectors before and after adjustment in one embodiment;

[0039] Figure 5 A schematic diagram of the original division area of ​​the inverter-stage sector in one embodiment;

[0040] Figure 6 A schematic diagram of initial division of inverter-stage sectors in one embodiment;

[0041] Figure 7 Schematic diagram of improved sector division of inverter level vector group U2U4U6 in one embodiment;

[0042] Figure 8 A schematic diagram of improved sector division of the inverter level vector group U1U3U5 in one embodiment;

[0043] Fig. 9A schematic flow chart of a control method for a double-stage matrix converter injected with third harmonics according to another embodiment;

[0044] Fig.10 A schematic diagram of an inverter stage vector combination in one embodiment;

[0045] Fig.11 A schematic diagram of an inverter stage vector combination in another embodiment;

[0046] Fig.12 is a timing diagram of a switch, an output filter inductor voltage, and an A-phase output current in one embodiment;

[0047] Fig.13 A block diagram of a control device for a double-stage matrix converter for third harmonic injection in one embodiment;

[0048] Fig.14 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0050] At present, there are two main ways to achieve common-mode voltage suppression in the system: the first is to add common-mode transformers and other devices to achieve the effect of common-mode voltage suppression, but this method will increase the size and cost of the entire system. The second is to optimize the modulation strategy to achieve common-mode voltage suppression, among which the improvement of space vector modulation strategy is the main one. However, there are few common-mode voltage suppression strategies for third harmonic injection two-stage matrix converter (3TSMC).

[0051] For a third harmonic injection two-stage matrix converter, an embodiment of the present application proposes a control method for a third harmonic injection two-stage matrix converter. The control method for a third harmonic injection two-stage matrix converter provided by the embodiment of the present application can be applied to Figure 1 In the application environment shown. The third harmonic injection two-stage matrix converter 102 is connected to the controller 104. The controller 104 collects the electrical information of the third harmonic injection two-stage matrix converter 102 at the beginning of the switching cycle of the third harmonic injection two-stage matrix converter 102, and performs pulse width modulation according to the electrical information to obtain a modulation signal of each switch tube. The controller 104 can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers or Internet of Things devices.

[0052] In one embodiment, Figure 2As shown, a control method for a third harmonic injection double-stage matrix converter is provided. Figure 1 The controller 104 in the embodiment is taken as an example to illustrate, and the following steps are included:

[0053] Step 202: At the beginning of a switching cycle, a target inverter-stage vector group of the inverter-stage three-phase bridge arms in a target converter is obtained.

[0054] The target converter is a double-stage matrix converter with third harmonic injection for pulse width modulation by the controller in the embodiment of the present application. Figure 3 The third harmonic injection two-stage matrix converter of the embodiment of the present application includes a three-phase AC power supply, an input LC filter, a three-phase bridge arm of a rectifier stage, a third harmonic injection circuit, a three-phase bridge arm of an inverter stage, and a three-phase load. Among them, the three-phase bridge arm of the inverter stage can be equivalently represented by 6 switch elements, and the phase voltage and line voltage depend on the state of the six power switches on the upper and lower inverter bridge arms corresponding to it. It is defined that when the state quantity of each switch is 1, the upper bridge arm is turned on, and when the switch state quantity is 0, the lower bridge arm is turned on, and the upper and lower bridge arms of each phase cannot be turned on at the same time. Then, different combinations of the six switches can constitute 8 different working states of the inverter stage, corresponding to 8 voltage vectors, including 6 effective voltage vectors, namely U1 (100), U2 (110), U3 (010), U4 (011), U5 (001), and U6 (101).

[0055] At the beginning of the switching cycle, the embodiment of the present application collects the power supply voltage and obtains the target inverter level vector group of the three-phase bridge arm of the inverter stage. The target inverter level vector group refers to a combination of inverter level voltage vectors selected for synthesizing the desired output voltage. Specifically, the embodiment of the present application can collect the input voltage information of the third harmonic injection matrix converter, and select the corresponding inverter level vector group as the target inverter level vector group according to the phase of the input voltage in the input voltage information. Since the phase of the input voltage can determine the modulation signal of the three-phase bridge arm of the rectifier stage and the bidirectional switch, the corresponding inverter level vector group is selected according to the phase of the input voltage, that is, the effect of deep suppression of the common mode voltage amplitude can be achieved by selecting different inverter level vector groups according to the state of the rectifier stage, thereby realizing the common mode voltage suppression of the third harmonic injection two-stage matrix converter under low modulation ratio.

[0056] For example, the three-phase input voltage u of the third harmonic injection matrix converter is collected. ia 、u ib 、u ic , perform abc / αβ coordinate transformation to obtain the αβ component u of the three-phase input voltage iα 、u iβ The phase θ of the three-phase input voltage is calculated through a dual generalized second-order integrator phase-locked loop, and then the three-phase bridge arm S of the rectifier stage is determined according to θ. a,b,cp , Sa,b,cn and bidirectional switch S a,b,cy , S ya,b,c The modulation signal.

[0057] In the embodiment of the present application, when θ belongs to and between, and between, and When θ is between , the inverter level vectors U2, U4, and U6 are selected to synthesize the desired output voltage; when θ belongs to and between, and between, and When between, the inverter level vectors U1, U3, and U5 are selected to synthesize the desired output voltage.

[0058] For the convenience of description, the embodiment of the present application can determine the rectifier level sector in which the input voltage is located according to the phase, and select the corresponding inverter level vector group as the target inverter level vector group through the rectifier level sector. Specifically, the 6 original rectifier level sectors are divided into 12, and then recombined into 6 new rectifier level sectors. The new rectifier level sector is determined according to θ. The specific interval of the new rectifier level sector is as follows: Figure 4 As shown. According to θ, the new rectifier level sector is determined to select the corresponding inverter level vector group. When θ is in sectors 1, 3, and 5, the inverter level vectors U2, U4, and U6 are selected to synthesize the desired output voltage; when θ is in sectors 2, 4, and 6, the inverter level vectors U1, U3, and U5 are selected for synthesis.

[0059] Step 204 : acquiring an initial vector synthesis order of the target inverter stage vector group based on the target inverter stage vector group and the initial inverter stage sector where the phase of the desired output voltage is located.

[0060] Among them, after the division area of ​​the inverter level sector is determined, the positive or negative of each phase in the three-phase output current is also determined accordingly. The embodiment of the present application is based on the principle that there is only one three-phase output current situation in each inverter level sector, and obtains the initial division area of ​​the inverter level sector, that is, the initial division area of ​​the inverter level sector refers to each inverter level sector in the initial division area, in theory, there is only one three-phase output current situation. One three-phase output current situation means that in each inverter level sector, the output current of each phase only has a positive or negative situation, and will not change between positive and negative.

[0061] In one possible implementation, please combine Figure 5 and Figure 6The embodiment of the present application adjusts the inverter level sector division, rotates the original division area of ​​the inverter level sector counterclockwise by a certain angle, and the specific rotation angle value can be the impedance angle of the load, to obtain the initial division area of ​​the inverter level sector, so that each inverter level sector in the initial division area has only one three-phase output current situation.

[0062] Exemplarily, each inverter-stage sector in the initial divided area uniquely corresponds to one three-phase output current condition, see Table 1.

[0063] Table 1 Correspondence between each inverter level sector and output current in the initial division area

[0064] <![CDATA[i oa ]]> <![CDATA[i ob ]]> <![CDATA[i oc ]]> Sector I + + - Sector II - + - Sector III - + + Sector IV - - + Sector V + - + Sector VI + - -

[0065] The embodiment of the present application determines the initial inverter level sector by the phase of the desired output voltage and the initial division area, and the initial inverter level sector refers to the sector in the initial division area where the desired output voltage phase is located. Combined with the target inverter level vector group and the initial inverter level sector where the phase of the desired output voltage is located, the initial vector synthesis order of the target inverter level vector group and the duty cycle of each vector are determined. The initial vector synthesis order refers to the timing arrangement of each inverter level vector in the target inverter level vector group when it is determined to be the initial inverter level sector.

[0066] For example, please refer to Table 2. When the target inverter level vector group is U2U4U6 and the phase of the expected output voltage is in sector I in the initial division area, the initial vector synthesis order of U6U2U4U2U6 is adopted, and the switch tube timing is 101-110-011-110-101.

[0067] Table 2 Inverter stage vector switch timing table

[0068]

[0069] Step 206, based on the initial vector synthesis order and the duty cycle of the target inverter stage vector group, obtain the estimated output current information within the switching cycle, and adjust the initial inverter stage sector based on the estimated output current information to obtain the target inverter stage sector.

[0070] In order to improve the common mode voltage suppression effect, the embodiment of the present application determines the initial vector synthesis order and the duty cycle of the target inverter stage vector group, and then calculates the estimated output current information of the current switching cycle in the working mode of the initial vector synthesis order, and determines whether the synthesis order of the target inverter stage vector group needs to be adjusted by the estimated output current information. That is, the vector synthesis order corresponding to the new target inverter stage sector is adopted.

[0071] Due to the pulsation of the output current, two phases of the three-phase output current at the sector switching point are prone to change. At this time, the dead zone effect will produce common-mode voltage spikes, affecting the effect of common-mode voltage suppression. Therefore, if the positive and negative output currents of two phases in each sector change, the sectors need to be readjusted so that the dead zone effect can weaken the impact of the method under the new sector division.

[0072] In one possible implementation, the initial inverter stage sector is adjusted based on the estimated output current information to obtain the target inverter stage sector, including: obtaining the positive and negative conditions of the target two-phase output current in the estimated output current information; when the target two-phase output current changes from positive to negative, the initial inverter stage sector is adjusted to obtain the target inverter stage sector; when the target two-phase output current does not change from positive to negative, the initial vector synthesis order and the duty cycle of the target inverter stage vector group are used to perform pulse width modulation to obtain the drive signal of each inverter stage tube.

[0073] Among them, the target two-phase output current is used to indicate the two-phase output current with the same polarity in the three-phase output current corresponding to the estimated output current information under theoretical conditions. When the polarity of the target two-phase output current is positive, the valley value of the target two-phase output current is obtained. If the valley value of the target two-phase output current is less than zero, the target two-phase output current changes positively or negatively. When the polarity of the target two-phase output current is negative, the peak value of the target two-phase output current is obtained. If the peak value of the target two-phase output current is greater than zero, the target two-phase output current changes positively or negatively. When the target two-phase output current changes positively or negatively, combined with the phase of the desired output voltage, the initial inverter level sector is adjusted to the inverter level sector on the adjacent side to obtain the target inverter level sector.

[0074] For example, please refer to Table 1. When the target inverter level vector group is U2U4U6, the phase of the expected output voltage is in sector I in the initial division area, determine the initial vector synthesis order and the duty cycle of the target inverter level vector group, and calculate the estimated output current information. The target two-phase output current corresponding to sector I is the A-phase output current and the B-phase output current, both of which are positive. The valley value of the A-phase output current and the valley value of the B-phase output current are obtained. If there is a valley value less than zero, the initial inverter level sector is adjusted.

[0075] Specifically, if the phase of the desired output voltage is at the beginning of sector I in the initial division area (adjacent to sector VI), sector I is adjusted to sector VI, that is, the vector synthesis order of target inverter sector VI is adopted. If the phase of the desired output voltage is at the end of sector I in the initial division area (adjacent to sector II), sector I is adjusted to sector II, that is, the vector synthesis order of target inverter sector II is adopted.

[0076] In another possible implementation, the adjustment of the sector can also be achieved by determining which phase of the target two-phase output current has a positive or negative change. It can be understood that, for example, when the target inverter level vector group is selected as U2U4U6, the initial inverter level sector is sector I, if the A phase output current valley value is less than zero, it is adjusted to sector II, and if the B phase output current valley value is less than zero, it is adjusted to sector VI.

[0077] For further explanation of sector adjustment, please refer to Figure 7 and Figure 8 Improved partitioning of the initial partitioned area.

[0078] contrast Figure 6 and Figure 7 , when the target inverter level vector group is U2U4U6, and the initial inverter level sector is sector Ⅰ, sector Ⅲ or sector Ⅴ, if the positive or negative change occurs in the three-phase output current corresponding to sector Ⅰ, sector Ⅲ or sector Ⅴ, it will be adjusted to the sector on the adjacent side, that is, using Figure 7 The improved division area is used to determine the target inverter stage sector where the desired output voltage is located.

[0079] contrast Figure 6 and Figure 8 , when the target inverter level vector group is U1U3U5, and the initial inverter level sector is sector II, sector IV or sector VI, if the positive or negative change occurs in the three-phase output current corresponding to sector II, sector IV or sector VI, it will be adjusted to the sector on the adjacent side, that is, using Figure 8 The improved division area is used to determine the target inverter stage sector where the desired output voltage is located.

[0080] Step 208 : acquiring a target vector synthesis order of the target inverter stage vector group based on the target inverter stage sector and the target inverter stage vector group, and performing pulse width modulation using the target vector synthesis order and the duty cycle.

[0081] The embodiment of the present application combines the target inverter stage sector and the target inverter stage vector group. Please refer to Table 2 to obtain the target vector synthesis order of the target inverter stage vector group, adjust the initial vector synthesis order according to the target vector synthesis order corresponding to the target inverter stage sector, and use the target vector synthesis order and duty cycle to perform pulse width modulation to obtain the driving signal of each tube of the inverter stage.

[0082] In the control method of the above-mentioned third harmonic injection two-stage matrix converter, at the beginning of the switching cycle, a target inverter stage vector group of the three-phase bridge arm of the inverter stage in the target converter is obtained; the target inverter stage vector group is used to synthesize the desired output voltage; based on the target inverter stage vector group and the initial inverter stage sector where the phase of the desired output voltage is located, the initial vector synthesis order of the target inverter stage vector group is obtained; based on the initial vector synthesis order and the duty cycle of the target inverter stage vector group, the estimated output current information within the switching cycle is obtained, and the initial inverter stage sector is adjusted based on the estimated output current information to obtain the target inverter stage sector; based on the target inverter stage sector and the target inverter stage vector group, the target vector synthesis order of the target inverter stage vector group is obtained, and the target vector synthesis order and the duty cycle are used for pulse width modulation. The above method can effectively suppress the amplitude of the 3TSMC common-mode voltage; can effectively reduce the high-frequency component of the 3TSMC common-mode voltage; is simple and reliable, does not require additional hardware, and is easy to implement compared to traditional control algorithms, only changing the modulation strategy of the inverter stage, and reduces the impact of the inverter stage bridge arm dead zone on this method.

[0083] In one embodiment, Fig. 9 As shown, a control method for a third harmonic injection double-stage matrix converter is provided, comprising the following steps:

[0084] Step 902: The switching cycle starts, and an inverter stage vector group is selected according to the rectifier stage sector to which the phase of the three-phase input voltage belongs.

[0085] For example, Fig.10 As shown, when the phase of the three-phase input voltage is in the rectifier level sectors 2, 4, and 6, the target inverter level vector group U1U3U5 is selected to synthesize the desired output voltage. Fig.11 As shown, when the phase of the three-phase input voltage is in the rectification stage sectors 1, 3, and 5, the target inverter stage vector group U2U4U6 is selected to synthesize the desired output voltage.

[0086] Step 904: Determine the duty cycle of the vector and the initial synthesis order of the vector according to the phase of the desired output voltage and the initial inverter stage sector.

[0087] For example, the phase of the desired output voltage is in sector I of the initial division area of ​​the inverter stage sector, the target inverter stage vector group U2U4U6, that is, VSI is located in sector I, and the initial order of selecting the target inverter stage vector group U2U4U6 vector synthesis method is 101-110-011-110-101.

[0088] Step 906, determine the two phases with the same polarity that need to be calculated through the inverter stage sector where the phase of the desired output voltage is located, and calculate the output current of the two phases through the duty cycle of the vector and the initial order of the vector.

[0089] For example, the initial inverter stage sector is sector I, and the output current of phase A and phase B needs to be calculated through Table 1. The output current information of phase A and phase B is calculated through the duty cycle corresponding to each vector in the vector group U2U4U6 and the initial synthesis order of U2U4U6.

[0090] Due to the pulsation of the output current, the three-phase output current situation at the sector switching point will change. At this time, the common-mode voltage spike will be generated due to the dead zone effect, affecting the effect of common-mode voltage suppression. Therefore, near the sector switching point, when the positive and negative output currents of two phases in each sector change, the output current peak or valley value of these two phases is calculated in each switching cycle. When the corresponding peak value is greater than zero or the corresponding valley value is less than zero, the positive and negative output currents of the two phases change. At this time, the sector needs to be adjusted so that the influence of the dead zone effect on this method is weakened under the new sector division.

[0091] Please refer to Fig.12 , taking the target inverter level vector group U2U4U6 of the initial inverter level sector I as an example, the valley value i of the output current of phase A oamin The calculation process is shown in equations (1), (2) and (3).

[0092]

[0093]

[0094] i oamin =i oa (t0)+Δi1+Δi2

[0095]

[0096] Among them, S a , S b , S c is the upper tube drive signal of the inverter bridge arm, δ1, δ2, δ3 are the duty cycles of each inverter vector, T s is the time of a switching cycle, L a is the output filter inductance of phase A, U dc is the bus voltage, Δi1 and Δi2 are the calculated values ​​of the rise and fall of the output current of phase A, i oa is the output current of phase A, u L is the output filter inductor voltage.

[0097] Step 908: When the peak values ​​of the output currents of the two phases are greater than zero or the valley values ​​are less than zero, the sectors are adjusted.

[0098] For example, if the valley value of the output current of phase A is less than 0, sector I is adjusted to sector II; if the valley value of the output current of phase B is less than 0, sector I is adjusted to sector VI.

[0099] Step 910: determine a new vector order according to the adjusted new sector.

[0100] For example, if the valley value of the output current of phase A is less than 0, sector I is adjusted to sector II, that is, vector group U2U4U6 and VSI are located in sector II. According to Table 2, the new order is 110-101-011-101-110.

[0101] Step 912, pulse width modulation is performed using the new vector order and the duty cycle of the vector to obtain a driving signal for each tube of the inverter stage.

[0102] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0103] Based on the same inventive concept, the embodiment of the present application also provides a control device for a third harmonic injection two-stage matrix converter for implementing the control method for the third harmonic injection two-stage matrix converter involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific definition in the embodiment of one or more third harmonic injection two-stage matrix converter control devices provided below can refer to the definition of the control method for the third harmonic injection two-stage matrix converter above, and will not be repeated here.

[0104] In one embodiment, Fig.13 As shown, a control device for a third harmonic injection double-stage matrix converter is provided, comprising: an acquisition module 1302, an initial module 1304, an adjustment module 1306 and a modulation module 1308, wherein:

[0105] The acquisition module 1302 is used to acquire a target inverter level vector group of the inverter level three-phase bridge arm in the target converter at the beginning of the switching cycle; the target inverter level vector group is used to synthesize the desired output voltage.

[0106] The initial module 1304 is configured to obtain an initial vector synthesis order of the target inverter stage vector group based on the target inverter stage vector group and the initial inverter stage sector where the phase of the desired output voltage is located.

[0107] The adjustment module 1306 is used to obtain the estimated output current information within the switching cycle based on the initial vector synthesis order and the duty cycle of the target inverter stage vector group, and adjust the initial inverter stage sector based on the estimated output current information to obtain the target inverter stage sector.

[0108] The modulation module 1308 is used to obtain a target vector synthesis order of the target inverter level vector group based on the target inverter level sector and the target inverter level vector group, and perform pulse width modulation using the target vector synthesis order and the duty cycle.

[0109] Each module in the control device for the third harmonic injection double-stage matrix converter can be implemented in whole or in part by software, hardware and a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0110] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Fig.14 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data related to the third harmonic injection two-stage matrix converter. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a control method for a third harmonic injection two-stage matrix converter is implemented.

[0111] Those skilled in the art will understand that Fig.14The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0112] In one embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0113] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0114] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0115] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions.

[0116] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0117] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0118] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A control method for a third harmonic injection double-stage matrix converter, characterized in that: The method comprises: At the beginning of the switching cycle, a target inverter level vector group of the inverter level three-phase bridge arm in the target converter is obtained; the target inverter level vector group is used to synthesize the desired output voltage; Based on the target inverter stage vector group and the initial inverter stage sector where the phase of the desired output voltage is located, acquiring an initial vector synthesis order of the target inverter stage vector group; Based on the initial vector synthesis order and the duty cycle of the target inverter stage vector group, the estimated output current information within the switching cycle is acquired, and based on the estimated output current information, the initial inverter stage sector is adjusted to obtain a target inverter stage sector; Based on the target inverter stage sector and the target inverter stage vector group, a target vector synthesis order of the target inverter stage vector group is acquired, and pulse width modulation is performed using the target vector synthesis order and the duty cycle; The adjusting the initial inverter-level sector based on the estimated output current information to obtain a target inverter-level sector includes: Obtaining the positive and negative conditions of the target two-phase output current in the estimated output current information, wherein the target two-phase output current is used to indicate two-phase output currents with the same polarity among the three-phase output currents corresponding to the estimated output current information under theoretical conditions; When the target two-phase output current changes from positive to negative, the initial inverter stage sector is adjusted to obtain the target inverter stage sector.

2. The method according to claim 1, characterized in that The obtaining of the positive and negative conditions of the target two-phase output current in the estimated output current information includes: When the polarity of the target two-phase output current is positive, obtaining the valley value of the target two-phase output current; If the valley value of the target two-phase output current is less than zero, the target two-phase output current changes positively or negatively.

3. The method according to claim 1, characterized in that The obtaining of the positive and negative conditions of the target two-phase output current in the estimated output current information includes: When the polarity of the target two-phase output current is negative, obtaining the peak value of the target two-phase output current; If the peak value of the target two-phase output current is greater than zero, the target two-phase output current changes positively or negatively.

4. The method according to any one of claims 1 to 3, characterized in that: When the target two-phase output current changes from positive to negative, the initial inverter level sector is adjusted to obtain the target inverter level sector, including: When the target two-phase output current changes from positive to negative, the initial inverter stage sector is adjusted to the inverter stage sector on the adjacent side in combination with the phase of the desired output voltage to obtain the target inverter stage sector.

5. The method according to claim 1, characterized in that The initial inverter-level sector is obtained by the following steps: Obtain the original partition area corresponding to the inverter-level sector; Rotate the original divided area counterclockwise by the impedance angle of the load to obtain the initial divided area corresponding to the inverter stage sector; The initial inverter stage sector is determined from the initial division area of ​​the inverter stage sector by the phase of the desired output voltage.

6. A control device for a third harmonic injection double-stage matrix converter, characterized in that: The device comprises: An acquisition module, used for acquiring a target inverter level vector group of the inverter level three-phase bridge arm in the target converter at the beginning of a switching cycle; the target inverter level vector group is used for synthesizing a desired output voltage; An initial module, configured to obtain an initial vector synthesis order of the target inverter stage vector group based on the target inverter stage vector group and an initial inverter stage sector where the phase of the desired output voltage is located; an adjustment module, configured to obtain estimated output current information within the switching cycle based on the initial vector synthesis order and the duty cycle of the target inverter stage vector group, and adjust the initial inverter stage sector based on the estimated output current information to obtain a target inverter stage sector; a modulation module, configured to obtain a target vector synthesis order of the target inverter stage vector group based on the target inverter stage sector and the target inverter stage vector group, and perform pulse width modulation using the target vector synthesis order and the duty cycle; The adjustment module is also used for: Obtaining the positive and negative conditions of the target two-phase output current in the estimated output current information, wherein the target two-phase output current is used to indicate two-phase output currents with the same polarity among the three-phase output currents corresponding to the estimated output current information under theoretical conditions; When the target two-phase output current changes from positive to negative, the initial inverter stage sector is adjusted to obtain the target inverter stage sector.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 5 are implemented.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

9. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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