A method for processing a silicon wafer and a silicon wafer

Abstract

The present application discloses a silicon wafer processing method and a silicon wafer. The silicon wafer processing method is used to process a silicon wafer to be processed, and the silicon wafer processing method includes: performing a first annealing treatment on the silicon wafer, the first annealing treatment having a first annealing temperature T1 and a first annealing time t1; performing a second annealing treatment on the silicon wafer that has undergone the first annealing treatment, the second annealing treatment having a second annealing temperature T2 and a second annealing time t2; satisfying: T1≥T2, t2>t1. By performing two annealing treatments on the silicon wafer to be processed during the silicon wafer processing process and controlling the temperature of the first annealing treatment to be greater than or equal to the temperature of the second annealing treatment and the time of the first annealing treatment to be less than the time of the second annealing treatment, the influence of the thermal history of the head and tail of the silicon wafer can be eliminated, and the oxygen precipitation of the silicon wafer can be controlled within a certain range under the condition of little difference in oxygen content.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and particularly relates to a silicon wafer processing method and a silicon wafer. Background Art

[0002] With the rapid development of current integrated circuits towards larger diameters, smaller feature line widths, and higher integration levels, the production process of integrated circuits has become increasingly complex. A mature complementary metal oxide semiconductor (CMOS) production process has hundreds of steps. Inevitably, impurities and defects such as metal contamination are introduced during the subsequent processing of silicon wafers. Therefore, the internal gettering process becomes particularly important. The internal gettering process mainly relies on oxygen precipitation (BMD) to achieve, and it has two specific functions: one is that oxygen precipitation serves as the core for impurity precipitation; the other is that oxygen precipitation introduces a stress field within the silicon lattice, thereby causing impurities to rapidly diffuse around the oxygen precipitation, so as to achieve the purpose of reducing or even eliminating metal impurities on the silicon wafer surface, and greatly improving the device quality. Research shows that high-temperature argon annealing can not only effectively eliminate the native defects in the near-surface region of the silicon wafer, but also form oxygen precipitation inside to improve the internal gettering ability of the silicon wafer, thereby improving the silicon wafer quality. However, the generation of oxygen precipitation is a very complex problem, which not only involves the single-crystal native thermal history, the initial oxygen concentration, but also has a great relationship with the vacancy concentration in the single crystal. If the BMD density is too high, there is a risk of leakage; if the BMD density is too low, it cannot play the role of gettering. This makes it an urgent problem to be solved currently on how to control the oxygen precipitation within a certain range. Summary of the Invention

[0003] The purpose of this application is to provide a silicon wafer processing method, which can eliminate the influence of the head and tail thermal history of the silicon wafer and control the oxygen precipitation of the silicon wafer within a certain range when the oxygen content difference is not significant.

[0004] An embodiment of this application provides a silicon wafer processing method for processing a silicon wafer to be processed. The silicon wafer processing method includes:

[0005] Performing a first annealing treatment on the silicon wafer. The first annealing treatment has a first annealing temperature T1 and a first annealing time t1;

[0006] Performing a second annealing treatment on the silicon wafer that has undergone the first annealing treatment. The second annealing treatment has a second annealing temperature T2 and a second annealing time t2;

[0007] Satisfying: T1≥T2, t2>t1.

[0008] In some embodiments, performing the first annealing treatment on the silicon wafer includes:

[0009] Place the silicon wafer in the first annealing furnace;

[0010] Introduce inert gas and oxygen into the first annealing furnace;

[0011] Heat the first annealing furnace from the first temperature T3 to the first annealing temperature T1 at the first heating rate V1 to perform the first annealing treatment on the silicon wafer.

[0012] In some embodiments, after performing the first annealing treatment on the silicon wafer, it further includes:

[0013] Cool the first annealing furnace from the first annealing temperature T1 to the second temperature T4 at the first cooling rate V2.

[0014] In some embodiments, the range of the first temperature T3 is 500 - 700 °C; and / or,

[0015] The range of the second temperature T4 is 500 - 700 °C; and / or,

[0016] The range of the first heating rate V1 is 50 - 60 °C / s; and / or,

[0017] The range of the first cooling rate V2 is 50 - 60 °C / s; and / or,

[0018] The flow rate range of the inert gas is 30 - 40 slm; and / or,

[0019] The density range of the oxygen is 3000 - 5000 ppm.

[0020] In some embodiments, the range of the first annealing temperature T1 is 1100 - 1250 °C; and / or,

[0021] The range of the second annealing temperature T2 is 1100 - 1250 °C; and / or,

[0022] The range of the first annealing time t1 is 10 - 15 s; and / or,

[0023] The range of the second annealing time t2 is 3000 - 4000 s; and / or,

[0024] The range of the first annealing temperature T1 is 1200 - 1250 °C, and the range of the second annealing temperature T2 is 1100 - 1200 °C.

[0025] In some embodiments, performing the second annealing treatment on the silicon wafer that has undergone the first annealing treatment includes:

[0026] Place the silicon wafer that has undergone the first annealing treatment in a second annealing furnace;

[0027] Introduce an inert gas into the second annealing furnace;

[0028] Heat the second annealing furnace from a third temperature T5 to the second annealing temperature T2 at a second heating rate V3 to perform a second annealing treatment on the silicon wafer.

[0029] In some embodiments, after performing the second annealing treatment on the silicon wafer, it further includes:

[0030] Cool the second annealing furnace from the second annealing temperature T2 to the fourth temperature T6 at a second cooling rate V4.

[0031] In some embodiments, the range of the third temperature T5 is 500 - 700 °C; and / or,

[0032] The range of the fourth temperature T6 is 500 - 700 °C; and / or,

[0033] The range of the second heating rate V3 is 1 - 7.5 °C / s; and / or,

[0034] The range of the second cooling rate V4 is 1 - 5 °C / s; and / or,

[0035] The flow rate range of the inert gas is 5 - 10 slm.

[0036] In some embodiments, before performing the first annealing treatment on the silicon wafer, it further includes:

[0037] Perform a first cleaning on the silicon wafer using a first cleaning solution, a second cleaning solution, and hydrofluoric acid;

[0038] Wherein, the first cleaning solution includes ammonia water, hydrogen peroxide, and deionized water, and the mass ratio of the ammonia water, the hydrogen peroxide, and the deionized water is 1 - 4:2 - 5:10 - 18; and / or,

[0039] The second cleaning solution includes hydrochloric acid, hydrogen peroxide, and deionized water, and the mass ratio of the hydrochloric acid, the hydrogen peroxide, and the deionized water is 1 - 4:2 - 5:10 - 18; and / or,

[0040] The hydrofluoric acid includes hydrogen fluoride and deionized water, and the mass ratio of the hydrogen fluoride and the deionized water is 1:6.

[0041] In some embodiments, after performing the first annealing treatment on the silicon wafer, it further includes:

[0042] The silicon wafer is subjected to a second cleaning using ozone water, hydrofluoric acid, a third cleaning solution, and a fourth cleaning solution, wherein the concentration of the ozone water is 10 to 40 ppm; and / or,

[0043] The hydrofluoric acid includes hydrogen fluoride and deionized water, and the mass ratio of the hydrogen fluoride to the deionized water is 0.2 to 1:10 to 40; and / or,

[0044] The third cleaning solution includes ammonia water, hydrogen peroxide, and deionized water, and the mass ratio of the ammonia water, the hydrogen peroxide, and the deionized water is 1 to 5:3 to 6:50 to 80; and / or,

[0045] The fourth cleaning solution includes hydrochloric acid, hydrogen peroxide, and deionized water, and the mass ratio of the hydrochloric acid, the hydrogen peroxide, and the deionized water is 0.02 to 0.1:0.02 to 0.1:10 to 40.

[0046] In some embodiments, between the first annealing treatment and the second annealing treatment, it further includes:

[0047] The silicon wafer is polished to obtain a polished wafer.

[0048] In some embodiments, the oxygen content of the silicon wafer to be processed is 12.26 to 12.99 ppma.

[0049] Correspondingly, the present application also provides a silicon wafer, which is prepared by the processing method as described above, and the density range of the bulk microdefects of the silicon wafer is 1.09E9 to 1.43E9 ea / cm 3 .

[0050] The beneficial effects of the present application are as follows:

[0051] The present application provides a silicon wafer processing method. By annealing the silicon wafer to be processed twice during the silicon wafer processing, and controlling that the temperature of the first annealing treatment is greater than or equal to the temperature of the second annealing treatment, and the time of the first annealing treatment is less than the time of the second annealing treatment, the influence of the thermal history of the head and tail of the silicon wafer can be eliminated, and the oxygen precipitation of the silicon wafer can be controlled within a certain range under the condition of little difference in oxygen content.

[0052] The present application also provides a silicon wafer, which can eliminate the influence of the thermal history of the head and tail of the silicon wafer and control the oxygen precipitation of the silicon wafer within a certain range under the condition of little difference in oxygen content. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 is a flowchart of the silicon wafer processing method provided by the present application;

[0054] Figure 2Schematic diagram of the microstructure of the head of the silicon wafer provided in Embodiment 1 of the present application;

[0055] Figure 3 Schematic diagram of the microstructure of the tail of the silicon wafer provided in Embodiment 1 of the present application;

[0056] Figure 4 Schematic diagram of the microstructure of the head of the silicon wafer provided in Comparative Example 1 of the present application;

[0057] Figure 5 Schematic diagram of the microstructure of the tail of the silicon wafer provided in Comparative Example 1 of the present application. Detailed implementation manners

[0058] The technical solutions of the present application will be clearly and completely described below in conjunction with the embodiments and drawings of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of the present application. The various embodiments of the present application may exist in the form of a range; it should be understood that the description in the form of a range is only for convenience and simplicity, and should not be construed as a rigid limitation on the scope of the present application; therefore, it should be considered that the described range description has specifically disclosed all possible sub-ranges and single values within that range. For example, it should be considered that the range description from 1 to 6 has specifically disclosed sub-ranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., and single numbers within the counted range, such as 1, 2, 3, 4, 5, and 6, which applies regardless of the range. Additionally, whenever a numerical range is indicated herein, it means including any cited number (fraction or integer) within the indicated range.

[0059] As Figure 1 shown, a silicon wafer processing method for processing a silicon wafer to be processed, the silicon wafer processing method includes:

[0060] Step S1: Anneal the silicon wafer for the first time, the first annealing treatment has a first annealing temperature T1, and the first annealing treatment has a first annealing time t1;

[0061] Step S2: Anneal the silicon wafer that has undergone the first annealing treatment for the second time, the second annealing treatment has a second annealing temperature T2, and the second annealing treatment has a second annealing time t2;

[0062] Satisfy: T1≥T2, t2>t1.

[0063] It can be understood that in the present application, by performing two annealing treatments on the silicon wafer to be processed during the silicon wafer processing, and controlling the temperature of the first annealing treatment to be greater than or equal to the temperature of the second annealing treatment, and the time of the first annealing treatment to be less than the time of the second annealing treatment, the influence of the thermal history of the head and tail of the silicon wafer can be eliminated, and the oxygen precipitation of the silicon wafer can be controlled within a certain range when the oxygen content difference is not significant.

[0064] In some embodiments, performing the first annealing treatment on the silicon wafer includes:

[0065] Step S11: Place the silicon wafer in the first annealing furnace;

[0066] Step S12: Introduce an inert gas and oxygen into the first annealing furnace;

[0067] Step S13: Heat the first annealing furnace from the first temperature T3 to the first annealing temperature T1 at the first heating rate V1 to perform the first annealing treatment on the silicon wafer. Specifically, the model of the first annealing furnace is Helios C200; the inert gas is argon with a purity of 99.999%; the purity of oxygen is 99.9%; the first temperature T3 is the standby temperature of the first annealing furnace.

[0068] It can be understood that in the present application, by performing the first annealing treatment on the silicon wafer in the first annealing furnace and introducing an inert gas and oxygen during the first annealing treatment, under the protection of the inert gas, when the temperature reaches 1200 - 1250 °C, the primary nuclei of the crystal are almost completely melted, and at this temperature, the equilibrium concentration of vacancies is higher than that of interstitials, and at the same time, the diffusion rate of interstitials is much higher than that of vacancies. During the time when the temperature is constant, interstitials will preferentially diffuse to the surface of the silicon wafer and combine with the vacancies on the surface of the silicon wafer. At the same time, in the oxygen atmosphere, interstitial atoms will also be injected from the surface of the silicon wafer, resulting in a large amount of recombination of interstitials and vacancies on the surface of the silicon wafer, greatly reducing the vacancies, and thus forming a concentration difference of vacancies on the surface and inside of the silicon wafer.

[0069] In some embodiments, after performing the first annealing treatment on the silicon wafer, it further includes:

[0070] Step S14: Cool the first annealing furnace from the first annealing temperature T1 to the second temperature T4 at the first cooling rate V2. Specifically, the second temperature T4 is the standby temperature of the first annealing furnace.

[0071] It can be understood that after the first annealing treatment, a concentration difference of vacancies is formed on the surface and inside of the silicon wafer. Due to the existence of the concentration difference, the vacancies are driven to diffuse towards the surface. However, by cooling the first annealing furnace from the first annealing temperature T1 to the second temperature T4, rapid cooling is achieved, so that most of the vacancies remain inside the silicon wafer, and finally a vacancy template with a certain concentration is formed. At the same time, the rapid cooling also reduces the stress concentration of the silicon wafer.

[0072] In some embodiments, the range of the first temperature T3 is 500 - 700 °C. Specifically, the first temperature T3 is one of 500 °C, 550 °C, 600 °C, 650 °C, 700 °C or a range composed of two of them.

[0073] In some embodiments, the range of the second temperature T4 is 500 - 700 °C. Specifically, the second temperature T4 is one of 500 °C, 550 °C, 600 °C, 650 °C, 700 °C or a range composed of two of them.

[0074] The first temperature T3 and the second temperature T4 can be the same or different.

[0075] In some embodiments, the range of the first heating rate V1 is 50 - 60 °C / s. Specifically, the first heating rate V1 is one of 50 °C / s, 51 °C / s, 52 °C / s, 53 °C / s, 54 °C / s, 55 °C / s, 56 °C / s, 57 °C / s, 58 °C / s, 59 °C / s, 60 °C / s or a range composed of two of them.

[0076] It can be understood that in this application, by controlling the first annealing furnace to heat up from the standby temperature to the first annealing temperature T1 at the first heating rate V1, the stress concentration of the silicon wafer can be reduced.

[0077] In some embodiments, the range of the first cooling rate V2 is 50 - 60 °C / s. Specifically, the first cooling rate V2 is one of 50 °C / s, 51 °C / s, 52 °C / s, 53 °C / s, 54 °C / s, 55 °C / s, 56 °C / s, 57 °C / s, 58 °C / s, 59 °C / s, 60 °C / s or a range composed of two of them.

[0078] It can be understood that in this application, by controlling the first annealing furnace to cool down from the first annealing temperature T1 to the standby temperature at the first cooling rate V2, while reducing the stress concentration of the silicon wafer, it can ensure that most of the vacancies remain inside the silicon wafer, and finally a vacancy template with a certain concentration is formed.

[0079] In some embodiments, the flow rate range of the inert gas is 30 to 40 slm. Specifically, the flow rate range of the inert gas is one or a range composed of two of 30 slm, 31 slm, 32 slm, 33 slm, 34 slm, 35 slm, 36 slm, 37 slm, 38 slm, 39 slm, 40 slm. The inert gas is argon.

[0080] In some embodiments, the flow rate range of oxygen is 3000 to 5000 slm. Specifically, the flow rate of oxygen is one or a range composed of two of 3000 slm, 3500 slm, 4000 slm, 4500 slm, 5000 slm.

[0081] In some embodiments, the range of the first annealing temperature T1 is 1100 to 1250 °C. Specifically, the first annealing temperature T1 is one or a range composed of two of 1100 °C, 1110 °C, 1120 °C, 1130 °C, 1140 °C, 1150 °C, 1160 °C, 1170 °C, 1180 °C, 1190 °C, 1200 °C, 1210 °C, 1220 °C, 1230 °C, 1240 °C, 1250 °C.

[0082] It can be understood that when the temperature reaches 1200 to 1250 °C, the primary nuclei of the crystal are almost completely melted. At this temperature, the equilibrium concentration of vacancies is higher than that of interstitial atoms, and at the same time, the diffusion rate of interstitial atoms is much higher than that of vacancies. During the time when the temperature is constant, interstitial atoms will preferentially diffuse to the surface of the silicon wafer and combine with the vacancies on the surface of the silicon wafer, resulting in a large amount of recombination of interstitial atoms and vacancies on the surface of the silicon wafer, greatly reducing the vacancies, and thus forming a concentration difference of vacancies on the surface and inside of the silicon wafer.

[0083] In some embodiments, the range of the second annealing temperature T2 is 1100 to 1250 °C. Specifically, the second annealing temperature T2 is one or a range composed of two of 1100 °C, 1110 °C, 1120 °C, 1130 °C, 1140 °C, 1150 °C, 1160 °C, 1170 °C, 1180 °C, 1190 °C, 1200 °C, 1210 °C, 1220 °C, 1230 °C, 1240 °C, 1250 °C.

[0084] It can be understood that by performing a second annealing treatment on the silicon wafer at the second annealing temperature T2, where the range of the second annealing temperature T2 is 1100 to 1250 °C, the temperature for BMD growth can be provided to enable the already nucleated BMD to continue to grow and thus stably exist.

[0085] In some embodiments, the range of the first annealing time t1 is 10 to 15 s. Specifically, the first annealing time t1 is one of 10 s, 11 s, 12 s, 13 s, 14 s, 15 s or a range composed of one of them and the other.

[0086] It can be understood that if the first annealing time t1 is too short, the interstitial cannot reach the silicon wafer surface and cannot recombine with the vacancies on the silicon wafer surface, and a vacancy concentration difference cannot be formed on the silicon wafer surface and inside. Similarly, if the first annealing time t1 is too long, the vacancies inside the silicon wafer will also diffuse to the silicon wafer surface, and a vacancy concentration difference cannot be formed on the silicon wafer surface and inside either.

[0087] In some embodiments, the range of the second annealing time t2 is 3000 to 4000 s. Specifically, the second annealing time t2 is one of 3000 s, 3200 s, 3400 s, 3600 s, 3800 s, 4000 s or a range composed of one of them and the other.

[0088] It can be understood that the second annealing time t2 is the time for BMD growth and stabilization. When the second annealing time t2 is too short, BMD cannot grow and the quantity is insufficient to reach stabilization. When the second annealing time t2 is too long, more metals will diffuse into the silicon wafer body, resulting in poor bulk metal.

[0089] In some embodiments, subjecting the silicon wafer that has undergone the first annealing treatment to a second annealing treatment includes:

[0090] Step S21: Place the silicon wafer that has undergone the first annealing treatment in a second annealing furnace;

[0091] Step S22: Introduce an inert gas into the second annealing furnace;

[0092] Step S23: Heat the second annealing furnace from a third temperature T5 to a second annealing temperature T2 at a second heating rate V3 to perform a second annealing treatment on the silicon wafer. Specifically, the inert gas is argon, and the purity of argon is 99.999%. Specifically, the third temperature T5 is the standby temperature of the second annealing furnace. The model of the second annealing furnace is DD-853V-8BL3.

[0093] In some embodiments, after performing the second annealing treatment on the silicon wafer, it further includes:

[0094] Step S24: Cool the second annealing furnace from the second annealing temperature T2 to a fourth temperature T6 at a second cooling rate V4. Specifically, the fourth temperature T6 is the standby temperature of the second annealing furnace.

[0095] It can be understood that after the second annealing treatment is completed, the second annealing furnace is cooled from the second annealing temperature T2 to the fourth temperature T6 at the second cooling rate V4, which can reduce the stress concentration of the silicon wafer and prevent the generation of slip lines (Slip).

[0096] In some embodiments, the range of the third temperature T5 is 500 - 700 °C. Specifically, the third temperature T5 is one of 500 °C, 550 °C, 600 °C, 650 °C, 700 °C or the range composed of one or both of them.

[0097] In some embodiments, the range of the fourth temperature T6 is 500 - 700 °C. Specifically, the fourth temperature T6 is one of 500 °C, 550 °C, 600 °C, 650 °C, 700 °C or the range composed of one or both of them.

[0098] It can be understood that the third temperature T5 and the fourth temperature T6 can be the same or different.

[0099] In some embodiments, the range of the second heating rate V3 is 1 - 7.5 °C / s. Specifically, the second heating rate V3 is one of 1 °C / s, 2 °C / s, 3 °C / s, 4 °C / s, 5 °C / s, 6 °C / s, 7 °C / s, 7.5 °C / s or the range composed of one or both of them.

[0100] It can be understood that in this application, by controlling the second annealing furnace to heat up from the standby temperature to the second annealing temperature T2 at the second heating rate V3, while reducing the stress concentration of the silicon wafer, the time for BMD nucleation can be guaranteed, so that BMD can nucleate on the formed vacancy template.

[0101] In some embodiments, the range of the second cooling rate V4 is 1 - 5 °C / s. Specifically, the second heating rate V3 is one of 1 °C / s, 2 °C / s, 3 °C / s, 4 °C / s, 5 °C / s or the range composed of one or both of them.

[0102] It can be understood that in this application, by controlling the second annealing furnace to cool down from the second annealing temperature T2 to the standby temperature at the second cooling rate V4, the stress concentration of the silicon wafer can be reduced.

[0103] In some embodiments, the flow rate range of the inert gas is 5 - 10 slm. Specifically, the flow rate range of the inert gas is one of 5 slm, 6 slm, 7 slm, 8 slm, 9 slm, 10 slm or the range composed of one or both of them.

[0104] It can be understood that by introducing an inert gas during the second annealing treatment and controlling the flow rate range of the inert gas to be 5 - 10 slm, the stability of the furnace pressure and furnace temperature in the second annealing furnace can be ensured.

[0105] In some embodiments, before the silicon wafer is subjected to the first annealing treatment, the following steps are further included:

[0106] The silicon wafer is subjected to the first cleaning using a first cleaning solution, a second cleaning solution, and hydrofluoric acid;

[0107] Wherein, the first cleaning solution includes ammonia water, hydrogen peroxide, and deionized water, and the mass ratio of ammonia water, hydrogen peroxide, and deionized water is 1-4: 2-5: 10-18.

[0108] Specifically, the mass ratio of ammonia water, hydrogen peroxide, and deionized water is one of 1:2:10, 2:3:12, 3:4:14, 4:5:16 or a range composed of two of them. Specifically, the ammonia water is of analytical purity with a content of 28%-30%; the hydrogen peroxide is of analytical purity with a content of 30%-32%; the equipment for the first cleaning is a Pre-cvd cleaning machine.

[0109] It can be understood that by performing the first cleaning on the silicon wafer before the first annealing, impurities on the surface of the silicon wafer can be removed, the cleanliness of the silicon wafer can be improved, and the first annealing furnace can be prevented from being contaminated during the first annealing treatment.

[0110] In some embodiments, the second cleaning solution includes hydrochloric acid, hydrogen peroxide, and deionized water, and the mass ratio of hydrochloric acid, hydrogen peroxide, and deionized water is 1-4: 2-5: 10-18. Specifically, it is one of 1:2:10, 2:3:12, 3:4:14, 3:4:14, 4:5:16 or a range composed of two of them. Specifically, the hydrochloric acid is of analytical purity with a content of 35%-38%.

[0111] In some embodiments, the hydrofluoric acid includes hydrogen fluoride and deionized water, and the mass ratio of hydrogen fluoride and deionized water is 1:6. Specifically, the hydrofluoric acid is of analytical purity with a concentration of 49%.

[0112] In some embodiments, when the first cleaning solution and the second cleaning solution are used for cleaning, the temperature is 60-80°C, and the cleaning time is 300-500s respectively. When hydrofluoric acid is used for cleaning, the temperature is 25-28°C, and the cleaning time is 300-500s.

[0113] It can be understood that the first cleaning solution can remove contaminants such as chemical residue and impurities on the surface of the silicon wafer. The second cleaning solution can remove contaminants such as metal residue and impurities on the surface of the silicon wafer. Hydrofluoric acid can remove the oxide film on the surface of the silicon wafer.

[0114] In some embodiments, after the silicon wafer is subjected to the first annealing treatment, the following steps are further included:

[0115] The silicon wafer is subjected to a second cleaning using ozone water, hydrofluoric acid, a third cleaning solution, and a fourth cleaning solution. Among them, the concentration of the ozone water is 10 to 40 ppm. Specifically, the concentration of the ozone water is one of 10 ppm, 20 ppm, 30 ppm, 40 ppm or a range composed of two of them. Specifically, the hydrofluoric acid is of analytical purity and has a concentration of 49%. The equipment for the second cleaning is an SCC final cleaning machine.

[0116] It can be understood that by subjecting the silicon wafer to a second cleaning before the second annealing, impurities on the surface of the silicon wafer can be removed, the cleanliness of the silicon wafer can be improved, and the second annealing furnace can be prevented from being contaminated during the second annealing process.

[0117] In some embodiments, the hydrofluoric acid includes hydrogen fluoride and deionized water, and the mass ratio of hydrogen fluoride to deionized water is 0.2 to 1:10 to 40. Specifically, it is one of 0.2:10, 0.5:35, 1:40 or a range composed of two of them. Specifically, the hydrofluoric acid is of analytical purity and has a concentration of 49%.

[0118] In some embodiments, the third cleaning solution includes ammonia water, hydrogen peroxide, and deionized water, and the mass ratio of ammonia water, hydrogen peroxide, and deionized water is 1 to 5:3 to 6:50 to 80. Specifically, it is one of 1:3:50, 2:4:60, 3:4:70, 4:5:80, 5:6:80 or a range composed of two of them. Specifically, the ammonia water is of analytical purity and has a content of 28% - 30%; the hydrogen peroxide is of analytical purity and has a content of 30% - 32%.

[0119] In some embodiments, the fourth cleaning solution includes hydrochloric acid, hydrogen peroxide, and deionized water, and the mass ratio of hydrochloric acid, hydrogen peroxide, and deionized water is 0.02 to 0.1:0.02 to 0.1:10 to 40. Specifically, the hydrochloric acid is of analytical purity and has a content of 35% - 38%; the hydrogen peroxide is of analytical purity and has a content of 30% - 32%.

[0120] In some embodiments, the temperature during the ozone water cleaning is 25 to 28 °C, and the cleaning time is 300 to 500 s. The temperature during the hydrofluoric acid cleaning is 25 to 28 °C, and the cleaning time is 300 to 500 s. The temperature during the third cleaning solution cleaning is 30 to 50 °C, and the cleaning time is 300 to 500 s. The temperature during the fourth cleaning solution cleaning is 30 to 50 °C, and the cleaning time is 300 to 500 s.

[0121] It can be understood that the ozone water can adjust the oxide film on the surface of the silicon wafer. The hydrofluoric acid can remove the oxide film on the surface of the silicon wafer. The third cleaning solution can remove contaminants such as residual liquid medicine and impurities on the surface of the silicon wafer. The fourth cleaning solution can remove contaminants such as metal residues and impurities on the surface of the silicon wafer.

[0122] In some embodiments, between the first annealing treatment and the second annealing treatment, the following steps are further included:

[0123] Step S3: Polish the silicon wafer to obtain a polished wafer.

[0124] After the silicon wafer is polished, the thickness of the silicon wafer is 700 - 750 um. Specifically, the thickness of the silicon wafer can be any one of 700 um, 705 um, 710 um, 715 um, 720 um, 725 um, 730 um, 735 um, 740 um, 745 um, 750 um or the range composed of any two of them.

[0125] In some embodiments, the oxygen content of the silicon wafer to be processed is 12.26 - 12.99 ppma. Specifically, the oxygen content of the silicon wafer to be processed is one of 12.26 ppma, 12.36 ppma, 12.46 ppma, 12.56 ppma, 12.66 ppma, 12.76 ppma, 12.86 ppma, 12.99 ppma or the range composed of any two of them.

[0126] It can be understood that when the oxygen content of the silicon wafer to be processed is controlled to be 12.26 - 12.99 ppma, the density range of the bulk microdefects of the prepared silicon wafer is 1.09E9 - 1.43E9 ea / cm 3 .

[0127] Correspondingly, the present application also provides a silicon wafer, which is prepared by the processing method as described above, and the density range of the bulk microdefects of the silicon wafer is 1.09E9 - 1.43E9 ea / cm 3 . Specifically, the density range of the bulk microdefects of the silicon wafer is 1.09E9 ea / cm 3 , 1.19E9 ea / cm 3 , 1.29E9 ea / cm 3 , 1.39E9 ea / cm 3 , 1.43E9 ea / cm 3 or the range composed of any two of them.

[0128] It can be understood that the present application provides a process with a small difference in initial oxygen content, and even with different thermal histories, a stable BMD density can be obtained; compared with the process with only the second annealing, the silicon wafer obtained by using the two - step annealing process of the present application has a stable BMD density.

[0129] The following is illustrated with specific embodiments.

[0130] Example 1

[0131] Place the silicon wafer in the first annealing furnace;

[0132] Ar and O₂ are introduced into the first annealing furnace, with the flow rate of Ar being 35 slm and the flow rate of O₂ being 4000 slm.

[0133] The first annealing furnace is heated from 600 °C to the first annealing temperature T1 at the first heating rate V1, and the silicon wafer is subjected to the first annealing treatment. The first heating rate V1 is 55 °C / s, the first annealing temperature T1 is 1180 °C, and the first annealing time t1 is 13 s.

[0134] After the first annealing treatment, the first annealing furnace is cooled from the first annealing temperature T1 to 600 °C at the first cooling rate V2.

[0135] The silicon wafer after the first annealing treatment is polished.

[0136] The polished silicon wafer is placed in the second annealing furnace.

[0137] Ar is introduced into the second annealing furnace, with the flow rate of Ar being 8 slm.

[0138] The second annealing furnace is heated from 600 °C to the second annealing temperature T2 at the second heating rate V3, and the silicon wafer is subjected to the second annealing treatment. The second heating rate V3 is 55 °C / s, the second annealing temperature T2 is 1180 °C, and the second annealing time t2 is 3500 s.

[0139] After the second annealing treatment, the second annealing furnace is cooled from the second annealing temperature T2 to 600 °C at the second cooling rate V4 to obtain the processed silicon wafer. Please refer to Figures 2 - 3 .

[0140] Comparative Example 1

[0141] The difference between Comparative Example 1 and Example 1 is that Comparative Example 1 does not undergo the first annealing treatment to obtain the processed silicon wafer. Please refer to Figures 4 - 5 .

[0142] Testing method for BMD

[0143] The silicon wafers processed in Example 1 and Comparative Example 1 are placed in a BMD tester with the model number LST2500. First, the silicon wafers are kept at 780 °C for 180 minutes; then, the silicon wafers are kept at 1000 °C for 960 minutes for BMD testing.

[0144] Table 1 shows the parameter settings and test results of Example 1 and Comparative Example 1

[0145]

[0146] Table 2 shows the test results of the BMD concentrations in Example 1 and Comparative Example 1.

[0147]

[0148]

[0149] Result analysis:

[0150] From the test results of Example 1, Comparative Example 1, and Tables 1-2, it can be seen that on the premise that the initial oxygen content of the silicon wafers has little difference, the BMD difference between the head and tail single-crystal silicon wafers obtained only by the second annealing is extremely large. Because the thermal history of the single-crystal head silicon wafer is longer and the thermal history of the single-crystal tail silicon wafer is shorter, the BMD of the head is usually higher than that of the tail and cannot be stabilized within a certain range; while the BMD of the head and tail single-crystal silicon wafers obtained by the first annealing and the second annealing has almost no difference. This is because through the first annealing treatment, a certain amount of vacancy templates are provided, and during the second annealing, BMD nucleates and grows at the vacancy templates, thus obtaining a BMD concentration stabilized within a certain range.

[0151] The above has introduced this application in detail. Specific examples are used in this article to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application; at the same time, for those skilled in the art, according to the idea of this application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to this application.

Claims

1. A method for processing a silicon wafer, characterized in that, For processing a silicon wafer to be processed, the silicon wafer processing method includes: Performing a first annealing treatment on the silicon wafer to provide a vacancy template, the first annealing treatment having a first annealing temperature T1 and a first annealing time t1; Performing the first annealing treatment on the silicon wafer includes: Placing the silicon wafer in a first annealing furnace; Introducing an inert gas and oxygen into the first annealing furnace; Heating the first annealing furnace from a first temperature T3 to the first annealing temperature T1 to perform the first annealing treatment on the silicon wafer; The silicon wafer that has undergone the first annealing treatment is subjected to a second annealing treatment to nucleate and grow bulk microdefects at the vacancy template, and the density range of the bulk microdefects is 1.09E9 - 1.43E9 ea / cm 3 , the second annealing treatment has a second annealing temperature T2, and the second annealing treatment has a second annealing time t2; Satisfying: T1≥T2, t2>t1; The range of the first annealing temperature T1 is 1100-1250°C; The range of the second annealing temperature T2 is 1100-1250°C; The range of the first annealing time t1 is 10-15 s; The range of the second annealing time t2 is 3000-4000 s; After performing the first annealing treatment on the silicon wafer, it further includes: Cooling the first annealing furnace from the first annealing temperature T1 to a second temperature T4 at a first cooling rate V2 to form a concentration difference of vacancy templates on the surface and inside of the silicon wafer.

2. The silicon wafer processing method according to claim 1, wherein The range of the first temperature T3 is 500-700°C; and / or, The range of the second temperature T4 is 500-700°C; and / or, The first annealing furnace is heated from the first temperature T3 to the first annealing temperature T1 at a first heating rate V1, and the range of the first heating rate V1 is 50-60°C / s; and / or, The range of the first cooling rate V2 is 50-60°C / s; and / or, The flow rate range of the inert gas is 30-40 slm; and / or, The density range of the oxygen is 3000-5000 ppm.

3. The silicon wafer processing method according to claim 1, wherein The range of the first annealing temperature T1 is 1200-1250°C, and the range of the second annealing temperature T2 is 1100-1200°C.

4. The silicon wafer processing method according to claim 1, characterized in that, Performing a second annealing treatment on the silicon wafer that has undergone the first annealing treatment includes: Placing the silicon wafer that has undergone the first annealing treatment in a second annealing furnace; Introducing an inert gas into the second annealing furnace; Heating the second annealing furnace from a third temperature T5 to the second annealing temperature T2 at a second heating rate V3 to perform the second annealing treatment on the silicon wafer.

5. The silicon wafer processing method according to claim 4, wherein After performing the second annealing treatment on the silicon wafer, it further includes: Cooling the second annealing furnace from the second annealing temperature T2 to a fourth temperature T6 at a second cooling rate V4.

6. The silicon wafer processing method according to claim 5, wherein The range of the third temperature T5 is 500-700°C; and / or, The range of the fourth temperature T6 is 500-700°C; and / or, The range of the second heating rate V3 is 1-7.5°C / s; and / or, The range of the second cooling rate V4 is 1-5°C / s; and / or, The flow rate range of the inert gas is 5 - 10 slm.

7. The silicon wafer processing method according to claim 1, wherein Before the first annealing treatment of the silicon wafer, it further includes: Performing a first cleaning on the silicon wafer with a first cleaning solution, a second cleaning solution, and hydrofluoric acid; wherein, the first cleaning solution includes ammonia water, hydrogen peroxide, and deionized water, and the mass ratio of the ammonia water, the hydrogen peroxide, and the deionized water is 1 - 4:2 - 5:10 - 18; and / or, the second cleaning solution includes hydrochloric acid, hydrogen peroxide, and deionized water, and the mass ratio of the hydrochloric acid, the hydrogen peroxide, and the deionized water is 1 - 4:2 - 5:10 - 18; and / or, the hydrofluoric acid includes hydrogen fluoride and deionized water, and the mass ratio of the hydrogen fluoride and the deionized water is 1:

6.

8. The silicon wafer processing method according to claim 1, characterized in that After the first annealing treatment of the silicon wafer, it further includes: Performing a second cleaning on the silicon wafer with ozone water, hydrofluoric acid, a third cleaning solution, and a fourth cleaning solution, wherein the concentration of the ozone water is 10 - 40 ppm; and / or, the hydrofluoric acid includes hydrogen fluoride and deionized water, and the mass ratio of the hydrogen fluoride and the deionized water is 0.2 - 1:10 - 40; and / or, the third cleaning solution includes ammonia water, hydrogen peroxide, and deionized water, and the mass ratio of the ammonia water, the hydrogen peroxide, and the deionized water is 1 - 5:3 - 6:50 - 80; and / or, the fourth cleaning solution includes hydrochloric acid, hydrogen peroxide, and deionized water, and the mass ratio of the hydrochloric acid, the hydrogen peroxide, and the deionized water is 0.02 - 0.1:0.02 - 0.1:10 - 40.

9. The silicon wafer processing method according to claim 1, characterized in that Between the first annealing treatment and the second annealing treatment, it further includes: Performing a polishing treatment on the silicon wafer to obtain a polished wafer.

10. The silicon wafer processing method according to claim 1, characterized in that, The oxygen content of the silicon wafer to be processed is 12.26 - 12.99 ppma.

11. A silicon wafer, characterized in that, A silicon wafer is prepared by using the processing method described in any one of claims 1 to 10, and the density range of the bulk microdefects of the silicon wafer is 1.09E9 to 1.43E9 ea / cm 3 .

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