An approximate floating point adder based on operand truncation

Abstract

The application provides an approximate floating point adder based on operand truncation, comprising a preprocessing module for performing size comparison of floating point data, data exchange, calculation of exponential difference value and shift and order operation; an approximate mantissa addition module for approximately adding floating point mantissas; an approximate leading 1 detection module for approximately detecting the position of the leading 1 of the mantissa addition result; a normalization module for performing sign bit judgment and mantissa normalization processing of the mantissa addition result; an exponential adjustment module for performing correction processing on the exponent of the normalized result; and a zero judgment correction circuit module for correcting zero judgment errors caused by approximation. The application effectively reduces circuit power consumption area and shortens critical path delay, compensates for the constant value 1 at the truncation of the mantissa addition output result, maximally realizes error compensation without consuming any additional resources, avoids the occurrence of large errors, and can realize a high-precision low-power approximate floating point adder.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of approximate circuit design, and particularly relates to an approximate floating-point adder based on operand truncation. BACKGROUND

[0002] With the continuous progress of science and technology and the advent of the big data era, the demand for computing of embedded and mobile devices is growing exponentially, which leads to the energy consumption of computing systems increasing at an alarming rate. At the same time, due to the failure of Moore's law and the end of Dennard scaling law, the performance of integrated circuits is difficult to further improve under the same power consumption constraint, and the energy consumption and efficiency of integrated circuits are facing severe challenges. Fortunately, due to the limitations of human perception, a large number of application programs have high error tolerance for computing results, such as image processing, machine learning and wireless communication systems. Therefore, as an innovative computing paradigm, approximate computing (AC) trades off a small amount of precision loss for a reduction in resource consumption and is widely used in fault-tolerant applications.

[0003] In hardware circuits, basic operation units are the key components of logic circuits, and their speed and power consumption play a decisive role in the overall performance of the circuit. Therefore, the approximate design of operation units has been an active research field for decades. Basic operation units can be divided into fixed-point units and floating-point units according to the format of the operands. The research on approximate fixed-point operation units is relatively mature, while the research on approximate floating-point operation units is relatively less. According to research, in order to cover the same dynamic range, a fixed-point unit needs to be more than 5 times larger than the corresponding floating-point unit and 40% slower. At the same time, a large amount of data in real life is continuous real numbers, and floating-point numbers have the characteristics of high precision and large range, which can represent real numbers more accurately. Therefore, in a large number of traditional and advanced computing systems, the main operation operation is based on floating-point operation units (FPU).

[0004] The floating-point adder is a basic arithmetic operation unit widely used in wireless communication systems, machine learning and high dynamic range (High-Dynamic Range, HDR) image processing, etc. When it is executed accurately, it has the characteristics of high complexity, large hardware resource consumption and slow running speed, which seriously limits the development and application of floating-point adders in digital integrated circuits. SUMMARY

[0005] The application provides an approximate floating-point adder based on operand truncation.

[0006] The application provides an approximate floating-point adder based on operand truncation, which comprises:

[0007] a pre-processing module for performing size comparison of floating-point data, data exchange, calculation of exponential difference, and shift and scale operation;

[0008] an approximate mantissa addition module for approximately adding floating-point mantissas;

[0009] an approximate leading 1 detection module for approximately detecting the position of the leading 1 of the mantissa addition result;

[0010] a normalization module for performing sign bit judgment and mantissa normalization of the mantissa addition result;

[0011] an exponential adjustment module for performing correction processing on the exponent of the normalized result;

[0012] a zero judgment correction circuit module for correcting zero judgment errors caused by approximation.

[0013] Further, the pre-processing module compares the absolute values of two floating-point numbers, exchanges the two floating-point numbers, ensures that the addend is the number with the largest absolute value, so that the result of the mantissa addition output is a positive number, subtracts the exponent of the smaller floating-point number from the exponent of the larger floating-point number to obtain an exponential difference, and performs a shift and scale operation on the smaller floating-point number according to the exponential difference to make the exponents of the two floating-point numbers the same.

[0014] Further, the approximate mantissa addition module first converts the operands to corresponding complements according to the results of the exclusive or of the operand sign bits, then truncates the low significant bits of the operands, and finally directly compensates for the constant value 1 at the truncated position of the mantissa addition result.

[0015] Further, the approximate leading 1 detection module only detects the result of the accurate addition of the reserved high significant bits.

[0016] Further, the normalization module performs sign bit judgment on the result, and shifts the mantissa according to the position of the leading 1 to make the highest bit of the mantissa 1.

[0017] Further, the exponential adjustment module subtracts the corresponding shift bit value according to the left shift during mantissa normalization, and adds the corresponding shift bit value according to the right shift during mantissa normalization.

[0018] Further, the zero judgment correction circuit module obtains a truncated and flag bit by adding a circuit that judges whether the truncated low significant bits of the two operands are equal, performs an and operation on the truncated and flag bit and the zero flag bit of the result before correction to obtain the zero flag bit of the result after correction, and adjusts the exponent value to zero.

[0019] The application provides an approximate floating point adder based on operand truncation, comprising a preprocessing module for performing size comparison of floating point data, data exchange, calculation of exponential difference value and shift and order operation; an approximate mantissa addition module for approximately adding floating point mantissas; an approximate leading 1 detection module for approximately detecting the position of the leading 1 of the mantissa addition result; a normalization module for performing sign bit judgment and mantissa normalization processing of the mantissa addition result; an exponential adjustment module for performing correction processing on the exponent of the normalized result; and a zero judgment correction circuit module for correcting zero judgment errors caused by approximation. In the application, the low significant bits of the operands in the approximate mantissa addition module and the reduction of the length of the detection data in the approximate leading 1 detection module effectively reduce the circuit power consumption area and shorten the critical path delay. The constant value 1 is compensated at the truncation of the mantissa addition output result, and the error compensation is maximized without consuming any additional resources. The zero judgment correction circuit module avoids the occurrence of large errors, and finally realizes the approximate floating point adder with high precision and low power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the present application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0021] Figure 1 A structure diagram of an approximate floating point adder based on operand truncation is provided for the embodiments of the present application.

[0022] Figure 2 A running flowchart of an approximate floating point adder based on operand truncation is provided for the embodiments of the present application.

[0023] Figure 3 An approximate circuit schematic diagram of mantissa truncation and compensation is provided for the embodiments of the present application.

[0024] Figure 4 A zero judgment circuit schematic diagram before correction is provided for the embodiments of the present application.

[0025] Figure 5 A zero judgment circuit schematic diagram after correction is provided for the embodiments of the present application. DETAILED DESCRIPTION

[0026] With reference to the drawings and embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of the present application.

[0027] In view of the large resource consumption of the existing accurate floating-point adder, an approximate floating-point adder with lower power consumption, area and delay is provided at the cost of a certain precision loss, as shown in Figure 1 An approximate floating-point adder based on operand truncation is provided, comprising:

[0028] The preprocessing module 10 is configured to compare the sizes of floating-point data, exchange the data, calculate the exponent difference, and perform the shift and alignment operation.

[0029] For example, the preprocessing module 10 compares the sizes of the absolute values of two floating-point numbers, exchanges the two floating-point numbers, ensures that the addend is the number with the largest absolute value, so that the result of the addition of the mantissa is a positive number, subtracts the exponent of the smaller floating-point number from the exponent of the larger floating-point number to obtain the exponent difference, and performs the shift and alignment operation on the smaller floating-point number according to the exponent difference to make the exponents of the two floating-point numbers the same.

[0030] The approximate mantissa addition module 20 is configured to approximately add the floating-point mantissas.

[0031] For example, the approximate mantissa addition module 20 first converts the operands into corresponding complements according to the result of the exclusive OR operation of the sign bits of the two operands, then truncates the low significant bits of the operands, and finally compensates for the constant value 1 at the truncated position of the addition result of the mantissa.

[0032] The approximate leading 1 detection module 30 is configured to approximately detect the position of the leading 1 of the addition result of the mantissa.

[0033] For example, the approximate leading 1 detection module only detects the result of the accurate addition of the reserved high significant bits.

[0034] The normalization module 40 is configured to perform the sign bit judgment and mantissa normalization processing of the addition result of the mantissa.

[0035] For example, the normalization module 40 performs the sign bit judgment of the result, and shifts the mantissa according to the position of the leading 1 to make the highest bit of the mantissa 1.

[0036] The exponent adjustment module 50 is configured to perform the correction processing of the exponent of the normalized result.

[0037] Exemplarily, the exponent adjustment module 50 subtracts the corresponding shift bit value according to the left shift when the mantissa is normalized, and adds the corresponding shift bit value according to the right shift when the mantissa is normalized.

[0038] The zero judgment correction circuit module 60 is used for correcting the zero judgment error caused by approximation.

[0039] Exemplarily, the zero judgment correction circuit module obtains the truncated and flag bit by adding the circuit judging whether the low significant bits of the two operands are equal, and obtains the corrected result zero flag bit by performing the AND operation between the truncated and flag bit and the result zero flag bit before correction, which is used for adjusting the exponent value to zero.

[0040] As shown in Figure 2 , the input signal of the embodiment of the present application is two half-precision floating point format addends, the data is exchanged by comparing the absolute values of the two floating point numbers in the preprocessing module, so that the addend is always the number with the larger absolute value, so that the result of the mantissa addition is always positive, saving the resource overhead of the complement conversion; the exponent of the larger data is subtracted by the exponent of the smaller data to obtain the exponent difference, and the smaller data is shifted according to the exponent difference to make the exponents of the two data same; in the approximate mantissa addition module, first, it is determined whether the operands are converted into the corresponding complements according to whether the sign bits of the two operands are same, then the low significant bits of the operands are truncated, and finally, the constant value 1 is directly compensated at the truncated position of the mantissa addition result; in the approximate leading 1 detection module, because the result at the truncated position is not accurate itself, only the result of the accurate addition of the reserved high significant bits is detected to obtain the position of the leading 1; in the normalization module, the sign bit of the result of the floating point adder is directly equal to the sign bit of the operand with the larger absolute value, and the shift value is obtained according to the number of bits between the position of the leading 1 and the highest bit, and then the mantissa is shifted correspondingly to make the highest bit of the mantissa 1; in the exponent adjustment module, the corresponding shift bit value is subtracted or added according to whether the mantissa is left shifted or right shifted when normalized. In the zero judgment correction circuit module, the truncated and flag bit is obtained by adding the circuit judging whether the low significant bits of the two operands are equal, and the corrected result zero flag bit is obtained by performing the AND operation between the truncated and flag bit and the result zero flag bit before correction, which is used for controlling the adjustment of the exponent value to zero. Finally, the selection of the sign bit, the exponent value and the mantissa value is performed, and the output result of the floating point adder is obtained by combining them together.

[0041] As shown in Figure 3 , in the mantissa addition, for the operand B', the bit data right shifted out of the order is not involved in the addition operation, because even if it is involved in the addition operation, it is added with the zero value supplemented after the operand A, and there is no carry to the front bit, so this part of data will be discarded after normalization. Figure 3The truncation of the low 3 bits of the operand can effectively shorten the critical path of the circuit, but it also leads to less information available during the operation, which can cause a large error in the final result. Therefore, after the truncation approximation, a corresponding compensation is made to improve the accuracy of the final result. The truncated operand will inevitably make the result of the mantissa addition smaller. By setting all the bits of the truncated result to 1, the error of the final result is no longer single-biased, but can be positive or negative. In the multi-stage operation of fault-tolerant applications, positive and negative errors can cancel each other out, which reflects the superiority of the present application. At the same time, by adjusting the number of truncated bits, approximate design of different precision can be realized.

[0042] The zero judgment logic is an important part of floating point operation. If the zero judgment circuit fails, the error of the mantissa addition result multiplied by the exponent value can cause a large error distance. Therefore, the zero judgment circuit needs to be accurately executed. The operand truncation approximation may cause the zero judgment circuit to fail in some specific cases. For example, when two half-precision floating point numbers A and B are positive and negative, the exponent values are equal, and the mantissa values are similar, as follows:

[0043] A = 0_11100_1000001111

[0044] B = 1_11100_1000001100

[0045] The exact result of the addition of A and B should not be zero, but when using the proposed operand low 3 bit truncation approximation scheme, the two mantissas participating in the subtraction operation will have equal high effective bit values, resulting in a zero value. Although the complete result obtained by adding the truncated low significant bits and the compensation value is not zero, because the approximate leading 1 detection is used, the truncated low significant bit result will not be detected, causing the zero judgment circuit to fail and the final result to be determined as zero. From the mantissa addition result alone, the small error generated is acceptable, but from the overall result, due to the amplification effect of the exponent value on the mantissa value, the large error distance between the final result and the exact result is unacceptable. At the same time, as the number of truncated bits increases, the probability of zero judgment error also increases. Therefore, additional circuitry is needed to avoid errors in the zero judgment circuit.

[0046] As shown in Figure 5 , compared to Figure 4The shown zero detection circuit before modification, added the judgment circuit of whether the truncated low significant bits are equal, for the approximate design of truncating 3 bits, it needs a 3-bit comparator. At the same time in the half-precision floating point adder, the result range of the approximate leading 1 detection is 0 to 8 (because the low 3 bits are truncated, only the high 9 bits are detected), only a 4-bit signal is needed to represent the detection value, so the result zero detection circuit also only needs a 4-bit comparator, which is the benefit brought by the existing approximate leading 1 detection module. When the high significant bits addition result is zero and the truncated low significant bits are equal, the final result will be judged as zero. Therefore, the output results of the two comparators are obtained through an AND gate to obtain the modified zero flag bit, which is used to control the index value to be zero.

[0047] The present application is described in detail above in conjunction with specific embodiments and exemplary examples, but these descriptions cannot be understood as limiting the present application. Those skilled in the art understand that the technical solutions and embodiments of the present application can be variously replaced, modified or improved without deviating from the spirit and scope of the present application, and these all fall within the scope of the present application. The protection scope of the present application is subject to the appended claims.

Claims

1. An approximate floating point adder based on operand truncation, characterized by, The application relates to a floating point addition method and device. The pre-processing module compares the absolute values of two floating points, exchanges the two floating points, ensures that the addend is the number with the largest absolute value, so that the result of the addition of the mantissas is a positive number, subtracts the exponent of the smaller floating point from the exponent of the larger floating point to obtain an exponent difference, and performs a shift and alignment operation on the smaller floating point according to the exponent difference so that the exponents of the two floating points are the same. The approximate mantissa addition module converts the two operation numbers into corresponding complements according to the result of the exclusive or of the sign bits of the two operation numbers, truncates the low effective bits of the operation numbers, and directly compensates a constant value 1 at the truncated position of the addition result of the mantissas. The approximate leading 1 detection module detects the position of the leading 1 of the addition result of the mantissas. The normalization module judges the sign bit of the addition result of the mantissas and performs normalization processing on the mantissas. The exponent adjustment module corrects the exponent of the normalized result. The zero judgment correction circuit module corrects the zero judgment error caused by approximation. The zero judgment correction circuit module adds a circuit for judging whether the truncated low effective bits of the two operation numbers are equal to obtain a truncated and flag bit, performs an and operation on the truncated and flag bit and the zero flag bit of the result before correction to obtain the zero flag bit of the result after correction, and adjusts the exponent value to zero. The approximate leading 1 detection module only detects the result of the accurate addition of the reserved high effective bits.

2. An approximate floating point adder based on operand truncation as claimed in claim 1, wherein, The normalization module judges the sign bit of the result and shifts the mantissa according to the position of the leading 1 so that the highest bit of the mantissa is 1.

3. The approximate floating point adder based on operand truncation of claim 1, wherein, The exponent adjustment module subtracts the corresponding shift bit value according to the left shift during the normalization of the mantissa, and adds the corresponding shift bit value according to the right shift during the normalization of the mantissa.

4. The approximate floating point adder based on operand truncation of claim 1, wherein, ​

Images