A multifunctional floating-point operation system and method based on FPGA

Abstract

The present invention relates to the field of digital signal processing technology, and in particular to a multifunctional floating-point operation system and method based on FPGA. The system includes: a floating-point frequency shift module, a floating-point FFT / IFFT / power spectrum module and a multifunctional floating-point complex multiplication operation module; the floating-point frequency shift module is used to receive a frequency shift factor and a control signal, to receive floating-point IQ data or floating-point frequency domain data, to send a frequency shift complex multiplication operation request to the multifunctional floating-point complex multiplication operation module, to receive and output the frequency shift result calculated by the multifunctional floating-point complex multiplication operation module; the floating-point FFT / IFFT / power spectrum module is used to receive the frequency shift result received by the floating-point frequency shift module, or to receive floating-point IQ data or floating-point frequency domain data; and to receive a control signal at the same time; and to send an FFT complex multiplication operation request to the multifunctional floating-point complex multiplication operation module, and to receive the FFT / IFFT result data and FFT / IFFT power spectrum data calculated by the multifunctional floating-point complex multiplication operation module. The present invention saves more than 50% of computing resources, power consumption and FPGA costs.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing, and in particular to a multifunctional floating-point operation system and method based on FPGA. Background Art

[0002] In the real-time signal processing of modern radars, floating-point operations such as time-domain frequency shift, FFT, IFFT, and power spectrum calculation are often required.

[0003] Currently, this type of floating-point signal processing usually uses DSP for calculations, but DSP has limited computing resources and cannot adapt to the multi-channel parallel calculations of modern radars, and the calculation speed is slow.

[0004] Another solution is to use FPGA for calculation, but FPGA generally uses fixed-point or block floating-point calculation, which can easily introduce calculation errors and overflow in radar signal processing.

[0005] In some radar systems, there are also examples of using FPGA for floating-point calculations such as time-domain frequency shift, FFT / IFFT, and power spectrum calculation. However, in these examples, time-domain frequency shift, FFT / IFFT, and power spectrum calculation are usually treated as independent modules. Summary of the invention

[0006] The purpose of the present invention is to overcome the above-mentioned defects of the prior art, thereby providing a multifunctional floating-point operation system and method based on FPGA.

[0007] In order to solve the above technical problems, the technical solution of the present invention provides a multifunctional floating-point operation system based on FPGA, including: a floating-point frequency shift module, a floating-point FFT / IFFT / power spectrum module and a multifunctional floating-point complex multiplication operation module; wherein,

[0008] The floating-point frequency shift module is used to receive the frequency shift factor and the control signal, to receive the floating-point IQ data or the floating-point frequency domain data, to send the frequency shift complex multiplication operation request to the multifunctional floating-point complex multiplication operation module, and to receive and output the frequency shift result calculated by the multifunctional floating-point complex multiplication operation module;

[0009] The floating-point FFT / IFFT / power spectrum module is used to receive the frequency shift result received by the floating-point frequency shift module, or to receive floating-point IQ data or floating-point frequency domain data; and is also used to receive control signals; and is used to send an FFT complex multiplication operation request to the multi-functional floating-point complex multiplication operation module, and to receive the FFT / IFFT result data and FFT / IFFT power spectrum data calculated by the multi-functional floating-point complex multiplication operation module.

[0010] As an improvement of the above system, the floating-point frequency shift module includes: a frequency shift initial value RAM, a frequency shift control submodule and an N-point frequency shift value RAM; wherein,

[0011] The frequency shift initial value RAM is used to receive the frequency shift factor and output the frequency shift initial value data of the N0th point to the frequency shift control submodule;

[0012] The frequency shift control submodule is used to receive frequency shift function bypass control data, frequency shift initial value RAM initialization data and floating point IQ data; to output frequency shift complex multiplication operation request to the multifunctional floating point complex multiplication operation module; and to receive and output the frequency shift result of the multifunctional floating point complex multiplication operation module;

[0013] The N-point frequency shift value RAM and the frequency shift control submodule are used to receive N-point frequency shift initial value data.

[0014] As an improvement of the above system, the frequency shift initial value RAM is used to store the 0th point frequency shift initial value data of different frequency shift values;

[0015] The N-point frequency shift value RAM is used to store the N-point frequency shift initial value data indicated by the frequency shift factor;

[0016] When the frequency shift function bypass control data is higher than a first preset value level, the frequency shift control submodule stops working.

[0017] As an improvement of the above system, the working process of the floating-point frequency shift module is as follows:

[0018] Under the instruction of the frequency shift initial value RAM initialization data, the 0th point frequency shift value FS(0) is read from the frequency shift initial value RAM according to the frequency shift factor, and the 0th point frequency shift value Fs(0) is sent to the multifunctional floating-point complex multiplication operation module, and the multifunctional floating-point complex multiplication operation module is requested to perform a complex multiplication operation to obtain the nth point frequency shift value FS(n) complex multiplication operation result; the received nth point frequency shift value FS(n) complex multiplication operation result of the multifunctional floating-point complex multiplication operation module is transmitted to the n-point frequency shift value RAM for storage; wherein the multifunctional floating-point complex multiplication operation module performs a recursive operation of FS(n)=Fs(n-1)*Fs(0), wherein Fs(n-1) is the n-1th point frequency shift value;

[0019] Driven by the floating-point IQ data, the n-th frequency shift value FS(n) is read from the N-point frequency shift value RAM in sequence, and a frequency shift operation request is generated and sent to the multifunctional floating-point complex multiplication operation module to obtain the IQ data FsOutIQ(n) after the n-th frequency shift as the frequency shift result and output it; wherein the multifunctional floating-point complex multiplication operation module calculates FsOutIQ(n)=IQ(n)*FS(n) in sequence, wherein FsOutIQ(n) is the IQ data after the n-th frequency shift, and IQ(n) is the n-th floating-point IQ data;

[0020] As an improvement of the above system, the floating point FFT / IFFT / power spectrum module includes: an FFT control submodule, an FFT butterfly operation submodule, an FFT calculation value memory and an FFT rotation factor table ROM; wherein,

[0021] The FFT control submodule is used for:

[0022] Receiving the frequency shift result received by the floating-point frequency shift module, or receiving floating-point IQ data or floating-point frequency domain data; and receiving a control signal at the same time;

[0023] Output FFT / IFFT power spectrum data and FFT / IFFT result data to the outside;

[0024] Output the rotation factor read address to the FFT rotation factor table ROM to obtain the rotation factor;

[0025] outputting the write address Xk, the read address Xn, the first write data Xk1 and the first write data Xk2 to the FFT calculated value memory; and

[0026] Output the first read data Xn1, the second read data Xn2, the rotation factor, the PSD indication and the IFFT indication to the FFT butterfly operation submodule;

[0027] The FFT butterfly operator module is used for:

[0028] Output the first write data Xk1 and the first write data Xk2 to the FFT control submodule; output the FFT complex multiplication operation request to the multifunctional floating-point complex multiplication operation module; receive the FFT / IFFT result data and FFT / IFFT power spectrum data output by the multifunctional floating-point complex multiplication module;

[0029] The FFT calculation value memory is used to return the first read data Xn1 and the second read data Xn2 to the FFT control submodule.

[0030] As an improvement of the above system, the control signal includes: frequency shift function bypass control data, bypass FFT signal, start FFT signal and bypass power spectrum density signal;

[0031] The working logic of the FFT control submodule is:

[0032] Step 1: If the frequency shift function bypass control data is higher than a first preset value, the floating-point IQ data or the floating-point frequency domain input data is used as floating-point FFT module input data, otherwise the frequency shift result is used as input data;

[0033] Step 2: If the bypass FFT signal is higher than the second preset value, the input data is directly forwarded to the FFT butterfly operator module, and the PSD indicator is set high to obtain FFT / IFFT power spectrum data from the FFT butterfly operator module and transmit it to the outside world;

[0034] Step 3: If the bypass FFT signal is lower than the second preset value, then

[0035] Step 3.1: Store the input data into the FFT calculation value memory;

[0036] Step 3.2: Under the drive of the FFT start signal, the rotation factor Wn is read out from the FFT rotation factor table ROM in turn, and the first read data Xn1 and the second read data Xn2 are read out from the FFT calculation value memory; the rotation factor Wn, the first read data Xn1 and the second read data Xn2 are sent to the FFT butterfly operation submodule for FFT intermediate calculation, and the first write data Xk1 and the second write data Xk2 obtained by the intermediate calculation are stored in the FFT calculation value memory;

[0037] Step 3.3: Read the FFT / IFFT result data from the FFT calculation value memory and output it; at the same time, if the bypass power spectrum density signal is lower than the third preset value, send the FFT / IFFT result data as the second write data Xn2 to the FFT butterfly operation submodule, and make the PSD indication high to obtain the FFT / IFFT power spectrum data and output it. If the bypass power spectrum density signal is higher than the third preset value, the power spectrum operation is not performed;

[0038] The FFT butterfly operator module uses the frequency extraction principle to perform operations;

[0039] If the PSD indicator is high, skip this step of calculation; otherwise, calculate the difference Xm between the first write data Xn1 and the second write data Xn2;

[0040] If the PSD indication is high, the FFT complex multiplication operation request {OP2, ai2, cj2, bi2, dj2} is:

[0041] OP2=1, ai2=real(Xn2)=cj2, bi2=imag(Xn2)=dj2; otherwise, OP2=IFFT indication, ai2=real(Xm), bi2=imag(Xm), cj2=real(Wn), dj2=imag(Wn).

[0042] As an improvement of the above system, the multifunctional floating-point complex multiplication operation module includes: 4 floating-point multiplier modules, 2 floating-point addition and subtraction modules and 5 multiplexers;

[0043] The external input of the multifunctional floating-point complex multiplication operation module is a frequency shift complex multiplication operation request {OP1, ai1, cj1, bi1, dj1} and an FFT complex multiplication operation request {OP2, ai2, cj2, bi2, dj2}; wherein,

[0044] OP1 is the level indication signal, ai1, cj1, bi1 and dj1 are 32-bit IEEE754 standard floating point data respectively;

[0045] The multifunctional floating-point operation module uses the OPsel signal as a multiplexer to switch between two groups of floating-point operation requests. The specific calculation is:

[0046] When the OPSel signal is lower than the fourth preset value and the OP1 signal is lower than the fifth preset value, the calculation request y=(i*ai1+j*bj1)*(i*ci1+j*dj1);

[0047] When the OPSel signal is lower than the fourth preset value and the OP1 signal is higher than the fifth preset value, the calculation request y=(i*ai1+j*bj1)*(i*ci1-j*dj1);

[0048] When the OPSel signal is higher than the fourth preset value and the OP1 signal is lower than the fifth preset value, the calculation request y=(i*ai2+j*bj2)*(i*ci2+j*dj2);

[0049] When the OPSel signal is higher than the fourth preset value and the OP2 signal is high, the calculation request y=(i*ai2+j*bj2)*(i*ci2-j*dj2) is calculated.

[0050] To achieve another object of the present invention, the present invention further provides a multifunctional floating-point operation method, which is implemented by the multifunctional floating-point operation system based on FPGA, comprising:

[0051] The floating-point frequency shift module receives the frequency shift factor and the control signal and receives the floating-point IQ data or the floating-point frequency domain data, generates a frequency shift complex multiplication operation request and sends it to the multifunctional floating-point complex multiplication operation module;

[0052] While the floating-point frequency shift module is receiving, the floating-point FFT / IFFT / power spectrum module receives the control signal, receives the frequency shift result received by the floating-point frequency shift module, or receives the floating-point IQ data or the floating-point frequency domain data; and simultaneously receives the control signal; generates an FFT complex multiplication operation request and sends it to the multifunctional floating-point complex multiplication operation module;

[0053] The multifunctional floating-point complex multiplication operation module sends the calculated frequency shift result to the floating-point frequency shift module, or sends the calculated FFT / IFFT result data and FFT / IFFT power spectrum data to the floating-point FFT / IFFT / power spectrum module.

[0054] Compared with the prior art, the advantages of the present invention are that the multifunctional floating-point operation system and method based on FPGA proposed in the present invention realizes floating-point frequency shift, FFT / IFFT, and power spectrum multifunctional floating-point operation, and solves the floating-point operation problem of FPGA. Compared with the conventional sub-module implementation solution, it saves more than 50% of resources, so it is more suitable for multi-channel signal processing of modern radars. It saves power consumption and FPGA cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 It is a schematic diagram of a multifunctional floating-point computing device;

[0056] Figure 2 This is the internal schematic diagram of the floating-point frequency shift module;

[0057] Figure 3 Internal schematic diagram of the multifunctional floating-point arithmetic module;

[0058] Figure 4 Schematic diagram of the floating-point FFT / IFFT / power spectrum module. DETAILED DESCRIPTION

[0059] The technical solution provided by the present invention is further illustrated below in conjunction with embodiments.

[0060] After studying the implementation method of floating-point time-domain frequency shift, FFT / IFFT and power spectrum calculation, the inventors found that:

[0061] 1. The implementation of FFT / IFFT using FPGA is usually divided into three stages in terms of timing: a. data input; b. FFT / IFFT calculation; c. FFT result output;

[0062] 2a. The basic operation unit of FFT is butterfly operation. Each butterfly operator requires 2 complex additions and 1 complex multiplication.

[0063] 2b. The basic operation unit of the time domain frequency shift operation is complex multiplication, and each operation performs a complex multiplication operation;

[0064] 2c. The power spectrum operation requires the real part of the complex multiplication operation;

[0065] 3a. In the 1a data input stage and 1c FFT result output stage, the butterfly operation unit is in an idle state and can be used for time domain frequency shift or power spectrum calculation.

[0066] Based on the above findings, the inventors proposed a multifunctional floating-point operation device based on FPGA, which can use the complex multiplication unit in the butterfly operator to perform time-domain frequency shift calculation in the data input stage, and perform power spectrum calculation in the FFT calculation result output stage; or perform power spectrum, FFT / IFFT, and power spectrum calculation separately. The device only needs 2 floating-point complex adders and 1 floating-point complex multiplier to complete the full pipeline operation of frequency shift, FFT / IFFT, and power spectrum calculation. If an independent module is used for implementation, at least 2 floating-point complex adders and 3 floating-point complex multipliers are required to achieve it. 1 floating-point complex adder = 2 scalar adders, 1 floating-point complex multiplier = 4 complex multipliers + 2 complex adders; both floating-point multipliers and floating-point adders require a large amount of FPGA's DSP and logic resources.

[0067] Example 1

[0068] like Figure 1 As shown, this embodiment provides a multifunctional floating-point operation system based on FPGA, including: a floating-point frequency shift module, a floating-point FFT / IFFT power spectrum calculation module, and a multifunctional floating-point butterfly operation module. The link relationship between the above parts is:

[0069] External frequency shift factor input, external floating-point IQ data / floating-point frequency domain data, and control signal are input to the floating-point frequency shift module; at the same time, floating-point IQ data / floating-point frequency domain data and control signal are also input to the floating-point FFT / IFFT / power spectrum module;

[0070] The floating-point frequency shift module obtains the frequency shift result output and transmits it to the floating-point FFT / IFFT / power spectrum module;

[0071] The floating-point FFT / IFFT / power spectrum module outputs FFT / IFFT power spectrum and FFT / IFFT operation results;

[0072] During the operation process, the floating-point frequency shift module and the floating-point FFT / IFFT / power spectrum module submit butterfly operation requests to the multifunctional floating-point butterfly operation module, and the results of the multifunctional floating-point butterfly operation are returned to the request module.

[0073] like Figure 2 As shown, the floating-point frequency shift module includes a frequency shift initial value memory, a frequency shift control submodule, and an N-point frequency shift value memory. The floating-point frequency shift module has the following link relationship:

[0074] The external input frequency shift factor is connected to the frequency shift initial value memory, and the output of the frequency shift initial value memory is connected to the frequency shift control submodule;

[0075] External input frequency shift function bypass control, frequency shift memory initialization, floating point IQ data input to the frequency shift control submodule;

[0076] The frequency shift complex multiplication operation request outputted by the frequency shift control submodule is connected to the multifunctional floating point complex multiplication module, and the complex multiplication operation result of the multifunctional floating point complex multiplication module is connected to the frequency shift control submodule;

[0077] The N-point frequency shift initial value signal is connected to the N-point frequency shift value memory module and the frequency shift control submodule; the module's calculation result IQ frequency shifted data is output to the outside world.

[0078] Among them, the frequency shift complex multiplication operation request is composed of {OP1, ai1, ci1, bj1, dj1}, OP1 is the level indication signal, ai1, cj1, bi1 and dj1 are 32-bit IEEE754 standard floating-point data respectively, OP1 is a high level, and the indicated complex multiplication operation request is: (i*ai1+j*bj1)*(i*ci1+j*dj1).

[0079] In the floating-point frequency shift module, the frequency shift initial value memory stores the N0th point data of different frequency shift values, namely, exp(j*2pi*f0).

[0080] The floating-point frequency shift module stores the N-point frequency shift value data indicated by the frequency shift factor, i.e., exp(j*2pi*f0*n), n={1,2...N}.

[0081] The floating-point frequency shift module has a byPassFreqShift switch signal. When this signal is high, the module does not work.

[0082] The working steps of the floating-point frequency shift module are divided into two parts: step 1, frequency shift initialization; step 2, frequency shift calculation.

[0083] The frequency shift initialization steps of the floating-point frequency shift module are:

[0084] 1. Under the instruction of the external signal for initializing the frequency shift memory, the value of the frequency shift value FS(0)=exp(j*2pi*f0) at the 0th point is read from the frequency shift initial value memory according to the frequency shift factor;

[0085] 2. The operation request is sent to the multifunctional floating-point complex multiplication module to perform a recursive operation of FS(n)=Fs(n-1)*Fs(0), where FS(n) is the frequency shift value of the nth point, and Fs(n-1) is the frequency shift value of the n-1th point;

[0086] 3. Store the result of the multifunctional floating-point complex multiplication module into the N-point frequency shift value memory.

[0087] The frequency shift calculation steps of the floating-point frequency shift module are:

[0088] 1. Driven by floating-point IQ data, FS(n) is read out from the N-point frequency shift value memory in sequence;

[0089] 2. The operation request is sent to the multifunctional floating-point complex multiplication module, and the IQ data after frequency shift at the nth point is calculated in sequence: FsOutIQ(n)=IQ(n)*FS(n); wherein IQ(n) is the floating-point IQ data at the nth point.

[0090] 3. Output the results of the multifunctional floating-point multiplication module to the outside world.

[0091] like Figure 3 As shown in the figure, the multifunctional floating-point operation module is composed of 4 floating-point multiplier modules, 2 floating-point addition and subtraction modules and 5 multiplexers. Its external input is 2 groups of floating-point operation requests {OP1, ai1, cj1, bi1, dj1}, {OP2, ai2, cj2, bi2, dj2}, which come from the floating-point frequency shift module and the floating-point FFT / IFFT / power spectrum module respectively, and 1 OPSel signal;

[0092] The multifunctional floating-point operation module uses the OPsel signal as a multiplexer to switch between two groups of floating-point operation requests. The specific calculation is:

[0093] When the OPSel signal is low and the OP1 signal is low, calculate y=(i*ai1+j*bj1)*(i*ci1+j*dj1)=i*(ac-db)+j*(bc+ad);

[0094] When the OPSel signal is low and the OP1 signal is high, calculate y=(i*ai1+j*bj1)*(i*ci1-j*dj1)=i*(ac+db)+j*(bc-ad);

[0095] When the OPSel signal is high and the OP1 signal is low, calculate y=(i*ai2+j*bj2)*(i*ci2+j*dj2)=i*(ac-db)+j*(bc+ad);

[0096] When the OPSel signal is high and the OP2 signal is high, y=(i*ai2+j*bj2)*(i*ci2-j*dj2)=i*(ac+db)+j*(bc-ad) is calculated.

[0097] like Figure 4 As shown in the figure, the floating-point FFT / IFFT / power spectrum module consists of an FFT control submodule, an FFT butterfly operation submodule, an FFT calculation value memory, and an FFT rotation factor table ROM. The connection relationship between the modules and submodules is as follows:

[0098] The external inputs StartFFT (start FFT signal), ByPassPSD (bypass power spectrum density signal), ByPassFFT (bypass FFT signal), byPassFreqShift (frequency shift function bypass control data), floating point IQ data / floating point frequency domain data, and IQ frequency shifted data are connected to the FFT control submodule;

[0099] The FFT control submodule outputs the power spectrum results and FFT / IFFT results to the outside;

[0100] The FFT control submodule outputs the twiddle factor read address to the FFT twiddle factor table ROM;

[0101] The FFT control submodule outputs the Xk write address, Xn read address, and Xk write data (Xk1, Xk2) to the FFT calculation value memory;

[0102] FFT calculation value memory returns Xn read data {Xn1, Xn2};

[0103] The FFT control submodule outputs Xn data, rotation factors, PSD indication, and IFFT indication to the FFT butterfly operation submodule;

[0104] The FFT butterfly operation submodule outputs Xk data to the FFT control submodule;

[0105] The FFT butterfly operation submodule outputs the FFT complex multiplication operation request to the multifunctional floating-point complex multiplication module;

[0106] The multifunctional floating-point complex multiplication module outputs the complex multiplication operation result to the FFT butterfly operation submodule.

[0107] The FFT butterfly operation submodule uses the frequency extraction method (DIF-FFT) principle for operation. The specific steps are as follows:

[0108] 1. If the PSD indicator is high, skip this step; otherwise calculate Xm = Xn1-Xn2;

[0109] 2. If the PSD indication is high, then {OP2=1, ai2=real(Xn2)=ci2, bj2=imag(Xn2)=dj2}; otherwise {OP2=IFFT indication, ai2=real(Xm), bj2=imag(Xm), ci2=real(Wn), dj2=imag(Wn)}, and send an FFT multiplication operation request to the multifunctional floating-point multiplication module;

[0110] 3. Let Xk2 be equal to the result of the multi-function floating-point complex multiplication operation, and return Xk1 and Xk2 to the FFT control submodule.

[0111] It is worth pointing out that a similar method can also be used to calculate the power spectrum based on the time extraction FFT (DIT-FFT).

[0112] The FFT rotation factor table stores the floating-point rotation factors Wn required for each FFT calculation stage.

[0113] The FFT control submodule is used to organize and control the addresses and data in the FFT input, output and calculation process. The details are as follows:

[0114] 1. If byPassFreqShift is high, floating point IQ data / floating point frequency domain data is used, otherwise IQ frequency shifted data is used as data input;

[0115] 2. If byPassFFT is high, the data input is directly forwarded to the FFT butterfly operation submodule, and the PSD indicator is set high; the complex multiplication result is output as the power spectrum operation result.

[0116] 3. If byPassFFT is low, then:

[0117] 3.1 Store data input into FFT calculation value memory

[0118] 3.2 Under the drive of the startFFT signal, the rotation factor Wn is read out from the FFT rotation factor table ROM in turn, and Xn1 and Xn2 are read out from the FFT calculation value memory; Wn, Xn1 and Xn2 are sent to the butterfly operator module for FFT intermediate calculation; then the intermediate calculation results Xk1 and Xk2 are stored in the FFT calculation value memory;

[0119] 3.3 After the calculation is completed, the FFT calculation result is read from the FFT calculation value memory and output; in this step, if byPassPSD is low, the FFT calculation result is sent to the FFT butterfly operation submodule as Xn2 at the same time, and the PSD indication is set to high; at the same time, the FFT butterfly operation submodule result is output as the power spectrum operation result; if byPassPSD is high, the power spectrum operation is not performed.

[0120] Example 2

[0121] This embodiment provides a multifunctional floating-point operation method based on FPGA, which is implemented based on the system provided in Embodiment 1.

[0122] The multifunctional floating-point operation method comprises:

[0123] The floating-point frequency shift module receives the frequency shift factor and the control signal and receives the floating-point IQ data or the floating-point frequency domain data, generates a frequency shift complex multiplication operation request and sends it to the multifunctional floating-point complex multiplication operation module;

[0124] While the floating-point frequency shift module is receiving, the floating-point FFT / IFFT / power spectrum module receives the control signal, receives the frequency shift result received by the floating-point frequency shift module, or receives the floating-point IQ data or the floating-point frequency domain data; and simultaneously receives the control signal; generates an FFT complex multiplication operation request and sends it to the multifunctional floating-point complex multiplication operation module;

[0125] The multifunctional floating-point complex multiplication operation module sends the calculated frequency shift result to the floating-point frequency shift module, or sends the calculated FFT / IFFT result data and FFT / IFFT power spectrum data to the floating-point FFT / IFFT / power spectrum module.

[0126] The present invention proposes a floating-point frequency shift, FFT / IFFT, and power spectrum multifunctional floating-point computing device based on FPGA, which solves the floating-point computing problem of FPGA. Compared with the conventional sub-module implementation solution, it saves more than 50% of resources, making it more suitable for multi-channel signal processing of modern radars. It saves power consumption and FPGA costs.

[0127] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention is described in detail with reference to the embodiments, it should be understood by those skilled in the art that any modification or equivalent replacement of the technical solutions of the present invention does not depart from the spirit and scope of the technical solutions of the present invention and should be included in the scope of the claims of the present invention.

Claims

1. A multifunctional floating-point computing system based on FPGA, comprising: Floating-point frequency shift module, floating-point FFT / IFFT / power spectrum module and multifunctional floating-point complex multiplication module; among them, The floating-point frequency shift module is used to receive the frequency shift factor and the control signal, to receive the floating-point IQ data or the floating-point frequency domain data, to send the frequency shift complex multiplication operation request to the multifunctional floating-point complex multiplication operation module, and to receive and output the frequency shift result calculated by the multifunctional floating-point complex multiplication operation module; The floating-point FFT / IFFT / power spectrum module is used to receive the frequency shift result received by the floating-point frequency shift module, or receive floating-point IQ data or floating-point frequency domain data; and is also used to receive control signals; and is used to send an FFT complex multiplication operation request to the multifunctional floating-point complex multiplication operation module, and receive the FFT / IFFT result data and FFT / IFFT power spectrum data calculated by the multifunctional floating-point complex multiplication operation module; The floating-point frequency shift module includes: a frequency shift initial value RAM, a frequency shift control submodule and an N-point frequency shift value RAM; wherein, The frequency shift initial value RAM is used to receive the frequency shift factor and output the frequency shift initial value data of the N0th point to the frequency shift control submodule; The frequency shift control submodule is used to receive frequency shift function bypass control data, frequency shift initial value RAM initialization data and floating point IQ data; to output frequency shift complex multiplication operation request to the multifunctional floating point complex multiplication operation module; and to receive and output the frequency shift result of the multifunctional floating point complex multiplication operation module; The N-point frequency shift value RAM and frequency shift control submodule are used to receive N-point frequency shift initial value data; The floating point FFT / IFFT / power spectrum module includes: an FFT control submodule, an FFT butterfly operation submodule, an FFT calculation value memory and an FFT rotation factor table ROM; wherein, The FFT control submodule is used for: Receiving the frequency shift result received by the floating-point frequency shift module, or receiving floating-point IQ data or floating-point frequency domain data; and receiving a control signal at the same time; Output FFT / IFFT power spectrum data and FFT / IFFT result data to the outside; Output the rotation factor read address to the FFT rotation factor table ROM to obtain the rotation factor; outputting the write address Xk, the read address Xn, the first write data Xk1 and the first write data Xk2 to the FFT calculated value memory; and Output the first read data Xn1, the second read data Xn2, the rotation factor, the PSD indication and the IFFT indication to the FFT butterfly operation submodule; The FFT butterfly operator module is used for: Output the first write data Xk1 and the first write data Xk2 to the FFT control submodule; output the FFT complex multiplication operation request to the multifunctional floating-point complex multiplication operation module; receive the FFT / IFFT result data and FFT / IFFT power spectrum data output by the multifunctional floating-point complex multiplication module; An FFT calculation value memory, used for returning the first read data Xn1 and the second read data Xn2 to the FFT control submodule; The multifunctional floating-point complex multiplication operation module includes: 4 floating-point multiplier modules, 2 floating-point addition and subtraction modules and 5 multiplexers; The external input of the multifunctional floating-point complex multiplication operation module is a frequency shift complex multiplication operation request {OP1, ai1, cj1, bi1, dj1} and an FFT complex multiplication operation request {OP2, ai2, cj2, bi2, dj2}; wherein, OP1 is the level indication signal, ai1, cj1, bi1 and dj1 are 32-bit IEEE754 standard floating point data respectively; The multifunctional floating-point operation module uses the OPsel signal as a multiplexer to switch between two groups of floating-point operation requests. The specific calculation is: When the OPSel signal is lower than the fourth preset value and the OP1 signal is lower than the fifth preset value, the calculation request y=(i*ai1+j*bj1)*(i*ci1+j*dj1); When the OPSel signal is lower than the fourth preset value and the OP1 signal is higher than the fifth preset value, the calculation request y=(i*ai1+j*bj1)*(i*ci1-j*dj1); When the OPSel signal is higher than the fourth preset value and the OP1 signal is lower than the fifth preset value, the calculation request y=(i*ai2+j*bj2)*(i*ci2+j*dj2); When the OPSel signal is higher than the fourth preset value and the OP2 signal is high, the calculation request y=(i*ai2+j*bj2)*(i*ci2-j*dj2) is calculated.

2. The multifunctional floating-point computing system based on FPGA according to claim 1, characterized in that: The frequency shift initial value RAM is used to store the 0th point frequency shift initial value data of different frequency shift values; The N-point frequency shift value RAM is used to store the N-point frequency shift initial value data indicated by the frequency shift factor; When the frequency shift function bypass control data is higher than a first preset value level, the frequency shift control submodule stops working.

3. The multifunctional floating-point operation system based on FPGA according to claim 1, characterized in that: The working process of the floating-point frequency shift module is as follows: Under the instruction of the frequency shift initial value RAM initialization data, the 0th point frequency shift value FS(0) is read from the frequency shift initial value RAM according to the frequency shift factor, and the 0th point frequency shift value Fs(0) is sent to the multifunctional floating-point complex multiplication operation module, and the multifunctional floating-point complex multiplication operation module is requested to perform a complex multiplication operation to obtain the nth point frequency shift value FS(n) complex multiplication operation result; the received nth point frequency shift value FS(n) complex multiplication operation result of the multifunctional floating-point complex multiplication operation module is transmitted to the n-point frequency shift value RAM for storage; wherein the multifunctional floating-point complex multiplication operation module performs a recursive operation of FS(n)=Fs(n-1)*Fs(0), wherein Fs(n-1) is the n-1th point frequency shift value; Driven by the floating-point IQ data, the n-th frequency shift value FS(n) is read from the N-point frequency shift value RAM in sequence, and a frequency shift operation request is generated and sent to the multifunctional floating-point complex multiplication operation module to obtain the IQ data FsOutIQ(n) after the n-th frequency shift as the frequency shift result and output it; wherein the multifunctional floating-point complex multiplication operation module calculates FsOutIQ(n)=IQ(n)*FS(n) in sequence, wherein FsOutIQ(n) is the IQ data after the n-th frequency shift, and IQ(n) is the n-th floating-point IQ data.

4. The multifunctional floating-point operation system based on FPGA according to claim 1, characterized in that: The control signal includes: frequency shift function bypass control data, bypass FFT signal, start FFT signal and bypass power spectrum density signal; The working logic of the FFT control submodule is: Step 1: If the frequency shift function bypass control data is higher than a first preset value, the floating-point IQ data or the floating-point frequency domain input data is used as the floating-point FFT module input data, otherwise the frequency shift result is used as the input data; Step 2: If the bypass FFT signal is higher than the second preset value, the input data is directly forwarded to the FFT butterfly operator module, and the PSD indicator is set high to obtain FFT / IFFT power spectrum data from the FFT butterfly operator module and transmit it to the outside world; Step 3: If the bypass FFT signal is lower than the second preset value, then Step 3.1: Store the input data into the FFT calculation value memory; Step 3.2: Under the drive of the FFT start signal, the rotation factor Wn is read out from the FFT rotation factor table ROM in turn, and the first read data Xn1 and the second read data Xn2 are read out from the FFT calculation value memory; the rotation factor Wn, the first read data Xn1 and the second read data Xn2 are sent to the FFT butterfly operation submodule for FFT intermediate calculation, and the first write data Xk1 and the second write data Xk2 obtained by the intermediate calculation are stored in the FFT calculation value memory; Step 3.3: Read the FFT / IFFT result data from the FFT calculation value memory and output it; at the same time, if the bypass power spectrum density signal is lower than the third preset value, send the FFT / IFFT result data as the second write data Xn2 to the FFT butterfly operation submodule, and make the PSD indication high to obtain the FFT / IFFT power spectrum data and output it. If the bypass power spectrum density signal is higher than the third preset value, the power spectrum operation is not performed; The FFT butterfly operator module uses the frequency extraction principle to perform operations; If the PSD indicator is high, skip this step of calculation; otherwise, calculate the difference Xm between the first write data Xn1 and the second write data Xn2; If the PSD indication is high, the FFT complex multiplication operation request {OP2, ai2, cj2, bi2, dj2} is: OP2=1, ai2=real(Xn2)=cj2, bi2=imag(Xn2)=dj2; otherwise, OP2=IFFT indication, ai2=real(Xm), bi2=imag(Xm), cj2=real(Wn), dj2=imag(Wn).

5. A multifunctional floating-point operation method, implemented based on the multifunctional floating-point operation system based on FPGA according to claim 1, comprising: The floating-point frequency shift module receives the frequency shift factor and the control signal and receives the floating-point IQ data or the floating-point frequency domain data, generates a frequency shift complex multiplication operation request and sends it to the multifunctional floating-point complex multiplication operation module; While the floating-point frequency shift module is receiving, the floating-point FFT / IFFT / power spectrum module receives a control signal, receives the frequency shift result received by the floating-point frequency shift module, or receives floating-point IQ data or floating-point frequency domain data; and simultaneously receiving a control signal; generating an FFT complex multiplication operation request and sending it to a multifunctional floating-point complex multiplication operation module; The multifunctional floating-point complex multiplication operation module sends the calculated frequency shift result to the floating-point frequency shift module, or sends the calculated FFT / IFFT result data and FFT / IFFT power spectrum data to the floating-point FFT / IFFT / power spectrum module.

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