RNF system-level verification system, method, device, equipment and storage medium

Abstract

The present application discloses a system-level verification system, method, device, electronic device and storage medium of RNF. The system includes: a VIP verification platform, each RNF and a memory module. The VIP verification platform includes an HNF and an SNF. Each RNF is connected to the HNF, the HNF is connected to the SNF, and the SNF is connected to the memory module. Each RNF includes a processor core, and the memory module is used to place a test program.

Description

Technical Field

[0001] The present application belongs to the field of computer technology, and specifically relates to a system-level verification method, device, equipment and readable storage medium of a RNF. Background Art

[0002] In the design of multi-core processors, each processor core has its corresponding requester node (RNF). These RNFs are responsible for receiving memory access requests generated by the processor core and sending the requests to the next level node, such as the home node (HNF) or subordinate node (SNF) through the coherent hub interface (CHI) protocol bus.

[0003] In a multi-core processor system, data consistency is a key factor in ensuring system stability and correctness, ensuring that all cores see consistent memory data when accessing shared memory. As the node for the processor core to send requests to the outside, RNF plays a very important role in maintaining multi-core data consistency: in write requests or operations involving data modification, RNF ensures data consistency by working in conjunction with HNF. Due to the key role of RNF in a multi-core processor system, system-level consistency verification of RNF is particularly important.

[0004] In the prior art, system-level consistency verification of RNF requires manual writing of test stimuli, which increases the workload of development. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a system-level verification system, method, apparatus, device and readable storage medium for RNF, which can solve the problem in the prior art that system-level consistency verification of RNF requires manual writing of test stimuli, thereby increasing the development workload.

[0006] In a first aspect, an embodiment of the present application provides a system-level verification system of an RNF, including:

[0007] VIP verification platform, each RNF and memory module, the VIP verification platform includes HNF and SNF;

[0008] Each of the RNFs is connected to the HNF, the HNF is connected to the SNF, and the SNF is connected to the memory module;

[0009] Each of the RNFs includes a processor core, and the memory module is used to store the test program.

[0010] Optionally, each of the RNFs is connected to the HNF via an interface of a CHI bus connected to the VIP verification platform;

[0011] The channels of the RNF include: a TXREQ channel, a TXDAT channel and a TXRSP channel for transmitting information of the HNF, and a RXRSP channel, a RXDAT channel and a RXSNP channel for transmitting information of the HNF;

[0012] The channels of the interface of the CHI bus include: an RXREQ channel, an RXDAT channel and an RXRSP channel for the RNF to transmit information, a TXRSP channel, a TXDAT channel and a TXSNP channel for the RNF to transmit information, an RXRSP channel and an RXDAT channel for the SNF to transmit information, and a TXREQ channel, a TXDAT channel and a TXRSP channel for the SNF to transmit information.

[0013] Optionally, the memory module is connected to an AXI bus, the SNF is connected to a CHI bus, and a chi_to_axi bridge is connected between the AXI bus and the CHI bus.

[0014] Optionally, the number of the RNFs is N, the number of the processor cores is N, and one RNF corresponds to one processor core; wherein N is a positive integer.

[0015] In a second aspect, an embodiment of the present application provides a system-level verification method of an RNF, including:

[0016] The top level of the VIP verification platform reads the test program and places it in a memory module connected to the VIP verification platform;

[0017] Each processor core connected to the VIP verification platform sends a read request to the memory module through the VIP verification platform; wherein the read request is used to obtain the test program;

[0018] In a case where the memory module returns the test program based on the read request, each of the processor cores generates a preset number of test stimuli according to the test program;

[0019] Each of the processor cores sends the test stimulus in the form of a request to the HNF in the VIP verification platform or the SNF in the VIP verification platform through the corresponding RNF;

[0020] In the case where each of the RNFs updates the cache status based on each of the test stimuli, a system-level verification is performed based on whether the change in the cache status of each of the RNFs complies with the CHI protocol.

[0021] Optionally, the request is any one of the following: a read request, a write request, a request without data, and a snoop request.

[0022] Optionally, in the case where each of the RNFs updates the cache state based on each of the test stimuli, before performing system-level verification according to whether the change of the cache state of each of the RNFs complies with the CHI protocol, the method further includes:

[0023] In the case where the request is a read request, obtaining cached data in the VIP verification platform or data in the memory module based on the read request;

[0024] In the case where the request is a write request, writing data in a cache in the VIP verification platform or the memory module based on the write request;

[0025] According to the acquired data or the written data, the cache status of each RNF is updated.

[0026] Optionally, in the case where each of the RNFs updates the cache state based on each of the test stimuli, performing system-level verification according to whether the change of the cache state of each of the RNFs complies with the CHI protocol includes:

[0027] In the case where each of the RNFs updates a cache state based on each of the test stimuli, performing system-level verification according to whether the change in the cache state of each of the RNFs includes changes between all of the following states;

[0028] Among them, the state change refers to a change from one state to another state; the RNF cache state includes: only exists in the current RNF cache, does not exist in other caches, and does not exist in the memory module; only exists in the current RNF cache, does not exist in other caches, and exists in the memory module; exists in the current RNF cache and also exists in other caches; does not exist in the current RNF cache.

[0029] In a third aspect, an embodiment of the present application provides a system-level verification device for RNF, including:

[0030] A reading module, used for reading the top-level test program of the VIP verification platform and placed in a memory module connected to the VIP verification platform;

[0031] A first sending module, configured for each processor core connected to the VIP verification platform to send a read request to the memory module through the VIP verification platform; wherein the read request is used to obtain the test program;

[0032] A generating module, configured to generate a preset number of test stimuli according to the test program by each processor core when the memory module returns the test program based on the read request;

[0033] A second sending module, configured for each of the processor cores to send the test stimulus in the form of a request to the HNF in the VIP verification platform or the SNF in the VIP verification platform through the corresponding RNF;

[0034] The verification module is used to perform system-level verification according to whether the change of the cache state of each RNF complies with the CHI protocol when each RNF updates the cache state based on each test stimulus.

[0035] Optionally, the request is any one of the following: a read request, a write request, a request without data, and a snoop request.

[0036] Optionally, the device further comprises:

[0037] An acquisition module, used for acquiring cached data in the VIP verification platform or data in the memory module based on the read request when the request is a read request;

[0038] A write module, used for writing data in the cache in the VIP verification platform or the memory module based on the write request when the request is a write request;

[0039] An update module is used to update the cache status of each RNF according to the acquired data or the written data.

[0040] Optionally, the verification module includes:

[0041] A verification unit, configured to perform system-level verification according to whether a change in the cache state of each RNF includes a change between all of the following states when each RNF updates a cache state based on each of the test stimuli;

[0042] Among them, the state change refers to a change from one state to another state; the RNF cache state includes: only exists in the current RNF cache, does not exist in other caches, and does not exist in the memory module; only exists in the current RNF cache, does not exist in other caches, and exists in the memory module; exists in the current RNF cache and also exists in other caches; does not exist in the current RNF cache.

[0043] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the program or instructions are executed by the processor, the steps of the method described in the first aspect are implemented.

[0044] In a fifth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the steps of the method described in the first aspect are implemented.

[0045] In a sixth aspect, an embodiment of the present application provides a chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run a program or instruction to implement the method described in the first aspect.

[0046] In a seventh aspect, an embodiment of the present application provides a computer program product, which is stored in a storage medium and is executed by at least one processor to implement the method described in the first aspect.

[0047] In an embodiment of the present application, a VIP verification platform is connected to a processor core to be tested, and each processor core includes an RNF. The processor core sends a read request to the memory module through the VIP verification platform, so that the memory module sends the test program to the processor core through the VIP verification platform, and the processor core generates a preset number of test stimuli based on the test program. Furthermore, the processor core sends a preset number of test stimuli to HNF or SNF in the form of a request through RNF, so that HNF or SNF completes the operation according to the request and returns a response, and then based on each test stimulus, the cache status of each RNF is updated accordingly. Among them, the VIP verification platform collects code coverage and functional coverage based on the update status of each RNF cache status to verify whether all cache status changes that comply with the CHI protocol are covered, thereby completing the verification. It can be seen that the system-level consistency verification of RNF provided in the embodiment of the present application does not require manual writing of test stimuli, thereby reducing the workload of development. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 is one of the block diagrams of a system-level verification system of an RNF according to an exemplary embodiment;

[0049] Figure 2 is a second block diagram of a system-level verification system of an RNF according to an exemplary embodiment;

[0050] Figure 3 is a flow chart of a system-level verification method of RNF according to an exemplary embodiment;

[0051] Figure 4 is a block diagram of a system-level verification device for RNF according to an exemplary embodiment;

[0052] Figure 5 A block diagram of an electronic device according to an exemplary embodiment;

[0053] Figure 6 The figure is a schematic diagram showing the hardware structure of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0055] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0056] The following, in conjunction with the accompanying drawings, describes in detail the system-level verification system of the RNF provided by the embodiment of the present application through specific embodiments and their application scenarios.

[0057] Figure 1 1 is a block diagram of a system-level verification system of an RNF according to an exemplary embodiment, and the system-level verification system of the RNF includes:

[0058] Verification Intellectual Property (VIP) verification platform 101, each RNF 102 and memory module 103, VIP verification platform 101 includes HNF and SNF;

[0059] Each RNF 102 is connected to the HNF, the HNF is connected to the SNF, and the SNF is connected to the memory module 103;

[0060] Each RNF 102 includes a processor core, and a memory module 103 is used to store the test program.

[0061] The VIP verification platform is a pre-designed and verified module that includes functions such as generating test stimuli, monitoring the input and output results of the design under test, and collecting coverage. The VIP verification platform is an existing verification component that can be quickly integrated into the verification environment and has good flexibility. The VIP verification platform supports various standard protocols, such as the Peripheral Component Interconnect Express (PCIe) protocol, the Advanced Xtensible Interface (AXI) protocol, the CHI protocol, etc. In addition, the VIP verification platform includes comprehensive protocol checking and coverage analysis. Compared with other verification platforms, the VIP verification platform can ensure that the design under test complies with the protocol specifications.

[0062] Among them, the CHI protocol is a new high-performance, scalable system-level interconnect consistency protocol proposed by ARM. The consistency characteristics are mainly reflected in: monitoring the read and write access of different processor cores, accelerators, and (input) I / (output) O devices to memory data; ensuring that the data between the cache and the main memory and between different caches remain synchronized; ensuring sequential access to the same data in the cache or memory.

[0063] This embodiment uses a configurable VIP verification platform to perform system-level verification of RNF, which includes a requester node (RN) that meets the CHI protocol, a node HN (Home Node) located in the interconnect (ICN), a subordinate node (SN), a CHI interface and an AXI interface.

[0064] Among them, RNF is one of the types of RN. It receives read requests and write requests from the processor core, converts them into requests that comply with the CHI protocol, and then sends them to the appropriate destination node, such as HNF and SNF, through the CHI protocol bus.

[0065] HNF is one type of HN. It receives requests from RNF, manages memory copies, and coordinates updates of multiple cache copies to ensure data consistency in the system. For example, when processing a write request, HNF will send an invalidation request to other RNFs to invalidate the shared data.

[0066] SNF is one of the types of SN, which receives a request from RNF or HNF, completes the required operation and returns a response.

[0067] In this embodiment, a configurable VIP verification platform is connected to the RNF under test, and each RNF includes a processor core. There is a cache in the core to place data of frequently accessed addresses in the cache, which can reduce the number of memory accesses, thereby improving the performance of the processor core.

[0068] Configuration of the VIP verification platform includes: the number and identification (ID) of the connected RNFs; the CHI protocol version used; the data width of the CHI bus; the type, number and ID of the RN, HN and SN in the verification platform; the interface type of the ICN on the RNF side and the interface type on the SNF side. Among them, this embodiment uses the ICN and SNF of the verification platform, and the ICN includes the HNF and the cache.

[0069] For reference, configure the number of RNF, HNF and SNF: the number of RNF is 0, the number of HNF is 1, and the number of SNF is 1. Use the CHI protocol of CHI_E version; the data width of the CHI bus is 256 bits, and the address width is 44 bits; configure the interface type of ICN, the interface type connected to RNF is RNF, and the interface type connected to SNF is SNF.

[0070] In addition, the field information of different channels of CHI bus is customized according to CHI protocol. Channels include: Response channel, Snoop channel, Data channel and Request channel. Field information includes data width of Data channel (SVT_CHI_DAT_FLIT_MAX_DATA_WIDTH), address width of Request channel (SVT_CHI_REQ_ADDR_WIDTH), etc.

[0071] Among them, this embodiment places the test program in the memory module. The top layer of the configurable VIP verification platform enables the processor core to obtain the instructions stored in the memory module by calling functions. After decoding, the RNF issues a request and then sends it to the HNF or SNF. Finally, the behavior of multiple RNFs is checked for consistency based on the printed logs, code coverage, and function coverage results.

[0072] In this embodiment, the test stimulus is automatically generated by the test program.

[0073] Based on the system-level verification system of RNF provided in this embodiment, the verification method is as follows: the processor core in each RNF sends a read request to the memory module through the VIP verification platform to obtain the test program, so that the processor core automatically generates a preset number of test stimuli according to the test program. Specifically, at the top level of the configurable VIP verification platform, the test program generated by the software is read by calling the readmemh() function, and then the test program is placed in the memory module. The processor core obtains the test program by sending a read request to the memory module. The processor core decodes the acquired test program, and then sends the preset number of test stimuli to the next level node, HNF or SNF, in the form of a request through RNF. Finally, the function points are extracted according to the design documents and the CHI protocol, and the code coverage and function coverage are collected to complete the verification.

[0074] In an embodiment of the present application, a VIP verification platform is connected to a processor core to be tested, and each processor core includes an RNF. The processor core sends a read request to the memory module through the VIP verification platform, so that the memory module sends the test program to the processor core through the VIP verification platform, and the processor core generates a preset number of test stimuli based on the test program. Furthermore, the processor core sends a preset number of test stimuli to HNF or SNF in the form of a request through RNF, so that HNF or SNF completes the operation according to the request and returns a response, and then based on each test stimulus, the cache status of each RNF is updated accordingly. Among them, the VIP verification platform collects code coverage and functional coverage based on the update status of each RNF cache status to verify whether all cache status changes that comply with the CHI protocol are covered, thereby completing the verification. It can be seen that the system-level consistency verification of RNF provided in the embodiment of the present application does not require manual writing of test stimuli, thereby reducing the workload of development.

[0075] In a system-level verification system of RNFs according to an exemplary embodiment, each RNF is connected to the HNF via an interface of a CHI bus connected to a VIP verification platform;

[0076] The channels of RNF include: TXREQ channel, TXDAT channel and TXRSP channel for HNF information transmission, and RXRSP channel, RXDAT channel and RXSNP channel for HNF information transmission;

[0077] The channels of the interface of the CHI bus include: RXREQ channel, RXDAT channel and RXRSP channel for RNF transmission information, TXRSP channel, TXDAT channel and TXSNP channel for RNF transmission information, RXRSP channel and RXDAT channel for SNF transmission information, and TXREQ channel, TXDAT channel and TXRSP channel for SNF transmission information.

[0078] In this embodiment, a verification environment is built using a configurable VIP verification platform.

[0079] like Figure 1 As shown, the instantiated RNF is connected to the interface of the CHI bus of the configurable VIP verification platform 10 to form a RNF-HNF-SNF system.

[0080] Among them, the channels of RNF include: an external sending request (TXREQ) channel, an external sending data (TXDAT) channel, and an external sending response (TXRSP) channel for HNF transmission information; a receiving response (RXRSP) channel, a receiving data (RXDAT) channel, and a receiving snoop request (RXSNP) channel for HNF transmission information.

[0081] The channels of the interface of the CHI bus connected thereto include: a receive request (RXREQ) channel, a RXDAT channel and a RXRSP channel for RNF transfer information; and a TXRSP channel, a TXDAT channel and a send snoop request (TXSNP) channel for RNF transfer information.

[0082] Among them, the external interface of RNF is the CHI protocol interface.

[0083] In addition, based on the connection relationship between HNF and SNF, the channels of the interface of the CHI bus include: an RXRSP channel and an RXDAT channel for transmitting information to the SNF; and a TXREQ channel, a TXDAT channel and a TXRSP channel for transmitting information to the SNF.

[0084] In this embodiment, a method for connecting an RNF to be tested to a VIP verification platform is provided, wherein the RNF is connected to the VIP verification platform via an interface of a CHI bus. Based on this connection relationship, channels included in each connected interface are introduced to ensure that the VIP verification platform can be used to implement system-level verification of the RNF.

[0085] In a system-level verification system of RNF according to an exemplary embodiment, a memory module is connected to an AXI bus, an SNF is connected to a CHI bus, and a chi_to_axi bridge is connected between the AXI bus and the CHI bus.

[0086] In this embodiment, the instantiated memory module is connected to the SNF in the configurable VIP verification platform to form a path to access the memory. The memory module is connected to the AXI bus, and the SNF is connected to the CHI bus, so the chi_to_axi bridge in the configurable VIP verification platform is used. The bridge can convert the CHI request into the AXI request, so that the AXI bus can be accessed.

[0087] Optionally, the data width of the memory module used is 128 bits and the address width is 32 bits.

[0088] Among them, the chi_to_axi bridge is configured, including the number of interfaces, interface type and data width of the AXI master and AXI slave. Specifically, the verification platform uses the AXI master interface, that is, the number of interfaces on the master side is 1, the number of interfaces on the slave side is 0, and the memory module with an AXI4 interface is used as the AXI slave side. The interface type of the AXImaster side is AXI4, and the data width is 128 bits.

[0089] In a system-level verification system of RNFs according to an exemplary embodiment, the number of RNFs is N, the number of processor cores is N, and one RNF corresponds to one processor core, where N is a positive integer.

[0090] In this embodiment, the number of RNFs is set to be configurable, so that it can be used for verification of different numbers of processor cores. For example, the number of RNFs is 4 or 8.

[0091] like Figure 2 As shown, in a system-level verification system of RNF shown according to an exemplary embodiment, the outermost layer of the VIP verification platform is the top layer, and the run_test() function is called at the top layer to start the verification platform. The top layer contains an empty test. The embodiment of the present application uses software to generate a test program and then generate a test stimulus, rather than directly using the written test stimulus. The empty test stimulus is used to start the verification platform. Further, test contains a CHI system environment. In this environment, the test time can be set, the verification platform can be configured, the field information of different channels can be customized, the chi_to_axi bridge can be turned on, the RNF and the ICN facing the RNF end of the ic_rn_if interface are connected, the SNF and the ICN facing the SNF end of the ic_sn_if interface are connected, and the AXI master end of the SNF is connected to the AXI end of the memory module. The CHI system environment includes: ICN, SN and configuration platform containing HN.

[0092] In a system-level verification system of an RNF according to an exemplary embodiment, a method of starting a test and pausing a test is as follows.

[0093] The system-level test of RNF is started by executing the makefile script with the command "make USE_SIMULATOR=vcsvlog". When the test program calls the WFI (Wait for Interrupt) instruction, the test of the current RNF is suspended.

[0094] Figure 3 The flowchart of a system-level verification method of RNF according to an exemplary embodiment is shown. The method is applied to an electronic device as an example for explanation. The system-level verification method of RNF includes the following steps:

[0095] In step 110, the top layer of the VIP verification platform reads the test program and places it in a memory module connected to the VIP verification platform.

[0096] like Figure 2 As shown, at the top level of the configurable VIP verification platform, the test program generated by the software is read by calling the readmemh() function, and then the test program is placed in the memory module.

[0097] In step 120, each processor core connected to the VIP verification platform sends a read request to the memory module through the VIP verification platform; wherein the read request is used to obtain the test program.

[0098] In this step, the processor core obtains the test program by sending a read request to the memory module.

[0099] Among them, the processor core sends a read request, which passes through the HNF and SNF in sequence and is finally sent to the memory module.

[0100] In step 130 , when the memory module returns the test program based on the read request, each processor core generates a preset number of test stimuli according to the test program.

[0101] In this step, the processor core decodes the acquired test program to obtain a preset number of test stimuli.

[0102] Optionally, the preset number is 10,000.

[0103] Among them, the memory module returns the test program, passes through SNF and HNF in sequence, and finally returns to the processor core.

[0104] In step 140, each processor core sends the test stimulus in the form of a request to the HNF in the VIP verification platform or the SNF in the VIP verification platform through the corresponding RNF.

[0105] In this step, the RNF sends the test stimulus in the form of a request to the next-level node, which is the HNF or SNF.

[0106] In step 150, when each RNF updates the cache status based on each test stimulus, a system-level verification is performed based on whether the change of the cache status of each RNF complies with the CHI protocol.

[0107] The RNF cache states are updated based on the test stimuli. Further, according to the changes of the RNF cache states, it is determined whether the changes of the RNF cache states comply with the CHI protocol.

[0108] Specifically, based on all changes in the RNF cache state that comply with the CHI protocol, it is determined whether all of them occur. If all of them occur, the functional coverage is 100% and the verification is completed.

[0109] In an embodiment of the present application, a VIP verification platform is connected to a processor core to be tested, and each processor core includes an RNF. The processor core sends a read request to the memory module through the VIP verification platform, so that the memory module sends the test program to the processor core through the VIP verification platform, and the processor core generates a preset number of test stimuli based on the test program. Furthermore, the processor core sends a preset number of test stimuli to HNF or SNF in the form of a request through RNF, so that HNF or SNF completes the operation according to the request and returns a response, and then based on each test stimulus, the cache status of each RNF is updated accordingly. Among them, the VIP verification platform collects code coverage and functional coverage based on the update status of each RNF cache status to verify whether all cache status changes that comply with the CHI protocol are covered, thereby completing the verification. It can be seen that the system-level consistency verification of RNF provided in the embodiment of the present application does not require manual writing of test stimuli, thereby reducing the workload of development.

[0110] In a process of a system-level verification method of an RNF according to an exemplary embodiment, the request is any one of the following: a read request, a write request, a request without data, and a snoop request.

[0111] In the CHI protocol, requests are transmitted in the form of packets. The contents of the packets contain various information about the request, including information that determines the properties of the request. This information is determined by fixed fields in the CHI protocol, and the field values ​​vary. These fields include Exclusive (whether exclusive access is supported), Snpatrr (whether Snoop requests are supported), ExpCompack (whether the request sent by RNF is completed after completion) and so on.

[0112] The snoop request can be described as follows: RNF0 sends a read request to HNF, which contains various information, including the access address. HNF accepts the request and checks whether the data of the requested address exists in the cache. If not, HNF will send a snoop request to other RNFs to check whether other RNFs have cached the data of the address. If so, HNF obtains the data and returns it to RNF0. The data is not obtained from the memory module here because the speed of reading the memory module is too slow. If the data exists in the RNF cache, there is no need to access the memory module.

[0113] In this embodiment, the purpose of verification is to verify whether the behavior of the RNF complies with the CHI protocol. In implementation, it can verify whether the attributes of the request comply with the CHI protocol, and more specifically, it can verify whether the changes in the cache status of each RNF comply with the CHI protocol.

[0114] In a process of a system-level verification method of an RNF according to an exemplary embodiment, before step 150, the method further includes the following steps:

[0115] In step A1, when the request is a read request, cached data or memory module data in the VIP verification platform is acquired based on the read request.

[0116] In this step, if the request sent by the RNF is a read request, it is necessary to obtain the data from the cache in the VIP verification platform or the data in the memory module.

[0117] In step A2, when the request is a write request, data is written into a cache or a memory module in the VIP verification platform based on the write request.

[0118] In this step, if the request sent by the RNF is a write request, the data needs to be written into the cache in the VIP verification platform or into the memory module.

[0119] In step A3, the cache status of each RNF is updated according to the acquired data or the written data.

[0120] In this step, the cache status of each RNF is updated based on the acquired data or the written data, so that the changes of the cache status of each RNF before and after the update can be obtained.

[0121] In a process of a system-level verification method of an RNF according to an exemplary embodiment, step 150 includes the following steps:

[0122] In sub-step B1, when each RNF updates the cache state based on each test stimulus, a system-level verification is performed based on whether the change of the cache state of each RNF includes changes between all the following states.

[0123] Among them, state change refers to a change from one state to another; RNF cache states include: only exists in the current RNF cache, does not exist in other caches, and does not exist in the memory module; only exists in the current RNF cache, does not exist in other caches, and exists in the memory module; exists in the current RNF cache and also exists in other caches; does not exist in the current RNF cache.

[0124] Specifically, the state changes that comply with the CHI protocol include: I->UC, I->SC, I->UD, UC->I, UC->SC, UC->UD, SC->I, SC->UC, SC->UD, UD->I, UD->UC, UD->SC.

[0125] Among them, the state that only exists in the current RNF cache, does not exist in other caches, and does not exist in the memory module is state UD (Unique Dirty); the state that only exists in the current RNF cache, does not exist in other caches, and exists in the memory module is state UC (Unique Clean); the state that exists in the current RNF cache and also in other caches is state SC (Share Clean); the state that does not exist in the current RNF cache is state I (Invalid).

[0126] In this embodiment, the code coverage is collected first. When the code coverage is 100%, the functional coverage is collected. If all the above-mentioned state changes that comply with the CHI protocol occur, the functional coverage is 100%, and the verification is completed.

[0127] In a system-level verification method of RNF shown according to an exemplary embodiment, VIP verification platform and hardware simulation platform verification are combined: the combination of the two can discover more complex errors (bugs) with wider coverage and higher accuracy.

[0128] In summary, this application uses a configurable VIP verification platform and combines the test program to automatically generate test stimuli for system-level consistency testing of RNF. It has the following advantages: the VIP verification platform can speed up the verification process and shorten the verification cycle; the VIP verification platform is developed in accordance with the CHI protocol and is fully functional. It can not only ensure the correctness of the verification environment, but also perform comprehensive verification; the VIP verification platform is reusable and highly flexible; compared with manually written test stimuli, the test stimuli generated by the test program have a wider coverage, high reusability, and high efficiency.

[0129] The RNF system-level verification method provided in the embodiment of the present application can be executed by a RNF system-level verification device. In the embodiment of the present application, the RNF system-level verification device performing the RNF system-level verification method is taken as an example to illustrate the RNF system-level verification device provided in the embodiment of the present application.

[0130] Figure 4 1 is a block diagram of a system-level verification device for RNF according to an exemplary embodiment, including:

[0131] The reading module 401 is used for reading the top-level test program of the VIP verification platform and is placed in a memory module connected to the VIP verification platform;

[0132] The first sending module 401 is used for each processor core connected to the VIP verification platform to send a read request to the memory module through the VIP verification platform; wherein the read request is used to obtain a test program;

[0133] A generating module 403, configured to generate a preset number of test stimuli according to the test program by each processor core when the memory module returns the test program based on the read request;

[0134] The second sending module 404 is used for each processor core to send the test stimulus in the form of a request to the HNF in the VIP verification platform or the SNF in the VIP verification platform through the corresponding RNF;

[0135] The verification module 405 is used to perform system-level verification according to whether the change of the cache state of each RNF complies with the CHI protocol when each RNF updates the cache state based on each test stimulus.

[0136] In an embodiment of the present application, a VIP verification platform is connected to a processor core to be tested, and each processor core includes an RNF. The processor core sends a read request to the memory module through the VIP verification platform, so that the memory module sends the test program to the processor core through the VIP verification platform, and the processor core generates a preset number of test stimuli based on the test program. Furthermore, the processor core sends a preset number of test stimuli to HNF or SNF in the form of a request through RNF, so that HNF or SNF completes the operation according to the request and returns a response, and then based on each test stimulus, the cache status of each RNF is updated accordingly. Among them, the VIP verification platform collects code coverage and functional coverage based on the update status of each RNF cache status to verify whether all cache status changes that comply with the CHI protocol are covered, thereby completing the verification. It can be seen that the system-level consistency verification of RNF provided in the embodiment of the present application does not require manual writing of test stimuli, thereby reducing the workload of development.

[0137] Optionally, the request is any one of the following: a read request, a write request, a request with no data, and a snoop request.

[0138] Optionally, the device further comprises:

[0139] An acquisition module, used for acquiring cached data or memory module data in the VIP verification platform based on the read request when the request is a read request;

[0140] A write module, used for writing data in a cache or a memory module in the VIP verification platform based on the write request when the request is a write request;

[0141] The update module is used to update the cache status of each RNF according to the acquired data or written data.

[0142] Optionally, the verification module 405 includes:

[0143] A verification unit, configured to perform system-level verification according to whether a change in the cache state of each RNF includes a change between all of the following states when each RNF updates a cache state based on each of the test stimuli;

[0144] Among them, state change refers to a change from one state to another; RNF cache states include: only exists in the current RNF cache, does not exist in other caches, and does not exist in the memory module; only exists in the current RNF cache, does not exist in other caches, and exists in the memory module; exists in the current RNF cache and also exists in other caches; does not exist in the current RNF cache.

[0145] The system-level verification device of RNF in the embodiment of the present application can be an electronic device, or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal, or it can be other devices other than a terminal. Exemplarily, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR) / virtual reality (virtual reality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc. It can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiment of the present application.

[0146] The system-level verification device of RNF provided in the embodiment of the present application can realize Figure 3 To avoid repetition, the various processes implemented by the method embodiment are not described here.

[0147] Alternatively, if Figure 5 As shown, an embodiment of the present application also provides an electronic device 500, including a processor 501 and a memory 502, wherein the memory 502 stores a program or instruction that can be executed on the processor 501, and when the program or instruction is executed by the processor 501, each step of the above-mentioned RNF system-level verification method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0148] It should be noted that the electronic devices in the embodiments of the present application include the mobile electronic devices and non-mobile electronic devices mentioned above.

[0149] Figure 6 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of the present application.

[0150] The electronic device 1000 includes but is not limited to: a radio frequency unit 1001, a network module 1002, an audio output unit 1003, an input unit 1004, a sensor 1005, a display unit 1006, a user input unit 1007, an interface unit 1008, a memory 1009, and a processor 1010 and other components.

[0151] Those skilled in the art will appreciate that the electronic device 1000 may also include a power source (such as a battery) for supplying power to each component, and the power source may be logically connected to the processor 1010 through a power management system, thereby implementing functions such as managing charging, discharging, and power consumption management through the power management system. Figure 6 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be described in detail here.

[0152] As can be seen from the above, the technical solution provided by the embodiment of the present application connects the VIP verification platform to the processor core to be tested, and each processor core includes RNF. The processor core sends a read request to the memory module through the VIP verification platform, so that the memory module sends the test program to the processor core through the VIP verification platform, and the processor core generates a preset number of test stimuli based on the test program. Furthermore, the processor core sends a preset number of test stimuli to HNF or SNF in the form of a request through RNF, so that HNF or SNF completes the operation according to the request and returns a response, and then based on each test stimulus, the cache status of each RNF is updated accordingly. Among them, the VIP verification platform collects code coverage and functional coverage based on the update status of each RNF cache status to verify whether all cache status changes that comply with the CHI protocol are covered, thereby completing the verification. It can be seen that the system-level consistency verification of RNF provided by the embodiment of the present application does not require manual writing of test stimuli, thereby reducing the workload of development.

[0153] It should be understood that in the embodiment of the present application, the input unit 1004 may include a graphics processor (Graphics Processing Unit, GPU) 10041 and a microphone 10042, and the graphics processor 10041 processes the image data of the static picture or video obtained by the image capture device (such as a camera) in the video capture mode or the image capture mode. The display unit 1006 may include a display panel 10061, and the display panel 10061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 1007 includes a touch panel 10071 and at least one of other input devices 10072. The touch panel 10071 is also called a touch screen. The touch panel 10071 may include two parts: a touch detection device and a touch controller. Other input devices 10072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.

[0154] The memory 1009 can be used to store software programs and various data. The memory 1009 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, an image playback function, etc.), etc. In addition, the memory 1009 may include a volatile memory or a non-volatile memory, or the memory 1009 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM) and a direct memory bus random access memory (DRRAM). The memory 109 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0155] The processor 1010 may include one or more processing units; optionally, the processor 1010 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It is understandable that the modem processor may not be integrated into the processor 1010.

[0156] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, each process of the above-mentioned RNF system-level verification method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0157] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0158] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned RNF system-level verification method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0159] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0160] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the system-level verification method embodiment of the RNF as described above, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0161] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0162] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0163] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A system-level verification method for RNF, characterized in that: include: The top level of the VIP verification platform reads the test program and places it in a memory module connected to the VIP verification platform; Each processor core connected to the VIP verification platform sends a read request to the memory module through the VIP verification platform; wherein the read request is used to obtain the test program; In a case where the memory module returns the test program based on the read request, each of the processor cores automatically generates a preset number of test stimuli according to the test program; Each of the processor cores sends the test stimulus in the form of a request to the HNF in the VIP verification platform or the SNF in the VIP verification platform through the corresponding RNF; In the case where the request is a read request, obtaining cached data in the VIP verification platform or data in the memory module based on the read request; In the case where the request is a write request, writing data in a cache in the VIP verification platform or the memory module based on the write request; According to the acquired data or the written data, the RNF cache status is updated; In the case where each of the RNFs updates a cache state based on each of the test stimuli, performing system-level verification according to whether a change in the cache state of each of the RNFs complies with the CHI protocol; In the case where each of the RNFs updates the cache state based on each of the test stimuli, performing system-level verification according to whether the change of the cache state of each of the RNFs complies with the CHI protocol includes: In the case where each of the RNFs updates a cache state based on each of the test stimuli, performing system-level verification according to whether the change in the cache state of each of the RNFs includes changes between all of the following states; Among them, the change of the RNF cache state refers to a change from one state to another state; the RNF cache state includes: only exists in the current RNF cache, does not exist in other caches, and does not exist in the memory module; only exists in the current RNF cache, does not exist in other caches, and exists in the memory module; exists in the current RNF cache and also exists in other caches; does not exist in the current RNF cache.

2. The method according to claim 1, characterized in that The request is any one of the following: a read request, a write request, a request with no data, and a snoop request.

3. A system-level verification device for RNF, characterized in that: include: The read module is used to read the top-level test program of the VIP verification platform and is placed in the memory module; A first sending module, configured for each processor core connected to the VIP verification platform to send a read request to the memory module; wherein the read request is used to obtain the test program; A generating module, configured to cause each processor core to automatically generate a preset number of test stimuli according to the test program when the memory module returns the test program based on the read request; A second sending module, configured for each of the processor cores to send the test stimulus in the form of a request to the HNF in the VIP verification platform or the SNF in the VIP verification platform through the corresponding RNF; An acquisition module, used for acquiring cached data in the VIP verification platform or data in the memory module based on the read request when the request is a read request; A write module, used for writing data in the cache in the VIP verification platform or the memory module based on the write request when the request is a write request; An updating module, used for updating the cache status of each RNF according to the acquired data or the written data; A verification module, configured to perform system-level verification according to whether the change of the cache state of each RNF complies with the CHI protocol when each RNF updates the cache state based on each test stimulus; The verification module comprises: A verification unit, configured to perform system-level verification according to whether a change in the cache state of each RNF includes a change between all of the following states when each RNF updates a cache state based on each of the test stimuli; Among them, the change of the RNF cache state refers to a change from one state to another state; the RNF cache state includes: only exists in the current RNF cache, does not exist in other caches, and does not exist in the memory module; only exists in the current RNF cache, does not exist in other caches, and exists in the memory module; exists in the current RNF cache and also exists in other caches; does not exist in the current RNF cache.

4. The device according to claim 3, characterized in that The request is any one of the following: a read request, a write request, a request with no data, and a snoop request.

5. A system-level verification system for RNF, characterized in that: include: VIP verification platform, each RNF and memory module, the VIP verification platform includes HNF and SNF; Each of the RNFs is connected to the HNF, the HNF is connected to the SNF, and the SNF is connected to the memory module; Wherein, each of the RNFs includes a processor core, and the memory module is used to store the test program; Each processor core connected to the VIP verification platform sends a read request to the memory module through the VIP verification platform; wherein the read request is used to obtain the test program; In a case where the memory module returns the test program based on the read request, each of the processor cores automatically generates a preset number of test stimuli according to the test program; Each of the processor cores sends the test stimulus in the form of a request to the HNF in the VIP verification platform or the SNF in the VIP verification platform through the corresponding RNF; In the case where the request is a read request, obtaining cached data in the VIP verification platform or data in the memory module based on the read request; In the case where the request is a write request, writing data in a cache in the VIP verification platform or the memory module based on the write request; According to the acquired data or the written data, the RNF cache status is updated; In the case where each of the RNFs updates a cache state based on each of the test stimuli, performing system-level verification according to whether a change in the cache state of each of the RNFs complies with the CHI protocol; In the case where each of the RNFs updates the cache state based on each of the test stimuli, performing system-level verification according to whether the change of the cache state of each of the RNFs complies with the CHI protocol includes: In the case where each of the RNFs updates a cache state based on each of the test stimuli, performing system-level verification according to whether the change in the cache state of each of the RNFs includes changes between all of the following states; Among them, the change of the RNF cache state refers to a change from one state to another state; the RNF cache state includes: only exists in the current RNF cache, does not exist in other caches, and does not exist in the memory module; only exists in the current RNF cache, does not exist in other caches, and exists in the memory module; exists in the current RNF cache and also exists in other caches; does not exist in the current RNF cache.

6. The system according to claim 5, characterized in that Each of the RNFs is connected to the HNF via an interface connected to the CHI bus of the VIP verification platform; The channels of the RNF include: a TXREQ channel, a TXDAT channel and a TXRSP channel for transmitting information of the HNF, and a RXRSP channel, a RXDAT channel and a RXSNP channel for transmitting information of the HNF; The channels of the interface of the CHI bus include: an RXREQ channel, an RXDAT channel and an RXRSP channel for the RNF to transmit information, a TXRSP channel, a TXDAT channel and a TXSNP channel for the RNF to transmit information, an RXRSP channel and an RXDAT channel for the SNF to transmit information, and a TXREQ channel, a TXDAT channel and a TXRSP channel for the SNF to transmit information.

7. The system according to claim 5, characterized in that The memory module is connected to the AXI bus, the SNF is connected to the CHI bus, and a chi_to_axi bridge is connected between the AXI bus and the CHI bus.

8. The system according to claim 5, characterized in that The number of the RNFs is N, the number of the processor cores is N, and one RNF corresponds to one processor core; wherein N is a positive integer.

9. An electronic device, characterized in that: include: processor; a memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the system-level verification method of the RNF as claimed in any one of claims 1 to 2.

10. A readable storage medium, characterized in that: The readable storage medium stores a program or an instruction, and when the program or the instruction is executed by the processor, the steps of the system-level verification method of the RNF as described in any one of claims 1 to 2 are implemented.

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