Data interaction method, device, electronic device and storage medium

Abstract

The embodiments of the present invention provide a data interaction method, device, electronic device and storage medium, which relate to the field of on-chip network technology. The on-chip network system includes: a first node, the first node includes: a network link interface and a final cache, the method includes: between the final cache and the network link interface in the first node, at least one first data buffer is set for the final cache; based on the first data buffer, data interaction between the network link interface and the final cache is realized. In the first node where the final cache of the on-chip network system is located, between the final cache and the network link interface, at least one first data buffer is set for the final cache, and the first data buffer between the final cache and the network link interface in the first node greatly speeds up the data transmission speed between the final cache and the network link interface, and greatly reduces the delay.

Description

Technical Field

[0001] The present invention relates to the technical field of network on chip, and in particular to a data interaction method, a data interaction device, an electronic device and a storage medium. Background Art

[0002] On-chip network refers to a network topology structure that is used to connect various functional modules or processing units inside a chip and can realize data transmission and communication. It is also called an on-chip interconnection network. The last-level cache of an on-chip network system refers to the last-level cache in the cache hierarchy between the processor and the main memory. The last-level cache is usually used to store frequently accessed but large-scale data blocks to provide faster access speeds and reduce the frequency of main memory access.

[0003] Currently, in a node where a last-level cache of an on-chip network system is located, data is directly transmitted between the last-level cache and a network link interface, resulting in a certain delay in data transmission. Summary of the invention

[0004] In view of the above problems, an embodiment of the present invention is proposed to provide a data interaction method that overcomes the above problems or at least partially solves the above problems, so as to reduce the data transmission delay between the last-level cache and the network link interface.

[0005] In a first aspect, the present invention provides a data interaction method, which is applied to an on-chip network system, wherein the on-chip network system comprises: a first node, wherein the first node comprises: a network link interface and a last-level cache, and the method comprises:

[0006] Between the final level cache and the network link interface in the first node, at least one first data buffer is provided for the final level cache;

[0007] Data interaction between the network link interface and the last-level cache is implemented based on the first data buffer.

[0008] In a second aspect, the present invention provides a data interaction device, which is applied to an on-chip network system, wherein the on-chip network system comprises: a first node, wherein the first node comprises: a network link interface and a last-level cache, and the device comprises:

[0009] A first data buffer setting module, configured to set at least one first data buffer for the last-level cache between the last-level cache and the network link interface in the first node;

[0010] A data interaction module is used to implement data interaction between the network link interface and the last-level cache based on the first data buffer.

[0011] In a third aspect, the present invention provides an electronic device, comprising: a multi-core processor, a memory, and a computer program stored in the memory and executable on the multi-core processor, wherein the multi-core processor implements the above-mentioned data interaction method when executing the program.

[0012] In a fourth aspect, the present invention provides a readable storage medium, which enables the electronic device to execute the above-mentioned data interaction method when the instructions or transactions in the storage medium are executed by a multi-core processor of the electronic device.

[0013] In a fifth aspect, the present invention provides a computer program product, including instructions or transactions, which, when executed by a multi-core processor in an electronic device, enable the electronic device to execute the above-mentioned data interaction method.

[0014] The present invention includes the following advantages:

[0015] In the first node where the last-level cache of the on-chip network system is located, at least one first data buffer is set for the last-level cache between the last-level cache and the network link interface, and data interaction between the network link interface and the last-level cache is realized based on the first data buffer. The first data buffer is set in the first node between the last-level cache and the network link interface, and is close to the network link interface and the last-level cache, which greatly speeds up the data transmission speed between the last-level cache and the network link interface and significantly reduces the data transmission delay between the last-level cache and the network link interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A partial structural diagram of a network-on-chip system of the present invention is shown;

[0017] Figure 2 A flow chart showing the steps of an embodiment of a data interaction method of the present invention is shown;

[0018] Figure 3 A structural block diagram of a data interaction device embodiment of the present invention is shown;

[0019] Figure 4 It is a structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] One of the core concepts of the embodiment of the present invention is that at least one first data buffer is set for the final cache between the final cache and the network link interface in the first node where the final cache of the on-chip network system is located, and the data interaction between the network link interface and the final cache is realized based on the first data buffer. The first data buffer set between the final cache and the network link interface in the first node is close to the network link interface and the final cache, which greatly speeds up the data transmission speed between the final cache and the network link interface, and greatly reduces the data transmission delay between the final cache and the network link interface. Moreover, due to the limited space of the final cache, the probability of the cache line in the final cache being evicted and replaced is relatively large, especially when the data in the cache line is modified, the data in the cache line is temporarily stored through the first data buffer, so as to facilitate the subsequent writing of the above data into the main memory. Further, at least one register stack is used as a first data buffer of the final cache. Since the data reading and writing speed of the register is very fast, the reading and writing within a single cycle can be easily realized, which can further speed up the data transmission speed between the final cache and the network link interface, and reduce the data transmission delay between the final cache and the network link interface. In addition, the control logic of the first data buffer of the present application is relatively simple, and has low complexity, high performance and small area while ensuring consistency.

[0022] The present application provides a data interaction method, which is applied to an on-chip network system. The on-chip network system may include: a first node, and the first node may include: a network link interface and a last level cache (Last Level Cache, LLC for short). The network link interface is an interface through which the first node communicates with the remaining nodes through the network link interface. The on-chip network system can achieve consistency according to a coherent hub interface (CHI) and the like, for example, an AMBA CHI consistency protocol and the like, and specific protocols and the like are not specifically limited.

[0023] Reference Figure 2 , the data interaction method may specifically include the following steps:

[0024] Step 101: Set at least one first data buffer for the last-level cache between the last-level cache and the network link interface in the first node.

[0025] The first data buffer may have two read and two write ports, one read and write port processes data interaction between the network link interface and the first data buffer, and the other read and write port processes data interaction between the first data buffer and the last-level cache.

[0026] The first data buffer here is set between the final cache and the network link interface in the first node. The first data buffer refers to a high-speed storage area for temporarily storing data for later processing. The size of the first data buffer can be adjusted as needed, and its purpose is to improve system performance, reduce delays and process data flow unevenness. The size of the first data buffer is not specifically limited. For example, the first data buffer can store 32 cache lines of data, or can store 64 cache lines of data. The first data buffer set in the first node, between the final cache and the network link interface, is close to the final cache and the network link interface, which greatly speeds up the data transmission speed between the final cache and the network link interface, and greatly reduces the data transmission delay between the final cache and the network link interface. There is no specific limitation on how many first data buffers are specifically set for a final cache.

[0027] For example, refer to Figure 1 The on-chip network system can comply with the AMBA CHI consistency protocol. The on-chip network system includes: a first node, where the first node is a consistency base node (HN-F) defined by the AMBA CHI protocol. The consistency base node can communicate with the remaining nodes ( Figure 1 The consistency base node may include: the network link interface and the final cache. The step is to set at least one first data buffer for the final cache between the final cache and the network link interface in the consistency base node. Figure 1 The data storage unit in is mainly used to store data.

[0028] Step 102: Implement data interaction between the network link interface and the last-level cache based on the first data buffer.

[0029] After setting at least one first data buffer for the final-level cache between the final-level cache and the network link interface in the first node, the present application will implement data interaction between the network link interface and the final-level cache based on the first data buffer. The first data buffer between the final-level cache and the network link interface in the first node greatly speeds up the data transmission speed between the final-level cache and the network link interface, and significantly reduces the data transmission delay between the final-level cache and the network link interface.

[0030] Optionally, the aforementioned step 101 may include: setting at least one register stack as a first data buffer of the final-level cache between the final-level cache and the network link interface in the first node. Specifically, the read and write speed of the final-level cache is much faster than the main memory of the on-chip network system, but it is still slower than the register. In this application, registers are used as the first data buffer of the final-level cache. Since the data read and write speed of the register is very fast, it is easy to achieve reading and writing within a single cycle, which can further speed up the data transmission speed between the final-level cache and the network link interface and further reduce delays.

[0031] It should be noted that the register file can be a two-read and two-write data register file, one read-write processing data interaction between the network link interface and the first data buffer, and the other read-write processing data interaction between the first data buffer and the last-level cache. The number of registers included in the register file is not specifically limited, and the specific type of the register is not specifically limited. For example, Figure 1 The data storage unit in the first data buffer may be a register file.

[0032] Optionally, the on-chip network system may further include: a second node, which is different from the aforementioned first node, and the second node includes: a front-level cache, where the front-level cache may refer to a cache that is closer to the last-level cache, and may be a first-level cache, a first-level cache, and a second-level cache, etc., which is not specifically limited. The method may also include: steps S1 and S2. Step S1, setting at least one second data buffer for the front-level cache in the second node; step S2, realizing data interaction with the front-level cache based on the second data buffer. The second node may also include a network link interface, which may be between the front-level cache and the network link interface in the second node, and at least one second data buffer is set for the front-level cache, or it may be a position closer to the processing core in the second node, and at least one second data buffer is set for the front-level cache. There is no specific limitation on how many second data buffers are set for the front-level cache. The present application will realize data interaction with the front-level cache based on the second data buffer, and the second data buffer set in the second node also greatly speeds up the data transmission speed of the front-level cache and greatly reduces the delay. Moreover, since the space of the previous level cache is limited, the cache line in the previous level cache is likely to be evicted and replaced. In particular, when the data in the cache line is modified, the data in the cache line is temporarily stored through the second data buffer to facilitate subsequent writing of the above data to the next level cache or main memory.

[0033] It should be noted that the specific implementation of the second data buffer may also refer to the aforementioned first data buffer, or the specific implementation of the second data buffer may be different from the aforementioned first data buffer, and no specific limitation is made to this.

[0034] Optionally, the aforementioned step 102 may include: when a cache line in the last-level cache is replaced and the data in the cache line is modified, writing the data in the cache line into the first data buffer; and writing the data written in the first data buffer into the main memory of the on-chip network system through the network link interface. Specifically, due to the limited space of the last-level cache, the probability of the cache line in the last-level cache being evicted and replaced is relatively high, especially when the data in the cache line is modified, that is, the cache line is a dirty cache line, and the data in the dirty cache line is temporarily stored through the first data buffer to facilitate the subsequent writing of the above data into the main memory. Specifically, the first data buffer will initiate a write request to the main memory to write the data in the dirty cache line into the main memory.

[0035] Optionally, the aforementioned step 102 may include: when the network link interface and the final cache write data to the first data buffer at the same time, in the order of the network link interface having the highest priority, the first data buffer having the second highest priority, and the final cache having the lowest priority, the data to be written of the network link interface, the data inside the first data buffer, and the data to be written of the final cache are merged, and the merged data are written into the first data buffer. Specifically, the network link interface is the interface for the first node and the other nodes to exchange data, so the data to be written of the network link interface is usually the latest data, and the final cache is farther away from the network link interface than the first data buffer, and the data to be written of the final cache usually has a certain delay, so in the present application, in the order of the network link interface having the highest priority, the first data buffer having the second highest priority, and the final cache having the lowest priority, the data to be written of the network link interface, the data inside the first data buffer, and the data to be written of the final cache are merged, and the merged data are written into the first data buffer, so that consistency can be ensured.

[0036] Optionally, before the aforementioned step 102, the method may further include: step 1021 and step 1022. Step 1021, setting a final-level cache read-write control pipeline between the final-level cache and the first data buffer, and the final-level cache read-write control pipeline controls the first enable signal between the final-level cache and the first data buffer; step 1022, setting a miss status holding register between the network link interface and the first data buffer, and the miss status holding register controls the second enable signal between the network link interface and the first data buffer. The aforementioned step 102 may include: based on the first enable signal and the second enable signal, realizing data interaction between the network link interface and the final-level cache. The first enable signal and the second enable signal here are both control signals for starting or stopping data interaction. The first data buffer has two read and two write ports. A final-level cache read-write control pipeline is provided between the final-level cache and the first data buffer. The final-level cache read-write control pipeline controls the first enable signal between the final-level cache and the first data buffer to control one read-write port. A miss status holding register (MSHR) is provided between the network link interface and the first data buffer. The second enable signal between the network link interface and the first data buffer is controlled by the MSHR to control another read-write port. Based on the first enable signal and the second enable signal, the two read and two write ports are controlled to realize data interaction between the network link interface and the final-level cache. The read-write control logic of the first data buffer is simply realized by the first enable signal, the second enable signal, the final-level cache read-write control pipeline, and the MSHR here.

[0037] Combine the following Figure 1 , further explaining this application.

[0038] As mentioned above, the on-chip network system can comply with the AMBA CHI consistency protocol, the consistency base node can communicate with other nodes through a network link interface, and the consistency base node can include: the network link interface and a final cache. Between the final cache and the network link interface in the consistency base node, a register stack is set for the final cache as a first data buffer of the final cache.

[0039] The first data buffer stores the corresponding cache lines and data byte enable signals. The first data buffer includes: two pairs of read and write ports, wherein the first enable signal of one pair of read and write ports is controlled by the final cache read and write control pipeline located between the final cache and the first data buffer, and this part of the path mainly realizes the cache line data interaction between the final cache and the first data buffer. The second enable signal of the other pair of read ports in the two pairs of read and write ports is controlled by MSHR to realize the cache line data transfer from the first data buffer to the network link interface, wherein the write port enable signal can be controlled by the network link interface to realize the cache line data transfer from the network link interface to the first data buffer.

[0040] The read port can read the required cache line and byte enable data from the first data buffer according to the read port address bus every cycle. The data of the write port of the network link interface is written into the corresponding position of the first data buffer at the end of the write enable signal cycle, and the new data written in the next cycle can be read from the first data buffer.

[0041] In addition, when the network link interface and the last-level cache write data to the first data buffer at the same time, the data to be written in the network link interface, the data inside the first data buffer, and the data to be written in the last-level cache are merged in the order that the network link interface has the highest priority, the first data buffer has the second highest priority, and the last-level cache has the lowest priority, and the merged data are written to the first data buffer.

[0042] The first data buffer write operation is divided into two categories: overwrite and merge operation. Overwrite operation is to write the data to be written by the network link interface to the corresponding position of the first data buffer only when the byte enable input by the network link interface is 1. Merge operation is to write the data to be written by the network link interface to the corresponding position of the first data buffer only when the byte enable value of the network link interface input is 1 and the byte enable of the first data buffer is 0.

[0043] In this embodiment, since the above-mentioned first data buffer is mainly composed of a register stack and has a very high read and write data, it can easily achieve reading and writing within a single cycle. In addition, in the consistency base node, the first data buffer is added between the network link interface and the last-level cache, which greatly speeds up the data transmission speed between the consistency base node and the link. Moreover, equipping the last-level cache with the first data buffer can conveniently temporarily store the dirty data cache lines replaced from the last-level cache for subsequent writing back to the main memory. Moreover, the above-mentioned first data buffer control logic is relatively simple, and under the premise of ensuring consistency, it still has low complexity, high performance and small area.

[0044] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0045] Reference Figure 3 , Figure 3 The structural block diagram of an embodiment of a data interaction device of the present invention is shown, and the data interaction device is applied to the aforementioned on-chip network system, and the on-chip network system includes: a first node, and the first node includes: a network link interface and a last-level cache. Here, reference can be made to the aforementioned related records, and no further description is given to avoid repetition. The data interaction device may include:

[0046] A first data buffer setting module 201, configured to set at least one first data buffer for the last-level cache between the last-level cache and the network link interface in the first node;

[0047] The data interaction module 202 is used to implement data interaction between the network link interface and the last-level cache based on the first data buffer.

[0048] Optionally, the data interaction module 202 may include:

[0049] A first data interaction submodule, configured to write the data in the cache line into the first data buffer when a cache line in the last-level cache is replaced and the data in the cache line is modified;

[0050] The second data interaction submodule is used to write the data written in the first data buffer into the main memory of the on-chip network system through the network link interface.

[0051] Optionally, the data interaction module 202 may include:

[0052] The third sub-module of data interaction is used to merge the data to be written in the network link interface, the data inside the first data buffer, and the data to be written in the last-level cache in the order of the network link interface having the highest priority, the first data buffer having the second priority, and the last-level cache having the lowest priority, and write the merged data into the first data buffer when the network link interface and the last-level cache write data to the first data buffer at the same time.

[0053] Optionally, the aforementioned data interaction device may further include:

[0054] A pipeline setting module, used for setting a cache read-write control pipeline between the final-level cache and the first data buffer, and the cache read-write control pipeline controls a first enable signal between the final-level cache and the first data buffer;

[0055] A miss status holding register setting module, used for setting a miss status holding register between the network link interface and the first data buffer, and controlling a second enable signal between the network link interface and the first data buffer by the miss status holding register;

[0056] The data interaction module 202 may include:

[0057] The fourth data interaction submodule is used to implement data interaction between the network link interface and the last-level cache based on the first enable signal and the second enable signal.

[0058] Optionally, the first data buffer setting module 201 may include:

[0059] The first data buffer setting submodule is used to set at least one register file between the final level cache and the network link interface in the first node as a first data buffer of the final level cache.

[0060] Optionally, the network on chip system further includes: a second node, the second node is different from the first node, the second node includes: a previous level cache, and the data interaction device may further include:

[0061] A second data buffer setting module, configured to set at least one second data buffer for the previous level cache in the second node;

[0062] The data interaction module is further used to implement data interaction with the previous level cache based on the second data buffer.

[0063] Figure 4 is a structural diagram of an electronic device provided by an embodiment of the present invention. Figure 4 The present invention also provides an electronic device, see Figure 4 , including: a multi-core processor 301, a memory 302, and a computer program 3021 stored in the memory and executable on the multi-core processor, and the multi-core processor implements the steps of the above-mentioned data interaction embodiments when executing the program.

[0064] The present invention also provides a readable storage medium, when the instructions or transactions in the storage medium are executed by a multi-core processor of an electronic device, the electronic device can execute the steps of each embodiment of the above data interaction method. A transaction mentioned in the present invention executes an operation, which can be reading from a memory or writing to a memory.

[0065] The present invention also provides a computer program product, including instructions or transactions, which, when executed by a multi-core processor in an electronic device, enable the electronic device to execute any one of the aforementioned data interaction methods.

[0066] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0067] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0068] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0069] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0070] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0071] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0072] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0073] The data interaction method and device, an electronic device and a storage medium provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principle and implementation mode of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A data interaction method, characterized in that: Applied to a network-on-chip system, the network-on-chip system comprises: a first node, the first node comprises: a network link interface and a last-level cache, the method comprises: Between the final level cache and the network link interface in the first node, at least one first data buffer is provided for the final level cache; Implementing data interaction between the network link interface and the last-level cache based on the first data buffer; The implementing data interaction between the network link interface and the last-level cache based on the first data buffer includes: In the case where the network link interface and the last-level cache write data to the first data buffer at the same time, the data to be written in the network link interface, the data in the first data buffer, and the data to be written in the last-level cache are merged in the order that the network link interface has the highest priority, the first data buffer has the second highest priority, and the last-level cache has the lowest priority, and the merged data is written into the first data buffer; The step of setting at least one first data buffer for the final level cache between the final level cache and the network link interface in the first node comprises: At least one register file is set between the final level cache and the network link interface in the first node as a first data buffer of the final level cache, and the first data buffer stores the corresponding cache line and data byte enable signal.

2. The method according to claim 1, characterized in that The implementing data interaction between the network link interface and the last-level cache based on the first data buffer includes: When a cache line in the last-level cache is replaced and data in the cache line is modified, writing the data in the cache line into the first data buffer; The data written into the first data buffer is written into the main memory of the on-chip network system through the network link interface.

3. The method according to claim 1, characterized in that Before implementing data interaction between the network link interface and the last-level cache based on the first data buffer, the method further includes: A final-level cache read / write control pipeline is provided between the final-level cache and the first data buffer, and a first enable signal between the final-level cache and the first data buffer is controlled by the final-level cache read / write control pipeline; A miss status holding register is provided between the network link interface and the first data buffer, and a second enable signal between the network link interface and the first data buffer is controlled by the miss status holding register; The implementing data interaction between the network link interface and the last-level cache based on the first data buffer includes: Based on the first enable signal and the second enable signal, data interaction between the network link interface and the last-level cache is implemented.

4. The method according to any one of claims 1 to 3, characterized in that: The network-on-chip system further includes: a second node, the second node is different from the first node, the second node includes: a previous level cache, and the method further includes: Setting at least one second data buffer for the previous level cache in the second node; Data interaction with the previous level cache is achieved based on the second data buffer.

5. A data interaction device, characterized in that: Applied to a network-on-chip system, the network-on-chip system comprises: a first node, the first node comprises: a network link interface and a last-level cache, the device comprises: A first data buffer setting module, configured to set at least one first data buffer for the last-level cache between the last-level cache and the network link interface in the first node; A data interaction module, used for realizing data interaction between the network link interface and the last-level cache based on the first data buffer; The data interaction module includes: a third data interaction submodule, for merging the data to be written in the network link interface, the data in the first data buffer, and the data to be written in the last-level cache in the order of the network link interface having the highest priority, the first data buffer having the second priority, and the last-level cache having the lowest priority, and writing the merged data into the first data buffer when the network link interface and the last-level cache write data to the first data buffer at the same time; The first data buffer setting module includes: The first data buffer setting submodule is used to set at least one register stack as a first data buffer of the final level cache between the final level cache and the network link interface in the first node, wherein the first data buffer stores corresponding cache lines and data byte enable signals.

6. An electronic device, characterized in that: include: A multi-core processor, a memory, and a computer program stored in the memory and executable on the multi-core processor, wherein the multi-core processor implements the data interaction method as claimed in any one of claims 1 to 4 when executing the computer program.

7. A readable storage medium, characterized in that: When the instructions or transactions in the storage medium are executed by a multi-core processor of an electronic device, the electronic device is enabled to execute the data interaction method described in any one of claims 1 to 4.

8. A computer program product, comprising instructions or transactions, which, when executed by a multi-core processor in an electronic device, enable the electronic device to execute the data interaction method according to any one of claims 1 to 4.

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